r9a09g056-sys.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * RZ/V2N System controller (SYS) driver
  4 *
  5 * Copyright (C) 2025 Renesas Electronics Corp.
  6 */
  7
  8#include <linux/bitfield.h>
  9#include <linux/bits.h>
 10#include <linux/device.h>
 11#include <linux/init.h>
 12#include <linux/io.h>
 13
 14#include "rz-sysc.h"
 15
 16/* Register Offsets */
 17#define SYS_LSI_MODE		0x300
 18#define SYS_LSI_MODE_SEC_EN	BIT(16)
 19/*
 20 * BOOTPLLCA[1:0]
 21 *	    [0,0] => 1.1GHZ
 22 *	    [0,1] => 1.5GHZ
 23 *	    [1,0] => 1.6GHZ
 24 *	    [1,1] => 1.7GHZ
 25 */
 26#define SYS_LSI_MODE_STAT_BOOTPLLCA55	GENMASK(12, 11)
 27#define SYS_LSI_MODE_CA55_1_7GHZ	0x3
 28
 29#define SYS_LSI_PRR			0x308
 30#define SYS_LSI_PRR_GPU_DIS		BIT(0)
 31#define SYS_LSI_PRR_ISP_DIS		BIT(4)
 32
 33#define SYS_RZV2N_FEATURE_G31		BIT(0)
 34#define SYS_RZV2N_FEATURE_C55		BIT(1)
 35#define SYS_RZV2N_FEATURE_SEC		BIT(2)
 36
 37#define SYS_LSI_OTPTSU0TRMVAL0		0x320
 38#define SYS_LSI_OTPTSU0TRMVAL1		0x324
 39#define SYS_LSI_OTPTSU1TRMVAL0		0x330
 40#define SYS_LSI_OTPTSU1TRMVAL1		0x334
 41#define SYS_GBETH0_CFG			0xf00
 42#define SYS_GBETH1_CFG			0xf04
 43#define SYS_PCIE_INTX_CH0		0x1000
 44#define SYS_PCIE_MSI1_CH0		0x1004
 45#define SYS_PCIE_MSI2_CH0		0x1008
 46#define SYS_PCIE_MSI3_CH0		0x100c
 47#define SYS_PCIE_MSI4_CH0		0x1010
 48#define SYS_PCIE_MSI5_CH0		0x1014
 49#define SYS_PCIE_PME_CH0		0x1018
 50#define SYS_PCIE_ACK_CH0		0x101c
 51#define SYS_PCIE_MISC_CH0		0x1020
 52#define SYS_PCIE_MODE_CH0		0x1024
 53#define SYS_ADC_CFG			0x1600
 54
 55static void rzv2n_sys_print_id(struct device *dev,
 56			       void __iomem *sysc_base,
 57			       struct soc_device_attribute *soc_dev_attr)
 58{
 59	u32 prr_val, mode_val;
 60	u8 feature_flags;
 61
 62	prr_val = readl(sysc_base + SYS_LSI_PRR);
 63	mode_val = readl(sysc_base + SYS_LSI_MODE);
 64
 65	/* Check GPU, ISP and Cryptographic configuration */
 66	feature_flags = !(prr_val & SYS_LSI_PRR_GPU_DIS) ? SYS_RZV2N_FEATURE_G31 : 0;
 67	feature_flags |= !(prr_val & SYS_LSI_PRR_ISP_DIS) ? SYS_RZV2N_FEATURE_C55 : 0;
 68	feature_flags |= (mode_val & SYS_LSI_MODE_SEC_EN) ? SYS_RZV2N_FEATURE_SEC : 0;
 69
 70	dev_info(dev, "Detected Renesas %s %sn%d Rev %s%s%s%s%s\n", soc_dev_attr->family,
 71		 soc_dev_attr->soc_id, 41 + feature_flags, soc_dev_attr->revision,
 72		 feature_flags ?  " with" : "",
 73		 feature_flags & SYS_RZV2N_FEATURE_G31 ? " GE3D (Mali-G31)" : "",
 74		 feature_flags & SYS_RZV2N_FEATURE_SEC ? " Cryptographic engine" : "",
 75		 feature_flags & SYS_RZV2N_FEATURE_C55 ? " ISP (Mali-C55)" : "");
 76
 77	/* Check CA55 PLL configuration */
 78	if (FIELD_GET(SYS_LSI_MODE_STAT_BOOTPLLCA55, mode_val) != SYS_LSI_MODE_CA55_1_7GHZ)
 79		dev_warn(dev, "CA55 PLL is not set to 1.7GHz\n");
 80}
 81
 82static const struct rz_sysc_soc_id_init_data rzv2n_sys_soc_id_init_data __initconst = {
 83	.family = "RZ/V2N",
 84	.id = 0x867d447,
 85	.devid_offset = 0x304,
 86	.revision_mask = GENMASK(31, 28),
 87	.specific_id_mask = GENMASK(27, 0),
 88	.print_id = rzv2n_sys_print_id,
 89};
 90
 91static bool rzv2n_regmap_readable_reg(struct device *dev, unsigned int reg)
 92{
 93	switch (reg) {
 94	case SYS_LSI_OTPTSU0TRMVAL0:
 95	case SYS_LSI_OTPTSU0TRMVAL1:
 96	case SYS_LSI_OTPTSU1TRMVAL0:
 97	case SYS_LSI_OTPTSU1TRMVAL1:
 98	case SYS_GBETH0_CFG:
 99	case SYS_GBETH1_CFG:
100	case SYS_PCIE_INTX_CH0:
101	case SYS_PCIE_MSI1_CH0:
102	case SYS_PCIE_MSI2_CH0:
103	case SYS_PCIE_MSI3_CH0:
104	case SYS_PCIE_MSI4_CH0:
105	case SYS_PCIE_MSI5_CH0:
106	case SYS_PCIE_PME_CH0:
107	case SYS_PCIE_ACK_CH0:
108	case SYS_PCIE_MISC_CH0:
109	case SYS_PCIE_MODE_CH0:
110	case SYS_ADC_CFG:
111		return true;
112	default:
113		return false;
114	}
115}
116
117static bool rzv2n_regmap_writeable_reg(struct device *dev, unsigned int reg)
118{
119	switch (reg) {
120	case SYS_GBETH0_CFG:
121	case SYS_GBETH1_CFG:
122	case SYS_PCIE_INTX_CH0:
123	case SYS_PCIE_MSI1_CH0:
124	case SYS_PCIE_MSI2_CH0:
125	case SYS_PCIE_MSI3_CH0:
126	case SYS_PCIE_MSI4_CH0:
127	case SYS_PCIE_MSI5_CH0:
128	case SYS_PCIE_PME_CH0:
129	case SYS_PCIE_ACK_CH0:
130	case SYS_PCIE_MISC_CH0:
131	case SYS_PCIE_MODE_CH0:
132	case SYS_ADC_CFG:
133		return true;
134	default:
135		return false;
136	}
137}
138
139const struct rz_sysc_init_data rzv2n_sys_init_data = {
140	.soc_id_init_data = &rzv2n_sys_soc_id_init_data,
141	.readable_reg = rzv2n_regmap_readable_reg,
142	.writeable_reg = rzv2n_regmap_writeable_reg,
143	.max_register = 0x170c,
144};