pwc-rzv2m.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (C) 2023 Renesas Electronics Corporation
  4 */
  5
  6#include <linux/delay.h>
  7#include <linux/gpio/driver.h>
  8#include <linux/platform_device.h>
  9#include <linux/reboot.h>
 10
 11#define PWC_PWCRST			0x00
 12#define PWC_PWCCKEN			0x04
 13#define PWC_PWCCTL			0x50
 14#define PWC_GPIO			0x80
 15
 16#define PWC_PWCRST_RSTSOFTAX		0x1
 17#define PWC_PWCCKEN_ENGCKMAIN		0x1
 18#define PWC_PWCCTL_PWOFF		0x1
 19
 20struct rzv2m_pwc_priv {
 21	void __iomem *base;
 22	struct device *dev;
 23	struct gpio_chip gp;
 24	DECLARE_BITMAP(ch_en_bits, 2);
 25};
 26
 27static int rzv2m_pwc_gpio_set(struct gpio_chip *chip, unsigned int offset,
 28			      int value)
 29{
 30	struct rzv2m_pwc_priv *priv = gpiochip_get_data(chip);
 31	u32 reg;
 32
 33	/* BIT 16 enables write to BIT 0, and BIT 17 enables write to BIT 1 */
 34	reg = BIT(offset + 16);
 35	if (value)
 36		reg |= BIT(offset);
 37
 38	writel(reg, priv->base + PWC_GPIO);
 39
 40	assign_bit(offset, priv->ch_en_bits, value);
 41
 42	return 0;
 43}
 44
 45static int rzv2m_pwc_gpio_get(struct gpio_chip *chip, unsigned int offset)
 46{
 47	struct rzv2m_pwc_priv *priv = gpiochip_get_data(chip);
 48
 49	return test_bit(offset, priv->ch_en_bits);
 50}
 51
 52static int rzv2m_pwc_gpio_direction_output(struct gpio_chip *gc,
 53					   unsigned int nr, int value)
 54{
 55	if (nr > 1)
 56		return -EINVAL;
 57
 58	rzv2m_pwc_gpio_set(gc, nr, value);
 59
 60	return 0;
 61}
 62
 63static const struct gpio_chip rzv2m_pwc_gc = {
 64	.label = "gpio_rzv2m_pwc",
 65	.owner = THIS_MODULE,
 66	.get = rzv2m_pwc_gpio_get,
 67	.set = rzv2m_pwc_gpio_set,
 68	.direction_output = rzv2m_pwc_gpio_direction_output,
 69	.can_sleep = false,
 70	.ngpio = 2,
 71	.base = -1,
 72};
 73
 74static int rzv2m_pwc_poweroff(struct sys_off_data *data)
 75{
 76	struct rzv2m_pwc_priv *priv = data->cb_data;
 77
 78	writel(PWC_PWCRST_RSTSOFTAX, priv->base + PWC_PWCRST);
 79	writel(PWC_PWCCKEN_ENGCKMAIN, priv->base + PWC_PWCCKEN);
 80	writel(PWC_PWCCTL_PWOFF, priv->base + PWC_PWCCTL);
 81
 82	mdelay(150);
 83
 84	dev_err(priv->dev, "Failed to power off the system");
 85
 86	return NOTIFY_DONE;
 87}
 88
 89static int rzv2m_pwc_probe(struct platform_device *pdev)
 90{
 91	struct rzv2m_pwc_priv *priv;
 92	int ret;
 93
 94	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 95	if (!priv)
 96		return -ENOMEM;
 97
 98	priv->base = devm_platform_ioremap_resource(pdev, 0);
 99	if (IS_ERR(priv->base))
100		return PTR_ERR(priv->base);
101
102	/*
103	 * The register used by this driver cannot be read, therefore set the
104	 * outputs to their default values and initialize priv->ch_en_bits
105	 * accordingly. BIT 16 enables write to BIT 0, BIT 17 enables write to
106	 * BIT 1, and the default value of both BIT 0 and BIT 1 is 0.
107	 */
108	writel(BIT(17) | BIT(16), priv->base + PWC_GPIO);
109	bitmap_zero(priv->ch_en_bits, 2);
110
111	priv->gp = rzv2m_pwc_gc;
112	priv->gp.parent = pdev->dev.parent;
113	priv->gp.fwnode = dev_fwnode(&pdev->dev);
114
115	ret = devm_gpiochip_add_data(&pdev->dev, &priv->gp, priv);
116	if (ret)
117		return ret;
118
119	if (device_property_read_bool(&pdev->dev, "renesas,rzv2m-pwc-power"))
120		ret = devm_register_power_off_handler(&pdev->dev,
121						      rzv2m_pwc_poweroff, priv);
122
123	return ret;
124}
125
126static const struct of_device_id rzv2m_pwc_of_match[] = {
127	{ .compatible = "renesas,rzv2m-pwc" },
128	{ /* sentinel */ }
129};
130MODULE_DEVICE_TABLE(of, rzv2m_pwc_of_match);
131
132static struct platform_driver rzv2m_pwc_driver = {
133	.probe = rzv2m_pwc_probe,
134	.driver = {
135		.name = "rzv2m_pwc",
136		.of_match_table = rzv2m_pwc_of_match,
137	},
138};
139module_platform_driver(rzv2m_pwc_driver);
140
141MODULE_LICENSE("GPL");
142MODULE_AUTHOR("Fabrizio Castro <castro.fabrizio.jz@renesas.com>");
143MODULE_DESCRIPTION("Renesas RZ/V2M PWC driver");