ubwc_config.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
  4 */
  5
  6#include <linux/debugfs.h>
  7#include <linux/io.h>
  8#include <linux/module.h>
  9#include <linux/of.h>
 10#include <linux/of_address.h>
 11#include <linux/platform_device.h>
 12
 13#include <linux/soc/qcom/ubwc.h>
 14
 15static const struct qcom_ubwc_cfg_data no_ubwc_data = {
 16	/* no UBWC, no HBB */
 17};
 18
 19static const struct qcom_ubwc_cfg_data kaanapali_data = {
 20	.ubwc_enc_version = UBWC_6_0,
 21	.ubwc_dec_version = UBWC_6_0,
 22	.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
 23			UBWC_SWIZZLE_ENABLE_LVL3,
 24	.ubwc_bank_spread = true,
 25	.highest_bank_bit = 16,
 26	.macrotile_mode = true,
 27};
 28
 29static const struct qcom_ubwc_cfg_data msm8937_data = {
 30	.ubwc_enc_version = UBWC_1_0,
 31	.ubwc_dec_version = UBWC_1_0,
 32	.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 |
 33			UBWC_SWIZZLE_ENABLE_LVL2 |
 34			UBWC_SWIZZLE_ENABLE_LVL3,
 35	.highest_bank_bit = 14,
 36};
 37
 38static const struct qcom_ubwc_cfg_data msm8998_data = {
 39	.ubwc_enc_version = UBWC_1_0,
 40	.ubwc_dec_version = UBWC_1_0,
 41	.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 |
 42			UBWC_SWIZZLE_ENABLE_LVL2 |
 43			UBWC_SWIZZLE_ENABLE_LVL3,
 44	.highest_bank_bit = 15,
 45};
 46
 47static const struct qcom_ubwc_cfg_data qcm2290_data = {
 48	/* no UBWC */
 49	.highest_bank_bit = 15,
 50};
 51
 52static const struct qcom_ubwc_cfg_data sa8775p_data = {
 53	.ubwc_enc_version = UBWC_4_0,
 54	.ubwc_dec_version = UBWC_4_0,
 55	.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL3,
 56	.ubwc_bank_spread = true,
 57	.highest_bank_bit = 13,
 58	.macrotile_mode = true,
 59};
 60
 61static const struct qcom_ubwc_cfg_data sar2130p_data = {
 62	.ubwc_enc_version = UBWC_3_0, /* 4.0.2 in hw */
 63	.ubwc_dec_version = UBWC_4_3,
 64	.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
 65			UBWC_SWIZZLE_ENABLE_LVL3,
 66	.ubwc_bank_spread = true,
 67	.highest_bank_bit = 13,
 68	.macrotile_mode = true,
 69};
 70
 71static const struct qcom_ubwc_cfg_data sc7180_data = {
 72	.ubwc_enc_version = UBWC_2_0,
 73	.ubwc_dec_version = UBWC_2_0,
 74	.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
 75			UBWC_SWIZZLE_ENABLE_LVL3,
 76	.ubwc_bank_spread = true,
 77	.highest_bank_bit = 14,
 78};
 79
 80static const struct qcom_ubwc_cfg_data sc7280_data = {
 81	.ubwc_enc_version = UBWC_3_0,
 82	.ubwc_dec_version = UBWC_4_0,
 83	.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
 84			UBWC_SWIZZLE_ENABLE_LVL3,
 85	.ubwc_bank_spread = true,
 86	.highest_bank_bit = 14,
 87	.macrotile_mode = true,
 88};
 89
 90static const struct qcom_ubwc_cfg_data sc8180x_data = {
 91	.ubwc_enc_version = UBWC_3_0,
 92	.ubwc_dec_version = UBWC_3_0,
 93	.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
 94			UBWC_SWIZZLE_ENABLE_LVL3,
 95	.highest_bank_bit = 16,
 96	.macrotile_mode = true,
 97};
 98
 99static const struct qcom_ubwc_cfg_data sc8280xp_data = {
100	.ubwc_enc_version = UBWC_4_0,
101	.ubwc_dec_version = UBWC_4_0,
102	.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
103			UBWC_SWIZZLE_ENABLE_LVL3,
104	.ubwc_bank_spread = true,
105	.highest_bank_bit = 16,
106	.macrotile_mode = true,
107};
108
109static const struct qcom_ubwc_cfg_data sdm670_data = {
110	.ubwc_enc_version = UBWC_2_0,
111	.ubwc_dec_version = UBWC_2_0,
112	.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
113			UBWC_SWIZZLE_ENABLE_LVL3,
114	.highest_bank_bit = 14,
115};
116
117static const struct qcom_ubwc_cfg_data sdm845_data = {
118	.ubwc_enc_version = UBWC_2_0,
119	.ubwc_dec_version = UBWC_2_0,
120	.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
121			UBWC_SWIZZLE_ENABLE_LVL3,
122	.highest_bank_bit = 15,
123};
124
125static const struct qcom_ubwc_cfg_data sm6115_data = {
126	.ubwc_enc_version = UBWC_1_0,
127	.ubwc_dec_version = UBWC_2_0,
128	.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 |
129			UBWC_SWIZZLE_ENABLE_LVL2 |
130			UBWC_SWIZZLE_ENABLE_LVL3,
131	.ubwc_bank_spread = true,
132	.highest_bank_bit = 14,
133};
134
135static const struct qcom_ubwc_cfg_data sm6125_data = {
136	.ubwc_enc_version = UBWC_1_0,
137	.ubwc_dec_version = UBWC_3_0,
138	.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 |
139			UBWC_SWIZZLE_ENABLE_LVL2 |
140			UBWC_SWIZZLE_ENABLE_LVL3,
141	.highest_bank_bit = 14,
142};
143
144static const struct qcom_ubwc_cfg_data sm6150_data = {
145	.ubwc_enc_version = UBWC_2_0,
146	.ubwc_dec_version = UBWC_2_0,
147	.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
148			UBWC_SWIZZLE_ENABLE_LVL3,
149	.highest_bank_bit = 14,
150};
151
152static const struct qcom_ubwc_cfg_data sm6350_data = {
153	.ubwc_enc_version = UBWC_2_0,
154	.ubwc_dec_version = UBWC_2_0,
155	.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
156			UBWC_SWIZZLE_ENABLE_LVL3,
157	.ubwc_bank_spread = true,
158	.highest_bank_bit = 14,
159};
160
161static const struct qcom_ubwc_cfg_data sm7150_data = {
162	.ubwc_enc_version = UBWC_2_0,
163	.ubwc_dec_version = UBWC_2_0,
164	.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
165			UBWC_SWIZZLE_ENABLE_LVL3,
166	.highest_bank_bit = 14,
167};
168
169static const struct qcom_ubwc_cfg_data sm8150_data = {
170	.ubwc_enc_version = UBWC_3_0,
171	.ubwc_dec_version = UBWC_3_0,
172	.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
173			UBWC_SWIZZLE_ENABLE_LVL3,
174	.highest_bank_bit = 15,
175};
176
177static const struct qcom_ubwc_cfg_data sm8250_data = {
178	.ubwc_enc_version = UBWC_4_0,
179	.ubwc_dec_version = UBWC_4_0,
180	.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
181			UBWC_SWIZZLE_ENABLE_LVL3,
182	.ubwc_bank_spread = true,
183	/* TODO: highest_bank_bit = 15 for LP_DDR4 */
184	.highest_bank_bit = 16,
185	.macrotile_mode = true,
186};
187
188static const struct qcom_ubwc_cfg_data sm8350_data = {
189	.ubwc_enc_version = UBWC_4_0,
190	.ubwc_dec_version = UBWC_4_0,
191	.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
192			UBWC_SWIZZLE_ENABLE_LVL3,
193	.ubwc_bank_spread = true,
194	/* TODO: highest_bank_bit = 15 for LP_DDR4 */
195	.highest_bank_bit = 16,
196	.macrotile_mode = true,
197};
198
199static const struct qcom_ubwc_cfg_data sm8550_data = {
200	.ubwc_enc_version = UBWC_4_0,
201	.ubwc_dec_version = UBWC_4_3,
202	.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
203			UBWC_SWIZZLE_ENABLE_LVL3,
204	.ubwc_bank_spread = true,
205	/* TODO: highest_bank_bit = 15 for LP_DDR4 */
206	.highest_bank_bit = 16,
207	.macrotile_mode = true,
208};
209
210static const struct qcom_ubwc_cfg_data sm8750_data = {
211	.ubwc_enc_version = UBWC_5_0,
212	.ubwc_dec_version = UBWC_5_0,
213	.ubwc_swizzle = 6,
214	.ubwc_bank_spread = true,
215	/* TODO: highest_bank_bit = 15 for LP_DDR4 */
216	.highest_bank_bit = 16,
217	.macrotile_mode = true,
218};
219
220static const struct qcom_ubwc_cfg_data x1e80100_data = {
221	.ubwc_enc_version = UBWC_4_0,
222	.ubwc_dec_version = UBWC_4_3,
223	.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
224			UBWC_SWIZZLE_ENABLE_LVL3,
225	.ubwc_bank_spread = true,
226	/* TODO: highest_bank_bit = 15 for LP_DDR4 */
227	.highest_bank_bit = 16,
228	.macrotile_mode = true,
229};
230
231static const struct qcom_ubwc_cfg_data glymur_data = {
232	.ubwc_enc_version = UBWC_5_0,
233	.ubwc_dec_version = UBWC_5_0,
234	.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
235			UBWC_SWIZZLE_ENABLE_LVL3,
236	.ubwc_bank_spread = true,
237	/* TODO: highest_bank_bit = 15 for LP_DDR4 */
238	.highest_bank_bit = 16,
239	.macrotile_mode = true,
240};
241
242static const struct of_device_id qcom_ubwc_configs[] __maybe_unused = {
243	{ .compatible = "qcom,apq8016", .data = &no_ubwc_data },
244	{ .compatible = "qcom,apq8026", .data = &no_ubwc_data },
245	{ .compatible = "qcom,apq8074", .data = &no_ubwc_data },
246	{ .compatible = "qcom,apq8096", .data = &msm8998_data },
247	{ .compatible = "qcom,kaanapali", .data = &kaanapali_data, },
248	{ .compatible = "qcom,glymur", .data = &glymur_data},
249	{ .compatible = "qcom,msm8226", .data = &no_ubwc_data },
250	{ .compatible = "qcom,msm8916", .data = &no_ubwc_data },
251	{ .compatible = "qcom,msm8917", .data = &no_ubwc_data },
252	{ .compatible = "qcom,msm8937", .data = &msm8937_data },
253	{ .compatible = "qcom,msm8929", .data = &no_ubwc_data },
254	{ .compatible = "qcom,msm8939", .data = &no_ubwc_data },
255	{ .compatible = "qcom,msm8953", .data = &msm8937_data },
256	{ .compatible = "qcom,msm8956", .data = &no_ubwc_data },
257	{ .compatible = "qcom,msm8974", .data = &no_ubwc_data },
258	{ .compatible = "qcom,msm8976", .data = &no_ubwc_data },
259	{ .compatible = "qcom,msm8996", .data = &msm8998_data },
260	{ .compatible = "qcom,msm8998", .data = &msm8998_data },
261	{ .compatible = "qcom,qcm2290", .data = &qcm2290_data, },
262	{ .compatible = "qcom,qcm6490", .data = &sc7280_data, },
263	{ .compatible = "qcom,qcs8300", .data = &sc8280xp_data, },
264	{ .compatible = "qcom,sa8155p", .data = &sm8150_data, },
265	{ .compatible = "qcom,sa8540p", .data = &sc8280xp_data, },
266	{ .compatible = "qcom,sa8775p", .data = &sa8775p_data, },
267	{ .compatible = "qcom,sar2130p", .data = &sar2130p_data },
268	{ .compatible = "qcom,sc7180", .data = &sc7180_data },
269	{ .compatible = "qcom,sc7280", .data = &sc7280_data, },
270	{ .compatible = "qcom,sc8180x", .data = &sc8180x_data, },
271	{ .compatible = "qcom,sc8280xp", .data = &sc8280xp_data, },
272	{ .compatible = "qcom,sda660", .data = &msm8937_data },
273	{ .compatible = "qcom,sdm450", .data = &msm8937_data },
274	{ .compatible = "qcom,sdm630", .data = &msm8937_data },
275	{ .compatible = "qcom,sdm632", .data = &msm8937_data },
276	{ .compatible = "qcom,sdm636", .data = &msm8937_data },
277	{ .compatible = "qcom,sdm660", .data = &msm8937_data },
278	{ .compatible = "qcom,sdm670", .data = &sdm670_data, },
279	{ .compatible = "qcom,sdm845", .data = &sdm845_data, },
280	{ .compatible = "qcom,sm4250", .data = &sm6115_data, },
281	{ .compatible = "qcom,sm6115", .data = &sm6115_data, },
282	{ .compatible = "qcom,sm6125", .data = &sm6125_data, },
283	{ .compatible = "qcom,sm6150", .data = &sm6150_data, },
284	{ .compatible = "qcom,sm6350", .data = &sm6350_data, },
285	{ .compatible = "qcom,sm6375", .data = &sm6350_data, },
286	{ .compatible = "qcom,sm7125", .data = &sc7180_data },
287	{ .compatible = "qcom,sm7150", .data = &sm7150_data, },
288	{ .compatible = "qcom,sm7225", .data = &sm6350_data, },
289	{ .compatible = "qcom,sm7325", .data = &sc7280_data, },
290	{ .compatible = "qcom,sm8150", .data = &sm8150_data, },
291	{ .compatible = "qcom,sm8250", .data = &sm8250_data, },
292	{ .compatible = "qcom,sm8350", .data = &sm8350_data, },
293	{ .compatible = "qcom,sm8450", .data = &sm8350_data, },
294	{ .compatible = "qcom,sm8550", .data = &sm8550_data, },
295	{ .compatible = "qcom,sm8650", .data = &sm8550_data, },
296	{ .compatible = "qcom,sm8750", .data = &sm8750_data, },
297	{ .compatible = "qcom,x1e80100", .data = &x1e80100_data, },
298	{ .compatible = "qcom,x1p42100", .data = &x1e80100_data, },
299	{ }
300};
301
302const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(void)
303{
304	const struct qcom_ubwc_cfg_data *data;
305
306	data = of_machine_get_match_data(qcom_ubwc_configs);
307	if (!data) {
308		pr_err("Couldn't find UBWC config data for this platform!\n");
309		return ERR_PTR(-EINVAL);
310	}
311
312	return data;
313}
314EXPORT_SYMBOL_GPL(qcom_ubwc_config_get_data);
315
316MODULE_LICENSE("GPL");
317MODULE_DESCRIPTION("UBWC config database for QTI SoCs");