mtk-svs.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (C) 2022 MediaTek Inc.
   4 * Copyright (C) 2022 Collabora Ltd.
   5 *                    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
   6 */
   7
   8#include <linux/bitfield.h>
   9#include <linux/bits.h>
  10#include <linux/clk.h>
  11#include <linux/completion.h>
  12#include <linux/cleanup.h>
  13#include <linux/cpu.h>
  14#include <linux/cpuidle.h>
  15#include <linux/debugfs.h>
  16#include <linux/device.h>
  17#include <linux/init.h>
  18#include <linux/interrupt.h>
  19#include <linux/kernel.h>
  20#include <linux/kthread.h>
  21#include <linux/module.h>
  22#include <linux/mutex.h>
  23#include <linux/nvmem-consumer.h>
  24#include <linux/of_address.h>
  25#include <linux/of_irq.h>
  26#include <linux/of_platform.h>
  27#include <linux/platform_device.h>
  28#include <linux/pm_domain.h>
  29#include <linux/pm_opp.h>
  30#include <linux/pm_runtime.h>
  31#include <linux/regulator/consumer.h>
  32#include <linux/reset.h>
  33#include <linux/seq_file.h>
  34#include <linux/slab.h>
  35#include <linux/spinlock.h>
  36#include <linux/thermal.h>
  37
  38/* svs bank mode support */
  39#define SVSB_MODE_ALL_DISABLE		0
  40#define SVSB_MODE_INIT01		BIT(1)
  41#define SVSB_MODE_INIT02		BIT(2)
  42#define SVSB_MODE_MON			BIT(3)
  43
  44/* svs bank volt flags */
  45#define SVSB_INIT01_PD_REQ		BIT(0)
  46#define SVSB_INIT01_VOLT_IGNORE		BIT(1)
  47#define SVSB_INIT01_VOLT_INC_ONLY	BIT(2)
  48#define SVSB_MON_VOLT_IGNORE		BIT(16)
  49#define SVSB_REMOVE_DVTFIXED_VOLT	BIT(24)
  50
  51/* svs bank register fields and common configuration */
  52#define SVSB_PTPCONFIG_DETMAX		GENMASK(15, 0)
  53#define SVSB_DET_MAX			FIELD_PREP(SVSB_PTPCONFIG_DETMAX, 0xffff)
  54#define SVSB_DET_WINDOW			0xa28
  55
  56/* DESCHAR */
  57#define SVSB_DESCHAR_FLD_MDES		GENMASK(7, 0)
  58#define SVSB_DESCHAR_FLD_BDES		GENMASK(15, 8)
  59
  60/* TEMPCHAR */
  61#define SVSB_TEMPCHAR_FLD_DVT_FIXED	GENMASK(7, 0)
  62#define SVSB_TEMPCHAR_FLD_MTDES		GENMASK(15, 8)
  63#define SVSB_TEMPCHAR_FLD_VCO		GENMASK(23, 16)
  64
  65/* DETCHAR */
  66#define SVSB_DETCHAR_FLD_DCMDET		GENMASK(7, 0)
  67#define SVSB_DETCHAR_FLD_DCBDET		GENMASK(15, 8)
  68
  69/* SVSEN (PTPEN) */
  70#define SVSB_PTPEN_INIT01		BIT(0)
  71#define SVSB_PTPEN_MON			BIT(1)
  72#define SVSB_PTPEN_INIT02		(SVSB_PTPEN_INIT01 | BIT(2))
  73#define SVSB_PTPEN_OFF			0x0
  74
  75/* FREQPCTS */
  76#define SVSB_FREQPCTS_FLD_PCT0_4	GENMASK(7, 0)
  77#define SVSB_FREQPCTS_FLD_PCT1_5	GENMASK(15, 8)
  78#define SVSB_FREQPCTS_FLD_PCT2_6	GENMASK(23, 16)
  79#define SVSB_FREQPCTS_FLD_PCT3_7	GENMASK(31, 24)
  80
  81/* INTSTS */
  82#define SVSB_INTSTS_VAL_CLEAN		0x00ffffff
  83#define SVSB_INTSTS_F0_COMPLETE		BIT(0)
  84#define SVSB_INTSTS_FLD_MONVOP		GENMASK(23, 16)
  85#define SVSB_RUNCONFIG_DEFAULT		0x80000000
  86
  87/* LIMITVALS */
  88#define SVSB_LIMITVALS_FLD_DTLO		GENMASK(7, 0)
  89#define SVSB_LIMITVALS_FLD_DTHI		GENMASK(15, 8)
  90#define SVSB_LIMITVALS_FLD_VMIN		GENMASK(23, 16)
  91#define SVSB_LIMITVALS_FLD_VMAX		GENMASK(31, 24)
  92#define SVSB_VAL_DTHI			0x1
  93#define SVSB_VAL_DTLO			0xfe
  94
  95/* INTEN */
  96#define SVSB_INTEN_F0EN			BIT(0)
  97#define SVSB_INTEN_DACK0UPEN		BIT(8)
  98#define SVSB_INTEN_DC0EN		BIT(9)
  99#define SVSB_INTEN_DC1EN		BIT(10)
 100#define SVSB_INTEN_DACK0LOEN		BIT(11)
 101#define SVSB_INTEN_INITPROD_OVF_EN	BIT(12)
 102#define SVSB_INTEN_INITSUM_OVF_EN	BIT(14)
 103#define SVSB_INTEN_MONVOPEN		GENMASK(23, 16)
 104#define SVSB_INTEN_INIT0x		(SVSB_INTEN_F0EN | SVSB_INTEN_DACK0UPEN |	\
 105					 SVSB_INTEN_DC0EN | SVSB_INTEN_DC1EN |		\
 106					 SVSB_INTEN_DACK0LOEN |				\
 107					 SVSB_INTEN_INITPROD_OVF_EN |			\
 108					 SVSB_INTEN_INITSUM_OVF_EN)
 109
 110/* TSCALCS */
 111#define SVSB_TSCALCS_FLD_MTS		GENMASK(11, 0)
 112#define SVSB_TSCALCS_FLD_BTS		GENMASK(23, 12)
 113
 114/* INIT2VALS */
 115#define SVSB_INIT2VALS_FLD_DCVOFFSETIN	GENMASK(15, 0)
 116#define SVSB_INIT2VALS_FLD_AGEVOFFSETIN	GENMASK(31, 16)
 117
 118/* VOPS */
 119#define SVSB_VOPS_FLD_VOP0_4		GENMASK(7, 0)
 120#define SVSB_VOPS_FLD_VOP1_5		GENMASK(15, 8)
 121#define SVSB_VOPS_FLD_VOP2_6		GENMASK(23, 16)
 122#define SVSB_VOPS_FLD_VOP3_7		GENMASK(31, 24)
 123
 124/* SVS Thermal Coefficients */
 125#define SVSB_TS_COEFF_MT8195		250460
 126#define SVSB_TS_COEFF_MT8186		204650
 127
 128/* Algo helpers */
 129#define FUSE_DATA_NOT_VALID		U32_MAX
 130
 131/* svs bank related setting */
 132#define BITS8				8
 133#define MAX_OPP_ENTRIES			16
 134#define REG_BYTES			4
 135#define SVSB_DC_SIGNED_BIT		BIT(15)
 136#define SVSB_DET_CLK_EN			BIT(31)
 137#define SVSB_TEMP_LOWER_BOUND		0xb2
 138#define SVSB_TEMP_UPPER_BOUND		0x64
 139
 140static DEFINE_SPINLOCK(svs_lock);
 141
 142#ifdef CONFIG_DEBUG_FS
 143#define debug_fops_ro(name)						\
 144	static int svs_##name##_debug_open(struct inode *inode,		\
 145					   struct file *filp)		\
 146	{								\
 147		return single_open(filp, svs_##name##_debug_show,	\
 148				   inode->i_private);			\
 149	}								\
 150	static const struct file_operations svs_##name##_debug_fops = {	\
 151		.owner = THIS_MODULE,					\
 152		.open = svs_##name##_debug_open,			\
 153		.read = seq_read,					\
 154		.llseek = seq_lseek,					\
 155		.release = single_release,				\
 156	}
 157
 158#define debug_fops_rw(name)						\
 159	static int svs_##name##_debug_open(struct inode *inode,		\
 160					   struct file *filp)		\
 161	{								\
 162		return single_open(filp, svs_##name##_debug_show,	\
 163				   inode->i_private);			\
 164	}								\
 165	static const struct file_operations svs_##name##_debug_fops = {	\
 166		.owner = THIS_MODULE,					\
 167		.open = svs_##name##_debug_open,			\
 168		.read = seq_read,					\
 169		.write = svs_##name##_debug_write,			\
 170		.llseek = seq_lseek,					\
 171		.release = single_release,				\
 172	}
 173
 174#define svs_dentry_data(name)	{__stringify(name), &svs_##name##_debug_fops}
 175#endif
 176
 177/**
 178 * enum svsb_sw_id - SVS Bank Software ID
 179 * @SVSB_SWID_CPU_LITTLE: CPU little cluster Bank
 180 * @SVSB_SWID_CPU_BIG:    CPU big cluster Bank
 181 * @SVSB_SWID_CCI:        Cache Coherent Interconnect Bank
 182 * @SVSB_SWID_GPU:        GPU Bank
 183 * @SVSB_SWID_MAX:        Total number of Banks
 184 */
 185enum svsb_sw_id {
 186	SVSB_SWID_CPU_LITTLE,
 187	SVSB_SWID_CPU_BIG,
 188	SVSB_SWID_CCI,
 189	SVSB_SWID_GPU,
 190	SVSB_SWID_MAX
 191};
 192
 193/**
 194 * enum svsb_type - SVS Bank 2-line: Type and Role
 195 * @SVSB_TYPE_NONE: One-line type Bank - Global role
 196 * @SVSB_TYPE_LOW:  Two-line type Bank - Low bank role
 197 * @SVSB_TYPE_HIGH: Two-line type Bank - High bank role
 198 * @SVSB_TYPE_MAX:  Total number of bank types
 199 */
 200enum svsb_type {
 201	SVSB_TYPE_NONE,
 202	SVSB_TYPE_LOW,
 203	SVSB_TYPE_HIGH,
 204	SVSB_TYPE_MAX
 205};
 206
 207/**
 208 * enum svsb_phase - svs bank phase enumeration
 209 * @SVSB_PHASE_ERROR: svs bank encounters unexpected condition
 210 * @SVSB_PHASE_INIT01: svs bank basic init for data calibration
 211 * @SVSB_PHASE_INIT02: svs bank can provide voltages to opp table
 212 * @SVSB_PHASE_MON: svs bank can provide voltages with thermal effect
 213 * @SVSB_PHASE_MAX: total number of svs bank phase (debug purpose)
 214 *
 215 * Each svs bank has its own independent phase and we enable each svs bank by
 216 * running their phase orderly. However, when svs bank encounters unexpected
 217 * condition, it will fire an irq (PHASE_ERROR) to inform svs software.
 218 *
 219 * svs bank general phase-enabled order:
 220 * SVSB_PHASE_INIT01 -> SVSB_PHASE_INIT02 -> SVSB_PHASE_MON
 221 */
 222enum svsb_phase {
 223	SVSB_PHASE_ERROR = 0,
 224	SVSB_PHASE_INIT01,
 225	SVSB_PHASE_INIT02,
 226	SVSB_PHASE_MON,
 227	SVSB_PHASE_MAX,
 228};
 229
 230enum svs_reg_index {
 231	DESCHAR = 0,
 232	TEMPCHAR,
 233	DETCHAR,
 234	AGECHAR,
 235	DCCONFIG,
 236	AGECONFIG,
 237	FREQPCT30,
 238	FREQPCT74,
 239	LIMITVALS,
 240	VBOOT,
 241	DETWINDOW,
 242	CONFIG,
 243	TSCALCS,
 244	RUNCONFIG,
 245	SVSEN,
 246	INIT2VALS,
 247	DCVALUES,
 248	AGEVALUES,
 249	VOP30,
 250	VOP74,
 251	TEMP,
 252	INTSTS,
 253	INTSTSRAW,
 254	INTEN,
 255	CHKINT,
 256	CHKSHIFT,
 257	STATUS,
 258	VDESIGN30,
 259	VDESIGN74,
 260	DVT30,
 261	DVT74,
 262	AGECOUNT,
 263	SMSTATE0,
 264	SMSTATE1,
 265	CTL0,
 266	DESDETSEC,
 267	TEMPAGESEC,
 268	CTRLSPARE0,
 269	CTRLSPARE1,
 270	CTRLSPARE2,
 271	CTRLSPARE3,
 272	CORESEL,
 273	THERMINTST,
 274	INTST,
 275	THSTAGE0ST,
 276	THSTAGE1ST,
 277	THSTAGE2ST,
 278	THAHBST0,
 279	THAHBST1,
 280	SPARE0,
 281	SPARE1,
 282	SPARE2,
 283	SPARE3,
 284	THSLPEVEB,
 285	SVS_REG_MAX,
 286};
 287
 288static const u32 svs_regs_v2[] = {
 289	[DESCHAR]		= 0x00,
 290	[TEMPCHAR]		= 0x04,
 291	[DETCHAR]		= 0x08,
 292	[AGECHAR]		= 0x0c,
 293	[DCCONFIG]		= 0x10,
 294	[AGECONFIG]		= 0x14,
 295	[FREQPCT30]		= 0x18,
 296	[FREQPCT74]		= 0x1c,
 297	[LIMITVALS]		= 0x20,
 298	[VBOOT]			= 0x24,
 299	[DETWINDOW]		= 0x28,
 300	[CONFIG]		= 0x2c,
 301	[TSCALCS]		= 0x30,
 302	[RUNCONFIG]		= 0x34,
 303	[SVSEN]			= 0x38,
 304	[INIT2VALS]		= 0x3c,
 305	[DCVALUES]		= 0x40,
 306	[AGEVALUES]		= 0x44,
 307	[VOP30]			= 0x48,
 308	[VOP74]			= 0x4c,
 309	[TEMP]			= 0x50,
 310	[INTSTS]		= 0x54,
 311	[INTSTSRAW]		= 0x58,
 312	[INTEN]			= 0x5c,
 313	[CHKINT]		= 0x60,
 314	[CHKSHIFT]		= 0x64,
 315	[STATUS]		= 0x68,
 316	[VDESIGN30]		= 0x6c,
 317	[VDESIGN74]		= 0x70,
 318	[DVT30]			= 0x74,
 319	[DVT74]			= 0x78,
 320	[AGECOUNT]		= 0x7c,
 321	[SMSTATE0]		= 0x80,
 322	[SMSTATE1]		= 0x84,
 323	[CTL0]			= 0x88,
 324	[DESDETSEC]		= 0xe0,
 325	[TEMPAGESEC]		= 0xe4,
 326	[CTRLSPARE0]		= 0xf0,
 327	[CTRLSPARE1]		= 0xf4,
 328	[CTRLSPARE2]		= 0xf8,
 329	[CTRLSPARE3]		= 0xfc,
 330	[CORESEL]		= 0x300,
 331	[THERMINTST]		= 0x304,
 332	[INTST]			= 0x308,
 333	[THSTAGE0ST]		= 0x30c,
 334	[THSTAGE1ST]		= 0x310,
 335	[THSTAGE2ST]		= 0x314,
 336	[THAHBST0]		= 0x318,
 337	[THAHBST1]		= 0x31c,
 338	[SPARE0]		= 0x320,
 339	[SPARE1]		= 0x324,
 340	[SPARE2]		= 0x328,
 341	[SPARE3]		= 0x32c,
 342	[THSLPEVEB]		= 0x330,
 343};
 344
 345static const char * const svs_swid_names[SVSB_SWID_MAX] = {
 346	"SVSB_CPU_LITTLE", "SVSB_CPU_BIG", "SVSB_CCI", "SVSB_GPU"
 347};
 348
 349static const char * const svs_type_names[SVSB_TYPE_MAX] = {
 350	"", "_LOW", "_HIGH"
 351};
 352
 353enum svs_fusemap_dev {
 354	BDEV_BDES,
 355	BDEV_MDES,
 356	BDEV_MTDES,
 357	BDEV_DCBDET,
 358	BDEV_DCMDET,
 359	BDEV_MAX
 360};
 361
 362enum svs_fusemap_glb {
 363	GLB_FT_PGM,
 364	GLB_VMIN,
 365	GLB_MAX
 366};
 367
 368struct svs_fusemap {
 369	s8 index;
 370	u8 ofst;
 371};
 372
 373/**
 374 * struct svs_platform - svs platform control
 375 * @base: svs platform register base
 376 * @dev: svs platform device
 377 * @main_clk: main clock for svs bank
 378 * @banks: svs banks that svs platform supports
 379 * @rst: svs platform reset control
 380 * @efuse_max: total number of svs efuse
 381 * @tefuse_max: total number of thermal efuse
 382 * @regs: svs platform registers map
 383 * @efuse: svs efuse data received from NVMEM framework
 384 * @tefuse: thermal efuse data received from NVMEM framework
 385 * @ts_coeff: thermal sensors coefficient
 386 * @bank_max: total number of svs banks
 387 */
 388struct svs_platform {
 389	void __iomem *base;
 390	struct device *dev;
 391	struct clk *main_clk;
 392	struct svs_bank *banks;
 393	struct reset_control *rst;
 394	size_t efuse_max;
 395	size_t tefuse_max;
 396	const u32 *regs;
 397	u32 *efuse;
 398	u32 *tefuse;
 399	u32 ts_coeff;
 400	u16 bank_max;
 401};
 402
 403struct svs_platform_data {
 404	char *name;
 405	struct svs_bank *banks;
 406	bool (*efuse_parsing)(struct svs_platform *svsp, const struct svs_platform_data *pdata);
 407	int (*probe)(struct svs_platform *svsp);
 408	const struct svs_fusemap *glb_fuse_map;
 409	const u32 *regs;
 410	u32 ts_coeff;
 411	u16 bank_max;
 412};
 413
 414/**
 415 * struct svs_bank_pdata - SVS Bank immutable config parameters
 416 * @dev_fuse_map: Bank fuse map data
 417 * @buck_name: Regulator name
 418 * @tzone_name: Thermal zone name
 419 * @age_config: Bank age configuration
 420 * @ctl0: TS-x selection
 421 * @dc_config: Bank dc configuration
 422 * @int_st: Bank interrupt identification
 423 * @turn_freq_base: Reference frequency for 2-line turn point
 424 * @tzone_htemp: Thermal zone high temperature threshold
 425 * @tzone_ltemp: Thermal zone low temperature threshold
 426 * @volt_step: Bank voltage step
 427 * @volt_base: Bank voltage base
 428 * @tzone_htemp_voffset: Thermal zone high temperature voltage offset
 429 * @tzone_ltemp_voffset: Thermal zone low temperature voltage offset
 430 * @chk_shift: Bank chicken shift
 431 * @cpu_id: CPU core ID for SVS CPU bank use only
 432 * @opp_count: Bank opp count
 433 * @vboot: Voltage request for bank init01 only
 434 * @vco: Bank VCO value
 435 * @sw_id: Bank software identification
 436 * @type: SVS Bank Type (1 or 2-line) and Role (high/low)
 437 * @set_freq_pct: function pointer to set bank frequency percent table
 438 * @get_volts: function pointer to get bank voltages
 439 */
 440struct svs_bank_pdata {
 441	const struct svs_fusemap *dev_fuse_map;
 442	char *buck_name;
 443	char *tzone_name;
 444	u32 age_config;
 445	u32 ctl0;
 446	u32 dc_config;
 447	u32 int_st;
 448	u32 turn_freq_base;
 449	u32 tzone_htemp;
 450	u32 tzone_ltemp;
 451	u32 volt_step;
 452	u32 volt_base;
 453	u16 tzone_htemp_voffset;
 454	u16 tzone_ltemp_voffset;
 455	u8 chk_shift;
 456	u8 cpu_id;
 457	u8 opp_count;
 458	u8 vboot;
 459	u8 vco;
 460	u8 sw_id;
 461	u8 type;
 462
 463	/* Callbacks */
 464	void (*set_freq_pct)(struct svs_platform *svsp, struct svs_bank *svsb);
 465	void (*get_volts)(struct svs_platform *svsp, struct svs_bank *svsb);
 466};
 467
 468/**
 469 * struct svs_bank - svs bank representation
 470 * @pdata: SVS Bank immutable config parameters
 471 * @dev: bank device
 472 * @opp_dev: device for opp table/buck control
 473 * @init_completion: the timeout completion for bank init
 474 * @buck: regulator used by opp_dev
 475 * @tzd: thermal zone device for getting temperature
 476 * @lock: mutex lock to protect voltage update process
 477 * @name: bank name
 478 * @phase: bank current phase
 479 * @volt_od: bank voltage overdrive
 480 * @reg_data: bank register data in different phase for debug purpose
 481 * @pm_runtime_enabled_count: bank pm runtime enabled count
 482 * @mode_support: bank mode support
 483 * @freq_base: reference frequency for bank init
 484 * @opp_dfreq: default opp frequency table
 485 * @opp_dvolt: default opp voltage table
 486 * @freq_pct: frequency percent table for bank init
 487 * @volt: bank voltage table
 488 * @volt_flags: bank voltage flags
 489 * @vmax: bank voltage maximum
 490 * @vmin: bank voltage minimum
 491 * @age_voffset_in: bank age voltage offset
 492 * @dc_voffset_in: bank dc voltage offset
 493 * @dvt_fixed: bank dvt fixed value
 494 * @core_sel: bank selection
 495 * @temp: bank temperature
 496 * @bts: svs efuse data
 497 * @mts: svs efuse data
 498 * @bdes: svs efuse data
 499 * @mdes: svs efuse data
 500 * @mtdes: svs efuse data
 501 * @dcbdet: svs efuse data
 502 * @dcmdet: svs efuse data
 503 * @turn_pt: 2-line turn point tells which opp_volt calculated by high/low bank
 504 * @vbin_turn_pt: voltage bin turn point helps know which svsb_volt should be overridden
 505 *
 506 * Svs bank will generate suitable voltages by below general math equation
 507 * and provide these voltages to opp voltage table.
 508 *
 509 * opp_volt[i] = (volt[i] * volt_step) + volt_base;
 510 */
 511struct svs_bank {
 512	const struct svs_bank_pdata pdata;
 513	struct device *dev;
 514	struct device *opp_dev;
 515	struct completion init_completion;
 516	struct regulator *buck;
 517	struct thermal_zone_device *tzd;
 518	struct mutex lock;
 519	int pm_runtime_enabled_count;
 520	short int volt_od;
 521	char *name;
 522	enum svsb_phase phase;
 523	u32 reg_data[SVSB_PHASE_MAX][SVS_REG_MAX];
 524	u8 mode_support;
 525	u32 opp_dfreq[MAX_OPP_ENTRIES];
 526	u32 opp_dvolt[MAX_OPP_ENTRIES];
 527	u32 freq_pct[MAX_OPP_ENTRIES];
 528	u32 volt[MAX_OPP_ENTRIES];
 529	u32 volt_flags;
 530	u32 freq_base;
 531	u32 turn_pt;
 532	u32 vbin_turn_pt;
 533	u32 core_sel;
 534	u32 temp;
 535	u16 age_voffset_in;
 536	u16 dc_voffset_in;
 537	u8 dvt_fixed;
 538	u8 vmax;
 539	u8 vmin;
 540	u16 bts;
 541	u16 mts;
 542	u16 bdes;
 543	u16 mdes;
 544	u8 mtdes;
 545	u8 dcbdet;
 546	u8 dcmdet;
 547};
 548
 549static u32 percent(u32 numerator, u32 denominator)
 550{
 551	/* If not divide 1000, "numerator * 100" will have data overflow. */
 552	numerator /= 1000;
 553	denominator /= 1000;
 554
 555	return DIV_ROUND_UP(numerator * 100, denominator);
 556}
 557
 558static u32 svs_readl_relaxed(struct svs_platform *svsp, enum svs_reg_index rg_i)
 559{
 560	return readl_relaxed(svsp->base + svsp->regs[rg_i]);
 561}
 562
 563static void svs_writel_relaxed(struct svs_platform *svsp, u32 val,
 564			       enum svs_reg_index rg_i)
 565{
 566	writel_relaxed(val, svsp->base + svsp->regs[rg_i]);
 567}
 568
 569static void svs_switch_bank(struct svs_platform *svsp, struct svs_bank *svsb)
 570{
 571	svs_writel_relaxed(svsp, svsb->core_sel, CORESEL);
 572}
 573
 574static u32 svs_bank_volt_to_opp_volt(u32 svsb_volt, u32 svsb_volt_step,
 575				     u32 svsb_volt_base)
 576{
 577	return (svsb_volt * svsb_volt_step) + svsb_volt_base;
 578}
 579
 580static u32 svs_opp_volt_to_bank_volt(u32 opp_u_volt, u32 svsb_volt_step,
 581				     u32 svsb_volt_base)
 582{
 583	return (opp_u_volt - svsb_volt_base) / svsb_volt_step;
 584}
 585
 586static int svs_sync_bank_volts_from_opp(struct svs_bank *svsb)
 587{
 588	const struct svs_bank_pdata *bdata = &svsb->pdata;
 589	struct dev_pm_opp *opp;
 590	u32 i, opp_u_volt;
 591
 592	for (i = 0; i < bdata->opp_count; i++) {
 593		opp = dev_pm_opp_find_freq_exact(svsb->opp_dev,
 594						 svsb->opp_dfreq[i],
 595						 true);
 596		if (IS_ERR(opp)) {
 597			dev_err(svsb->dev, "cannot find freq = %u (%ld)\n",
 598				svsb->opp_dfreq[i], PTR_ERR(opp));
 599			return PTR_ERR(opp);
 600		}
 601
 602		opp_u_volt = dev_pm_opp_get_voltage(opp);
 603		svsb->volt[i] = svs_opp_volt_to_bank_volt(opp_u_volt,
 604							  bdata->volt_step,
 605							  bdata->volt_base);
 606		dev_pm_opp_put(opp);
 607	}
 608
 609	return 0;
 610}
 611
 612static int svs_adjust_pm_opp_volts(struct svs_bank *svsb)
 613{
 614	int ret = -EPERM, tzone_temp = 0;
 615	const struct svs_bank_pdata *bdata = &svsb->pdata;
 616	u32 i, svsb_volt, opp_volt, temp_voffset = 0, opp_start, opp_stop;
 617
 618	mutex_lock(&svsb->lock);
 619
 620	/*
 621	 * 2-line bank updates its corresponding opp volts.
 622	 * 1-line bank updates all opp volts.
 623	 */
 624	if (bdata->type == SVSB_TYPE_HIGH) {
 625		opp_start = 0;
 626		opp_stop = svsb->turn_pt;
 627	} else if (bdata->type == SVSB_TYPE_LOW) {
 628		opp_start = svsb->turn_pt;
 629		opp_stop = bdata->opp_count;
 630	} else {
 631		opp_start = 0;
 632		opp_stop = bdata->opp_count;
 633	}
 634
 635	/* Get thermal effect */
 636	if (!IS_ERR_OR_NULL(svsb->tzd)) {
 637		ret = thermal_zone_get_temp(svsb->tzd, &tzone_temp);
 638		if (ret || (svsb->temp > SVSB_TEMP_UPPER_BOUND &&
 639			    svsb->temp < SVSB_TEMP_LOWER_BOUND)) {
 640			dev_err(svsb->dev, "%s: %d (0x%x), run default volts\n",
 641				bdata->tzone_name, ret, svsb->temp);
 642			svsb->phase = SVSB_PHASE_ERROR;
 643		}
 644
 645		if (tzone_temp >= bdata->tzone_htemp)
 646			temp_voffset += bdata->tzone_htemp_voffset;
 647		else if (tzone_temp <= bdata->tzone_ltemp)
 648			temp_voffset += bdata->tzone_ltemp_voffset;
 649
 650		/* 2-line bank update all opp volts when running mon mode */
 651		if (svsb->phase == SVSB_PHASE_MON && (bdata->type == SVSB_TYPE_HIGH ||
 652						      bdata->type == SVSB_TYPE_LOW)) {
 653			opp_start = 0;
 654			opp_stop = bdata->opp_count;
 655		}
 656	}
 657
 658	/* vmin <= svsb_volt (opp_volt) <= default opp voltage */
 659	for (i = opp_start; i < opp_stop; i++) {
 660		switch (svsb->phase) {
 661		case SVSB_PHASE_ERROR:
 662			opp_volt = svsb->opp_dvolt[i];
 663			break;
 664		case SVSB_PHASE_INIT01:
 665			/* do nothing */
 666			goto unlock_mutex;
 667		case SVSB_PHASE_INIT02:
 668		case SVSB_PHASE_MON:
 669			svsb_volt = max(svsb->volt[i] + temp_voffset, svsb->vmin);
 670			opp_volt = svs_bank_volt_to_opp_volt(svsb_volt,
 671							     bdata->volt_step,
 672							     bdata->volt_base);
 673			break;
 674		default:
 675			dev_err(svsb->dev, "unknown phase: %u\n", svsb->phase);
 676			ret = -EINVAL;
 677			goto unlock_mutex;
 678		}
 679
 680		opp_volt = min(opp_volt, svsb->opp_dvolt[i]);
 681		ret = dev_pm_opp_adjust_voltage(svsb->opp_dev,
 682						svsb->opp_dfreq[i],
 683						opp_volt, opp_volt,
 684						svsb->opp_dvolt[i]);
 685		if (ret) {
 686			dev_err(svsb->dev, "set %uuV fail: %d\n",
 687				opp_volt, ret);
 688			goto unlock_mutex;
 689		}
 690	}
 691
 692unlock_mutex:
 693	mutex_unlock(&svsb->lock);
 694
 695	return ret;
 696}
 697
 698static void svs_bank_disable_and_restore_default_volts(struct svs_platform *svsp,
 699						       struct svs_bank *svsb)
 700{
 701	unsigned long flags;
 702
 703	if (svsb->mode_support == SVSB_MODE_ALL_DISABLE)
 704		return;
 705
 706	spin_lock_irqsave(&svs_lock, flags);
 707	svs_switch_bank(svsp, svsb);
 708	svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN);
 709	svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS);
 710	spin_unlock_irqrestore(&svs_lock, flags);
 711
 712	svsb->phase = SVSB_PHASE_ERROR;
 713	svs_adjust_pm_opp_volts(svsb);
 714}
 715
 716#ifdef CONFIG_DEBUG_FS
 717static int svs_dump_debug_show(struct seq_file *m, void *p)
 718{
 719	struct svs_platform *svsp = (struct svs_platform *)m->private;
 720	struct svs_bank *svsb;
 721	unsigned long svs_reg_addr;
 722	u32 idx, i, j, bank_id;
 723
 724	for (i = 0; i < svsp->efuse_max; i++)
 725		if (svsp->efuse && svsp->efuse[i])
 726			seq_printf(m, "M_HW_RES%d = 0x%08x\n",
 727				   i, svsp->efuse[i]);
 728
 729	for (i = 0; i < svsp->tefuse_max; i++)
 730		if (svsp->tefuse)
 731			seq_printf(m, "THERMAL_EFUSE%d = 0x%08x\n",
 732				   i, svsp->tefuse[i]);
 733
 734	for (bank_id = 0, idx = 0; idx < svsp->bank_max; idx++, bank_id++) {
 735		svsb = &svsp->banks[idx];
 736
 737		for (i = SVSB_PHASE_INIT01; i <= SVSB_PHASE_MON; i++) {
 738			seq_printf(m, "Bank_number = %u\n", bank_id);
 739
 740			if (i == SVSB_PHASE_INIT01 || i == SVSB_PHASE_INIT02)
 741				seq_printf(m, "mode = init%d\n", i);
 742			else if (i == SVSB_PHASE_MON)
 743				seq_puts(m, "mode = mon\n");
 744			else
 745				seq_puts(m, "mode = error\n");
 746
 747			for (j = DESCHAR; j < SVS_REG_MAX; j++) {
 748				svs_reg_addr = (unsigned long)(svsp->base +
 749							       svsp->regs[j]);
 750				seq_printf(m, "0x%08lx = 0x%08x\n",
 751					   svs_reg_addr, svsb->reg_data[i][j]);
 752			}
 753		}
 754	}
 755
 756	return 0;
 757}
 758
 759debug_fops_ro(dump);
 760
 761static int svs_enable_debug_show(struct seq_file *m, void *v)
 762{
 763	struct svs_bank *svsb = (struct svs_bank *)m->private;
 764
 765	switch (svsb->phase) {
 766	case SVSB_PHASE_ERROR:
 767		seq_puts(m, "disabled\n");
 768		break;
 769	case SVSB_PHASE_INIT01:
 770		seq_puts(m, "init1\n");
 771		break;
 772	case SVSB_PHASE_INIT02:
 773		seq_puts(m, "init2\n");
 774		break;
 775	case SVSB_PHASE_MON:
 776		seq_puts(m, "mon mode\n");
 777		break;
 778	default:
 779		seq_puts(m, "unknown\n");
 780		break;
 781	}
 782
 783	return 0;
 784}
 785
 786static ssize_t svs_enable_debug_write(struct file *filp,
 787				      const char __user *buffer,
 788				      size_t count, loff_t *pos)
 789{
 790	struct svs_bank *svsb = file_inode(filp)->i_private;
 791	struct svs_platform *svsp = dev_get_drvdata(svsb->dev);
 792	int enabled, ret;
 793	char *buf __free(kfree) = NULL;
 794
 795	if (count >= PAGE_SIZE)
 796		return -EINVAL;
 797
 798	buf = (char *)memdup_user_nul(buffer, count);
 799	if (IS_ERR(buf))
 800		return PTR_ERR(buf);
 801
 802	ret = kstrtoint(buf, 10, &enabled);
 803	if (ret)
 804		return ret;
 805
 806	if (!enabled) {
 807		svs_bank_disable_and_restore_default_volts(svsp, svsb);
 808		svsb->mode_support = SVSB_MODE_ALL_DISABLE;
 809	}
 810
 811	return count;
 812}
 813
 814debug_fops_rw(enable);
 815
 816static int svs_status_debug_show(struct seq_file *m, void *v)
 817{
 818	struct svs_bank *svsb = (struct svs_bank *)m->private;
 819	struct dev_pm_opp *opp;
 820	int tzone_temp = 0, ret;
 821	u32 i;
 822
 823	ret = thermal_zone_get_temp(svsb->tzd, &tzone_temp);
 824	if (ret)
 825		seq_printf(m, "%s: temperature ignore, vbin_turn_pt = %u, turn_pt = %u\n",
 826			   svsb->name, svsb->vbin_turn_pt, svsb->turn_pt);
 827	else
 828		seq_printf(m, "%s: temperature = %d, vbin_turn_pt = %u, turn_pt = %u\n",
 829			   svsb->name, tzone_temp, svsb->vbin_turn_pt,
 830			   svsb->turn_pt);
 831
 832	for (i = 0; i < svsb->pdata.opp_count; i++) {
 833		opp = dev_pm_opp_find_freq_exact(svsb->opp_dev,
 834						 svsb->opp_dfreq[i], true);
 835		if (IS_ERR(opp)) {
 836			seq_printf(m, "%s: cannot find freq = %u (%ld)\n",
 837				   svsb->name, svsb->opp_dfreq[i],
 838				   PTR_ERR(opp));
 839			return PTR_ERR(opp);
 840		}
 841
 842		seq_printf(m, "opp_freq[%02u]: %u, opp_volt[%02u]: %lu, ",
 843			   i, svsb->opp_dfreq[i], i,
 844			   dev_pm_opp_get_voltage(opp));
 845		seq_printf(m, "svsb_volt[%02u]: 0x%x, freq_pct[%02u]: %u\n",
 846			   i, svsb->volt[i], i, svsb->freq_pct[i]);
 847		dev_pm_opp_put(opp);
 848	}
 849
 850	return 0;
 851}
 852
 853debug_fops_ro(status);
 854
 855static int svs_create_debug_cmds(struct svs_platform *svsp)
 856{
 857	struct svs_bank *svsb;
 858	struct dentry *svs_dir, *svsb_dir, *file_entry;
 859	const char *d = "/sys/kernel/debug/svs";
 860	u32 i, idx;
 861
 862	struct svs_dentry {
 863		const char *name;
 864		const struct file_operations *fops;
 865	};
 866
 867	struct svs_dentry svs_entries[] = {
 868		svs_dentry_data(dump),
 869	};
 870
 871	struct svs_dentry svsb_entries[] = {
 872		svs_dentry_data(enable),
 873		svs_dentry_data(status),
 874	};
 875
 876	svs_dir = debugfs_create_dir("svs", NULL);
 877	if (IS_ERR(svs_dir)) {
 878		dev_err(svsp->dev, "cannot create %s: %ld\n",
 879			d, PTR_ERR(svs_dir));
 880		return PTR_ERR(svs_dir);
 881	}
 882
 883	for (i = 0; i < ARRAY_SIZE(svs_entries); i++) {
 884		file_entry = debugfs_create_file(svs_entries[i].name, 0664,
 885						 svs_dir, svsp,
 886						 svs_entries[i].fops);
 887		if (IS_ERR(file_entry)) {
 888			dev_err(svsp->dev, "cannot create %s/%s: %ld\n",
 889				d, svs_entries[i].name, PTR_ERR(file_entry));
 890			return PTR_ERR(file_entry);
 891		}
 892	}
 893
 894	for (idx = 0; idx < svsp->bank_max; idx++) {
 895		svsb = &svsp->banks[idx];
 896
 897		if (svsb->mode_support == SVSB_MODE_ALL_DISABLE)
 898			continue;
 899
 900		svsb_dir = debugfs_create_dir(svsb->name, svs_dir);
 901		if (IS_ERR(svsb_dir)) {
 902			dev_err(svsp->dev, "cannot create %s/%s: %ld\n",
 903				d, svsb->name, PTR_ERR(svsb_dir));
 904			return PTR_ERR(svsb_dir);
 905		}
 906
 907		for (i = 0; i < ARRAY_SIZE(svsb_entries); i++) {
 908			file_entry = debugfs_create_file(svsb_entries[i].name,
 909							 0664, svsb_dir, svsb,
 910							 svsb_entries[i].fops);
 911			if (IS_ERR(file_entry)) {
 912				dev_err(svsp->dev, "no %s/%s/%s?: %ld\n",
 913					d, svsb->name, svsb_entries[i].name,
 914					PTR_ERR(file_entry));
 915				return PTR_ERR(file_entry);
 916			}
 917		}
 918	}
 919
 920	return 0;
 921}
 922#endif /* CONFIG_DEBUG_FS */
 923
 924static u32 interpolate(u32 f0, u32 f1, u32 v0, u32 v1, u32 fx)
 925{
 926	u32 vx;
 927
 928	if (v0 == v1 || f0 == f1)
 929		return v0;
 930
 931	/* *100 to have decimal fraction factor */
 932	vx = (v0 * 100) - ((((v0 - v1) * 100) / (f0 - f1)) * (f0 - fx));
 933
 934	return DIV_ROUND_UP(vx, 100);
 935}
 936
 937static void svs_get_bank_volts_v3(struct svs_platform *svsp, struct svs_bank *svsb)
 938{
 939	const struct svs_bank_pdata *bdata = &svsb->pdata;
 940	u32 i, j, *vop, vop74, vop30, turn_pt = svsb->turn_pt;
 941	u32 b_sft, shift_byte = 0, opp_start = 0, opp_stop = 0;
 942	u32 middle_index = (bdata->opp_count / 2);
 943
 944	if (svsb->phase == SVSB_PHASE_MON &&
 945	    svsb->volt_flags & SVSB_MON_VOLT_IGNORE)
 946		return;
 947
 948	vop74 = svs_readl_relaxed(svsp, VOP74);
 949	vop30 = svs_readl_relaxed(svsp, VOP30);
 950
 951	/* Target is to set svsb->volt[] by algorithm */
 952	if (turn_pt < middle_index) {
 953		if (bdata->type == SVSB_TYPE_HIGH) {
 954			/* volt[0] ~ volt[turn_pt - 1] */
 955			for (i = 0; i < turn_pt; i++) {
 956				b_sft = BITS8 * (shift_byte % REG_BYTES);
 957				vop = (shift_byte < REG_BYTES) ? &vop30 :
 958								 &vop74;
 959				svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0);
 960				shift_byte++;
 961			}
 962		} else if (bdata->type == SVSB_TYPE_LOW) {
 963			/* volt[turn_pt] + volt[j] ~ volt[opp_count - 1] */
 964			j = bdata->opp_count - 7;
 965			svsb->volt[turn_pt] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, vop30);
 966			shift_byte++;
 967			for (i = j; i < bdata->opp_count; i++) {
 968				b_sft = BITS8 * (shift_byte % REG_BYTES);
 969				vop = (shift_byte < REG_BYTES) ? &vop30 :
 970								 &vop74;
 971				svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0);
 972				shift_byte++;
 973			}
 974
 975			/* volt[turn_pt + 1] ~ volt[j - 1] by interpolate */
 976			for (i = turn_pt + 1; i < j; i++)
 977				svsb->volt[i] = interpolate(svsb->freq_pct[turn_pt],
 978							    svsb->freq_pct[j],
 979							    svsb->volt[turn_pt],
 980							    svsb->volt[j],
 981							    svsb->freq_pct[i]);
 982		}
 983	} else {
 984		if (bdata->type == SVSB_TYPE_HIGH) {
 985			/* volt[0] + volt[j] ~ volt[turn_pt - 1] */
 986			j = turn_pt - 7;
 987			svsb->volt[0] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, vop30);
 988			shift_byte++;
 989			for (i = j; i < turn_pt; i++) {
 990				b_sft = BITS8 * (shift_byte % REG_BYTES);
 991				vop = (shift_byte < REG_BYTES) ? &vop30 :
 992								 &vop74;
 993				svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0);
 994				shift_byte++;
 995			}
 996
 997			/* volt[1] ~ volt[j - 1] by interpolate */
 998			for (i = 1; i < j; i++)
 999				svsb->volt[i] = interpolate(svsb->freq_pct[0],
1000							    svsb->freq_pct[j],
1001							    svsb->volt[0],
1002							    svsb->volt[j],
1003							    svsb->freq_pct[i]);
1004		} else if (bdata->type == SVSB_TYPE_LOW) {
1005			/* volt[turn_pt] ~ volt[opp_count - 1] */
1006			for (i = turn_pt; i < bdata->opp_count; i++) {
1007				b_sft = BITS8 * (shift_byte % REG_BYTES);
1008				vop = (shift_byte < REG_BYTES) ? &vop30 :
1009								 &vop74;
1010				svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0);
1011				shift_byte++;
1012			}
1013		}
1014	}
1015
1016	if (bdata->type == SVSB_TYPE_HIGH) {
1017		opp_start = 0;
1018		opp_stop = svsb->turn_pt;
1019	} else if (bdata->type == SVSB_TYPE_LOW) {
1020		opp_start = svsb->turn_pt;
1021		opp_stop = bdata->opp_count;
1022	}
1023
1024	for (i = opp_start; i < opp_stop; i++)
1025		if (svsb->volt_flags & SVSB_REMOVE_DVTFIXED_VOLT)
1026			svsb->volt[i] -= svsb->dvt_fixed;
1027
1028	/* For voltage bin support */
1029	if (svsb->opp_dfreq[0] > svsb->freq_base) {
1030		svsb->volt[0] = svs_opp_volt_to_bank_volt(svsb->opp_dvolt[0],
1031							  bdata->volt_step,
1032							  bdata->volt_base);
1033
1034		/* Find voltage bin turn point */
1035		for (i = 0; i < bdata->opp_count; i++) {
1036			if (svsb->opp_dfreq[i] <= svsb->freq_base) {
1037				svsb->vbin_turn_pt = i;
1038				break;
1039			}
1040		}
1041
1042		/* Override svs bank voltages */
1043		for (i = 1; i < svsb->vbin_turn_pt; i++)
1044			svsb->volt[i] = interpolate(svsb->freq_pct[0],
1045						    svsb->freq_pct[svsb->vbin_turn_pt],
1046						    svsb->volt[0],
1047						    svsb->volt[svsb->vbin_turn_pt],
1048						    svsb->freq_pct[i]);
1049	}
1050}
1051
1052static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp, struct svs_bank *svsb)
1053{
1054	const struct svs_bank_pdata *bdata = &svsb->pdata;
1055	u32 i, j, *freq_pct, freq_pct74 = 0, freq_pct30 = 0;
1056	u32 b_sft, shift_byte = 0, turn_pt;
1057	u32 middle_index = (bdata->opp_count / 2);
1058
1059	for (i = 0; i < bdata->opp_count; i++) {
1060		if (svsb->opp_dfreq[i] <= bdata->turn_freq_base) {
1061			svsb->turn_pt = i;
1062			break;
1063		}
1064	}
1065
1066	turn_pt = svsb->turn_pt;
1067
1068	/* Target is to fill out freq_pct74 / freq_pct30 by algorithm */
1069	if (turn_pt < middle_index) {
1070		if (bdata->type == SVSB_TYPE_HIGH) {
1071			/*
1072			 * If we don't handle this situation,
1073			 * SVSB_TYPE_HIGH's FREQPCT74 / FREQPCT30 would keep "0"
1074			 * and this leads SVSB_TYPE_LOW to work abnormally.
1075			 */
1076			if (turn_pt == 0)
1077				freq_pct30 = svsb->freq_pct[0];
1078
1079			/* freq_pct[0] ~ freq_pct[turn_pt - 1] */
1080			for (i = 0; i < turn_pt; i++) {
1081				b_sft = BITS8 * (shift_byte % REG_BYTES);
1082				freq_pct = (shift_byte < REG_BYTES) ?
1083					   &freq_pct30 : &freq_pct74;
1084				*freq_pct |= (svsb->freq_pct[i] << b_sft);
1085				shift_byte++;
1086			}
1087		} else if (bdata->type == SVSB_TYPE_LOW) {
1088			/*
1089			 * freq_pct[turn_pt] +
1090			 * freq_pct[opp_count - 7] ~ freq_pct[opp_count -1]
1091			 */
1092			freq_pct30 = svsb->freq_pct[turn_pt];
1093			shift_byte++;
1094			j = bdata->opp_count - 7;
1095			for (i = j; i < bdata->opp_count; i++) {
1096				b_sft = BITS8 * (shift_byte % REG_BYTES);
1097				freq_pct = (shift_byte < REG_BYTES) ?
1098					   &freq_pct30 : &freq_pct74;
1099				*freq_pct |= (svsb->freq_pct[i] << b_sft);
1100				shift_byte++;
1101			}
1102		}
1103	} else {
1104		if (bdata->type == SVSB_TYPE_HIGH) {
1105			/*
1106			 * freq_pct[0] +
1107			 * freq_pct[turn_pt - 7] ~ freq_pct[turn_pt - 1]
1108			 */
1109			freq_pct30 = svsb->freq_pct[0];
1110			shift_byte++;
1111			j = turn_pt - 7;
1112			for (i = j; i < turn_pt; i++) {
1113				b_sft = BITS8 * (shift_byte % REG_BYTES);
1114				freq_pct = (shift_byte < REG_BYTES) ?
1115					   &freq_pct30 : &freq_pct74;
1116				*freq_pct |= (svsb->freq_pct[i] << b_sft);
1117				shift_byte++;
1118			}
1119		} else if (bdata->type == SVSB_TYPE_LOW) {
1120			/* freq_pct[turn_pt] ~ freq_pct[opp_count - 1] */
1121			for (i = turn_pt; i < bdata->opp_count; i++) {
1122				b_sft = BITS8 * (shift_byte % REG_BYTES);
1123				freq_pct = (shift_byte < REG_BYTES) ?
1124					   &freq_pct30 : &freq_pct74;
1125				*freq_pct |= (svsb->freq_pct[i] << b_sft);
1126				shift_byte++;
1127			}
1128		}
1129	}
1130
1131	svs_writel_relaxed(svsp, freq_pct74, FREQPCT74);
1132	svs_writel_relaxed(svsp, freq_pct30, FREQPCT30);
1133}
1134
1135static void svs_get_bank_volts_v2(struct svs_platform *svsp, struct svs_bank *svsb)
1136{
1137	const struct svs_bank_pdata *bdata = &svsb->pdata;
1138	u32 temp, i;
1139
1140	temp = svs_readl_relaxed(svsp, VOP74);
1141	svsb->volt[14] = FIELD_GET(SVSB_VOPS_FLD_VOP3_7, temp);
1142	svsb->volt[12] = FIELD_GET(SVSB_VOPS_FLD_VOP2_6, temp);
1143	svsb->volt[10] = FIELD_GET(SVSB_VOPS_FLD_VOP1_5, temp);
1144	svsb->volt[8] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, temp);
1145
1146	temp = svs_readl_relaxed(svsp, VOP30);
1147	svsb->volt[6] = FIELD_GET(SVSB_VOPS_FLD_VOP3_7, temp);
1148	svsb->volt[4] = FIELD_GET(SVSB_VOPS_FLD_VOP2_6, temp);
1149	svsb->volt[2] = FIELD_GET(SVSB_VOPS_FLD_VOP1_5, temp);
1150	svsb->volt[0] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, temp);
1151
1152	for (i = 0; i <= 12; i += 2)
1153		svsb->volt[i + 1] = interpolate(svsb->freq_pct[i],
1154						svsb->freq_pct[i + 2],
1155						svsb->volt[i],
1156						svsb->volt[i + 2],
1157						svsb->freq_pct[i + 1]);
1158
1159	svsb->volt[15] = interpolate(svsb->freq_pct[12],
1160				     svsb->freq_pct[14],
1161				     svsb->volt[12],
1162				     svsb->volt[14],
1163				     svsb->freq_pct[15]);
1164
1165	for (i = 0; i < bdata->opp_count; i++)
1166		svsb->volt[i] += svsb->volt_od;
1167
1168	/* For voltage bin support */
1169	if (svsb->opp_dfreq[0] > svsb->freq_base) {
1170		svsb->volt[0] = svs_opp_volt_to_bank_volt(svsb->opp_dvolt[0],
1171							  bdata->volt_step,
1172							  bdata->volt_base);
1173
1174		/* Find voltage bin turn point */
1175		for (i = 0; i < bdata->opp_count; i++) {
1176			if (svsb->opp_dfreq[i] <= svsb->freq_base) {
1177				svsb->vbin_turn_pt = i;
1178				break;
1179			}
1180		}
1181
1182		/* Override svs bank voltages */
1183		for (i = 1; i < svsb->vbin_turn_pt; i++)
1184			svsb->volt[i] = interpolate(svsb->freq_pct[0],
1185						    svsb->freq_pct[svsb->vbin_turn_pt],
1186						    svsb->volt[0],
1187						    svsb->volt[svsb->vbin_turn_pt],
1188						    svsb->freq_pct[i]);
1189	}
1190}
1191
1192static void svs_set_bank_freq_pct_v2(struct svs_platform *svsp, struct svs_bank *svsb)
1193{
1194	u32 freqpct74_val, freqpct30_val;
1195
1196	freqpct74_val = FIELD_PREP(SVSB_FREQPCTS_FLD_PCT0_4, svsb->freq_pct[8]) |
1197			FIELD_PREP(SVSB_FREQPCTS_FLD_PCT1_5, svsb->freq_pct[10]) |
1198			FIELD_PREP(SVSB_FREQPCTS_FLD_PCT2_6, svsb->freq_pct[12]) |
1199			FIELD_PREP(SVSB_FREQPCTS_FLD_PCT3_7, svsb->freq_pct[14]);
1200
1201	freqpct30_val = FIELD_PREP(SVSB_FREQPCTS_FLD_PCT0_4, svsb->freq_pct[0]) |
1202			FIELD_PREP(SVSB_FREQPCTS_FLD_PCT1_5, svsb->freq_pct[2]) |
1203			FIELD_PREP(SVSB_FREQPCTS_FLD_PCT2_6, svsb->freq_pct[4]) |
1204			FIELD_PREP(SVSB_FREQPCTS_FLD_PCT3_7, svsb->freq_pct[6]);
1205
1206	svs_writel_relaxed(svsp, freqpct74_val, FREQPCT74);
1207	svs_writel_relaxed(svsp, freqpct30_val, FREQPCT30);
1208}
1209
1210static void svs_set_bank_phase(struct svs_platform *svsp,
1211			       unsigned int bank_idx,
1212			       enum svsb_phase target_phase)
1213{
1214	struct svs_bank *svsb = &svsp->banks[bank_idx];
1215	const struct svs_bank_pdata *bdata = &svsb->pdata;
1216	u32 des_char, temp_char, det_char, limit_vals, init2vals, ts_calcs;
1217
1218	svs_switch_bank(svsp, svsb);
1219
1220	des_char = FIELD_PREP(SVSB_DESCHAR_FLD_BDES, svsb->bdes) |
1221		   FIELD_PREP(SVSB_DESCHAR_FLD_MDES, svsb->mdes);
1222	svs_writel_relaxed(svsp, des_char, DESCHAR);
1223
1224	temp_char = FIELD_PREP(SVSB_TEMPCHAR_FLD_VCO, bdata->vco) |
1225		    FIELD_PREP(SVSB_TEMPCHAR_FLD_MTDES, svsb->mtdes) |
1226		    FIELD_PREP(SVSB_TEMPCHAR_FLD_DVT_FIXED, svsb->dvt_fixed);
1227	svs_writel_relaxed(svsp, temp_char, TEMPCHAR);
1228
1229	det_char = FIELD_PREP(SVSB_DETCHAR_FLD_DCBDET, svsb->dcbdet) |
1230		   FIELD_PREP(SVSB_DETCHAR_FLD_DCMDET, svsb->dcmdet);
1231	svs_writel_relaxed(svsp, det_char, DETCHAR);
1232
1233	svs_writel_relaxed(svsp, bdata->dc_config, DCCONFIG);
1234	svs_writel_relaxed(svsp, bdata->age_config, AGECONFIG);
1235	svs_writel_relaxed(svsp, SVSB_RUNCONFIG_DEFAULT, RUNCONFIG);
1236
1237	bdata->set_freq_pct(svsp, svsb);
1238
1239	limit_vals = FIELD_PREP(SVSB_LIMITVALS_FLD_DTLO, SVSB_VAL_DTLO) |
1240		     FIELD_PREP(SVSB_LIMITVALS_FLD_DTHI, SVSB_VAL_DTHI) |
1241		     FIELD_PREP(SVSB_LIMITVALS_FLD_VMIN, svsb->vmin) |
1242		     FIELD_PREP(SVSB_LIMITVALS_FLD_VMAX, svsb->vmax);
1243	svs_writel_relaxed(svsp, limit_vals, LIMITVALS);
1244
1245	svs_writel_relaxed(svsp, SVSB_DET_WINDOW, DETWINDOW);
1246	svs_writel_relaxed(svsp, SVSB_DET_MAX, CONFIG);
1247	svs_writel_relaxed(svsp, bdata->chk_shift, CHKSHIFT);
1248	svs_writel_relaxed(svsp, bdata->ctl0, CTL0);
1249	svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS);
1250
1251	switch (target_phase) {
1252	case SVSB_PHASE_INIT01:
1253		svs_writel_relaxed(svsp, bdata->vboot, VBOOT);
1254		svs_writel_relaxed(svsp, SVSB_INTEN_INIT0x, INTEN);
1255		svs_writel_relaxed(svsp, SVSB_PTPEN_INIT01, SVSEN);
1256		break;
1257	case SVSB_PHASE_INIT02:
1258		init2vals = FIELD_PREP(SVSB_INIT2VALS_FLD_AGEVOFFSETIN, svsb->age_voffset_in) |
1259			    FIELD_PREP(SVSB_INIT2VALS_FLD_DCVOFFSETIN, svsb->dc_voffset_in);
1260		svs_writel_relaxed(svsp, SVSB_INTEN_INIT0x, INTEN);
1261		svs_writel_relaxed(svsp, init2vals, INIT2VALS);
1262		svs_writel_relaxed(svsp, SVSB_PTPEN_INIT02, SVSEN);
1263		break;
1264	case SVSB_PHASE_MON:
1265		ts_calcs = FIELD_PREP(SVSB_TSCALCS_FLD_BTS, svsb->bts) |
1266			   FIELD_PREP(SVSB_TSCALCS_FLD_MTS, svsb->mts);
1267		svs_writel_relaxed(svsp, ts_calcs, TSCALCS);
1268		svs_writel_relaxed(svsp, SVSB_INTEN_MONVOPEN, INTEN);
1269		svs_writel_relaxed(svsp, SVSB_PTPEN_MON, SVSEN);
1270		break;
1271	default:
1272		dev_err(svsb->dev, "requested unknown target phase: %u\n",
1273			target_phase);
1274		break;
1275	}
1276}
1277
1278static inline void svs_save_bank_register_data(struct svs_platform *svsp,
1279					       unsigned short bank_idx,
1280					       enum svsb_phase phase)
1281{
1282	struct svs_bank *svsb = &svsp->banks[bank_idx];
1283	enum svs_reg_index rg_i;
1284
1285	for (rg_i = DESCHAR; rg_i < SVS_REG_MAX; rg_i++)
1286		svsb->reg_data[phase][rg_i] = svs_readl_relaxed(svsp, rg_i);
1287}
1288
1289static inline void svs_error_isr_handler(struct svs_platform *svsp,
1290					 unsigned short bank_idx)
1291{
1292	struct svs_bank *svsb = &svsp->banks[bank_idx];
1293
1294	dev_err(svsb->dev, "%s: CORESEL = 0x%08x\n",
1295		__func__, svs_readl_relaxed(svsp, CORESEL));
1296	dev_err(svsb->dev, "SVSEN = 0x%08x, INTSTS = 0x%08x\n",
1297		svs_readl_relaxed(svsp, SVSEN),
1298		svs_readl_relaxed(svsp, INTSTS));
1299	dev_err(svsb->dev, "SMSTATE0 = 0x%08x, SMSTATE1 = 0x%08x\n",
1300		svs_readl_relaxed(svsp, SMSTATE0),
1301		svs_readl_relaxed(svsp, SMSTATE1));
1302	dev_err(svsb->dev, "TEMP = 0x%08x\n", svs_readl_relaxed(svsp, TEMP));
1303
1304	svs_save_bank_register_data(svsp, bank_idx, SVSB_PHASE_ERROR);
1305
1306	svsb->phase = SVSB_PHASE_ERROR;
1307	svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN);
1308	svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS);
1309}
1310
1311static inline void svs_init01_isr_handler(struct svs_platform *svsp,
1312					  unsigned short bank_idx)
1313{
1314	struct svs_bank *svsb = &svsp->banks[bank_idx];
1315	u32 val;
1316
1317	dev_info(svsb->dev, "%s: VDN74~30:0x%08x~0x%08x, DC:0x%08x\n",
1318		 __func__, svs_readl_relaxed(svsp, VDESIGN74),
1319		 svs_readl_relaxed(svsp, VDESIGN30),
1320		 svs_readl_relaxed(svsp, DCVALUES));
1321
1322	svs_save_bank_register_data(svsp, bank_idx, SVSB_PHASE_INIT01);
1323
1324	svsb->phase = SVSB_PHASE_INIT01;
1325	val = ~(svs_readl_relaxed(svsp, DCVALUES) & GENMASK(15, 0)) + 1;
1326	svsb->dc_voffset_in = val & GENMASK(15, 0);
1327	if (svsb->volt_flags & SVSB_INIT01_VOLT_IGNORE ||
1328	    (svsb->dc_voffset_in & SVSB_DC_SIGNED_BIT &&
1329	     svsb->volt_flags & SVSB_INIT01_VOLT_INC_ONLY))
1330		svsb->dc_voffset_in = 0;
1331
1332	svsb->age_voffset_in = svs_readl_relaxed(svsp, AGEVALUES) &
1333			       GENMASK(15, 0);
1334
1335	svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN);
1336	svs_writel_relaxed(svsp, SVSB_INTSTS_F0_COMPLETE, INTSTS);
1337	svsb->core_sel &= ~SVSB_DET_CLK_EN;
1338}
1339
1340static inline void svs_init02_isr_handler(struct svs_platform *svsp,
1341					  unsigned short bank_idx)
1342{
1343	struct svs_bank *svsb = &svsp->banks[bank_idx];
1344	const struct svs_bank_pdata *bdata = &svsb->pdata;
1345
1346	dev_info(svsb->dev, "%s: VOP74~30:0x%08x~0x%08x, DC:0x%08x\n",
1347		 __func__, svs_readl_relaxed(svsp, VOP74),
1348		 svs_readl_relaxed(svsp, VOP30),
1349		 svs_readl_relaxed(svsp, DCVALUES));
1350
1351	svs_save_bank_register_data(svsp, bank_idx, SVSB_PHASE_INIT02);
1352
1353	svsb->phase = SVSB_PHASE_INIT02;
1354	bdata->get_volts(svsp, svsb);
1355
1356	svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN);
1357	svs_writel_relaxed(svsp, SVSB_INTSTS_F0_COMPLETE, INTSTS);
1358}
1359
1360static inline void svs_mon_mode_isr_handler(struct svs_platform *svsp,
1361					    unsigned short bank_idx)
1362{
1363	struct svs_bank *svsb = &svsp->banks[bank_idx];
1364	const struct svs_bank_pdata *bdata = &svsb->pdata;
1365
1366	svs_save_bank_register_data(svsp, bank_idx, SVSB_PHASE_MON);
1367
1368	svsb->phase = SVSB_PHASE_MON;
1369	bdata->get_volts(svsp, svsb);
1370
1371	svsb->temp = svs_readl_relaxed(svsp, TEMP) & GENMASK(7, 0);
1372	svs_writel_relaxed(svsp, SVSB_INTSTS_FLD_MONVOP, INTSTS);
1373}
1374
1375static irqreturn_t svs_isr(int irq, void *data)
1376{
1377	struct svs_platform *svsp = data;
1378	const struct svs_bank_pdata *bdata;
1379	struct svs_bank *svsb = NULL;
1380	unsigned long flags;
1381	u32 idx, int_sts, svs_en;
1382
1383	for (idx = 0; idx < svsp->bank_max; idx++) {
1384		svsb = &svsp->banks[idx];
1385		bdata = &svsb->pdata;
1386		WARN(!svsb, "%s: svsb(%s) is null", __func__, svsb->name);
1387
1388		spin_lock_irqsave(&svs_lock, flags);
1389
1390		/* Find out which svs bank fires interrupt */
1391		if (bdata->int_st & svs_readl_relaxed(svsp, INTST)) {
1392			spin_unlock_irqrestore(&svs_lock, flags);
1393			continue;
1394		}
1395
1396		svs_switch_bank(svsp, svsb);
1397		int_sts = svs_readl_relaxed(svsp, INTSTS);
1398		svs_en = svs_readl_relaxed(svsp, SVSEN);
1399
1400		if (int_sts == SVSB_INTSTS_F0_COMPLETE &&
1401		    svs_en == SVSB_PTPEN_INIT01)
1402			svs_init01_isr_handler(svsp, idx);
1403		else if (int_sts == SVSB_INTSTS_F0_COMPLETE &&
1404			 svs_en == SVSB_PTPEN_INIT02)
1405			svs_init02_isr_handler(svsp, idx);
1406		else if (int_sts & SVSB_INTSTS_FLD_MONVOP)
1407			svs_mon_mode_isr_handler(svsp, idx);
1408		else
1409			svs_error_isr_handler(svsp, idx);
1410
1411		spin_unlock_irqrestore(&svs_lock, flags);
1412		break;
1413	}
1414
1415	svs_adjust_pm_opp_volts(svsb);
1416
1417	if (svsb->phase == SVSB_PHASE_INIT01 ||
1418	    svsb->phase == SVSB_PHASE_INIT02)
1419		complete(&svsb->init_completion);
1420
1421	return IRQ_HANDLED;
1422}
1423
1424static bool svs_mode_available(struct svs_platform *svsp, u8 mode)
1425{
1426	int i;
1427
1428	for (i = 0; i < svsp->bank_max; i++)
1429		if (svsp->banks[i].mode_support & mode)
1430			return true;
1431	return false;
1432}
1433
1434static int svs_init01(struct svs_platform *svsp)
1435{
1436	const struct svs_bank_pdata *bdata;
1437	struct svs_bank *svsb;
1438	unsigned long flags, time_left;
1439	bool search_done;
1440	int ret = 0, r;
1441	u32 opp_freq, opp_vboot, buck_volt, idx, i;
1442
1443	if (!svs_mode_available(svsp, SVSB_MODE_INIT01))
1444		return 0;
1445
1446	/* Keep CPUs' core power on for svs_init01 initialization */
1447	cpuidle_pause_and_lock();
1448
1449	 /* Svs bank init01 preparation - power enable */
1450	for (idx = 0; idx < svsp->bank_max; idx++) {
1451		svsb = &svsp->banks[idx];
1452		bdata = &svsb->pdata;
1453
1454		if (!(svsb->mode_support & SVSB_MODE_INIT01))
1455			continue;
1456
1457		ret = regulator_enable(svsb->buck);
1458		if (ret) {
1459			dev_err(svsb->dev, "%s enable fail: %d\n",
1460				bdata->buck_name, ret);
1461			goto svs_init01_resume_cpuidle;
1462		}
1463
1464		/* Some buck doesn't support mode change. Show fail msg only */
1465		ret = regulator_set_mode(svsb->buck, REGULATOR_MODE_FAST);
1466		if (ret)
1467			dev_notice(svsb->dev, "set fast mode fail: %d\n", ret);
1468
1469		if (svsb->volt_flags & SVSB_INIT01_PD_REQ) {
1470			if (!pm_runtime_enabled(svsb->opp_dev)) {
1471				pm_runtime_enable(svsb->opp_dev);
1472				svsb->pm_runtime_enabled_count++;
1473			}
1474
1475			ret = pm_runtime_resume_and_get(svsb->opp_dev);
1476			if (ret < 0) {
1477				dev_err(svsb->dev, "mtcmos on fail: %d\n", ret);
1478				goto svs_init01_resume_cpuidle;
1479			}
1480		}
1481	}
1482
1483	/*
1484	 * Svs bank init01 preparation - vboot voltage adjustment
1485	 * Sometimes two svs banks use the same buck. Therefore,
1486	 * we have to set each svs bank to target voltage(vboot) first.
1487	 */
1488	for (idx = 0; idx < svsp->bank_max; idx++) {
1489		svsb = &svsp->banks[idx];
1490		bdata = &svsb->pdata;
1491
1492		if (!(svsb->mode_support & SVSB_MODE_INIT01))
1493			continue;
1494
1495		/*
1496		 * Find the fastest freq that can be run at vboot and
1497		 * fix to that freq until svs_init01 is done.
1498		 */
1499		search_done = false;
1500		opp_vboot = svs_bank_volt_to_opp_volt(bdata->vboot,
1501						      bdata->volt_step,
1502						      bdata->volt_base);
1503
1504		for (i = 0; i < bdata->opp_count; i++) {
1505			opp_freq = svsb->opp_dfreq[i];
1506			if (!search_done && svsb->opp_dvolt[i] <= opp_vboot) {
1507				ret = dev_pm_opp_adjust_voltage(svsb->opp_dev,
1508								opp_freq,
1509								opp_vboot,
1510								opp_vboot,
1511								opp_vboot);
1512				if (ret) {
1513					dev_err(svsb->dev,
1514						"set opp %uuV vboot fail: %d\n",
1515						opp_vboot, ret);
1516					goto svs_init01_finish;
1517				}
1518
1519				search_done = true;
1520			} else {
1521				ret = dev_pm_opp_disable(svsb->opp_dev,
1522							 svsb->opp_dfreq[i]);
1523				if (ret) {
1524					dev_err(svsb->dev,
1525						"opp %uHz disable fail: %d\n",
1526						svsb->opp_dfreq[i], ret);
1527					goto svs_init01_finish;
1528				}
1529			}
1530		}
1531	}
1532
1533	/* Svs bank init01 begins */
1534	for (idx = 0; idx < svsp->bank_max; idx++) {
1535		svsb = &svsp->banks[idx];
1536		bdata = &svsb->pdata;
1537
1538		if (!(svsb->mode_support & SVSB_MODE_INIT01))
1539			continue;
1540
1541		opp_vboot = svs_bank_volt_to_opp_volt(bdata->vboot,
1542						      bdata->volt_step,
1543						      bdata->volt_base);
1544
1545		buck_volt = regulator_get_voltage(svsb->buck);
1546		if (buck_volt != opp_vboot) {
1547			dev_err(svsb->dev,
1548				"buck voltage: %uuV, expected vboot: %uuV\n",
1549				buck_volt, opp_vboot);
1550			ret = -EPERM;
1551			goto svs_init01_finish;
1552		}
1553
1554		spin_lock_irqsave(&svs_lock, flags);
1555		svs_set_bank_phase(svsp, idx, SVSB_PHASE_INIT01);
1556		spin_unlock_irqrestore(&svs_lock, flags);
1557
1558		time_left = wait_for_completion_timeout(&svsb->init_completion,
1559							msecs_to_jiffies(5000));
1560		if (!time_left) {
1561			dev_err(svsb->dev, "init01 completion timeout\n");
1562			ret = -EBUSY;
1563			goto svs_init01_finish;
1564		}
1565	}
1566
1567svs_init01_finish:
1568	for (idx = 0; idx < svsp->bank_max; idx++) {
1569		svsb = &svsp->banks[idx];
1570		bdata = &svsb->pdata;
1571
1572		if (!(svsb->mode_support & SVSB_MODE_INIT01))
1573			continue;
1574
1575		for (i = 0; i < bdata->opp_count; i++) {
1576			r = dev_pm_opp_enable(svsb->opp_dev,
1577					      svsb->opp_dfreq[i]);
1578			if (r)
1579				dev_err(svsb->dev, "opp %uHz enable fail: %d\n",
1580					svsb->opp_dfreq[i], r);
1581		}
1582
1583		if (svsb->volt_flags & SVSB_INIT01_PD_REQ) {
1584			r = pm_runtime_put_sync(svsb->opp_dev);
1585			if (r)
1586				dev_err(svsb->dev, "mtcmos off fail: %d\n", r);
1587
1588			if (svsb->pm_runtime_enabled_count > 0) {
1589				pm_runtime_disable(svsb->opp_dev);
1590				svsb->pm_runtime_enabled_count--;
1591			}
1592		}
1593
1594		r = regulator_set_mode(svsb->buck, REGULATOR_MODE_NORMAL);
1595		if (r)
1596			dev_notice(svsb->dev, "set normal mode fail: %d\n", r);
1597
1598		r = regulator_disable(svsb->buck);
1599		if (r)
1600			dev_err(svsb->dev, "%s disable fail: %d\n",
1601				bdata->buck_name, r);
1602	}
1603
1604svs_init01_resume_cpuidle:
1605	cpuidle_resume_and_unlock();
1606
1607	return ret;
1608}
1609
1610static int svs_init02(struct svs_platform *svsp)
1611{
1612	const struct svs_bank_pdata *bdata;
1613	struct svs_bank *svsb;
1614	unsigned long flags, time_left;
1615	int ret;
1616	u32 idx;
1617
1618	if (!svs_mode_available(svsp, SVSB_MODE_INIT02))
1619		return 0;
1620
1621	for (idx = 0; idx < svsp->bank_max; idx++) {
1622		svsb = &svsp->banks[idx];
1623
1624		if (!(svsb->mode_support & SVSB_MODE_INIT02))
1625			continue;
1626
1627		reinit_completion(&svsb->init_completion);
1628		spin_lock_irqsave(&svs_lock, flags);
1629		svs_set_bank_phase(svsp, idx, SVSB_PHASE_INIT02);
1630		spin_unlock_irqrestore(&svs_lock, flags);
1631
1632		time_left = wait_for_completion_timeout(&svsb->init_completion,
1633							msecs_to_jiffies(5000));
1634		if (!time_left) {
1635			dev_err(svsb->dev, "init02 completion timeout\n");
1636			ret = -EBUSY;
1637			goto out_of_init02;
1638		}
1639	}
1640
1641	/*
1642	 * 2-line high/low bank update its corresponding opp voltages only.
1643	 * Therefore, we sync voltages from opp for high/low bank voltages
1644	 * consistency.
1645	 */
1646	for (idx = 0; idx < svsp->bank_max; idx++) {
1647		svsb = &svsp->banks[idx];
1648		bdata = &svsb->pdata;
1649
1650		if (!(svsb->mode_support & SVSB_MODE_INIT02))
1651			continue;
1652
1653		if (bdata->type == SVSB_TYPE_HIGH || bdata->type == SVSB_TYPE_LOW) {
1654			if (svs_sync_bank_volts_from_opp(svsb)) {
1655				dev_err(svsb->dev, "sync volt fail\n");
1656				ret = -EPERM;
1657				goto out_of_init02;
1658			}
1659		}
1660	}
1661
1662	return 0;
1663
1664out_of_init02:
1665	for (idx = 0; idx < svsp->bank_max; idx++) {
1666		svsb = &svsp->banks[idx];
1667		svs_bank_disable_and_restore_default_volts(svsp, svsb);
1668	}
1669
1670	return ret;
1671}
1672
1673static void svs_mon_mode(struct svs_platform *svsp)
1674{
1675	struct svs_bank *svsb;
1676	unsigned long flags;
1677	u32 idx;
1678
1679	for (idx = 0; idx < svsp->bank_max; idx++) {
1680		svsb = &svsp->banks[idx];
1681
1682		if (!(svsb->mode_support & SVSB_MODE_MON))
1683			continue;
1684
1685		spin_lock_irqsave(&svs_lock, flags);
1686		svs_set_bank_phase(svsp, idx, SVSB_PHASE_MON);
1687		spin_unlock_irqrestore(&svs_lock, flags);
1688	}
1689}
1690
1691static int svs_start(struct svs_platform *svsp)
1692{
1693	int ret;
1694
1695	ret = svs_init01(svsp);
1696	if (ret)
1697		return ret;
1698
1699	ret = svs_init02(svsp);
1700	if (ret)
1701		return ret;
1702
1703	svs_mon_mode(svsp);
1704
1705	return 0;
1706}
1707
1708static int svs_suspend(struct device *dev)
1709{
1710	struct svs_platform *svsp = dev_get_drvdata(dev);
1711	int ret;
1712	u32 idx;
1713
1714	for (idx = 0; idx < svsp->bank_max; idx++) {
1715		struct svs_bank *svsb = &svsp->banks[idx];
1716
1717		svs_bank_disable_and_restore_default_volts(svsp, svsb);
1718	}
1719
1720	ret = reset_control_assert(svsp->rst);
1721	if (ret) {
1722		dev_err(svsp->dev, "cannot assert reset %d\n", ret);
1723		return ret;
1724	}
1725
1726	clk_disable_unprepare(svsp->main_clk);
1727
1728	return 0;
1729}
1730
1731static int svs_resume(struct device *dev)
1732{
1733	struct svs_platform *svsp = dev_get_drvdata(dev);
1734	int ret;
1735
1736	ret = clk_prepare_enable(svsp->main_clk);
1737	if (ret) {
1738		dev_err(svsp->dev, "cannot enable main_clk, disable svs\n");
1739		return ret;
1740	}
1741
1742	ret = reset_control_deassert(svsp->rst);
1743	if (ret) {
1744		dev_err(svsp->dev, "cannot deassert reset %d\n", ret);
1745		goto out_of_resume;
1746	}
1747
1748	ret = svs_init02(svsp);
1749	if (ret)
1750		goto svs_resume_reset_assert;
1751
1752	svs_mon_mode(svsp);
1753
1754	return 0;
1755
1756svs_resume_reset_assert:
1757	dev_err(svsp->dev, "assert reset: %d\n",
1758		reset_control_assert(svsp->rst));
1759
1760out_of_resume:
1761	clk_disable_unprepare(svsp->main_clk);
1762	return ret;
1763}
1764
1765static int svs_bank_resource_setup(struct svs_platform *svsp)
1766{
1767	const struct svs_bank_pdata *bdata;
1768	struct svs_bank *svsb;
1769	struct dev_pm_opp *opp;
1770	char tz_name_buf[20];
1771	unsigned long freq;
1772	int count, ret;
1773	u32 idx, i;
1774
1775	dev_set_drvdata(svsp->dev, svsp);
1776
1777	for (idx = 0; idx < svsp->bank_max; idx++) {
1778		svsb = &svsp->banks[idx];
1779		bdata = &svsb->pdata;
1780
1781		if (bdata->sw_id >= SVSB_SWID_MAX || bdata->type >= SVSB_TYPE_MAX) {
1782			dev_err(svsb->dev, "unknown bank sw_id or type\n");
1783			return -EINVAL;
1784		}
1785
1786		svsb->dev = devm_kzalloc(svsp->dev, sizeof(*svsb->dev), GFP_KERNEL);
1787		if (!svsb->dev)
1788			return -ENOMEM;
1789
1790		svsb->name = devm_kasprintf(svsp->dev, GFP_KERNEL, "%s%s",
1791					    svs_swid_names[bdata->sw_id],
1792					    svs_type_names[bdata->type]);
1793		if (!svsb->name)
1794			return -ENOMEM;
1795
1796		ret = dev_set_name(svsb->dev, "%s", svsb->name);
1797		if (ret)
1798			return ret;
1799
1800		dev_set_drvdata(svsb->dev, svsp);
1801
1802		ret = devm_pm_opp_of_add_table(svsb->opp_dev);
1803		if (ret) {
1804			dev_err(svsb->dev, "add opp table fail: %d\n", ret);
1805			return ret;
1806		}
1807
1808		mutex_init(&svsb->lock);
1809		init_completion(&svsb->init_completion);
1810
1811		if (svsb->mode_support & SVSB_MODE_INIT01) {
1812			svsb->buck = devm_regulator_get_optional(svsb->opp_dev,
1813								 bdata->buck_name);
1814			if (IS_ERR(svsb->buck)) {
1815				dev_err(svsb->dev, "cannot get \"%s-supply\"\n",
1816					bdata->buck_name);
1817				return PTR_ERR(svsb->buck);
1818			}
1819		}
1820
1821		if (!IS_ERR_OR_NULL(bdata->tzone_name)) {
1822			snprintf(tz_name_buf, ARRAY_SIZE(tz_name_buf),
1823				 "%s-thermal", bdata->tzone_name);
1824			svsb->tzd = thermal_zone_get_zone_by_name(tz_name_buf);
1825			if (IS_ERR(svsb->tzd)) {
1826				dev_err(svsb->dev, "cannot get \"%s\" thermal zone\n",
1827					tz_name_buf);
1828				return PTR_ERR(svsb->tzd);
1829			}
1830		}
1831
1832		count = dev_pm_opp_get_opp_count(svsb->opp_dev);
1833		if (bdata->opp_count != count) {
1834			dev_err(svsb->dev,
1835				"opp_count not \"%u\" but get \"%d\"?\n",
1836				bdata->opp_count, count);
1837			return count;
1838		}
1839
1840		for (i = 0, freq = ULONG_MAX; i < bdata->opp_count; i++, freq--) {
1841			opp = dev_pm_opp_find_freq_floor(svsb->opp_dev, &freq);
1842			if (IS_ERR(opp)) {
1843				dev_err(svsb->dev, "cannot find freq = %ld\n",
1844					PTR_ERR(opp));
1845				return PTR_ERR(opp);
1846			}
1847
1848			svsb->opp_dfreq[i] = freq;
1849			svsb->opp_dvolt[i] = dev_pm_opp_get_voltage(opp);
1850			svsb->freq_pct[i] = percent(svsb->opp_dfreq[i],
1851						    svsb->freq_base);
1852			dev_pm_opp_put(opp);
1853		}
1854	}
1855
1856	return 0;
1857}
1858
1859static int svs_get_efuse_data(struct svs_platform *svsp,
1860			      const char *nvmem_cell_name,
1861			      u32 **svsp_efuse, size_t *svsp_efuse_max)
1862{
1863	struct nvmem_cell *cell;
1864
1865	cell = nvmem_cell_get(svsp->dev, nvmem_cell_name);
1866	if (IS_ERR(cell)) {
1867		dev_err(svsp->dev, "no \"%s\"? %ld\n",
1868			nvmem_cell_name, PTR_ERR(cell));
1869		return PTR_ERR(cell);
1870	}
1871
1872	*svsp_efuse = nvmem_cell_read(cell, svsp_efuse_max);
1873	if (IS_ERR(*svsp_efuse)) {
1874		nvmem_cell_put(cell);
1875		return PTR_ERR(*svsp_efuse);
1876	}
1877
1878	*svsp_efuse_max /= sizeof(u32);
1879	nvmem_cell_put(cell);
1880
1881	return 0;
1882}
1883
1884static u32 svs_get_fuse_val(u32 *fuse_array, const struct svs_fusemap *fmap, u8 nbits)
1885{
1886	u32 val;
1887
1888	if (fmap->index < 0)
1889		return FUSE_DATA_NOT_VALID;
1890
1891	val = fuse_array[fmap->index] >> fmap->ofst;
1892	val &= GENMASK(nbits - 1, 0);
1893
1894	return val;
1895}
1896
1897static bool svs_is_available(struct svs_platform *svsp)
1898{
1899	int i, num_populated = 0;
1900
1901	/* If at least two fuse arrays are populated, SVS is calibrated */
1902	for (i = 0; i < svsp->efuse_max; i++) {
1903		if (svsp->efuse[i])
1904			num_populated++;
1905
1906		if (num_populated > 1)
1907			return true;
1908	}
1909
1910	return false;
1911}
1912
1913static bool svs_common_parse_efuse(struct svs_platform *svsp,
1914				   const struct svs_platform_data *pdata)
1915{
1916	const struct svs_fusemap *gfmap = pdata->glb_fuse_map;
1917	struct svs_fusemap tfm = { 0, 24 };
1918	u32 golden_temp, val;
1919	u8 ft_pgm, vmin;
1920	int i;
1921
1922	if (!svs_is_available(svsp))
1923		return false;
1924
1925	/* Get golden temperature from SVS-Thermal calibration */
1926	val = svs_get_fuse_val(svsp->tefuse, &tfm, 8);
1927
1928	/* If golden temp is not programmed, use the default of 50 */
1929	golden_temp = val ? val : 50;
1930
1931	/* Parse fused SVS calibration */
1932	ft_pgm = svs_get_fuse_val(svsp->efuse, &gfmap[GLB_FT_PGM], 8);
1933	vmin = svs_get_fuse_val(svsp->efuse, &gfmap[GLB_VMIN], 2);
1934
1935	for (i = 0; i < svsp->bank_max; i++) {
1936		struct svs_bank *svsb = &svsp->banks[i];
1937		const struct svs_bank_pdata *bdata = &svsb->pdata;
1938		const struct svs_fusemap *dfmap = bdata->dev_fuse_map;
1939
1940		if (vmin == 1)
1941			svsb->vmin = 0x1e;
1942
1943		if (ft_pgm == 0)
1944			svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE;
1945
1946		svsb->mtdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_MTDES], 8);
1947		svsb->bdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_BDES], 8);
1948		svsb->mdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_MDES], 8);
1949		svsb->dcbdet = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_DCBDET], 8);
1950		svsb->dcmdet = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_DCMDET], 8);
1951		svsb->vmax += svsb->dvt_fixed;
1952
1953		svsb->mts = (svsp->ts_coeff * 2) / 1000;
1954		svsb->bts = (((500 * golden_temp + svsp->ts_coeff) / 1000) - 25) * 4;
1955	}
1956
1957	return true;
1958}
1959
1960static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp,
1961				     const struct svs_platform_data *pdata)
1962{
1963	struct svs_bank *svsb;
1964	const struct svs_bank_pdata *bdata;
1965	int format[6], x_roomt[6], o_vtsmcu[5], o_vtsabb, tb_roomt = 0;
1966	int adc_ge_t, adc_oe_t, ge, oe, gain, degc_cali, adc_cali_en_t;
1967	int o_slope, o_slope_sign, ts_id;
1968	u32 idx, i, ft_pgm, mts, temp0, temp1, temp2;
1969
1970	for (i = 0; i < svsp->efuse_max; i++)
1971		if (svsp->efuse[i])
1972			dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n",
1973				 i, svsp->efuse[i]);
1974
1975	if (!svsp->efuse[2]) {
1976		dev_notice(svsp->dev, "svs_efuse[2] = 0x0?\n");
1977		return false;
1978	}
1979
1980	/* Svs efuse parsing */
1981	ft_pgm = svs_get_fuse_val(svsp->efuse, &pdata->glb_fuse_map[GLB_FT_PGM], 4);
1982
1983	for (idx = 0; idx < svsp->bank_max; idx++) {
1984		svsb = &svsp->banks[idx];
1985		bdata = &svsb->pdata;
1986		const struct svs_fusemap *dfmap = bdata->dev_fuse_map;
1987
1988		if (ft_pgm <= 1)
1989			svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE;
1990
1991		svsb->mtdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_MTDES], 8);
1992		svsb->bdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_BDES], 8);
1993		svsb->mdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_MDES], 8);
1994		svsb->dcbdet = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_DCBDET], 8);
1995		svsb->dcmdet = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_DCMDET], 8);
1996
1997		switch (bdata->sw_id) {
1998		case SVSB_SWID_CPU_LITTLE:
1999		case SVSB_SWID_CCI:
2000			if (ft_pgm <= 3)
2001				svsb->volt_od += 10;
2002			else
2003				svsb->volt_od += 2;
2004			break;
2005		case SVSB_SWID_CPU_BIG:
2006			if (ft_pgm <= 3)
2007				svsb->volt_od += 15;
2008			else
2009				svsb->volt_od += 12;
2010			break;
2011		case SVSB_SWID_GPU:
2012			if (ft_pgm != FUSE_DATA_NOT_VALID && ft_pgm >= 2) {
2013				svsb->freq_base = 800000000; /* 800MHz */
2014				svsb->dvt_fixed = 2;
2015			}
2016			break;
2017		default:
2018			dev_err(svsb->dev, "unknown sw_id: %u\n", bdata->sw_id);
2019			return false;
2020		}
2021	}
2022
2023	/* Thermal efuse parsing */
2024	adc_ge_t = (svsp->tefuse[1] >> 22) & GENMASK(9, 0);
2025	adc_oe_t = (svsp->tefuse[1] >> 12) & GENMASK(9, 0);
2026
2027	o_vtsmcu[0] = (svsp->tefuse[0] >> 17) & GENMASK(8, 0);
2028	o_vtsmcu[1] = (svsp->tefuse[0] >> 8) & GENMASK(8, 0);
2029	o_vtsmcu[2] = svsp->tefuse[1] & GENMASK(8, 0);
2030	o_vtsmcu[3] = (svsp->tefuse[2] >> 23) & GENMASK(8, 0);
2031	o_vtsmcu[4] = (svsp->tefuse[2] >> 5) & GENMASK(8, 0);
2032	o_vtsabb = (svsp->tefuse[2] >> 14) & GENMASK(8, 0);
2033
2034	degc_cali = (svsp->tefuse[0] >> 1) & GENMASK(5, 0);
2035	adc_cali_en_t = svsp->tefuse[0] & BIT(0);
2036	o_slope_sign = (svsp->tefuse[0] >> 7) & BIT(0);
2037
2038	ts_id = (svsp->tefuse[1] >> 9) & BIT(0);
2039	if (!ts_id) {
2040		o_slope = 1534;
2041	} else {
2042		o_slope = (svsp->tefuse[0] >> 26) & GENMASK(5, 0);
2043		if (!o_slope_sign)
2044			o_slope = 1534 + o_slope * 10;
2045		else
2046			o_slope = 1534 - o_slope * 10;
2047	}
2048
2049	if (adc_cali_en_t == 0 ||
2050	    adc_ge_t < 265 || adc_ge_t > 758 ||
2051	    adc_oe_t < 265 || adc_oe_t > 758 ||
2052	    o_vtsmcu[0] < -8 || o_vtsmcu[0] > 484 ||
2053	    o_vtsmcu[1] < -8 || o_vtsmcu[1] > 484 ||
2054	    o_vtsmcu[2] < -8 || o_vtsmcu[2] > 484 ||
2055	    o_vtsmcu[3] < -8 || o_vtsmcu[3] > 484 ||
2056	    o_vtsmcu[4] < -8 || o_vtsmcu[4] > 484 ||
2057	    o_vtsabb < -8 || o_vtsabb > 484 ||
2058	    degc_cali < 1 || degc_cali > 63) {
2059		dev_err(svsp->dev, "bad thermal efuse, no mon mode\n");
2060		goto remove_mt8183_svsb_mon_mode;
2061	}
2062
2063	ge = ((adc_ge_t - 512) * 10000) / 4096;
2064	oe = (adc_oe_t - 512);
2065	gain = (10000 + ge);
2066
2067	format[0] = (o_vtsmcu[0] + 3350 - oe);
2068	format[1] = (o_vtsmcu[1] + 3350 - oe);
2069	format[2] = (o_vtsmcu[2] + 3350 - oe);
2070	format[3] = (o_vtsmcu[3] + 3350 - oe);
2071	format[4] = (o_vtsmcu[4] + 3350 - oe);
2072	format[5] = (o_vtsabb + 3350 - oe);
2073
2074	for (i = 0; i < 6; i++)
2075		x_roomt[i] = (((format[i] * 10000) / 4096) * 10000) / gain;
2076
2077	temp0 = (10000 * 100000 / gain) * 15 / 18;
2078	mts = (temp0 * 10) / o_slope;
2079
2080	for (idx = 0; idx < svsp->bank_max; idx++) {
2081		svsb = &svsp->banks[idx];
2082		bdata = &svsb->pdata;
2083		svsb->mts = mts;
2084
2085		switch (bdata->sw_id) {
2086		case SVSB_SWID_CPU_LITTLE:
2087			tb_roomt = x_roomt[3];
2088			break;
2089		case SVSB_SWID_CPU_BIG:
2090			tb_roomt = x_roomt[4];
2091			break;
2092		case SVSB_SWID_CCI:
2093			tb_roomt = x_roomt[3];
2094			break;
2095		case SVSB_SWID_GPU:
2096			tb_roomt = x_roomt[1];
2097			break;
2098		default:
2099			dev_err(svsb->dev, "unknown sw_id: %u\n", bdata->sw_id);
2100			goto remove_mt8183_svsb_mon_mode;
2101		}
2102
2103		temp0 = (degc_cali * 10 / 2);
2104		temp1 = ((10000 * 100000 / 4096 / gain) *
2105			 oe + tb_roomt * 10) * 15 / 18;
2106		temp2 = temp1 * 100 / o_slope;
2107
2108		svsb->bts = (temp0 + temp2 - 250) * 4 / 10;
2109	}
2110
2111	return true;
2112
2113remove_mt8183_svsb_mon_mode:
2114	for (idx = 0; idx < svsp->bank_max; idx++) {
2115		svsb = &svsp->banks[idx];
2116		svsb->mode_support &= ~SVSB_MODE_MON;
2117	}
2118
2119	return true;
2120}
2121
2122static struct device *svs_get_subsys_device(struct svs_platform *svsp,
2123					    const char *node_name)
2124{
2125	struct platform_device *pdev;
2126	struct device_node *np;
2127
2128	np = of_find_node_by_name(NULL, node_name);
2129	if (!np) {
2130		dev_err(svsp->dev, "cannot find %s node\n", node_name);
2131		return ERR_PTR(-ENODEV);
2132	}
2133
2134	pdev = of_find_device_by_node(np);
2135	of_node_put(np);
2136	if (!pdev) {
2137		dev_err(svsp->dev, "cannot find pdev by %s\n", node_name);
2138		return ERR_PTR(-ENXIO);
2139	}
2140
2141	return &pdev->dev;
2142}
2143
2144static struct device *svs_add_device_link(struct svs_platform *svsp,
2145					  const char *node_name)
2146{
2147	struct device *dev;
2148	struct device_link *sup_link;
2149
2150	dev = svs_get_subsys_device(svsp, node_name);
2151	if (IS_ERR(dev))
2152		return dev;
2153
2154	sup_link = device_link_add(svsp->dev, dev,
2155				   DL_FLAG_AUTOREMOVE_CONSUMER);
2156	if (!sup_link) {
2157		dev_err(svsp->dev, "sup_link is NULL\n");
2158		return ERR_PTR(-EINVAL);
2159	}
2160
2161	if (sup_link->supplier->links.status != DL_DEV_DRIVER_BOUND)
2162		return ERR_PTR(-EPROBE_DEFER);
2163
2164	return dev;
2165}
2166
2167static void svs_put_device(void *_dev)
2168{
2169	struct device *dev = _dev;
2170
2171	put_device(dev);
2172}
2173
2174static int svs_mt8192_platform_probe(struct svs_platform *svsp)
2175{
2176	struct device *dev;
2177	u32 idx;
2178	int ret;
2179
2180	svsp->rst = devm_reset_control_get_optional(svsp->dev, "svs_rst");
2181	if (IS_ERR(svsp->rst))
2182		return dev_err_probe(svsp->dev, PTR_ERR(svsp->rst),
2183				     "cannot get svs reset control\n");
2184
2185	dev = svs_add_device_link(svsp, "thermal-sensor");
2186	if (IS_ERR(dev))
2187		return dev_err_probe(svsp->dev, PTR_ERR(dev),
2188				     "failed to get lvts device\n");
2189	put_device(dev);
2190
2191	for (idx = 0; idx < svsp->bank_max; idx++) {
2192		struct svs_bank *svsb = &svsp->banks[idx];
2193		const struct svs_bank_pdata *bdata = &svsb->pdata;
2194
2195		switch (bdata->sw_id) {
2196		case SVSB_SWID_CPU_LITTLE:
2197		case SVSB_SWID_CPU_BIG:
2198			svsb->opp_dev = get_cpu_device(bdata->cpu_id);
2199			get_device(svsb->opp_dev);
2200			break;
2201		case SVSB_SWID_CCI:
2202			svsb->opp_dev = svs_add_device_link(svsp, "cci");
2203			break;
2204		case SVSB_SWID_GPU:
2205			if (bdata->type == SVSB_TYPE_LOW)
2206				svsb->opp_dev = svs_get_subsys_device(svsp, "gpu");
2207			else
2208				svsb->opp_dev = svs_add_device_link(svsp, "gpu");
2209			break;
2210		default:
2211			dev_err(svsb->dev, "unknown sw_id: %u\n", bdata->sw_id);
2212			return -EINVAL;
2213		}
2214
2215		if (IS_ERR(svsb->opp_dev))
2216			return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev),
2217					     "failed to get OPP device for bank %d\n",
2218					     idx);
2219
2220		ret = devm_add_action_or_reset(svsp->dev, svs_put_device,
2221					       svsb->opp_dev);
2222		if (ret)
2223			return ret;
2224	}
2225
2226	return 0;
2227}
2228
2229static int svs_mt8183_platform_probe(struct svs_platform *svsp)
2230{
2231	struct device *dev;
2232	u32 idx;
2233	int ret;
2234
2235	dev = svs_add_device_link(svsp, "thermal-sensor");
2236	if (IS_ERR(dev))
2237		return dev_err_probe(svsp->dev, PTR_ERR(dev),
2238				     "failed to get thermal device\n");
2239	put_device(dev);
2240
2241	for (idx = 0; idx < svsp->bank_max; idx++) {
2242		struct svs_bank *svsb = &svsp->banks[idx];
2243		const struct svs_bank_pdata *bdata = &svsb->pdata;
2244
2245		switch (bdata->sw_id) {
2246		case SVSB_SWID_CPU_LITTLE:
2247		case SVSB_SWID_CPU_BIG:
2248			svsb->opp_dev = get_cpu_device(bdata->cpu_id);
2249			get_device(svsb->opp_dev);
2250			break;
2251		case SVSB_SWID_CCI:
2252			svsb->opp_dev = svs_add_device_link(svsp, "cci");
2253			break;
2254		case SVSB_SWID_GPU:
2255			svsb->opp_dev = svs_add_device_link(svsp, "gpu");
2256			break;
2257		default:
2258			dev_err(svsb->dev, "unknown sw_id: %u\n", bdata->sw_id);
2259			return -EINVAL;
2260		}
2261
2262		if (IS_ERR(svsb->opp_dev))
2263			return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev),
2264					     "failed to get OPP device for bank %d\n",
2265					     idx);
2266
2267		ret = devm_add_action_or_reset(svsp->dev, svs_put_device,
2268					       svsb->opp_dev);
2269		if (ret)
2270			return ret;
2271	}
2272
2273	return 0;
2274}
2275
2276static struct svs_bank svs_mt8195_banks[] = {
2277	{
2278		.pdata = (const struct svs_bank_pdata) {
2279			.sw_id			= SVSB_SWID_GPU,
2280			.type			= SVSB_TYPE_LOW,
2281			.set_freq_pct		= svs_set_bank_freq_pct_v3,
2282			.get_volts		= svs_get_bank_volts_v3,
2283			.opp_count		= MAX_OPP_ENTRIES,
2284			.turn_freq_base		= 640000000,
2285			.volt_step		= 6250,
2286			.volt_base		= 400000,
2287			.age_config		= 0x555555,
2288			.dc_config		= 0x1,
2289			.vco			= 0x18,
2290			.chk_shift		= 0x87,
2291			.int_st			= BIT(0),
2292			.ctl0			= 0x00540003,
2293			.dev_fuse_map		= (const struct svs_fusemap[BDEV_MAX]) {
2294				{ 10, 16 }, { 10, 24 }, { 10, 0 }, { 8, 0 }, { 8, 8 }
2295			}
2296		},
2297		.mode_support	= SVSB_MODE_INIT02,
2298		.volt_flags	= SVSB_REMOVE_DVTFIXED_VOLT,
2299		.freq_base	= 640000000,
2300		.core_sel	= 0x0fff0100,
2301		.dvt_fixed	= 0x1,
2302		.vmax		= 0x38,
2303		.vmin		= 0x14,
2304	},
2305	{
2306		.pdata = (const struct svs_bank_pdata) {
2307			.sw_id			= SVSB_SWID_GPU,
2308			.type			= SVSB_TYPE_HIGH,
2309			.set_freq_pct		= svs_set_bank_freq_pct_v3,
2310			.get_volts		= svs_get_bank_volts_v3,
2311			.tzone_name		= "gpu",
2312			.opp_count		= MAX_OPP_ENTRIES,
2313			.turn_freq_base		= 640000000,
2314			.volt_step		= 6250,
2315			.volt_base		= 400000,
2316			.age_config		= 0x555555,
2317			.dc_config		= 0x1,
2318			.vco			= 0x18,
2319			.chk_shift		= 0x87,
2320			.int_st			= BIT(1),
2321			.ctl0			= 0x00540003,
2322			.tzone_htemp		= 85000,
2323			.tzone_htemp_voffset	= 0,
2324			.tzone_ltemp		= 25000,
2325			.tzone_ltemp_voffset	= 7,
2326			.dev_fuse_map		= (const struct svs_fusemap[BDEV_MAX]) {
2327				{ 9, 16 }, { 9, 24 }, { 9, 0 }, { 8, 0 }, { 8, 8 }
2328			},
2329		},
2330		.volt_flags	= SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE,
2331		.mode_support	= SVSB_MODE_INIT02 | SVSB_MODE_MON,
2332		.freq_base	= 880000000,
2333		.core_sel	= 0x0fff0101,
2334		.dvt_fixed	= 0x6,
2335		.vmax		= 0x38,
2336		.vmin		= 0x14,
2337	},
2338};
2339
2340static struct svs_bank svs_mt8192_banks[] = {
2341	{
2342		.pdata = (const struct svs_bank_pdata) {
2343			.sw_id			= SVSB_SWID_GPU,
2344			.type			= SVSB_TYPE_LOW,
2345			.set_freq_pct		= svs_set_bank_freq_pct_v3,
2346			.get_volts		= svs_get_bank_volts_v3,
2347			.tzone_name		= "gpu",
2348			.opp_count		= MAX_OPP_ENTRIES,
2349			.turn_freq_base		= 688000000,
2350			.volt_step		= 6250,
2351			.volt_base		= 400000,
2352			.age_config		= 0x555555,
2353			.dc_config		= 0x1,
2354			.vco			= 0x18,
2355			.chk_shift		= 0x87,
2356			.int_st			= BIT(0),
2357			.ctl0			= 0x00540003,
2358			.tzone_htemp		= 85000,
2359			.tzone_htemp_voffset	= 0,
2360			.tzone_ltemp		= 25000,
2361			.tzone_ltemp_voffset	= 7,
2362			.dev_fuse_map		= (const struct svs_fusemap[BDEV_MAX]) {
2363				{ 10, 16 }, { 10, 24 }, { 10, 0 }, { 17, 0 }, { 17, 8 }
2364			}
2365		},
2366		.volt_flags	= SVSB_REMOVE_DVTFIXED_VOLT,
2367		.mode_support	= SVSB_MODE_INIT02,
2368		.freq_base	= 688000000,
2369		.core_sel	= 0x0fff0100,
2370		.dvt_fixed	= 0x1,
2371		.vmax		= 0x60,
2372		.vmin		= 0x1a,
2373	},
2374	{
2375		.pdata = (const struct svs_bank_pdata) {
2376			.sw_id			= SVSB_SWID_GPU,
2377			.type			= SVSB_TYPE_HIGH,
2378			.set_freq_pct		= svs_set_bank_freq_pct_v3,
2379			.get_volts		= svs_get_bank_volts_v3,
2380			.tzone_name		= "gpu",
2381			.opp_count		= MAX_OPP_ENTRIES,
2382			.turn_freq_base		= 688000000,
2383			.volt_step		= 6250,
2384			.volt_base		= 400000,
2385			.age_config		= 0x555555,
2386			.dc_config		= 0x1,
2387			.vco			= 0x18,
2388			.chk_shift		= 0x87,
2389			.int_st			= BIT(1),
2390			.ctl0			= 0x00540003,
2391			.tzone_htemp		= 85000,
2392			.tzone_htemp_voffset	= 0,
2393			.tzone_ltemp		= 25000,
2394			.tzone_ltemp_voffset	= 7,
2395			.dev_fuse_map		= (const struct svs_fusemap[BDEV_MAX]) {
2396				{ 9, 16 }, { 9, 24 }, { 17, 0 }, { 17, 16 }, { 17, 24 }
2397			}
2398		},
2399		.volt_flags	= SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE,
2400		.mode_support	= SVSB_MODE_INIT02 | SVSB_MODE_MON,
2401		.freq_base	= 902000000,
2402		.core_sel	= 0x0fff0101,
2403		.dvt_fixed	= 0x6,
2404		.vmax		= 0x60,
2405		.vmin		= 0x1a,
2406	},
2407};
2408
2409static struct svs_bank svs_mt8188_banks[] = {
2410	{
2411		.pdata = (const struct svs_bank_pdata) {
2412			.sw_id			= SVSB_SWID_GPU,
2413			.type			= SVSB_TYPE_LOW,
2414			.set_freq_pct		= svs_set_bank_freq_pct_v3,
2415			.get_volts		= svs_get_bank_volts_v3,
2416			.opp_count		= MAX_OPP_ENTRIES,
2417			.turn_freq_base		= 640000000,
2418			.volt_step		= 6250,
2419			.volt_base		= 400000,
2420			.age_config		= 0x555555,
2421			.dc_config		= 0x555555,
2422			.vco			= 0x10,
2423			.chk_shift		= 0x87,
2424			.int_st			= BIT(0),
2425			.ctl0			= 0x00100003,
2426			.dev_fuse_map		= (const struct svs_fusemap[BDEV_MAX]) {
2427				{ 5, 16 }, { 5, 24 }, { 5, 0 }, { 15, 16 }, { 15, 24 }
2428			}
2429		},
2430		.volt_flags	= SVSB_REMOVE_DVTFIXED_VOLT,
2431		.mode_support	= SVSB_MODE_INIT02,
2432		.freq_base	= 640000000,
2433		.core_sel	= 0x0fff0000,
2434		.dvt_fixed	= 0x1,
2435		.vmax		= 0x38,
2436		.vmin		= 0x1c,
2437	},
2438	{
2439		.pdata = (const struct svs_bank_pdata) {
2440			.sw_id			= SVSB_SWID_GPU,
2441			.type			= SVSB_TYPE_HIGH,
2442			.set_freq_pct		= svs_set_bank_freq_pct_v3,
2443			.get_volts		= svs_get_bank_volts_v3,
2444			.tzone_name		= "gpu",
2445			.opp_count		= MAX_OPP_ENTRIES,
2446			.turn_freq_base		= 640000000,
2447			.volt_step		= 6250,
2448			.volt_base		= 400000,
2449			.age_config		= 0x555555,
2450			.dc_config		= 0x555555,
2451			.vco			= 0x10,
2452			.chk_shift		= 0x87,
2453			.int_st			= BIT(1),
2454			.ctl0			= 0x00100003,
2455			.tzone_htemp		= 85000,
2456			.tzone_htemp_voffset	= 0,
2457			.tzone_ltemp		= 25000,
2458			.tzone_ltemp_voffset	= 7,
2459			.dev_fuse_map		= (const struct svs_fusemap[BDEV_MAX]) {
2460				{ 4, 16 }, { 4, 24 }, { 4, 0 }, { 14, 0 }, { 14, 8 }
2461			}
2462		},
2463		.volt_flags	= SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE,
2464		.mode_support	= SVSB_MODE_INIT02 | SVSB_MODE_MON,
2465		.freq_base	= 880000000,
2466		.core_sel	= 0x0fff0001,
2467		.dvt_fixed	= 0x4,
2468		.vmax		= 0x38,
2469		.vmin		= 0x1c,
2470	},
2471};
2472
2473static struct svs_bank svs_mt8186_banks[] = {
2474	{
2475		.pdata = (const struct svs_bank_pdata) {
2476			.sw_id			= SVSB_SWID_CPU_BIG,
2477			.type			= SVSB_TYPE_LOW,
2478			.set_freq_pct		= svs_set_bank_freq_pct_v3,
2479			.get_volts		= svs_get_bank_volts_v3,
2480			.cpu_id			= 6,
2481			.opp_count		= MAX_OPP_ENTRIES,
2482			.turn_freq_base		= 1670000000,
2483			.volt_step		= 6250,
2484			.volt_base		= 400000,
2485			.age_config		= 0x1,
2486			.dc_config		= 0x1,
2487			.vco			= 0x10,
2488			.chk_shift		= 0x87,
2489			.int_st			= BIT(0),
2490			.ctl0			= 0x00540003,
2491			.dev_fuse_map		= (const struct svs_fusemap[BDEV_MAX]) {
2492				{ 3, 16 }, { 3, 24 }, { 3, 0 }, { 14, 16 }, { 14, 24 }
2493			}
2494		},
2495		.volt_flags	= SVSB_REMOVE_DVTFIXED_VOLT,
2496		.volt_od	= 4,
2497		.mode_support	= SVSB_MODE_INIT02,
2498		.freq_base	= 1670000000,
2499		.core_sel	= 0x0fff0100,
2500		.dvt_fixed	= 0x3,
2501		.vmax		= 0x59,
2502		.vmin		= 0x20,
2503	},
2504	{
2505		.pdata = (const struct svs_bank_pdata) {
2506			.sw_id			= SVSB_SWID_CPU_BIG,
2507			.type			= SVSB_TYPE_HIGH,
2508			.set_freq_pct		= svs_set_bank_freq_pct_v3,
2509			.get_volts		= svs_get_bank_volts_v3,
2510			.cpu_id			= 6,
2511			.tzone_name		= "cpu-big",
2512			.opp_count		= MAX_OPP_ENTRIES,
2513			.turn_freq_base		= 1670000000,
2514			.volt_step		= 6250,
2515			.volt_base		= 400000,
2516			.age_config		= 0x1,
2517			.dc_config		= 0x1,
2518			.vco			= 0x10,
2519			.chk_shift		= 0x87,
2520			.int_st			= BIT(1),
2521			.ctl0			= 0x00540003,
2522			.tzone_htemp		= 85000,
2523			.tzone_htemp_voffset	= 8,
2524			.tzone_ltemp		= 25000,
2525			.tzone_ltemp_voffset	= 8,
2526			.dev_fuse_map		= (const struct svs_fusemap[BDEV_MAX]) {
2527				{ 2, 16 }, { 2, 24 }, { 2, 0 }, { 13, 0 }, { 13, 8 }
2528			}
2529		},
2530		.volt_flags	= SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE,
2531		.volt_od	= 4,
2532		.mode_support	= SVSB_MODE_INIT02 | SVSB_MODE_MON,
2533		.freq_base	= 2050000000,
2534		.core_sel	= 0x0fff0101,
2535		.dvt_fixed	= 0x6,
2536		.vmax		= 0x73,
2537		.vmin		= 0x20,
2538	},
2539	{
2540		.pdata = (const struct svs_bank_pdata) {
2541			.sw_id			= SVSB_SWID_CPU_LITTLE,
2542			.set_freq_pct		= svs_set_bank_freq_pct_v2,
2543			.get_volts		= svs_get_bank_volts_v2,
2544			.cpu_id			= 0,
2545			.tzone_name		= "cpu-little",
2546			.opp_count		= MAX_OPP_ENTRIES,
2547			.volt_step		= 6250,
2548			.volt_base		= 400000,
2549			.age_config		= 0x1,
2550			.dc_config		= 0x1,
2551			.vco			= 0x10,
2552			.chk_shift		= 0x87,
2553			.int_st			= BIT(2),
2554			.ctl0			= 0x3210000f,
2555			.tzone_htemp		= 85000,
2556			.tzone_htemp_voffset	= 8,
2557			.tzone_ltemp		= 25000,
2558			.tzone_ltemp_voffset	= 8,
2559			.dev_fuse_map		= (const struct svs_fusemap[BDEV_MAX]) {
2560				{ 4, 16 }, { 4, 24 }, { 4, 0 }, { 14, 0 }, { 14, 8 }
2561			}
2562		},
2563		.volt_flags	= SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE,
2564		.volt_od	= 3,
2565		.mode_support	= SVSB_MODE_INIT02 | SVSB_MODE_MON,
2566		.freq_base	= 2000000000,
2567		.core_sel	= 0x0fff0102,
2568		.dvt_fixed	= 0x6,
2569		.vmax		= 0x65,
2570		.vmin		= 0x20,
2571	},
2572	{
2573		.pdata = (const struct svs_bank_pdata) {
2574			.sw_id			= SVSB_SWID_CCI,
2575			.set_freq_pct		= svs_set_bank_freq_pct_v2,
2576			.get_volts		= svs_get_bank_volts_v2,
2577			.tzone_name		= "cci",
2578			.opp_count		= MAX_OPP_ENTRIES,
2579			.volt_step		= 6250,
2580			.volt_base		= 400000,
2581			.age_config		= 0x1,
2582			.dc_config		= 0x1,
2583			.vco			= 0x10,
2584			.chk_shift		= 0x87,
2585			.int_st			= BIT(3),
2586			.ctl0			= 0x3210000f,
2587			.tzone_htemp		= 85000,
2588			.tzone_htemp_voffset	= 8,
2589			.tzone_ltemp		= 25000,
2590			.tzone_ltemp_voffset	= 8,
2591			.dev_fuse_map		= (const struct svs_fusemap[BDEV_MAX]) {
2592				{ 5, 16 }, { 5, 24 }, { 5, 0 }, { 15, 16 }, { 15, 24 }
2593			}
2594		},
2595		.volt_flags	= SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE,
2596		.volt_od	= 3,
2597		.mode_support	= SVSB_MODE_INIT02 | SVSB_MODE_MON,
2598		.freq_base	= 1400000000,
2599		.core_sel	= 0x0fff0103,
2600		.dvt_fixed	= 0x6,
2601		.vmax		= 0x65,
2602		.vmin		= 0x20,
2603	},
2604	{
2605		.pdata = (const struct svs_bank_pdata) {
2606			.sw_id			= SVSB_SWID_GPU,
2607			.set_freq_pct		= svs_set_bank_freq_pct_v2,
2608			.get_volts		= svs_get_bank_volts_v2,
2609			.tzone_name		= "gpu",
2610			.opp_count		= MAX_OPP_ENTRIES,
2611			.volt_step		= 6250,
2612			.volt_base		= 400000,
2613			.age_config		= 0x555555,
2614			.dc_config		= 0x1,
2615			.vco			= 0x10,
2616			.chk_shift		= 0x87,
2617			.int_st			= BIT(4),
2618			.ctl0			= 0x00100003,
2619			.tzone_htemp		= 85000,
2620			.tzone_htemp_voffset	= 8,
2621			.tzone_ltemp		= 25000,
2622			.tzone_ltemp_voffset	= 7,
2623			.dev_fuse_map		= (const struct svs_fusemap[BDEV_MAX]) {
2624				{ 6, 16 }, { 6, 24 }, { 6, 0 }, { 15, 8 }, { 15, 0 }
2625			}
2626		},
2627		.volt_flags	= SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE,
2628		.mode_support	= SVSB_MODE_INIT02 | SVSB_MODE_MON,
2629		.freq_base	= 850000000,
2630		.core_sel	= 0x0fff0104,
2631		.dvt_fixed	= 0x4,
2632		.vmax		= 0x58,
2633		.vmin		= 0x20,
2634	},
2635};
2636
2637static struct svs_bank svs_mt8183_banks[] = {
2638	{
2639		.pdata = (const struct svs_bank_pdata) {
2640			.sw_id			= SVSB_SWID_CPU_LITTLE,
2641			.set_freq_pct		= svs_set_bank_freq_pct_v2,
2642			.get_volts		= svs_get_bank_volts_v2,
2643			.cpu_id			= 0,
2644			.buck_name		= "proc",
2645			.opp_count		= MAX_OPP_ENTRIES,
2646			.vboot			= 0x30,
2647			.volt_step		= 6250,
2648			.volt_base		= 500000,
2649			.age_config		= 0x555555,
2650			.dc_config		= 0x555555,
2651			.vco			= 0x10,
2652			.chk_shift		= 0x77,
2653			.int_st			= BIT(0),
2654			.ctl0			= 0x00010001,
2655			.dev_fuse_map		= (const struct svs_fusemap[BDEV_MAX]) {
2656				{ 16, 0 }, { 16, 8 }, { 17, 16 }, { 16, 16 }, { 16, 24 }
2657			}
2658		},
2659		.volt_flags	= SVSB_INIT01_VOLT_INC_ONLY,
2660		.mode_support	= SVSB_MODE_INIT01 | SVSB_MODE_INIT02,
2661		.freq_base	= 1989000000,
2662		.core_sel	= 0x8fff0000,
2663		.dvt_fixed	= 0x7,
2664		.vmax		= 0x64,
2665		.vmin		= 0x18,
2666
2667	},
2668	{
2669		.pdata = (const struct svs_bank_pdata) {
2670			.sw_id			= SVSB_SWID_CPU_BIG,
2671			.set_freq_pct		= svs_set_bank_freq_pct_v2,
2672			.get_volts		= svs_get_bank_volts_v2,
2673			.cpu_id			= 4,
2674			.buck_name		= "proc",
2675			.opp_count		= MAX_OPP_ENTRIES,
2676			.vboot			= 0x30,
2677			.volt_step		= 6250,
2678			.volt_base		= 500000,
2679			.age_config		= 0x555555,
2680			.dc_config		= 0x555555,
2681			.vco			= 0x10,
2682			.chk_shift		= 0x77,
2683			.int_st			= BIT(1),
2684			.ctl0			= 0x00000001,
2685			.dev_fuse_map		= (const struct svs_fusemap[BDEV_MAX]) {
2686				{ 18, 0 }, { 18, 8 }, { 17, 0 }, { 18, 16 }, { 18, 24 }
2687			}
2688		},
2689		.volt_flags	= SVSB_INIT01_VOLT_INC_ONLY,
2690		.mode_support	= SVSB_MODE_INIT01 | SVSB_MODE_INIT02,
2691		.freq_base	= 1989000000,
2692		.core_sel	= 0x8fff0001,
2693		.dvt_fixed	= 0x7,
2694		.vmax		= 0x58,
2695		.vmin		= 0x10,
2696
2697	},
2698	{
2699		.pdata = (const struct svs_bank_pdata) {
2700			.sw_id			= SVSB_SWID_CCI,
2701			.set_freq_pct		= svs_set_bank_freq_pct_v2,
2702			.get_volts		= svs_get_bank_volts_v2,
2703			.buck_name		= "proc",
2704			.opp_count		= MAX_OPP_ENTRIES,
2705			.vboot			= 0x30,
2706			.volt_step		= 6250,
2707			.volt_base		= 500000,
2708			.age_config		= 0x555555,
2709			.dc_config		= 0x555555,
2710			.vco			= 0x10,
2711			.chk_shift		= 0x77,
2712			.int_st			= BIT(2),
2713			.ctl0			= 0x00100003,
2714			.dev_fuse_map		= (const struct svs_fusemap[BDEV_MAX]) {
2715				{ 4, 0 }, { 4, 8 }, { 5, 16 }, { 4, 16 }, { 4, 24 }
2716			}
2717		},
2718		.volt_flags	= SVSB_INIT01_VOLT_INC_ONLY,
2719		.mode_support	= SVSB_MODE_INIT01 | SVSB_MODE_INIT02,
2720		.freq_base	= 1196000000,
2721		.core_sel	= 0x8fff0002,
2722		.dvt_fixed	= 0x7,
2723		.vmax		= 0x64,
2724		.vmin		= 0x18,
2725	},
2726	{
2727		.pdata = (const struct svs_bank_pdata) {
2728			.sw_id			= SVSB_SWID_GPU,
2729			.set_freq_pct		= svs_set_bank_freq_pct_v2,
2730			.get_volts		= svs_get_bank_volts_v2,
2731			.buck_name		= "mali",
2732			.tzone_name		= "gpu",
2733			.opp_count		= MAX_OPP_ENTRIES,
2734			.vboot			= 0x30,
2735			.volt_step		= 6250,
2736			.volt_base		= 500000,
2737			.age_config		= 0x555555,
2738			.dc_config		= 0x555555,
2739			.vco			= 0x10,
2740			.chk_shift		= 0x77,
2741			.int_st			= BIT(3),
2742			.ctl0			= 0x00050001,
2743			.tzone_htemp		= 85000,
2744			.tzone_htemp_voffset	= 0,
2745			.tzone_ltemp		= 25000,
2746			.tzone_ltemp_voffset	= 3,
2747			.dev_fuse_map		= (const struct svs_fusemap[BDEV_MAX]) {
2748				{ 6, 0 }, { 6, 8 }, { 5, 0 }, { 6, 16 }, { 6, 24 }
2749			}
2750		},
2751		.volt_flags	= SVSB_INIT01_PD_REQ | SVSB_INIT01_VOLT_INC_ONLY,
2752		.mode_support	= SVSB_MODE_INIT01 | SVSB_MODE_INIT02 | SVSB_MODE_MON,
2753		.freq_base	= 900000000,
2754		.core_sel	= 0x8fff0003,
2755		.dvt_fixed	= 0x3,
2756		.vmax		= 0x40,
2757		.vmin		= 0x14,
2758	},
2759};
2760
2761static const struct svs_platform_data svs_mt8195_platform_data = {
2762	.name = "mt8195-svs",
2763	.banks = svs_mt8195_banks,
2764	.efuse_parsing = svs_common_parse_efuse,
2765	.probe = svs_mt8192_platform_probe,
2766	.regs = svs_regs_v2,
2767	.bank_max = ARRAY_SIZE(svs_mt8195_banks),
2768	.ts_coeff = SVSB_TS_COEFF_MT8195,
2769	.glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) {
2770		{ 0, 0 }, { 19, 4 }
2771	}
2772};
2773
2774static const struct svs_platform_data svs_mt8192_platform_data = {
2775	.name = "mt8192-svs",
2776	.banks = svs_mt8192_banks,
2777	.efuse_parsing = svs_common_parse_efuse,
2778	.probe = svs_mt8192_platform_probe,
2779	.regs = svs_regs_v2,
2780	.bank_max = ARRAY_SIZE(svs_mt8192_banks),
2781	.ts_coeff = SVSB_TS_COEFF_MT8195,
2782	.glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) {
2783		/* FT_PGM not present */
2784		{ -1, 0 }, { 19, 4 }
2785	}
2786};
2787
2788static const struct svs_platform_data svs_mt8188_platform_data = {
2789	.name = "mt8188-svs",
2790	.banks = svs_mt8188_banks,
2791	.efuse_parsing = svs_common_parse_efuse,
2792	.probe = svs_mt8192_platform_probe,
2793	.regs = svs_regs_v2,
2794	.bank_max = ARRAY_SIZE(svs_mt8188_banks),
2795	.ts_coeff = SVSB_TS_COEFF_MT8195,
2796	.glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) {
2797		/* FT_PGM and VMIN not present */
2798		{ -1, 0 }, { -1, 0 }
2799	}
2800};
2801
2802static const struct svs_platform_data svs_mt8186_platform_data = {
2803	.name = "mt8186-svs",
2804	.banks = svs_mt8186_banks,
2805	.efuse_parsing = svs_common_parse_efuse,
2806	.probe = svs_mt8192_platform_probe,
2807	.regs = svs_regs_v2,
2808	.bank_max = ARRAY_SIZE(svs_mt8186_banks),
2809	.ts_coeff = SVSB_TS_COEFF_MT8186,
2810	.glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) {
2811		/* FT_PGM and VMIN not present */
2812		{ -1, 0 }, { -1, 0 }
2813	}
2814};
2815
2816static const struct svs_platform_data svs_mt8183_platform_data = {
2817	.name = "mt8183-svs",
2818	.banks = svs_mt8183_banks,
2819	.efuse_parsing = svs_mt8183_efuse_parsing,
2820	.probe = svs_mt8183_platform_probe,
2821	.regs = svs_regs_v2,
2822	.bank_max = ARRAY_SIZE(svs_mt8183_banks),
2823	.glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) {
2824		/* VMIN not present */
2825		{ 0, 4 }, { -1, 0 }
2826	}
2827};
2828
2829static const struct of_device_id svs_of_match[] = {
2830	{ .compatible = "mediatek,mt8195-svs", .data = &svs_mt8195_platform_data },
2831	{ .compatible = "mediatek,mt8192-svs", .data = &svs_mt8192_platform_data },
2832	{ .compatible = "mediatek,mt8188-svs", .data = &svs_mt8188_platform_data },
2833	{ .compatible = "mediatek,mt8186-svs", .data = &svs_mt8186_platform_data },
2834	{ .compatible = "mediatek,mt8183-svs", .data = &svs_mt8183_platform_data },
2835	{ /* sentinel */ }
2836};
2837MODULE_DEVICE_TABLE(of, svs_of_match);
2838
2839static int svs_probe(struct platform_device *pdev)
2840{
2841	struct svs_platform *svsp;
2842	const struct svs_platform_data *svsp_data;
2843	int ret, svsp_irq;
2844
2845	svsp_data = of_device_get_match_data(&pdev->dev);
2846
2847	svsp = devm_kzalloc(&pdev->dev, sizeof(*svsp), GFP_KERNEL);
2848	if (!svsp)
2849		return -ENOMEM;
2850
2851	svsp->dev = &pdev->dev;
2852	svsp->banks = svsp_data->banks;
2853	svsp->regs = svsp_data->regs;
2854	svsp->bank_max = svsp_data->bank_max;
2855	svsp->ts_coeff = svsp_data->ts_coeff;
2856
2857	ret = svsp_data->probe(svsp);
2858	if (ret)
2859		return ret;
2860
2861	ret = svs_get_efuse_data(svsp, "svs-calibration-data",
2862				 &svsp->efuse, &svsp->efuse_max);
2863	if (ret)
2864		return dev_err_probe(&pdev->dev, ret, "Cannot read SVS calibration\n");
2865
2866	ret = svs_get_efuse_data(svsp, "t-calibration-data",
2867				 &svsp->tefuse, &svsp->tefuse_max);
2868	if (ret) {
2869		dev_err_probe(&pdev->dev, ret, "Cannot read SVS-Thermal calibration\n");
2870		goto svs_probe_free_efuse;
2871	}
2872
2873	if (!svsp_data->efuse_parsing(svsp, svsp_data)) {
2874		ret = dev_err_probe(svsp->dev, -EINVAL, "efuse data parsing failed\n");
2875		goto svs_probe_free_tefuse;
2876	}
2877
2878	ret = svs_bank_resource_setup(svsp);
2879	if (ret) {
2880		dev_err_probe(svsp->dev, ret, "svs bank resource setup fail\n");
2881		goto svs_probe_free_tefuse;
2882	}
2883
2884	svsp_irq = platform_get_irq(pdev, 0);
2885	if (svsp_irq < 0) {
2886		ret = svsp_irq;
2887		goto svs_probe_free_tefuse;
2888	}
2889
2890	svsp->main_clk = devm_clk_get(svsp->dev, "main");
2891	if (IS_ERR(svsp->main_clk)) {
2892		ret = dev_err_probe(svsp->dev, PTR_ERR(svsp->main_clk),
2893				    "failed to get clock\n");
2894		goto svs_probe_free_tefuse;
2895	}
2896
2897	ret = clk_prepare_enable(svsp->main_clk);
2898	if (ret) {
2899		dev_err_probe(svsp->dev, ret, "cannot enable main clk\n");
2900		goto svs_probe_free_tefuse;
2901	}
2902
2903	svsp->base = of_iomap(svsp->dev->of_node, 0);
2904	if (IS_ERR_OR_NULL(svsp->base)) {
2905		ret = dev_err_probe(svsp->dev, -EINVAL, "cannot find svs register base\n");
2906		goto svs_probe_clk_disable;
2907	}
2908
2909	ret = devm_request_threaded_irq(svsp->dev, svsp_irq, NULL, svs_isr,
2910					IRQF_ONESHOT, svsp_data->name, svsp);
2911	if (ret) {
2912		dev_err_probe(svsp->dev, ret, "register irq(%d) failed\n", svsp_irq);
2913		goto svs_probe_iounmap;
2914	}
2915
2916	ret = svs_start(svsp);
2917	if (ret) {
2918		dev_err_probe(svsp->dev, ret, "svs start fail\n");
2919		goto svs_probe_iounmap;
2920	}
2921
2922#ifdef CONFIG_DEBUG_FS
2923	ret = svs_create_debug_cmds(svsp);
2924	if (ret) {
2925		dev_err_probe(svsp->dev, ret, "svs create debug cmds fail\n");
2926		goto svs_probe_iounmap;
2927	}
2928#endif
2929
2930	return 0;
2931
2932svs_probe_iounmap:
2933	iounmap(svsp->base);
2934svs_probe_clk_disable:
2935	clk_disable_unprepare(svsp->main_clk);
2936svs_probe_free_tefuse:
2937	kfree(svsp->tefuse);
2938svs_probe_free_efuse:
2939	kfree(svsp->efuse);
2940	return ret;
2941}
2942
2943static DEFINE_SIMPLE_DEV_PM_OPS(svs_pm_ops, svs_suspend, svs_resume);
2944
2945static struct platform_driver svs_driver = {
2946	.probe	= svs_probe,
2947	.driver	= {
2948		.name		= "mtk-svs",
2949		.pm		= &svs_pm_ops,
2950		.of_match_table	= svs_of_match,
2951	},
2952};
2953
2954module_platform_driver(svs_driver);
2955
2956MODULE_AUTHOR("Roger Lu <roger.lu@mediatek.com>");
2957MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
2958MODULE_DESCRIPTION("MediaTek SVS driver");
2959MODULE_LICENSE("GPL");