mt8365-mmsys.h

 1/* SPDX-License-Identifier: GPL-2.0-only */
 2
 3#ifndef __SOC_MEDIATEK_MT8365_MMSYS_H
 4#define __SOC_MEDIATEK_MT8365_MMSYS_H
 5
 6#define MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN	0xf3c
 7#define MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL	0xf4c
 8#define MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN	0xf50
 9#define MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN	0xf54
10#define MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN	0xf60
11#define MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN	0xf64
12#define MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN		0xf68
13#define MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL	0xfd0
14#define MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN		0xfd8
15#define MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00	0xfdc
16
17#define MT8365_DISP_MS_IN_OUT_MASK			GENMASK(3, 0)
18#define MT8365_RDMA0_SOUT_COLOR0			0x1
19#define MT8365_DITHER_MOUT_EN_DSI0			BIT(0)
20#define MT8365_DSI0_SEL_IN_DITHER			0x1
21#define MT8365_RDMA0_SEL_IN_OVL0			0x0
22#define MT8365_RDMA0_RSZ0_SEL_IN_RDMA0			0x0
23#define MT8365_DISP_COLOR_SEL_IN_COLOR0			0x0
24#define MT8365_OVL0_MOUT_PATH0_SEL			BIT(0)
25#define MT8365_RDMA1_SOUT_DPI0				0x1
26#define MT8365_DPI0_SEL_IN_RDMA1			0x0
27#define MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK		0x1
28#define MT8365_DPI0_SEL_IN_RDMA1			0x0
29
30static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = {
31	MMSYS_ROUTE(OVL0, RDMA0,
32		    MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,
33		    MT8365_DISP_MS_IN_OUT_MASK, MT8365_OVL0_MOUT_PATH0_SEL),
34	MMSYS_ROUTE(OVL0, RDMA0,
35		    MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN,
36		    MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_SEL_IN_OVL0),
37	MMSYS_ROUTE(RDMA0, COLOR0,
38		    MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL,
39		    MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_SOUT_COLOR0),
40	MMSYS_ROUTE(COLOR0, CCORR,
41		    MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN,
42		    MT8365_DISP_MS_IN_OUT_MASK, MT8365_DISP_COLOR_SEL_IN_COLOR0),
43	MMSYS_ROUTE(DITHER0, DSI0,
44		    MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,
45		    MT8365_DISP_MS_IN_OUT_MASK, MT8365_DITHER_MOUT_EN_DSI0),
46	MMSYS_ROUTE(DITHER0, DSI0,
47		    MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
48		    MT8365_DISP_MS_IN_OUT_MASK, MT8365_DSI0_SEL_IN_DITHER),
49	MMSYS_ROUTE(RDMA0, COLOR0,
50		    MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN,
51		    MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_RSZ0_SEL_IN_RDMA0),
52	MMSYS_ROUTE(RDMA1, DPI0,
53		    MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00,
54		    MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK,
55		    MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK),
56	MMSYS_ROUTE(RDMA1, DPI0,
57		    MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN,
58		    MT8365_DISP_MS_IN_OUT_MASK, MT8365_DPI0_SEL_IN_RDMA1),
59	MMSYS_ROUTE(RDMA1, DPI0,
60		    MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL,
61		    MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA1_SOUT_DPI0),
62};
63
64#endif /* __SOC_MEDIATEK_MT8365_MMSYS_H */