FILE
mt8195-mmsys.h
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linux-6.19.14/drivers/soc/mediatek/mt8195-mmsys.h
1/* SPDX-License-Identifier: GPL-2.0-only */ 2 3#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H 4#define __SOC_MEDIATEK_MT8195_MMSYS_H 5 6#define MT8195_VDO0_OVL_MOUT_EN 0xf14 7#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0) 8#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1) 9#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2) 10#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4) 11#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5) 12#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6) 13 14#define MT8195_VDO0_SEL_IN 0xf34 15#define MT8195_SEL_IN_VPP_MERGE_FROM_MASK GENMASK(1, 0) 16#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0) 17#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0) 18#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0) 19#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK GENMASK(4, 4) 20#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4) 21#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4) 22#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK GENMASK(5, 5) 23#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5) 24#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5) 25#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK GENMASK(8, 8) 26#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8) 27#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8) 28#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK GENMASK(9, 9) 29#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9) 30#define MT8195_SEL_IN_DP_INTF0_FROM_MASK GENMASK(13, 12) 31#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 0) 32#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12) 33#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12) 34#define MT8195_SEL_IN_DSI0_FROM_MASK GENMASK(16, 16) 35#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 16) 36#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 16) 37#define MT8195_SEL_IN_DSI1_FROM_MASK GENMASK(17, 17) 38#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT (0 << 17) 39#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 << 17) 40#define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK GENMASK(20, 20) 41#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 (0 << 20) 42#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE (1 << 20) 43#define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK GENMASK(21, 21) 44#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0 << 21) 45#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 (1 << 21) 46#define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK GENMASK(22, 22) 47#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 (0 << 22) 48 49#define MT8195_VDO0_SEL_OUT 0xf38 50#define MT8195_SOUT_DISP_DITHER0_TO_MASK BIT(0) 51#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0) 52#define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0) 53#define MT8195_SOUT_DISP_DITHER1_TO_MASK GENMASK(2, 1) 54#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << 1) 55#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE (1 << 1) 56#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 << 1) 57#define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK GENMASK(4, 4) 58#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4) 59#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 (1 << 4) 60#define MT8195_SOUT_VPP_MERGE_TO_MASK GENMASK(10, 8) 61#define MT8195_SOUT_VPP_MERGE_TO_DSI1 (0 << 8) 62#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 8) 63#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 8) 64#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 8) 65#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 8) 66#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK(11, 11) 67#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11) 68#define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK(13, 12) 69#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 << 12) 70#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 << 12) 71#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE (2 << 12) 72#define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK GENMASK(17, 16) 73#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 << 16) 74#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 (1 << 16) 75#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16) 76#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16) 77 78#define MT8195_VDO1_SW0_RST_B 0x1d0 79#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30 80#define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70 81#define MT8195_VDO1_HDR_TOP_CFG 0xd00 82#define MT8195_VDO1_MIXER_IN1_ALPHA 0xd30 83#define MT8195_VDO1_MIXER_IN1_PAD 0xd40 84 85#define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04 86#define MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 1 87 88#define MT8195_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08 89#define MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 1 90 91#define MT8195_VDO1_DISP_DPI1_SEL_IN 0xf10 92#define MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT 0 93 94#define MT8195_VDO1_DISP_DP_INTF0_SEL_IN 0xf14 95#define MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT 0 96 97#define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18 98#define MT8195_MERGE4_SOUT_TO_DPI1_SEL 2 99#define MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL 3 100 101#define MT8195_VDO1_MIXER_IN1_SEL_IN 0xf24 102#define MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT 1 103 104#define MT8195_VDO1_MIXER_IN2_SEL_IN 0xf28 105#define MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT 1 106 107#define MT8195_VDO1_MIXER_IN3_SEL_IN 0xf2c 108#define MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT 1 109 110#define MT8195_VDO1_MIXER_IN4_SEL_IN 0xf30 111#define MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT 1 112 113#define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34 114#define MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL 1 115 116#define MT8195_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c 117#define MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 1 118 119#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40 120#define MT8195_SOUT_TO_MIXER_IN1_SEL 1 121 122#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44 123#define MT8195_SOUT_TO_MIXER_IN2_SEL 1 124 125#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48 126#define MT8195_SOUT_TO_MIXER_IN3_SEL 1 127 128#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c 129#define MT8195_SOUT_TO_MIXER_IN4_SEL 1 130 131#define MT8195_VDO1_MERGE4_ASYNC_SEL_IN 0xf50 132#define MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT 1 133 134#define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58 135#define MT8195_MIXER_IN1_SOUT_TO_DISP_MIXER 0 136 137#define MT8195_VDO1_MIXER_IN2_SOUT_SEL 0xf5c 138#define MT8195_MIXER_IN2_SOUT_TO_DISP_MIXER 0 139 140#define MT8195_VDO1_MIXER_IN3_SOUT_SEL 0xf60 141#define MT8195_MIXER_IN3_SOUT_TO_DISP_MIXER 0 142 143#define MT8195_VDO1_MIXER_IN4_SOUT_SEL 0xf64 144#define MT8195_MIXER_IN4_SOUT_TO_DISP_MIXER 0 145 146#define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68 147#define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0 148 149/* VPPSYS1 */ 150#define MT8195_VPP1_HW_DCM_1ST_DIS0 0x150 151#define MT8195_VPP1_HW_DCM_1ST_DIS1 0x160 152#define MT8195_VPP1_HW_DCM_2ND_DIS0 0x1a0 153#define MT8195_VPP1_HW_DCM_2ND_DIS1 0x1b0 154#define MT8195_SVPP2_BUF_BF_RSZ_SWITCH 0xf48 155#define MT8195_SVPP3_BUF_BF_RSZ_SWITCH 0xf74 156 157/* VPPSYS1 HW DCM client*/ 158#define MT8195_SVPP1_MDP_RSZ BIT(25) 159#define MT8195_SVPP2_MDP_RSZ BIT(4) 160#define MT8195_SVPP3_MDP_RSZ BIT(5) 161 162static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = { 163 MMSYS_ROUTE(OVL0, RDMA0, 164 MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0, 165 MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0), 166 MMSYS_ROUTE(OVL0, WDMA0, 167 MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0, 168 MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0), 169 MMSYS_ROUTE(OVL0, OVL1, 170 MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1, 171 MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1), 172 MMSYS_ROUTE(OVL1, RDMA1, 173 MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1, 174 MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1), 175 MMSYS_ROUTE(OVL1, WDMA1, 176 MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1, 177 MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1), 178 MMSYS_ROUTE(OVL1, OVL0, 179 MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0, 180 MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0), 181 MMSYS_ROUTE(DSC0, MERGE0, 182 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK, 183 MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT), 184 MMSYS_ROUTE(DITHER1, MERGE0, 185 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK, 186 MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1), 187 MMSYS_ROUTE(MERGE5, MERGE0, 188 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK, 189 MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0), 190 MMSYS_ROUTE(DITHER0, DSC0, 191 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK, 192 MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0), 193 MMSYS_ROUTE(MERGE0, DSC0, 194 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK, 195 MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE), 196 MMSYS_ROUTE(DITHER1, DSC1, 197 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK, 198 MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1), 199 MMSYS_ROUTE(MERGE0, DSC1, 200 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK, 201 MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE), 202 MMSYS_ROUTE(MERGE0, DP_INTF1, 203 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, 204 MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE), 205 MMSYS_ROUTE(MERGE0, DPI0, 206 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, 207 MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE), 208 MMSYS_ROUTE(MERGE0, DPI1, 209 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, 210 MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE), 211 MMSYS_ROUTE(DSC1, DP_INTF1, 212 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, 213 MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT), 214 MMSYS_ROUTE(DSC1, DPI0, 215 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, 216 MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT), 217 MMSYS_ROUTE(DSC1, DPI1, 218 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK, 219 MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT), 220 MMSYS_ROUTE(DSC0, DP_INTF1, 221 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK, 222 MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT), 223 MMSYS_ROUTE(DSC0, DPI0, 224 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK, 225 MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT), 226 MMSYS_ROUTE(DSC0, DPI1, 227 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK, 228 MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT), 229 MMSYS_ROUTE(DSC1, DP_INTF0, 230 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK, 231 MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT), 232 MMSYS_ROUTE(MERGE0, DP_INTF0, 233 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK, 234 MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE), 235 MMSYS_ROUTE(MERGE5, DP_INTF0, 236 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK, 237 MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0), 238 MMSYS_ROUTE(DSC0, DSI0, 239 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK, 240 MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT), 241 MMSYS_ROUTE(DITHER0, DSI0, 242 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK, 243 MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0), 244 MMSYS_ROUTE(DSC1, DSI1, 245 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK, 246 MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT), 247 MMSYS_ROUTE(MERGE0, DSI1, 248 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK, 249 MT8195_SEL_IN_DSI1_FROM_VPP_MERGE), 250 MMSYS_ROUTE(OVL1, WDMA1, 251 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK, 252 MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1), 253 MMSYS_ROUTE(MERGE0, WDMA1, 254 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK, 255 MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE), 256 MMSYS_ROUTE(DSC1, DSI1, 257 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 258 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN), 259 MMSYS_ROUTE(DSC1, DP_INTF0, 260 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 261 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN), 262 MMSYS_ROUTE(DSC1, DP_INTF1, 263 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 264 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN), 265 MMSYS_ROUTE(DSC1, DPI0, 266 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 267 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN), 268 MMSYS_ROUTE(DSC1, DPI1, 269 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 270 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN), 271 MMSYS_ROUTE(DSC1, MERGE0, 272 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 273 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN), 274 MMSYS_ROUTE(DITHER1, DSI1, 275 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 276 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1), 277 MMSYS_ROUTE(DITHER1, DP_INTF0, 278 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 279 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1), 280 MMSYS_ROUTE(DITHER1, DPI0, 281 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 282 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1), 283 MMSYS_ROUTE(DITHER1, DPI1, 284 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK, 285 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1), 286 MMSYS_ROUTE(OVL0, WDMA0, 287 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK, 288 MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0), 289 MMSYS_ROUTE(DITHER0, DSC0, 290 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK, 291 MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN), 292 MMSYS_ROUTE(DITHER0, DSI0, 293 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK, 294 MT8195_SOUT_DISP_DITHER0_TO_DSI0), 295 MMSYS_ROUTE(DITHER1, DSC1, 296 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, 297 MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN), 298 MMSYS_ROUTE(DITHER1, MERGE0, 299 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, 300 MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE), 301 MMSYS_ROUTE(DITHER1, DSI1, 302 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, 303 MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT), 304 MMSYS_ROUTE(DITHER1, DP_INTF0, 305 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, 306 MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT), 307 MMSYS_ROUTE(DITHER1, DP_INTF1, 308 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, 309 MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT), 310 MMSYS_ROUTE(DITHER1, DPI0, 311 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, 312 MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT), 313 MMSYS_ROUTE(DITHER1, DPI1, 314 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK, 315 MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT), 316 MMSYS_ROUTE(MERGE5, MERGE0, 317 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK, 318 MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE), 319 MMSYS_ROUTE(MERGE5, DP_INTF0, 320 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK, 321 MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0), 322 MMSYS_ROUTE(MERGE0, DSI1, 323 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, 324 MT8195_SOUT_VPP_MERGE_TO_DSI1), 325 MMSYS_ROUTE(MERGE0, DP_INTF0, 326 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, 327 MT8195_SOUT_VPP_MERGE_TO_DP_INTF0), 328 MMSYS_ROUTE(MERGE0, DP_INTF1, 329 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, 330 MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0), 331 MMSYS_ROUTE(MERGE0, DPI0, 332 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, 333 MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0), 334 MMSYS_ROUTE(MERGE0, DPI1, 335 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, 336 MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0), 337 MMSYS_ROUTE(MERGE0, WDMA1, 338 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, 339 MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1), 340 MMSYS_ROUTE(MERGE0, DSC0, 341 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, 342 MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN), 343 MMSYS_ROUTE(MERGE0, DSC1, 344 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK, 345 MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN), 346 MMSYS_ROUTE(DSC0, DSI0, 347 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, 348 MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0), 349 MMSYS_ROUTE(DSC0, DP_INTF1, 350 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, 351 MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0), 352 MMSYS_ROUTE(DSC0, DPI0, 353 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, 354 MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0), 355 MMSYS_ROUTE(DSC0, DPI1, 356 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, 357 MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0), 358 MMSYS_ROUTE(DSC0, MERGE0, 359 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK, 360 MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE), 361 MMSYS_ROUTE(DSC1, DSI1, 362 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, 363 MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1), 364 MMSYS_ROUTE(DSC1, DP_INTF0, 365 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, 366 MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0), 367 MMSYS_ROUTE(DSC1, DP_INTF1, 368 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, 369 MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0), 370 MMSYS_ROUTE(DSC1, DPI0, 371 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, 372 MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0), 373 MMSYS_ROUTE(DSC1, DPI1, 374 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, 375 MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0), 376 MMSYS_ROUTE(DSC1, MERGE0, 377 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK, 378 MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE), 379}; 380 381static const struct mtk_mmsys_routes mmsys_mt8195_vdo1_routing_table[] = { 382 MMSYS_ROUTE(MDP_RDMA0, MERGE1, 383 MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0), 384 MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0), 385 MMSYS_ROUTE(MDP_RDMA1, MERGE1, 386 MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0), 387 MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1), 388 MMSYS_ROUTE(MDP_RDMA2, MERGE2, 389 MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0), 390 MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2), 391 MMSYS_ROUTE(MERGE1, ETHDR_MIXER, 392 MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0), 393 MT8195_SOUT_TO_MIXER_IN1_SEL), 394 MMSYS_ROUTE(MERGE2, ETHDR_MIXER, 395 MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0), 396 MT8195_SOUT_TO_MIXER_IN2_SEL), 397 MMSYS_ROUTE(MERGE3, ETHDR_MIXER, 398 MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0), 399 MT8195_SOUT_TO_MIXER_IN3_SEL), 400 MMSYS_ROUTE(MERGE4, ETHDR_MIXER, 401 MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0), 402 MT8195_SOUT_TO_MIXER_IN4_SEL), 403 MMSYS_ROUTE(ETHDR_MIXER, MERGE5, 404 MT8195_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0), 405 MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL), 406 MMSYS_ROUTE(MERGE1, ETHDR_MIXER, 407 MT8195_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0), 408 MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT), 409 MMSYS_ROUTE(MERGE2, ETHDR_MIXER, 410 MT8195_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0), 411 MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT), 412 MMSYS_ROUTE(MERGE3, ETHDR_MIXER, 413 MT8195_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0), 414 MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT), 415 MMSYS_ROUTE(MERGE4, ETHDR_MIXER, 416 MT8195_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0), 417 MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT), 418 MMSYS_ROUTE(ETHDR_MIXER, MERGE5, 419 MT8195_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0), 420 MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER), 421 MMSYS_ROUTE(ETHDR_MIXER, MERGE5, 422 MT8195_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0), 423 MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT), 424 MMSYS_ROUTE(MERGE5, DPI1, 425 MT8195_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0), 426 MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT), 427 MMSYS_ROUTE(MERGE5, DPI1, 428 MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0), 429 MT8195_MERGE4_SOUT_TO_DPI1_SEL), 430 MMSYS_ROUTE(MERGE5, DP_INTF1, 431 MT8195_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0), 432 MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT), 433 MMSYS_ROUTE(MERGE5, DP_INTF1, 434 MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0), 435 MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL), 436}; 437#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
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