mt8173-mmsys.h

 1/* SPDX-License-Identifier: GPL-2.0-only */
 2
 3#ifndef __SOC_MEDIATEK_MT8173_MMSYS_H
 4#define __SOC_MEDIATEK_MT8173_MMSYS_H
 5
 6#define MT8173_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN	0x040
 7#define MT8173_DISP_REG_CONFIG_DISP_OVL1_MOUT_EN	0x044
 8#define MT8173_DISP_REG_CONFIG_DISP_OD_MOUT_EN		0x048
 9#define MT8173_DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN	0x04c
10#define MT8173_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN	0x050
11#define MT8173_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN	0x084
12#define MT8173_DISP_REG_CONFIG_DISP_COLOR1_SEL_IN	0x088
13#define MT8173_DISP_REG_CONFIG_DISP_AAL_SEL_IN		0x08c
14#define MT8173_DISP_REG_CONFIG_DISP_UFOE_SEL_IN		0x0a0
15#define MT8173_DISP_REG_CONFIG_DSI0_SEL_IN		0x0a4
16#define MT8173_DISP_REG_CONFIG_DPI_SEL_IN		0x0ac
17#define MT8173_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN	0x0b0
18#define MT8173_DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN	0x0c8
19#define MT8173_DISP_REG_CONFIG_DISP_COLOR0_SOUT_SEL_IN	0x0bc
20
21#define MT8173_AAL_SEL_IN_MERGE				BIT(0)
22#define MT8173_COLOR0_SEL_IN_OVL0			BIT(0)
23#define MT8173_COLOR0_SOUT_MERGE			BIT(0)
24#define MT8173_DPI0_SEL_IN_MASK				GENMASK(1, 0)
25#define MT8173_DPI0_SEL_IN_RDMA1			BIT(0)
26#define MT8173_DSI0_SEL_IN_UFOE				BIT(0)
27#define MT8173_GAMMA_MOUT_EN_RDMA1			BIT(0)
28#define MT8173_OD0_MOUT_EN_RDMA0			BIT(0)
29#define MT8173_OVL0_MOUT_EN_COLOR0			BIT(0)
30#define MT8173_OVL1_MOUT_EN_COLOR1			BIT(0)
31#define MT8173_UFOE_MOUT_EN_DSI0			BIT(0)
32#define MT8173_UFOE_SEL_IN_RDMA0			BIT(0)
33#define MT8173_RDMA0_SOUT_COLOR0			BIT(0)
34
35static const struct mtk_mmsys_routes mt8173_mmsys_routing_table[] = {
36	MMSYS_ROUTE(OVL0, COLOR0,
37		    MT8173_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, MT8173_OVL0_MOUT_EN_COLOR0,
38		    MT8173_OVL0_MOUT_EN_COLOR0),
39	MMSYS_ROUTE(OD0, RDMA0,
40		    MT8173_DISP_REG_CONFIG_DISP_OD_MOUT_EN, MT8173_OD0_MOUT_EN_RDMA0,
41		    MT8173_OD0_MOUT_EN_RDMA0),
42	MMSYS_ROUTE(UFOE, DSI0,
43		    MT8173_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, MT8173_UFOE_MOUT_EN_DSI0,
44		    MT8173_UFOE_MOUT_EN_DSI0),
45	MMSYS_ROUTE(COLOR0, AAL0,
46		    MT8173_DISP_REG_CONFIG_DISP_COLOR0_SOUT_SEL_IN, MT8173_COLOR0_SOUT_MERGE,
47		    0 /* SOUT to AAL */),
48	MMSYS_ROUTE(RDMA0, UFOE,
49		    MT8173_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8173_RDMA0_SOUT_COLOR0,
50		    0 /* SOUT to UFOE */),
51	MMSYS_ROUTE(OVL0, COLOR0,
52		    MT8173_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, MT8173_COLOR0_SEL_IN_OVL0,
53		    MT8173_COLOR0_SEL_IN_OVL0),
54	MMSYS_ROUTE(AAL0, COLOR0,
55		    MT8173_DISP_REG_CONFIG_DISP_AAL_SEL_IN, MT8173_AAL_SEL_IN_MERGE,
56		    0 /* SEL_IN from COLOR0 */),
57	MMSYS_ROUTE(RDMA0, UFOE,
58		    MT8173_DISP_REG_CONFIG_DISP_UFOE_SEL_IN, MT8173_UFOE_SEL_IN_RDMA0,
59		    0 /* SEL_IN from RDMA0 */),
60	MMSYS_ROUTE(UFOE, DSI0,
61		    MT8173_DISP_REG_CONFIG_DSI0_SEL_IN, MT8173_DSI0_SEL_IN_UFOE,
62		    0 /* SEL_IN from UFOE */),
63	MMSYS_ROUTE(OVL1, COLOR1,
64		    MT8173_DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, MT8173_OVL1_MOUT_EN_COLOR1,
65		    MT8173_OVL1_MOUT_EN_COLOR1),
66	MMSYS_ROUTE(GAMMA, RDMA1,
67		    MT8173_DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, MT8173_GAMMA_MOUT_EN_RDMA1,
68		    MT8173_GAMMA_MOUT_EN_RDMA1),
69	MMSYS_ROUTE(RDMA1, DPI0,
70		    MT8173_DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
71		    RDMA1_SOUT_DPI0),
72	MMSYS_ROUTE(OVL1, COLOR1,
73		    MT8173_DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1,
74		    COLOR1_SEL_IN_OVL1),
75	MMSYS_ROUTE(RDMA1, DPI0,
76		    MT8173_DISP_REG_CONFIG_DPI_SEL_IN, MT8173_DPI0_SEL_IN_MASK,
77		    MT8173_DPI0_SEL_IN_RDMA1),
78};
79
80#endif /* __SOC_MEDIATEK_MT8173_MMSYS_H */