soc-imx8m.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright 2019 NXP.
  4 */
  5
  6#include <linux/init.h>
  7#include <linux/io.h>
  8#include <linux/of_address.h>
  9#include <linux/slab.h>
 10#include <linux/sys_soc.h>
 11#include <linux/platform_device.h>
 12#include <linux/arm-smccc.h>
 13#include <linux/of.h>
 14#include <linux/clk.h>
 15
 16#define REV_B1				0x21
 17
 18#define IMX8MQ_SW_INFO_B1		0x40
 19#define IMX8MQ_SW_MAGIC_B1		0xff0055aa
 20
 21#define IMX_SIP_GET_SOC_INFO		0xc2000006
 22
 23#define OCOTP_UID_LOW			0x410
 24#define OCOTP_UID_HIGH			0x420
 25
 26#define IMX8MP_OCOTP_UID_OFFSET		0x10
 27#define IMX8MP_OCOTP_UID_HIGH		0xE00
 28
 29/* Same as ANADIG_DIGPROG_IMX7D */
 30#define ANADIG_DIGPROG_IMX8MM	0x800
 31
 32struct imx8_soc_data {
 33	char *name;
 34	const char *ocotp_compatible;
 35	int (*soc_revision)(struct platform_device *pdev, u32 *socrev);
 36	int (*soc_uid)(struct platform_device *pdev, u64 *socuid);
 37};
 38
 39struct imx8_soc_drvdata {
 40	void __iomem *ocotp_base;
 41	struct clk *clk;
 42};
 43
 44#ifdef CONFIG_HAVE_ARM_SMCCC
 45static u32 imx8mq_soc_revision_from_atf(void)
 46{
 47	struct arm_smccc_res res;
 48
 49	arm_smccc_smc(IMX_SIP_GET_SOC_INFO, 0, 0, 0, 0, 0, 0, 0, &res);
 50
 51	if (res.a0 == SMCCC_RET_NOT_SUPPORTED)
 52		return 0;
 53	else
 54		return res.a0 & 0xff;
 55}
 56#else
 57static inline u32 imx8mq_soc_revision_from_atf(void) { return 0; };
 58#endif
 59
 60static int imx8m_soc_uid(struct platform_device *pdev, u64 *socuid)
 61{
 62	struct imx8_soc_drvdata *drvdata = platform_get_drvdata(pdev);
 63	void __iomem *ocotp_base = drvdata->ocotp_base;
 64
 65	*socuid = readl_relaxed(ocotp_base + OCOTP_UID_HIGH);
 66	*socuid <<= 32;
 67	*socuid |= readl_relaxed(ocotp_base + OCOTP_UID_LOW);
 68
 69	return 0;
 70}
 71
 72static int imx8mq_soc_revision(struct platform_device *pdev, u32 *socrev)
 73{
 74	struct imx8_soc_drvdata *drvdata = platform_get_drvdata(pdev);
 75	void __iomem *ocotp_base = drvdata->ocotp_base;
 76	u32 magic;
 77	u32 rev;
 78
 79	/*
 80	 * SOC revision on older imx8mq is not available in fuses so query
 81	 * the value from ATF instead.
 82	 */
 83	rev = imx8mq_soc_revision_from_atf();
 84	if (!rev) {
 85		magic = readl_relaxed(ocotp_base + IMX8MQ_SW_INFO_B1);
 86		if (magic == IMX8MQ_SW_MAGIC_B1)
 87			rev = REV_B1;
 88	}
 89
 90	*socrev = rev;
 91
 92	return 0;
 93}
 94
 95static int imx8mp_soc_uid(struct platform_device *pdev, u64 *socuid)
 96{
 97	struct imx8_soc_drvdata *drvdata = platform_get_drvdata(pdev);
 98	void __iomem *ocotp_base = drvdata->ocotp_base;
 99
100	socuid[0] = readl_relaxed(ocotp_base + OCOTP_UID_HIGH + IMX8MP_OCOTP_UID_OFFSET);
101	socuid[0] <<= 32;
102	socuid[0] |= readl_relaxed(ocotp_base + OCOTP_UID_LOW + IMX8MP_OCOTP_UID_OFFSET);
103
104	socuid[1] = readl_relaxed(ocotp_base + IMX8MP_OCOTP_UID_HIGH + 0x10);
105	socuid[1] <<= 32;
106	socuid[1] |= readl_relaxed(ocotp_base + IMX8MP_OCOTP_UID_HIGH);
107
108	return 0;
109}
110
111static int imx8mm_soc_revision(struct platform_device *pdev, u32 *socrev)
112{
113	struct device_node *np __free(device_node) =
114		of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop");
115	void __iomem *anatop_base;
116
117	if (!np)
118		return -EINVAL;
119
120	anatop_base = of_iomap(np, 0);
121	if (!anatop_base)
122		return -EINVAL;
123
124	*socrev = readl_relaxed(anatop_base + ANADIG_DIGPROG_IMX8MM);
125
126	iounmap(anatop_base);
127
128	return 0;
129}
130
131static int imx8m_soc_prepare(struct platform_device *pdev, const char *ocotp_compatible)
132{
133	struct device_node *np __free(device_node) =
134		of_find_compatible_node(NULL, NULL, ocotp_compatible);
135	struct imx8_soc_drvdata *drvdata = platform_get_drvdata(pdev);
136	int ret = 0;
137
138	if (!np)
139		return -EINVAL;
140
141	drvdata->ocotp_base = of_iomap(np, 0);
142	if (!drvdata->ocotp_base)
143		return -EINVAL;
144
145	drvdata->clk = of_clk_get_by_name(np, NULL);
146	if (IS_ERR(drvdata->clk)) {
147		ret = PTR_ERR(drvdata->clk);
148		goto err_clk;
149	}
150
151	ret = clk_prepare_enable(drvdata->clk);
152	if (ret)
153		goto err_clk;
154
155	return 0;
156
157err_clk:
158	iounmap(drvdata->ocotp_base);
159	return ret;
160}
161
162static void imx8m_soc_unprepare(struct platform_device *pdev)
163{
164	struct imx8_soc_drvdata *drvdata = platform_get_drvdata(pdev);
165
166	clk_disable_unprepare(drvdata->clk);
167	clk_put(drvdata->clk);
168	iounmap(drvdata->ocotp_base);
169}
170
171static const struct imx8_soc_data imx8mq_soc_data = {
172	.name = "i.MX8MQ",
173	.ocotp_compatible = "fsl,imx8mq-ocotp",
174	.soc_revision = imx8mq_soc_revision,
175	.soc_uid = imx8m_soc_uid,
176};
177
178static const struct imx8_soc_data imx8mm_soc_data = {
179	.name = "i.MX8MM",
180	.ocotp_compatible = "fsl,imx8mm-ocotp",
181	.soc_revision = imx8mm_soc_revision,
182	.soc_uid = imx8m_soc_uid,
183};
184
185static const struct imx8_soc_data imx8mn_soc_data = {
186	.name = "i.MX8MN",
187	.ocotp_compatible = "fsl,imx8mm-ocotp",
188	.soc_revision = imx8mm_soc_revision,
189	.soc_uid = imx8m_soc_uid,
190};
191
192static const struct imx8_soc_data imx8mp_soc_data = {
193	.name = "i.MX8MP",
194	.ocotp_compatible = "fsl,imx8mm-ocotp",
195	.soc_revision = imx8mm_soc_revision,
196	.soc_uid = imx8mp_soc_uid,
197};
198
199static __maybe_unused const struct of_device_id imx8_soc_match[] = {
200	{ .compatible = "fsl,imx8mq", .data = &imx8mq_soc_data, },
201	{ .compatible = "fsl,imx8mm", .data = &imx8mm_soc_data, },
202	{ .compatible = "fsl,imx8mn", .data = &imx8mn_soc_data, },
203	{ .compatible = "fsl,imx8mp", .data = &imx8mp_soc_data, },
204	{ }
205};
206
207#define imx8_revision(dev, soc_rev) \
208	(soc_rev) ? \
209	devm_kasprintf((dev), GFP_KERNEL, "%d.%d", ((soc_rev) >> 4) & 0xf, (soc_rev) & 0xf) : \
210	"unknown"
211
212static void imx8m_unregister_soc(void *data)
213{
214	soc_device_unregister(data);
215}
216
217static void imx8m_unregister_cpufreq(void *data)
218{
219	platform_device_unregister(data);
220}
221
222static int imx8m_soc_probe(struct platform_device *pdev)
223{
224	struct soc_device_attribute *soc_dev_attr;
225	struct platform_device *cpufreq_dev;
226	const struct imx8_soc_data *data;
227	struct imx8_soc_drvdata *drvdata;
228	struct device *dev = &pdev->dev;
229	const struct of_device_id *id;
230	struct soc_device *soc_dev;
231	u32 soc_rev = 0;
232	u64 soc_uid[2] = {0, 0};
233	int ret;
234
235	soc_dev_attr = devm_kzalloc(dev, sizeof(*soc_dev_attr), GFP_KERNEL);
236	if (!soc_dev_attr)
237		return -ENOMEM;
238
239	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
240	if (!drvdata)
241		return -ENOMEM;
242
243	platform_set_drvdata(pdev, drvdata);
244
245	soc_dev_attr->family = "Freescale i.MX";
246
247	ret = of_property_read_string(of_root, "model", &soc_dev_attr->machine);
248	if (ret)
249		return ret;
250
251	id = of_match_node(imx8_soc_match, of_root);
252	if (!id)
253		return -ENODEV;
254
255	data = id->data;
256	if (data) {
257		soc_dev_attr->soc_id = data->name;
258		ret = imx8m_soc_prepare(pdev, data->ocotp_compatible);
259		if (ret)
260			return ret;
261
262		if (data->soc_revision) {
263			ret = data->soc_revision(pdev, &soc_rev);
264			if (ret) {
265				imx8m_soc_unprepare(pdev);
266				return ret;
267			}
268		}
269		if (data->soc_uid) {
270			ret = data->soc_uid(pdev, soc_uid);
271			if (ret) {
272				imx8m_soc_unprepare(pdev);
273				return ret;
274			}
275		}
276		imx8m_soc_unprepare(pdev);
277	}
278
279	soc_dev_attr->revision = imx8_revision(dev, soc_rev);
280	if (!soc_dev_attr->revision)
281		return -ENOMEM;
282
283	if (soc_uid[1])
284		soc_dev_attr->serial_number = devm_kasprintf(dev, GFP_KERNEL, "%016llX%016llX",
285							     soc_uid[1], soc_uid[0]);
286	else
287		soc_dev_attr->serial_number = devm_kasprintf(dev, GFP_KERNEL, "%016llX",
288							     soc_uid[0]);
289	if (!soc_dev_attr->serial_number)
290		return -ENOMEM;
291
292	soc_dev = soc_device_register(soc_dev_attr);
293	if (IS_ERR(soc_dev))
294		return PTR_ERR(soc_dev);
295
296	ret = devm_add_action(dev, imx8m_unregister_soc, soc_dev);
297	if (ret)
298		return ret;
299
300	pr_info("SoC: %s revision %s\n", soc_dev_attr->soc_id,
301		soc_dev_attr->revision);
302
303	if (IS_ENABLED(CONFIG_ARM_IMX_CPUFREQ_DT)) {
304		cpufreq_dev = platform_device_register_simple("imx-cpufreq-dt", -1, NULL, 0);
305		if (IS_ERR(cpufreq_dev))
306			return dev_err_probe(dev, PTR_ERR(cpufreq_dev),
307					     "Failed to register imx-cpufreq-dev device\n");
308		ret = devm_add_action(dev, imx8m_unregister_cpufreq, cpufreq_dev);
309		if (ret)
310			return ret;
311	}
312
313	return 0;
314}
315
316static struct platform_driver imx8m_soc_driver = {
317	.probe = imx8m_soc_probe,
318	.driver = {
319		.name = "imx8m-soc",
320	},
321};
322
323static int __init imx8_soc_init(void)
324{
325	struct platform_device *pdev;
326	int ret;
327
328	/* No match means this is non-i.MX8M hardware, do nothing. */
329	if (!of_match_node(imx8_soc_match, of_root))
330		return 0;
331
332	ret = platform_driver_register(&imx8m_soc_driver);
333	if (ret) {
334		pr_err("Failed to register imx8m-soc platform driver: %d\n", ret);
335		return ret;
336	}
337
338	pdev = platform_device_register_simple("imx8m-soc", -1, NULL, 0);
339	if (IS_ERR(pdev)) {
340		pr_err("Failed to register imx8m-soc platform device: %ld\n", PTR_ERR(pdev));
341		platform_driver_unregister(&imx8m_soc_driver);
342		return PTR_ERR(pdev);
343	}
344
345	return 0;
346}
347device_initcall(imx8_soc_init);
348MODULE_DESCRIPTION("NXP i.MX8M SoC driver");
349MODULE_LICENSE("GPL");