gpio.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * QUICC Engine GPIOs
  4 *
  5 * Copyright (c) MontaVista Software, Inc. 2008.
  6 *
  7 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
  8 */
  9
 10#include <linux/kernel.h>
 11#include <linux/init.h>
 12#include <linux/spinlock.h>
 13#include <linux/err.h>
 14#include <linux/io.h>
 15#include <linux/gpio/consumer.h>
 16#include <linux/gpio/driver.h>
 17#include <linux/slab.h>
 18#include <linux/export.h>
 19#include <linux/platform_device.h>
 20
 21#include <soc/fsl/qe/qe.h>
 22
 23#define PIN_MASK(gpio) (1UL << (QE_PIO_PINS - 1 - (gpio)))
 24
 25struct qe_gpio_chip {
 26	struct gpio_chip gc;
 27	void __iomem *regs;
 28	spinlock_t lock;
 29
 30	/* shadowed data register to clear/set bits safely */
 31	u32 cpdata;
 32
 33	/* saved_regs used to restore dedicated functions */
 34	struct qe_pio_regs saved_regs;
 35};
 36
 37static void qe_gpio_save_regs(struct qe_gpio_chip *qe_gc)
 38{
 39	struct qe_pio_regs __iomem *regs = qe_gc->regs;
 40
 41	qe_gc->cpdata = ioread32be(&regs->cpdata);
 42	qe_gc->saved_regs.cpdata = qe_gc->cpdata;
 43	qe_gc->saved_regs.cpdir1 = ioread32be(&regs->cpdir1);
 44	qe_gc->saved_regs.cpdir2 = ioread32be(&regs->cpdir2);
 45	qe_gc->saved_regs.cppar1 = ioread32be(&regs->cppar1);
 46	qe_gc->saved_regs.cppar2 = ioread32be(&regs->cppar2);
 47	qe_gc->saved_regs.cpodr = ioread32be(&regs->cpodr);
 48}
 49
 50static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
 51{
 52	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
 53	struct qe_pio_regs __iomem *regs = qe_gc->regs;
 54	u32 pin_mask = PIN_MASK(gpio);
 55
 56	return !!(ioread32be(&regs->cpdata) & pin_mask);
 57}
 58
 59static int qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
 60{
 61	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
 62	struct qe_pio_regs __iomem *regs = qe_gc->regs;
 63	unsigned long flags;
 64	u32 pin_mask = PIN_MASK(gpio);
 65
 66	spin_lock_irqsave(&qe_gc->lock, flags);
 67
 68	if (val)
 69		qe_gc->cpdata |= pin_mask;
 70	else
 71		qe_gc->cpdata &= ~pin_mask;
 72
 73	iowrite32be(qe_gc->cpdata, &regs->cpdata);
 74
 75	spin_unlock_irqrestore(&qe_gc->lock, flags);
 76
 77	return 0;
 78}
 79
 80static int qe_gpio_set_multiple(struct gpio_chip *gc,
 81				unsigned long *mask, unsigned long *bits)
 82{
 83	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
 84	struct qe_pio_regs __iomem *regs = qe_gc->regs;
 85	unsigned long flags;
 86	int i;
 87
 88	spin_lock_irqsave(&qe_gc->lock, flags);
 89
 90	for (i = 0; i < gc->ngpio; i++) {
 91		if (*mask == 0)
 92			break;
 93		if (__test_and_clear_bit(i, mask)) {
 94			if (test_bit(i, bits))
 95				qe_gc->cpdata |= PIN_MASK(i);
 96			else
 97				qe_gc->cpdata &= ~PIN_MASK(i);
 98		}
 99	}
100
101	iowrite32be(qe_gc->cpdata, &regs->cpdata);
102
103	spin_unlock_irqrestore(&qe_gc->lock, flags);
104
105	return 0;
106}
107
108static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
109{
110	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
111	unsigned long flags;
112
113	spin_lock_irqsave(&qe_gc->lock, flags);
114
115	__par_io_config_pin(qe_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0);
116
117	spin_unlock_irqrestore(&qe_gc->lock, flags);
118
119	return 0;
120}
121
122static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
123{
124	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
125	unsigned long flags;
126
127	qe_gpio_set(gc, gpio, val);
128
129	spin_lock_irqsave(&qe_gc->lock, flags);
130
131	__par_io_config_pin(qe_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0);
132
133	spin_unlock_irqrestore(&qe_gc->lock, flags);
134
135	return 0;
136}
137
138struct qe_pin {
139	/*
140	 * The qe_gpio_chip name is unfortunate, we should change that to
141	 * something like qe_pio_controller. Someday.
142	 */
143	struct qe_gpio_chip *controller;
144	int num;
145};
146
147/**
148 * qe_pin_request - Request a QE pin
149 * @dev:	device to get the pin from
150 * @index:	index of the pin in the device tree
151 * Context:	non-atomic
152 *
153 * This function return qe_pin so that you could use it with the rest of
154 * the QE Pin Multiplexing API.
155 */
156struct qe_pin *qe_pin_request(struct device *dev, int index)
157{
158	struct qe_pin *qe_pin;
159	struct gpio_chip *gc;
160	struct gpio_desc *gpiod;
161	int gpio_num;
162	int err;
163
164	qe_pin = kzalloc(sizeof(*qe_pin), GFP_KERNEL);
165	if (!qe_pin) {
166		dev_dbg(dev, "%s: can't allocate memory\n", __func__);
167		return ERR_PTR(-ENOMEM);
168	}
169
170	/*
171	 * Request gpio as nonexclusive as it was likely reserved by the
172	 * caller, and we are not planning on controlling it, we only need
173	 * the descriptor to the to the gpio chip structure.
174	 */
175	gpiod = gpiod_get_index(dev, NULL, index,
176			        GPIOD_ASIS | GPIOD_FLAGS_BIT_NONEXCLUSIVE);
177	err = PTR_ERR_OR_ZERO(gpiod);
178	if (err)
179		goto err0;
180
181	gc = gpiod_to_chip(gpiod);
182	gpio_num = desc_to_gpio(gpiod);
183	/* We no longer need this descriptor */
184	gpiod_put(gpiod);
185
186	if (WARN_ON(!gc)) {
187		err = -ENODEV;
188		goto err0;
189	}
190
191	qe_pin->controller = gpiochip_get_data(gc);
192	/*
193	 * FIXME: this gets the local offset on the gpio_chip so that the driver
194	 * can manipulate pin control settings through its custom API. The real
195	 * solution is to create a real pin control driver for this.
196	 */
197	qe_pin->num = gpio_num - gc->base;
198
199	if (!fwnode_device_is_compatible(gc->fwnode, "fsl,mpc8323-qe-pario-bank")) {
200		dev_dbg(dev, "%s: tried to get a non-qe pin\n", __func__);
201		err = -EINVAL;
202		goto err0;
203	}
204	return qe_pin;
205err0:
206	kfree(qe_pin);
207	dev_dbg(dev, "%s failed with status %d\n", __func__, err);
208	return ERR_PTR(err);
209}
210EXPORT_SYMBOL(qe_pin_request);
211
212/**
213 * qe_pin_free - Free a pin
214 * @qe_pin:	pointer to the qe_pin structure
215 * Context:	any
216 *
217 * This function frees the qe_pin structure and makes a pin available
218 * for further qe_pin_request() calls.
219 */
220void qe_pin_free(struct qe_pin *qe_pin)
221{
222	kfree(qe_pin);
223}
224EXPORT_SYMBOL(qe_pin_free);
225
226/**
227 * qe_pin_set_dedicated - Revert a pin to a dedicated peripheral function mode
228 * @qe_pin:	pointer to the qe_pin structure
229 * Context:	any
230 *
231 * This function resets a pin to a dedicated peripheral function that
232 * has been set up by the firmware.
233 */
234void qe_pin_set_dedicated(struct qe_pin *qe_pin)
235{
236	struct qe_gpio_chip *qe_gc = qe_pin->controller;
237	struct qe_pio_regs __iomem *regs = qe_gc->regs;
238	struct qe_pio_regs *sregs = &qe_gc->saved_regs;
239	int pin = qe_pin->num;
240	u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1));
241	u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2);
242	bool second_reg = pin > (QE_PIO_PINS / 2) - 1;
243	unsigned long flags;
244
245	spin_lock_irqsave(&qe_gc->lock, flags);
246
247	if (second_reg) {
248		qe_clrsetbits_be32(&regs->cpdir2, mask2,
249				   sregs->cpdir2 & mask2);
250		qe_clrsetbits_be32(&regs->cppar2, mask2,
251				   sregs->cppar2 & mask2);
252	} else {
253		qe_clrsetbits_be32(&regs->cpdir1, mask2,
254				   sregs->cpdir1 & mask2);
255		qe_clrsetbits_be32(&regs->cppar1, mask2,
256				   sregs->cppar1 & mask2);
257	}
258
259	if (sregs->cpdata & mask1)
260		qe_gc->cpdata |= mask1;
261	else
262		qe_gc->cpdata &= ~mask1;
263
264	iowrite32be(qe_gc->cpdata, &regs->cpdata);
265	qe_clrsetbits_be32(&regs->cpodr, mask1, sregs->cpodr & mask1);
266	spin_unlock_irqrestore(&qe_gc->lock, flags);
267}
268EXPORT_SYMBOL(qe_pin_set_dedicated);
269
270/**
271 * qe_pin_set_gpio - Set a pin to the GPIO mode
272 * @qe_pin:	pointer to the qe_pin structure
273 * Context:	any
274 *
275 * This function sets a pin to the GPIO mode.
276 */
277void qe_pin_set_gpio(struct qe_pin *qe_pin)
278{
279	struct qe_gpio_chip *qe_gc = qe_pin->controller;
280	struct qe_pio_regs __iomem *regs = qe_gc->regs;
281	unsigned long flags;
282
283	spin_lock_irqsave(&qe_gc->lock, flags);
284
285	/* Let's make it input by default, GPIO API is able to change that. */
286	__par_io_config_pin(regs, qe_pin->num, QE_PIO_DIR_IN, 0, 0, 0);
287
288	spin_unlock_irqrestore(&qe_gc->lock, flags);
289}
290EXPORT_SYMBOL(qe_pin_set_gpio);
291
292static int qe_gpio_probe(struct platform_device *ofdev)
293{
294	struct device *dev = &ofdev->dev;
295	struct device_node *np = dev->of_node;
296	struct qe_gpio_chip *qe_gc;
297	struct gpio_chip *gc;
298
299	qe_gc = devm_kzalloc(dev, sizeof(*qe_gc), GFP_KERNEL);
300	if (!qe_gc)
301		return -ENOMEM;
302
303	spin_lock_init(&qe_gc->lock);
304
305	gc = &qe_gc->gc;
306
307	gc->base = -1;
308	gc->ngpio = QE_PIO_PINS;
309	gc->direction_input = qe_gpio_dir_in;
310	gc->direction_output = qe_gpio_dir_out;
311	gc->get = qe_gpio_get;
312	gc->set = qe_gpio_set;
313	gc->set_multiple = qe_gpio_set_multiple;
314	gc->parent = dev;
315	gc->owner = THIS_MODULE;
316
317	gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", np);
318	if (!gc->label)
319		return -ENOMEM;
320
321	qe_gc->regs = devm_of_iomap(dev, np, 0, NULL);
322	if (IS_ERR(qe_gc->regs))
323		return PTR_ERR(qe_gc->regs);
324
325	qe_gpio_save_regs(qe_gc);
326
327	return devm_gpiochip_add_data(dev, gc, qe_gc);
328}
329
330static const struct of_device_id qe_gpio_match[] = {
331	{
332		.compatible = "fsl,mpc8323-qe-pario-bank",
333	},
334	{},
335};
336MODULE_DEVICE_TABLE(of, qe_gpio_match);
337
338static struct platform_driver qe_gpio_driver = {
339	.probe		= qe_gpio_probe,
340	.driver		= {
341		.name	= "qe-gpio",
342		.of_match_table	= qe_gpio_match,
343	},
344};
345
346static int __init qe_gpio_init(void)
347{
348	return platform_driver_register(&qe_gpio_driver);
349}
350arch_initcall(qe_gpio_init);