meson-clk-measure.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (c) 2018 BayLibre, SAS
   4 * Author: Neil Armstrong <narmstrong@baylibre.com>
   5 */
   6
   7#include <linux/of_address.h>
   8#include <linux/platform_device.h>
   9#include <linux/bitfield.h>
  10#include <linux/seq_file.h>
  11#include <linux/debugfs.h>
  12#include <linux/regmap.h>
  13#include <linux/module.h>
  14
  15static DEFINE_MUTEX(measure_lock);
  16
  17#define MSR_DURATION		GENMASK(15, 0)
  18#define MSR_ENABLE		BIT(16)
  19#define MSR_CONT		BIT(17) /* continuous measurement */
  20#define MSR_INTR		BIT(18) /* interrupts */
  21#define MSR_RUN			BIT(19)
  22#define MSR_CLK_SRC		GENMASK(26, 20)
  23#define MSR_BUSY		BIT(31)
  24
  25#define MSR_VAL_MASK		GENMASK(15, 0)
  26
  27#define DIV_MIN			32
  28#define DIV_STEP		32
  29#define DIV_MAX			640
  30
  31struct meson_msr_id {
  32	struct meson_msr *priv;
  33	unsigned int id;
  34	const char *name;
  35};
  36
  37struct msr_reg_offset {
  38	unsigned int duty_val;
  39	unsigned int freq_ctrl;
  40	unsigned int duty_ctrl;
  41	unsigned int freq_val;
  42};
  43
  44struct meson_msr_data {
  45	struct meson_msr_id *msr_table;
  46	unsigned int msr_count;
  47	const struct msr_reg_offset *reg;
  48};
  49
  50struct meson_msr {
  51	struct regmap *regmap;
  52	struct meson_msr_data data;
  53};
  54
  55#define CLK_MSR_ID(__id, __name) \
  56	[__id] = {.id = __id, .name = __name,}
  57
  58static const struct meson_msr_id clk_msr_m8[] = {
  59	CLK_MSR_ID(0, "ring_osc_out_ee0"),
  60	CLK_MSR_ID(1, "ring_osc_out_ee1"),
  61	CLK_MSR_ID(2, "ring_osc_out_ee2"),
  62	CLK_MSR_ID(3, "a9_ring_osck"),
  63	CLK_MSR_ID(6, "vid_pll"),
  64	CLK_MSR_ID(7, "clk81"),
  65	CLK_MSR_ID(8, "encp"),
  66	CLK_MSR_ID(9, "encl"),
  67	CLK_MSR_ID(11, "eth_rmii"),
  68	CLK_MSR_ID(13, "amclk"),
  69	CLK_MSR_ID(14, "fec_clk_0"),
  70	CLK_MSR_ID(15, "fec_clk_1"),
  71	CLK_MSR_ID(16, "fec_clk_2"),
  72	CLK_MSR_ID(18, "a9_clk_div16"),
  73	CLK_MSR_ID(19, "hdmi_sys"),
  74	CLK_MSR_ID(20, "rtc_osc_clk_out"),
  75	CLK_MSR_ID(21, "i2s_clk_in_src0"),
  76	CLK_MSR_ID(22, "clk_rmii_from_pad"),
  77	CLK_MSR_ID(23, "hdmi_ch0_tmds"),
  78	CLK_MSR_ID(24, "lvds_fifo"),
  79	CLK_MSR_ID(26, "sc_clk_int"),
  80	CLK_MSR_ID(28, "sar_adc"),
  81	CLK_MSR_ID(30, "mpll_clk_test_out"),
  82	CLK_MSR_ID(31, "audac_clkpi"),
  83	CLK_MSR_ID(32, "vdac"),
  84	CLK_MSR_ID(33, "sdhc_rx"),
  85	CLK_MSR_ID(34, "sdhc_sd"),
  86	CLK_MSR_ID(35, "mali"),
  87	CLK_MSR_ID(36, "hdmi_tx_pixel"),
  88	CLK_MSR_ID(38, "vdin_meas"),
  89	CLK_MSR_ID(39, "pcm_sclk"),
  90	CLK_MSR_ID(40, "pcm_mclk"),
  91	CLK_MSR_ID(41, "eth_rx_tx"),
  92	CLK_MSR_ID(42, "pwm_d"),
  93	CLK_MSR_ID(43, "pwm_c"),
  94	CLK_MSR_ID(44, "pwm_b"),
  95	CLK_MSR_ID(45, "pwm_a"),
  96	CLK_MSR_ID(46, "pcm2_sclk"),
  97	CLK_MSR_ID(47, "ddr_dpll_pt"),
  98	CLK_MSR_ID(48, "pwm_f"),
  99	CLK_MSR_ID(49, "pwm_e"),
 100	CLK_MSR_ID(59, "hcodec"),
 101	CLK_MSR_ID(60, "usb_32k_alt"),
 102	CLK_MSR_ID(61, "gpio"),
 103	CLK_MSR_ID(62, "vid2_pll"),
 104	CLK_MSR_ID(63, "mipi_csi_cfg"),
 105};
 106
 107static const struct meson_msr_id clk_msr_gx[] = {
 108	CLK_MSR_ID(0, "ring_osc_out_ee_0"),
 109	CLK_MSR_ID(1, "ring_osc_out_ee_1"),
 110	CLK_MSR_ID(2, "ring_osc_out_ee_2"),
 111	CLK_MSR_ID(3, "a53_ring_osc"),
 112	CLK_MSR_ID(4, "gp0_pll"),
 113	CLK_MSR_ID(6, "enci"),
 114	CLK_MSR_ID(7, "clk81"),
 115	CLK_MSR_ID(8, "encp"),
 116	CLK_MSR_ID(9, "encl"),
 117	CLK_MSR_ID(10, "vdac"),
 118	CLK_MSR_ID(11, "rgmii_tx"),
 119	CLK_MSR_ID(12, "pdm"),
 120	CLK_MSR_ID(13, "amclk"),
 121	CLK_MSR_ID(14, "fec_0"),
 122	CLK_MSR_ID(15, "fec_1"),
 123	CLK_MSR_ID(16, "fec_2"),
 124	CLK_MSR_ID(17, "sys_pll_div16"),
 125	CLK_MSR_ID(18, "sys_cpu_div16"),
 126	CLK_MSR_ID(19, "hdmitx_sys"),
 127	CLK_MSR_ID(20, "rtc_osc_out"),
 128	CLK_MSR_ID(21, "i2s_in_src0"),
 129	CLK_MSR_ID(22, "eth_phy_ref"),
 130	CLK_MSR_ID(23, "hdmi_todig"),
 131	CLK_MSR_ID(26, "sc_int"),
 132	CLK_MSR_ID(28, "sar_adc"),
 133	CLK_MSR_ID(31, "mpll_test_out"),
 134	CLK_MSR_ID(32, "vdec"),
 135	CLK_MSR_ID(35, "mali"),
 136	CLK_MSR_ID(36, "hdmi_tx_pixel"),
 137	CLK_MSR_ID(37, "i958"),
 138	CLK_MSR_ID(38, "vdin_meas"),
 139	CLK_MSR_ID(39, "pcm_sclk"),
 140	CLK_MSR_ID(40, "pcm_mclk"),
 141	CLK_MSR_ID(41, "eth_rx_or_rmii"),
 142	CLK_MSR_ID(42, "mp0_out"),
 143	CLK_MSR_ID(43, "fclk_div5"),
 144	CLK_MSR_ID(44, "pwm_b"),
 145	CLK_MSR_ID(45, "pwm_a"),
 146	CLK_MSR_ID(46, "vpu"),
 147	CLK_MSR_ID(47, "ddr_dpll_pt"),
 148	CLK_MSR_ID(48, "mp1_out"),
 149	CLK_MSR_ID(49, "mp2_out"),
 150	CLK_MSR_ID(50, "mp3_out"),
 151	CLK_MSR_ID(51, "nand_core"),
 152	CLK_MSR_ID(52, "sd_emmc_b"),
 153	CLK_MSR_ID(53, "sd_emmc_a"),
 154	CLK_MSR_ID(55, "vid_pll_div_out"),
 155	CLK_MSR_ID(56, "cci"),
 156	CLK_MSR_ID(57, "wave420l_c"),
 157	CLK_MSR_ID(58, "wave420l_b"),
 158	CLK_MSR_ID(59, "hcodec"),
 159	CLK_MSR_ID(60, "alt_32k"),
 160	CLK_MSR_ID(61, "gpio_msr"),
 161	CLK_MSR_ID(62, "hevc"),
 162	CLK_MSR_ID(66, "vid_lock"),
 163	CLK_MSR_ID(70, "pwm_f"),
 164	CLK_MSR_ID(71, "pwm_e"),
 165	CLK_MSR_ID(72, "pwm_d"),
 166	CLK_MSR_ID(73, "pwm_c"),
 167	CLK_MSR_ID(75, "aoclkx2_int"),
 168	CLK_MSR_ID(76, "aoclk_int"),
 169	CLK_MSR_ID(77, "rng_ring_osc_0"),
 170	CLK_MSR_ID(78, "rng_ring_osc_1"),
 171	CLK_MSR_ID(79, "rng_ring_osc_2"),
 172	CLK_MSR_ID(80, "rng_ring_osc_3"),
 173	CLK_MSR_ID(81, "vapb"),
 174	CLK_MSR_ID(82, "ge2d"),
 175};
 176
 177static const struct meson_msr_id clk_msr_axg[] = {
 178	CLK_MSR_ID(0, "ring_osc_out_ee_0"),
 179	CLK_MSR_ID(1, "ring_osc_out_ee_1"),
 180	CLK_MSR_ID(2, "ring_osc_out_ee_2"),
 181	CLK_MSR_ID(3, "a53_ring_osc"),
 182	CLK_MSR_ID(4, "gp0_pll"),
 183	CLK_MSR_ID(5, "gp1_pll"),
 184	CLK_MSR_ID(7, "clk81"),
 185	CLK_MSR_ID(9, "encl"),
 186	CLK_MSR_ID(17, "sys_pll_div16"),
 187	CLK_MSR_ID(18, "sys_cpu_div16"),
 188	CLK_MSR_ID(20, "rtc_osc_out"),
 189	CLK_MSR_ID(23, "mmc_clk"),
 190	CLK_MSR_ID(28, "sar_adc"),
 191	CLK_MSR_ID(31, "mpll_test_out"),
 192	CLK_MSR_ID(40, "mod_eth_tx_clk"),
 193	CLK_MSR_ID(41, "mod_eth_rx_clk_rmii"),
 194	CLK_MSR_ID(42, "mp0_out"),
 195	CLK_MSR_ID(43, "fclk_div5"),
 196	CLK_MSR_ID(44, "pwm_b"),
 197	CLK_MSR_ID(45, "pwm_a"),
 198	CLK_MSR_ID(46, "vpu"),
 199	CLK_MSR_ID(47, "ddr_dpll_pt"),
 200	CLK_MSR_ID(48, "mp1_out"),
 201	CLK_MSR_ID(49, "mp2_out"),
 202	CLK_MSR_ID(50, "mp3_out"),
 203	CLK_MSR_ID(51, "sd_emmm_c"),
 204	CLK_MSR_ID(52, "sd_emmc_b"),
 205	CLK_MSR_ID(61, "gpio_msr"),
 206	CLK_MSR_ID(66, "audio_slv_lrclk_c"),
 207	CLK_MSR_ID(67, "audio_slv_lrclk_b"),
 208	CLK_MSR_ID(68, "audio_slv_lrclk_a"),
 209	CLK_MSR_ID(69, "audio_slv_sclk_c"),
 210	CLK_MSR_ID(70, "audio_slv_sclk_b"),
 211	CLK_MSR_ID(71, "audio_slv_sclk_a"),
 212	CLK_MSR_ID(72, "pwm_d"),
 213	CLK_MSR_ID(73, "pwm_c"),
 214	CLK_MSR_ID(74, "wifi_beacon"),
 215	CLK_MSR_ID(75, "tdmin_lb_lrcl"),
 216	CLK_MSR_ID(76, "tdmin_lb_sclk"),
 217	CLK_MSR_ID(77, "rng_ring_osc_0"),
 218	CLK_MSR_ID(78, "rng_ring_osc_1"),
 219	CLK_MSR_ID(79, "rng_ring_osc_2"),
 220	CLK_MSR_ID(80, "rng_ring_osc_3"),
 221	CLK_MSR_ID(81, "vapb"),
 222	CLK_MSR_ID(82, "ge2d"),
 223	CLK_MSR_ID(84, "audio_resample"),
 224	CLK_MSR_ID(85, "audio_pdm_sys"),
 225	CLK_MSR_ID(86, "audio_spdifout"),
 226	CLK_MSR_ID(87, "audio_spdifin"),
 227	CLK_MSR_ID(88, "audio_lrclk_f"),
 228	CLK_MSR_ID(89, "audio_lrclk_e"),
 229	CLK_MSR_ID(90, "audio_lrclk_d"),
 230	CLK_MSR_ID(91, "audio_lrclk_c"),
 231	CLK_MSR_ID(92, "audio_lrclk_b"),
 232	CLK_MSR_ID(93, "audio_lrclk_a"),
 233	CLK_MSR_ID(94, "audio_sclk_f"),
 234	CLK_MSR_ID(95, "audio_sclk_e"),
 235	CLK_MSR_ID(96, "audio_sclk_d"),
 236	CLK_MSR_ID(97, "audio_sclk_c"),
 237	CLK_MSR_ID(98, "audio_sclk_b"),
 238	CLK_MSR_ID(99, "audio_sclk_a"),
 239	CLK_MSR_ID(100, "audio_mclk_f"),
 240	CLK_MSR_ID(101, "audio_mclk_e"),
 241	CLK_MSR_ID(102, "audio_mclk_d"),
 242	CLK_MSR_ID(103, "audio_mclk_c"),
 243	CLK_MSR_ID(104, "audio_mclk_b"),
 244	CLK_MSR_ID(105, "audio_mclk_a"),
 245	CLK_MSR_ID(106, "pcie_refclk_n"),
 246	CLK_MSR_ID(107, "pcie_refclk_p"),
 247	CLK_MSR_ID(108, "audio_locker_out"),
 248	CLK_MSR_ID(109, "audio_locker_in"),
 249};
 250
 251static const struct meson_msr_id clk_msr_g12a[] = {
 252	CLK_MSR_ID(0, "ring_osc_out_ee_0"),
 253	CLK_MSR_ID(1, "ring_osc_out_ee_1"),
 254	CLK_MSR_ID(2, "ring_osc_out_ee_2"),
 255	CLK_MSR_ID(3, "sys_cpu_ring_osc"),
 256	CLK_MSR_ID(4, "gp0_pll"),
 257	CLK_MSR_ID(6, "enci"),
 258	CLK_MSR_ID(7, "clk81"),
 259	CLK_MSR_ID(8, "encp"),
 260	CLK_MSR_ID(9, "encl"),
 261	CLK_MSR_ID(10, "vdac"),
 262	CLK_MSR_ID(11, "eth_tx"),
 263	CLK_MSR_ID(12, "hifi_pll"),
 264	CLK_MSR_ID(13, "mod_tcon"),
 265	CLK_MSR_ID(14, "fec_0"),
 266	CLK_MSR_ID(15, "fec_1"),
 267	CLK_MSR_ID(16, "fec_2"),
 268	CLK_MSR_ID(17, "sys_pll_div16"),
 269	CLK_MSR_ID(18, "sys_cpu_div16"),
 270	CLK_MSR_ID(19, "lcd_an_ph2"),
 271	CLK_MSR_ID(20, "rtc_osc_out"),
 272	CLK_MSR_ID(21, "lcd_an_ph3"),
 273	CLK_MSR_ID(22, "eth_phy_ref"),
 274	CLK_MSR_ID(23, "mpll_50m"),
 275	CLK_MSR_ID(24, "eth_125m"),
 276	CLK_MSR_ID(25, "eth_rmii"),
 277	CLK_MSR_ID(26, "sc_int"),
 278	CLK_MSR_ID(27, "in_mac"),
 279	CLK_MSR_ID(28, "sar_adc"),
 280	CLK_MSR_ID(29, "pcie_inp"),
 281	CLK_MSR_ID(30, "pcie_inn"),
 282	CLK_MSR_ID(31, "mpll_test_out"),
 283	CLK_MSR_ID(32, "vdec"),
 284	CLK_MSR_ID(33, "sys_cpu_ring_osc_1"),
 285	CLK_MSR_ID(34, "eth_mpll_50m"),
 286	CLK_MSR_ID(35, "mali"),
 287	CLK_MSR_ID(36, "hdmi_tx_pixel"),
 288	CLK_MSR_ID(37, "cdac"),
 289	CLK_MSR_ID(38, "vdin_meas"),
 290	CLK_MSR_ID(39, "bt656"),
 291	CLK_MSR_ID(41, "eth_rx_or_rmii"),
 292	CLK_MSR_ID(42, "mp0_out"),
 293	CLK_MSR_ID(43, "fclk_div5"),
 294	CLK_MSR_ID(44, "pwm_b"),
 295	CLK_MSR_ID(45, "pwm_a"),
 296	CLK_MSR_ID(46, "vpu"),
 297	CLK_MSR_ID(47, "ddr_dpll_pt"),
 298	CLK_MSR_ID(48, "mp1_out"),
 299	CLK_MSR_ID(49, "mp2_out"),
 300	CLK_MSR_ID(50, "mp3_out"),
 301	CLK_MSR_ID(51, "sd_emmc_c"),
 302	CLK_MSR_ID(52, "sd_emmc_b"),
 303	CLK_MSR_ID(53, "sd_emmc_a"),
 304	CLK_MSR_ID(54, "vpu_clkc"),
 305	CLK_MSR_ID(55, "vid_pll_div_out"),
 306	CLK_MSR_ID(56, "wave420l_a"),
 307	CLK_MSR_ID(57, "wave420l_c"),
 308	CLK_MSR_ID(58, "wave420l_b"),
 309	CLK_MSR_ID(59, "hcodec"),
 310	CLK_MSR_ID(61, "gpio_msr"),
 311	CLK_MSR_ID(62, "hevcb"),
 312	CLK_MSR_ID(63, "dsi_meas"),
 313	CLK_MSR_ID(64, "spicc_1"),
 314	CLK_MSR_ID(65, "spicc_0"),
 315	CLK_MSR_ID(66, "vid_lock"),
 316	CLK_MSR_ID(67, "dsi_phy"),
 317	CLK_MSR_ID(68, "hdcp22_esm"),
 318	CLK_MSR_ID(69, "hdcp22_skp"),
 319	CLK_MSR_ID(70, "pwm_f"),
 320	CLK_MSR_ID(71, "pwm_e"),
 321	CLK_MSR_ID(72, "pwm_d"),
 322	CLK_MSR_ID(73, "pwm_c"),
 323	CLK_MSR_ID(75, "hevcf"),
 324	CLK_MSR_ID(77, "rng_ring_osc_0"),
 325	CLK_MSR_ID(78, "rng_ring_osc_1"),
 326	CLK_MSR_ID(79, "rng_ring_osc_2"),
 327	CLK_MSR_ID(80, "rng_ring_osc_3"),
 328	CLK_MSR_ID(81, "vapb"),
 329	CLK_MSR_ID(82, "ge2d"),
 330	CLK_MSR_ID(83, "co_rx"),
 331	CLK_MSR_ID(84, "co_tx"),
 332	CLK_MSR_ID(89, "hdmi_todig"),
 333	CLK_MSR_ID(90, "hdmitx_sys"),
 334	CLK_MSR_ID(91, "sys_cpub_div16"),
 335	CLK_MSR_ID(92, "sys_pll_cpub_div16"),
 336	CLK_MSR_ID(94, "eth_phy_rx"),
 337	CLK_MSR_ID(95, "eth_phy_pll"),
 338	CLK_MSR_ID(96, "vpu_b"),
 339	CLK_MSR_ID(97, "cpu_b_tmp"),
 340	CLK_MSR_ID(98, "ts"),
 341	CLK_MSR_ID(99, "ring_osc_out_ee_3"),
 342	CLK_MSR_ID(100, "ring_osc_out_ee_4"),
 343	CLK_MSR_ID(101, "ring_osc_out_ee_5"),
 344	CLK_MSR_ID(102, "ring_osc_out_ee_6"),
 345	CLK_MSR_ID(103, "ring_osc_out_ee_7"),
 346	CLK_MSR_ID(104, "ring_osc_out_ee_8"),
 347	CLK_MSR_ID(105, "ring_osc_out_ee_9"),
 348	CLK_MSR_ID(106, "ephy_test"),
 349	CLK_MSR_ID(107, "au_dac_g128x"),
 350	CLK_MSR_ID(108, "audio_locker_out"),
 351	CLK_MSR_ID(109, "audio_locker_in"),
 352	CLK_MSR_ID(110, "audio_tdmout_c_sclk"),
 353	CLK_MSR_ID(111, "audio_tdmout_b_sclk"),
 354	CLK_MSR_ID(112, "audio_tdmout_a_sclk"),
 355	CLK_MSR_ID(113, "audio_tdmin_lb_sclk"),
 356	CLK_MSR_ID(114, "audio_tdmin_c_sclk"),
 357	CLK_MSR_ID(115, "audio_tdmin_b_sclk"),
 358	CLK_MSR_ID(116, "audio_tdmin_a_sclk"),
 359	CLK_MSR_ID(117, "audio_resample"),
 360	CLK_MSR_ID(118, "audio_pdm_sys"),
 361	CLK_MSR_ID(119, "audio_spdifout_b"),
 362	CLK_MSR_ID(120, "audio_spdifout"),
 363	CLK_MSR_ID(121, "audio_spdifin"),
 364	CLK_MSR_ID(122, "audio_pdm_dclk"),
 365};
 366
 367static const struct meson_msr_id clk_msr_sm1[] = {
 368	CLK_MSR_ID(0, "ring_osc_out_ee_0"),
 369	CLK_MSR_ID(1, "ring_osc_out_ee_1"),
 370	CLK_MSR_ID(2, "ring_osc_out_ee_2"),
 371	CLK_MSR_ID(3, "ring_osc_out_ee_3"),
 372	CLK_MSR_ID(4, "gp0_pll"),
 373	CLK_MSR_ID(5, "gp1_pll"),
 374	CLK_MSR_ID(6, "enci"),
 375	CLK_MSR_ID(7, "clk81"),
 376	CLK_MSR_ID(8, "encp"),
 377	CLK_MSR_ID(9, "encl"),
 378	CLK_MSR_ID(10, "vdac"),
 379	CLK_MSR_ID(11, "eth_tx"),
 380	CLK_MSR_ID(12, "hifi_pll"),
 381	CLK_MSR_ID(13, "mod_tcon"),
 382	CLK_MSR_ID(14, "fec_0"),
 383	CLK_MSR_ID(15, "fec_1"),
 384	CLK_MSR_ID(16, "fec_2"),
 385	CLK_MSR_ID(17, "sys_pll_div16"),
 386	CLK_MSR_ID(18, "sys_cpu_div16"),
 387	CLK_MSR_ID(19, "lcd_an_ph2"),
 388	CLK_MSR_ID(20, "rtc_osc_out"),
 389	CLK_MSR_ID(21, "lcd_an_ph3"),
 390	CLK_MSR_ID(22, "eth_phy_ref"),
 391	CLK_MSR_ID(23, "mpll_50m"),
 392	CLK_MSR_ID(24, "eth_125m"),
 393	CLK_MSR_ID(25, "eth_rmii"),
 394	CLK_MSR_ID(26, "sc_int"),
 395	CLK_MSR_ID(27, "in_mac"),
 396	CLK_MSR_ID(28, "sar_adc"),
 397	CLK_MSR_ID(29, "pcie_inp"),
 398	CLK_MSR_ID(30, "pcie_inn"),
 399	CLK_MSR_ID(31, "mpll_test_out"),
 400	CLK_MSR_ID(32, "vdec"),
 401	CLK_MSR_ID(34, "eth_mpll_50m"),
 402	CLK_MSR_ID(35, "mali"),
 403	CLK_MSR_ID(36, "hdmi_tx_pixel"),
 404	CLK_MSR_ID(37, "cdac"),
 405	CLK_MSR_ID(38, "vdin_meas"),
 406	CLK_MSR_ID(39, "bt656"),
 407	CLK_MSR_ID(40, "arm_ring_osc_out_4"),
 408	CLK_MSR_ID(41, "eth_rx_or_rmii"),
 409	CLK_MSR_ID(42, "mp0_out"),
 410	CLK_MSR_ID(43, "fclk_div5"),
 411	CLK_MSR_ID(44, "pwm_b"),
 412	CLK_MSR_ID(45, "pwm_a"),
 413	CLK_MSR_ID(46, "vpu"),
 414	CLK_MSR_ID(47, "ddr_dpll_pt"),
 415	CLK_MSR_ID(48, "mp1_out"),
 416	CLK_MSR_ID(49, "mp2_out"),
 417	CLK_MSR_ID(50, "mp3_out"),
 418	CLK_MSR_ID(51, "sd_emmc_c"),
 419	CLK_MSR_ID(52, "sd_emmc_b"),
 420	CLK_MSR_ID(53, "sd_emmc_a"),
 421	CLK_MSR_ID(54, "vpu_clkc"),
 422	CLK_MSR_ID(55, "vid_pll_div_out"),
 423	CLK_MSR_ID(56, "wave420l_a"),
 424	CLK_MSR_ID(57, "wave420l_c"),
 425	CLK_MSR_ID(58, "wave420l_b"),
 426	CLK_MSR_ID(59, "hcodec"),
 427	CLK_MSR_ID(60, "arm_ring_osc_out_5"),
 428	CLK_MSR_ID(61, "gpio_msr"),
 429	CLK_MSR_ID(62, "hevcb"),
 430	CLK_MSR_ID(63, "dsi_meas"),
 431	CLK_MSR_ID(64, "spicc_1"),
 432	CLK_MSR_ID(65, "spicc_0"),
 433	CLK_MSR_ID(66, "vid_lock"),
 434	CLK_MSR_ID(67, "dsi_phy"),
 435	CLK_MSR_ID(68, "hdcp22_esm"),
 436	CLK_MSR_ID(69, "hdcp22_skp"),
 437	CLK_MSR_ID(70, "pwm_f"),
 438	CLK_MSR_ID(71, "pwm_e"),
 439	CLK_MSR_ID(72, "pwm_d"),
 440	CLK_MSR_ID(73, "pwm_c"),
 441	CLK_MSR_ID(74, "arm_ring_osc_out_6"),
 442	CLK_MSR_ID(75, "hevcf"),
 443	CLK_MSR_ID(76, "arm_ring_osc_out_7"),
 444	CLK_MSR_ID(77, "rng_ring_osc_0"),
 445	CLK_MSR_ID(78, "rng_ring_osc_1"),
 446	CLK_MSR_ID(79, "rng_ring_osc_2"),
 447	CLK_MSR_ID(80, "rng_ring_osc_3"),
 448	CLK_MSR_ID(81, "vapb"),
 449	CLK_MSR_ID(82, "ge2d"),
 450	CLK_MSR_ID(83, "co_rx"),
 451	CLK_MSR_ID(84, "co_tx"),
 452	CLK_MSR_ID(85, "arm_ring_osc_out_8"),
 453	CLK_MSR_ID(86, "arm_ring_osc_out_9"),
 454	CLK_MSR_ID(87, "mipi_dsi_phy"),
 455	CLK_MSR_ID(88, "cis2_adapt"),
 456	CLK_MSR_ID(89, "hdmi_todig"),
 457	CLK_MSR_ID(90, "hdmitx_sys"),
 458	CLK_MSR_ID(91, "nna_core"),
 459	CLK_MSR_ID(92, "nna_axi"),
 460	CLK_MSR_ID(93, "vad"),
 461	CLK_MSR_ID(94, "eth_phy_rx"),
 462	CLK_MSR_ID(95, "eth_phy_pll"),
 463	CLK_MSR_ID(96, "vpu_b"),
 464	CLK_MSR_ID(97, "cpu_b_tmp"),
 465	CLK_MSR_ID(98, "ts"),
 466	CLK_MSR_ID(99, "arm_ring_osc_out_10"),
 467	CLK_MSR_ID(100, "arm_ring_osc_out_11"),
 468	CLK_MSR_ID(101, "arm_ring_osc_out_12"),
 469	CLK_MSR_ID(102, "arm_ring_osc_out_13"),
 470	CLK_MSR_ID(103, "arm_ring_osc_out_14"),
 471	CLK_MSR_ID(104, "arm_ring_osc_out_15"),
 472	CLK_MSR_ID(105, "arm_ring_osc_out_16"),
 473	CLK_MSR_ID(106, "ephy_test"),
 474	CLK_MSR_ID(107, "au_dac_g128x"),
 475	CLK_MSR_ID(108, "audio_locker_out"),
 476	CLK_MSR_ID(109, "audio_locker_in"),
 477	CLK_MSR_ID(110, "audio_tdmout_c_sclk"),
 478	CLK_MSR_ID(111, "audio_tdmout_b_sclk"),
 479	CLK_MSR_ID(112, "audio_tdmout_a_sclk"),
 480	CLK_MSR_ID(113, "audio_tdmin_lb_sclk"),
 481	CLK_MSR_ID(114, "audio_tdmin_c_sclk"),
 482	CLK_MSR_ID(115, "audio_tdmin_b_sclk"),
 483	CLK_MSR_ID(116, "audio_tdmin_a_sclk"),
 484	CLK_MSR_ID(117, "audio_resample"),
 485	CLK_MSR_ID(118, "audio_pdm_sys"),
 486	CLK_MSR_ID(119, "audio_spdifout_b"),
 487	CLK_MSR_ID(120, "audio_spdifout"),
 488	CLK_MSR_ID(121, "audio_spdifin"),
 489	CLK_MSR_ID(122, "audio_pdm_dclk"),
 490	CLK_MSR_ID(123, "audio_resampled"),
 491	CLK_MSR_ID(124, "earcrx_pll"),
 492	CLK_MSR_ID(125, "earcrx_pll_test"),
 493	CLK_MSR_ID(126, "csi_phy0"),
 494	CLK_MSR_ID(127, "csi2_data"),
 495};
 496
 497static const struct meson_msr_id clk_msr_c3[] = {
 498	CLK_MSR_ID(0,	"sys_clk"),
 499	CLK_MSR_ID(1,	"axi_clk"),
 500	CLK_MSR_ID(2,	"rtc_clk"),
 501	CLK_MSR_ID(3,	"p20_usb2_ckout"),
 502	CLK_MSR_ID(4,	"eth_mpll_test"),
 503	CLK_MSR_ID(5,	"sys_pll"),
 504	CLK_MSR_ID(6,	"cpu_clk_div16"),
 505	CLK_MSR_ID(7,	"ts_pll"),
 506	CLK_MSR_ID(8,	"fclk_div2"),
 507	CLK_MSR_ID(9,	"fclk_div2p5"),
 508	CLK_MSR_ID(10,	"fclk_div3"),
 509	CLK_MSR_ID(11,	"fclk_div4"),
 510	CLK_MSR_ID(12,	"fclk_div5"),
 511	CLK_MSR_ID(13,	"fclk_div7"),
 512	CLK_MSR_ID(15,	"fclk_50m"),
 513	CLK_MSR_ID(16,	"sys_oscin32k_i"),
 514	CLK_MSR_ID(17,	"mclk_pll"),
 515	CLK_MSR_ID(19,	"hifi_pll"),
 516	CLK_MSR_ID(20,	"gp0_pll"),
 517	CLK_MSR_ID(21,	"gp1_pll"),
 518	CLK_MSR_ID(22,	"eth_mppll_50m_ckout"),
 519	CLK_MSR_ID(23,	"sys_pll_div16"),
 520	CLK_MSR_ID(24,	"ddr_dpll_pt_clk"),
 521	CLK_MSR_ID(26,	"nna_core"),
 522	CLK_MSR_ID(27,	"rtc_sec_pulse_out"),
 523	CLK_MSR_ID(28,	"rtc_osc_clk_out"),
 524	CLK_MSR_ID(29,	"debug_in_clk"),
 525	CLK_MSR_ID(30,	"mod_eth_phy_ref_clk"),
 526	CLK_MSR_ID(31,	"mod_eth_tx_clk"),
 527	CLK_MSR_ID(32,	"eth_125m"),
 528	CLK_MSR_ID(33,	"eth_rmii"),
 529	CLK_MSR_ID(34,	"co_clkin_to_mac"),
 530	CLK_MSR_ID(36,	"co_rx_clk"),
 531	CLK_MSR_ID(37,	"co_tx_clk"),
 532	CLK_MSR_ID(38,	"eth_phy_rxclk"),
 533	CLK_MSR_ID(39,	"eth_phy_plltxclk"),
 534	CLK_MSR_ID(40,	"ephy_test_clk"),
 535	CLK_MSR_ID(66,	"vapb"),
 536	CLK_MSR_ID(67,	"ge2d"),
 537	CLK_MSR_ID(68,	"dewarpa"),
 538	CLK_MSR_ID(70,	"mipi_dsi_meas"),
 539	CLK_MSR_ID(71,	"dsi_phy"),
 540	CLK_MSR_ID(79,	"rama"),
 541	CLK_MSR_ID(94,	"vc9000e_core"),
 542	CLK_MSR_ID(95,	"vc9000e_sys"),
 543	CLK_MSR_ID(96,	"vc9000e_aclk"),
 544	CLK_MSR_ID(97,	"hcodec"),
 545	CLK_MSR_ID(106,	"deskew_pll_clk_div32_out"),
 546	CLK_MSR_ID(107,	"mipi_csi_phy_clk_out[0]"),
 547	CLK_MSR_ID(108,	"mipi_csi_phy_clk_out[1]"),
 548	CLK_MSR_ID(110,	"spifc"),
 549	CLK_MSR_ID(111,	"saradc"),
 550	CLK_MSR_ID(112,	"ts"),
 551	CLK_MSR_ID(113,	"sd_emmc_c"),
 552	CLK_MSR_ID(114,	"sd_emmc_b"),
 553	CLK_MSR_ID(115,	"sd_emmc_a"),
 554	CLK_MSR_ID(116,	"gpio_msr_clk"),
 555	CLK_MSR_ID(117,	"spicc_b"),
 556	CLK_MSR_ID(118,	"spicc_a"),
 557	CLK_MSR_ID(122,	"mod_audio_pdm_dclk_o"),
 558	CLK_MSR_ID(124,	"o_earcrx_dmac_clk"),
 559	CLK_MSR_ID(125,	"o_earcrx_cmdc_clk"),
 560	CLK_MSR_ID(126,	"o_earctx_dmac_clk"),
 561	CLK_MSR_ID(127,	"o_earctx_cmdc_clk"),
 562	CLK_MSR_ID(128,	"o_tohdmitx_bclk"),
 563	CLK_MSR_ID(129,	"o_tohdmitx_mclk"),
 564	CLK_MSR_ID(130,	"o_tohdmitx_spdif_clk"),
 565	CLK_MSR_ID(131,	"o_toacodec_bclk"),
 566	CLK_MSR_ID(132,	"o_toacodec_mclk"),
 567	CLK_MSR_ID(133,	"o_spdifout_b_mst_clk"),
 568	CLK_MSR_ID(134,	"o_spdifout_mst_clk"),
 569	CLK_MSR_ID(135,	"o_spdifin_mst_clk"),
 570	CLK_MSR_ID(136,	"o_audio_mclk"),
 571	CLK_MSR_ID(137,	"o_vad_clk"),
 572	CLK_MSR_ID(138,	"o_tdmout_d_sclk"),
 573	CLK_MSR_ID(139,	"o_tdmout_c_sclk"),
 574	CLK_MSR_ID(140,	"o_tdmout_b_sclk"),
 575	CLK_MSR_ID(141,	"o_tdmout_a_sclk"),
 576	CLK_MSR_ID(142,	"o_tdminb_1b_sclk"),
 577	CLK_MSR_ID(143,	"o_tdmin_1b_sclk"),
 578	CLK_MSR_ID(144,	"o_tdmin_d_sclk"),
 579	CLK_MSR_ID(145,	"o_tdmin_c_sclk"),
 580	CLK_MSR_ID(146,	"o_tdmin_b_sclk"),
 581	CLK_MSR_ID(147,	"o_tdmin_a_sclk"),
 582	CLK_MSR_ID(148,	"o_resampleb_clk"),
 583	CLK_MSR_ID(149,	"o_resamplea_clk"),
 584	CLK_MSR_ID(150,	"o_pdmb_sysclk"),
 585	CLK_MSR_ID(151,	"o_pdmb_dclk"),
 586	CLK_MSR_ID(152,	"o_pdm_sysclk"),
 587	CLK_MSR_ID(153,	"o_pdm_dclk"),
 588	CLK_MSR_ID(154,	"c_alockerb_out_clk"),
 589	CLK_MSR_ID(155,	"c_alockerb_in_clk"),
 590	CLK_MSR_ID(156,	"c_alocker_out_clk"),
 591	CLK_MSR_ID(157,	"c_alocker_in_clk"),
 592	CLK_MSR_ID(158,	"audio_mst_clk[34]"),
 593	CLK_MSR_ID(159,	"audio_mst_clk[35]"),
 594	CLK_MSR_ID(160,	"pwm_n"),
 595	CLK_MSR_ID(161,	"pwm_m"),
 596	CLK_MSR_ID(162,	"pwm_l"),
 597	CLK_MSR_ID(163,	"pwm_k"),
 598	CLK_MSR_ID(164,	"pwm_j"),
 599	CLK_MSR_ID(165,	"pwm_i"),
 600	CLK_MSR_ID(166,	"pwm_h"),
 601	CLK_MSR_ID(167,	"pwm_g"),
 602	CLK_MSR_ID(168,	"pwm_f"),
 603	CLK_MSR_ID(169,	"pwm_e"),
 604	CLK_MSR_ID(170,	"pwm_d"),
 605	CLK_MSR_ID(171,	"pwm_c"),
 606	CLK_MSR_ID(172,	"pwm_b"),
 607	CLK_MSR_ID(173,	"pwm_a"),
 608	CLK_MSR_ID(174,	"AU_DAC1_CLK_TO_GPIO"),
 609	CLK_MSR_ID(175,	"AU_ADC_CLK_TO_GPIO"),
 610	CLK_MSR_ID(176,	"rng_ring_osc_clk[0]"),
 611	CLK_MSR_ID(177,	"rng_ring_osc_clk[1]"),
 612	CLK_MSR_ID(178,	"rng_ring_osc_clk[2]"),
 613	CLK_MSR_ID(179,	"rng_ring_osc_clk[3]"),
 614	CLK_MSR_ID(180,	"sys_cpu_ring_osc_clk[0]"),
 615	CLK_MSR_ID(181,	"sys_cpu_ring_osc_clk[1]"),
 616	CLK_MSR_ID(182,	"sys_cpu_ring_osc_clk[2]"),
 617	CLK_MSR_ID(183,	"sys_cpu_ring_osc_clk[3]"),
 618	CLK_MSR_ID(184,	"sys_cpu_ring_osc_clk[4]"),
 619	CLK_MSR_ID(185,	"sys_cpu_ring_osc_clk[5]"),
 620	CLK_MSR_ID(186,	"sys_cpu_ring_osc_clk[6]"),
 621	CLK_MSR_ID(187,	"sys_cpu_ring_osc_clk[7]"),
 622	CLK_MSR_ID(188,	"sys_cpu_ring_osc_clk[8]"),
 623	CLK_MSR_ID(189,	"sys_cpu_ring_osc_clk[9]"),
 624	CLK_MSR_ID(190,	"sys_cpu_ring_osc_clk[10]"),
 625	CLK_MSR_ID(191,	"sys_cpu_ring_osc_clk[11]"),
 626	CLK_MSR_ID(192,	"am_ring_osc_clk_out[12](dmc)"),
 627	CLK_MSR_ID(193,	"am_ring_osc_clk_out[13](rama)"),
 628	CLK_MSR_ID(194,	"am_ring_osc_clk_out[14](nna)"),
 629	CLK_MSR_ID(195,	"am_ring_osc_clk_out[15](nna)"),
 630	CLK_MSR_ID(200,	"rng_ring_osc_clk_1[0]"),
 631	CLK_MSR_ID(201,	"rng_ring_osc_clk_1[1]"),
 632	CLK_MSR_ID(202,	"rng_ring_osc_clk_1[2]"),
 633	CLK_MSR_ID(203,	"rng_ring_osc_clk_1[3]"),
 634
 635};
 636
 637static const struct meson_msr_id clk_msr_s4[] = {
 638	CLK_MSR_ID(0, "sys_clk"),
 639	CLK_MSR_ID(1, "axi_clk"),
 640	CLK_MSR_ID(2, "rtc_clk"),
 641	CLK_MSR_ID(5, "mali"),
 642	CLK_MSR_ID(6, "cpu_clk_div16"),
 643	CLK_MSR_ID(7, "ceca_clk"),
 644	CLK_MSR_ID(8, "cecb_clk"),
 645	CLK_MSR_ID(10, "fclk_div5"),
 646	CLK_MSR_ID(11, "mpll0"),
 647	CLK_MSR_ID(12, "mpll1"),
 648	CLK_MSR_ID(13, "mpll2"),
 649	CLK_MSR_ID(14, "mpll3"),
 650	CLK_MSR_ID(15, "fclk_50m"),
 651	CLK_MSR_ID(16, "pcie_clk_inp"),
 652	CLK_MSR_ID(17, "pcie_clk_inn"),
 653	CLK_MSR_ID(18, "mpll_clk_test_out"),
 654	CLK_MSR_ID(19, "hifi_pll"),
 655	CLK_MSR_ID(20, "gp0_pll"),
 656	CLK_MSR_ID(21, "gp1_pll"),
 657	CLK_MSR_ID(22, "eth_mppll_50m_ckout"),
 658	CLK_MSR_ID(23, "sys_pll_div16"),
 659	CLK_MSR_ID(24, "ddr_dpll_pt_clk"),
 660	CLK_MSR_ID(30, "mod_eth_phy_ref_clk"),
 661	CLK_MSR_ID(31, "mod_eth_tx_clk"),
 662	CLK_MSR_ID(32, "eth_125m"),
 663	CLK_MSR_ID(33, "eth_rmii"),
 664	CLK_MSR_ID(34, "co_clkin_to_mac"),
 665	CLK_MSR_ID(35, "mod_eth_rx_clk_rmii"),
 666	CLK_MSR_ID(36, "co_rx_clk"),
 667	CLK_MSR_ID(37, "co_tx_clk"),
 668	CLK_MSR_ID(38, "eth_phy_rxclk"),
 669	CLK_MSR_ID(39, "eth_phy_plltxclk"),
 670	CLK_MSR_ID(40, "ephy_test_clk"),
 671	CLK_MSR_ID(50, "vid_pll_div_clk_out"),
 672	CLK_MSR_ID(51, "enci"),
 673	CLK_MSR_ID(52, "encp"),
 674	CLK_MSR_ID(53, "encl"),
 675	CLK_MSR_ID(54, "vdac"),
 676	CLK_MSR_ID(55, "cdac_clk_c"),
 677	CLK_MSR_ID(56, "mod_tcon_clko"),
 678	CLK_MSR_ID(57, "lcd_an_clk_ph2"),
 679	CLK_MSR_ID(58, "lcd_an_clk_ph3"),
 680	CLK_MSR_ID(59, "hdmitx_pixel"),
 681	CLK_MSR_ID(60, "vdin_meas"),
 682	CLK_MSR_ID(61, "vpu"),
 683	CLK_MSR_ID(62, "vpu_clkb"),
 684	CLK_MSR_ID(63, "vpu_clkb_tmp"),
 685	CLK_MSR_ID(64, "vpu_clkc"),
 686	CLK_MSR_ID(65, "vid_lock"),
 687	CLK_MSR_ID(66, "vapb"),
 688	CLK_MSR_ID(67, "ge2d"),
 689	CLK_MSR_ID(68, "cts_hdcp22_esmclk"),
 690	CLK_MSR_ID(69, "cts_hdcp22_skpclk"),
 691	CLK_MSR_ID(76, "hdmitx_tmds"),
 692	CLK_MSR_ID(77, "hdmitx_sys_clk"),
 693	CLK_MSR_ID(78, "hdmitx_fe_clk"),
 694	CLK_MSR_ID(79, "rama"),
 695	CLK_MSR_ID(93, "vdec"),
 696	CLK_MSR_ID(99, "hevcf"),
 697	CLK_MSR_ID(100, "demod_core"),
 698	CLK_MSR_ID(101, "adc_extclk_in"),
 699	CLK_MSR_ID(102, "cts_demod_core_t2_clk"),
 700	CLK_MSR_ID(103, "adc_dpll_intclk"),
 701	CLK_MSR_ID(104, "adc_dpll_clk_b3"),
 702	CLK_MSR_ID(105, "s2_adc_clk"),
 703	CLK_MSR_ID(106, "deskew_pll_clk_div32_out"),
 704	CLK_MSR_ID(110, "sc"),
 705	CLK_MSR_ID(111, "sar_adc"),
 706	CLK_MSR_ID(113, "sd_emmc_c"),
 707	CLK_MSR_ID(114, "sd_emmc_b"),
 708	CLK_MSR_ID(115, "sd_emmc_a"),
 709	CLK_MSR_ID(116, "gpio_msr_clk"),
 710	CLK_MSR_ID(118, "spicc0"),
 711	CLK_MSR_ID(121, "ts"),
 712	CLK_MSR_ID(130, "audio_vad_clk"),
 713	CLK_MSR_ID(131, "acodec_dac_clk_x128"),
 714	CLK_MSR_ID(132, "audio_locker_in_clk"),
 715	CLK_MSR_ID(133, "audio_locker_out_clk"),
 716	CLK_MSR_ID(134, "audio_tdmout_c_sclk"),
 717	CLK_MSR_ID(135, "audio_tdmout_b_sclk"),
 718	CLK_MSR_ID(136, "audio_tdmout_a_sclk"),
 719	CLK_MSR_ID(137, "audio_tdmin_lb_sclk"),
 720	CLK_MSR_ID(138, "audio_tdmin_c_sclk"),
 721	CLK_MSR_ID(139, "audio_tdmin_b_sclk"),
 722	CLK_MSR_ID(140, "audio_tdmin_a_sclk"),
 723	CLK_MSR_ID(141, "audio_resamplea_clk"),
 724	CLK_MSR_ID(142, "audio_pdm_sysclk"),
 725	CLK_MSR_ID(143, "audio_spdifout_b_mst_clk"),
 726	CLK_MSR_ID(144, "audio_spdifout_mst_clk"),
 727	CLK_MSR_ID(145, "audio_spdifin_mst_clk"),
 728	CLK_MSR_ID(146, "audio_pdm_dclk"),
 729	CLK_MSR_ID(147, "audio_resampleb_clk"),
 730	CLK_MSR_ID(160, "pwm_j"),
 731	CLK_MSR_ID(161, "pwm_i"),
 732	CLK_MSR_ID(162, "pwm_h"),
 733	CLK_MSR_ID(163, "pwm_g"),
 734	CLK_MSR_ID(164, "pwm_f"),
 735	CLK_MSR_ID(165, "pwm_e"),
 736	CLK_MSR_ID(166, "pwm_d"),
 737	CLK_MSR_ID(167, "pwm_c"),
 738	CLK_MSR_ID(168, "pwm_b"),
 739	CLK_MSR_ID(169, "pwm_a"),
 740	CLK_MSR_ID(176, "rng_ring_0"),
 741	CLK_MSR_ID(177, "rng_ring_1"),
 742	CLK_MSR_ID(178, "rng_ring_2"),
 743	CLK_MSR_ID(179, "rng_ring_3"),
 744	CLK_MSR_ID(180, "dmc_osc_ring(LVT16)"),
 745	CLK_MSR_ID(181, "gpu_osc_ring0(LVT16)"),
 746	CLK_MSR_ID(182, "gpu_osc_ring1(ULVT16)"),
 747	CLK_MSR_ID(183, "gpu_osc_ring2(SLVT16)"),
 748	CLK_MSR_ID(184, "vpu_osc_ring0(SVT24)"),
 749	CLK_MSR_ID(185, "vpu_osc_ring1(LVT20)"),
 750	CLK_MSR_ID(186, "vpu_osc_ring2(LVT16)"),
 751	CLK_MSR_ID(187, "dos_osc_ring0(SVT24)"),
 752	CLK_MSR_ID(188, "dos_osc_ring1(SVT16)"),
 753	CLK_MSR_ID(189, "dos_osc_ring2(LVT16)"),
 754	CLK_MSR_ID(190, "dos_osc_ring3(ULVT20)"),
 755	CLK_MSR_ID(192, "axi_sram_osc_ring(SVT16)"),
 756	CLK_MSR_ID(193, "demod_osc_ring0"),
 757	CLK_MSR_ID(194, "demod_osc_ring1"),
 758	CLK_MSR_ID(195, "sar_osc_ring"),
 759	CLK_MSR_ID(196, "sys_cpu_osc_ring0"),
 760	CLK_MSR_ID(197, "sys_cpu_osc_ring1"),
 761	CLK_MSR_ID(198, "sys_cpu_osc_ring2"),
 762	CLK_MSR_ID(199, "sys_cpu_osc_ring3"),
 763	CLK_MSR_ID(200, "sys_cpu_osc_ring4"),
 764	CLK_MSR_ID(201, "sys_cpu_osc_ring5"),
 765	CLK_MSR_ID(202, "sys_cpu_osc_ring6"),
 766	CLK_MSR_ID(203, "sys_cpu_osc_ring7"),
 767	CLK_MSR_ID(204, "sys_cpu_osc_ring8"),
 768	CLK_MSR_ID(205, "sys_cpu_osc_ring9"),
 769	CLK_MSR_ID(206, "sys_cpu_osc_ring10"),
 770	CLK_MSR_ID(207, "sys_cpu_osc_ring11"),
 771	CLK_MSR_ID(208, "sys_cpu_osc_ring12"),
 772	CLK_MSR_ID(209, "sys_cpu_osc_ring13"),
 773	CLK_MSR_ID(210, "sys_cpu_osc_ring14"),
 774	CLK_MSR_ID(211, "sys_cpu_osc_ring15"),
 775	CLK_MSR_ID(212, "sys_cpu_osc_ring16"),
 776	CLK_MSR_ID(213, "sys_cpu_osc_ring17"),
 777	CLK_MSR_ID(214, "sys_cpu_osc_ring18"),
 778	CLK_MSR_ID(215, "sys_cpu_osc_ring19"),
 779	CLK_MSR_ID(216, "sys_cpu_osc_ring20"),
 780	CLK_MSR_ID(217, "sys_cpu_osc_ring21"),
 781	CLK_MSR_ID(218, "sys_cpu_osc_ring22"),
 782	CLK_MSR_ID(219, "sys_cpu_osc_ring23"),
 783	CLK_MSR_ID(220, "sys_cpu_osc_ring24"),
 784	CLK_MSR_ID(221, "sys_cpu_osc_ring25"),
 785	CLK_MSR_ID(222, "sys_cpu_osc_ring26"),
 786	CLK_MSR_ID(223, "sys_cpu_osc_ring27"),
 787
 788};
 789
 790static int meson_measure_id(struct meson_msr_id *clk_msr_id,
 791			    unsigned int duration)
 792{
 793	struct meson_msr *priv = clk_msr_id->priv;
 794	const struct msr_reg_offset *reg = priv->data.reg;
 795	unsigned int val;
 796	int ret;
 797
 798	ret = mutex_lock_interruptible(&measure_lock);
 799	if (ret)
 800		return ret;
 801
 802	regmap_write(priv->regmap, reg->freq_ctrl, 0);
 803
 804	/* Set measurement duration */
 805	regmap_update_bits(priv->regmap, reg->freq_ctrl, MSR_DURATION,
 806			   FIELD_PREP(MSR_DURATION, duration - 1));
 807
 808	/* Set ID */
 809	regmap_update_bits(priv->regmap, reg->freq_ctrl, MSR_CLK_SRC,
 810			   FIELD_PREP(MSR_CLK_SRC, clk_msr_id->id));
 811
 812	/* Enable & Start */
 813	regmap_update_bits(priv->regmap, reg->freq_ctrl,
 814			   MSR_RUN | MSR_ENABLE,
 815			   MSR_RUN | MSR_ENABLE);
 816
 817	ret = regmap_read_poll_timeout(priv->regmap, reg->freq_ctrl,
 818				       val, !(val & MSR_BUSY), 10, 10000);
 819	if (ret) {
 820		mutex_unlock(&measure_lock);
 821		return ret;
 822	}
 823
 824	/* Disable */
 825	regmap_update_bits(priv->regmap, reg->freq_ctrl, MSR_ENABLE, 0);
 826
 827	/* Get the value in multiple of gate time counts */
 828	regmap_read(priv->regmap, reg->freq_val, &val);
 829
 830	mutex_unlock(&measure_lock);
 831
 832	if (val >= MSR_VAL_MASK)
 833		return -EINVAL;
 834
 835	return DIV_ROUND_CLOSEST_ULL((val & MSR_VAL_MASK) * 1000000ULL,
 836				     duration);
 837}
 838
 839static int meson_measure_best_id(struct meson_msr_id *clk_msr_id,
 840				    unsigned int *precision)
 841{
 842	unsigned int duration = DIV_MAX;
 843	int ret;
 844
 845	/* Start from max duration and down to min duration */
 846	do {
 847		ret = meson_measure_id(clk_msr_id, duration);
 848		if (ret >= 0)
 849			*precision = (2 * 1000000) / duration;
 850		else
 851			duration -= DIV_STEP;
 852	} while (duration >= DIV_MIN && ret == -EINVAL);
 853
 854	return ret;
 855}
 856
 857static int clk_msr_show(struct seq_file *s, void *data)
 858{
 859	struct meson_msr_id *clk_msr_id = s->private;
 860	unsigned int precision = 0;
 861	int val;
 862
 863	val = meson_measure_best_id(clk_msr_id, &precision);
 864	if (val < 0)
 865		return val;
 866
 867	seq_printf(s, "%d\t+/-%dHz\n", val, precision);
 868
 869	return 0;
 870}
 871DEFINE_SHOW_ATTRIBUTE(clk_msr);
 872
 873static int clk_msr_summary_show(struct seq_file *s, void *data)
 874{
 875	struct meson_msr_id *msr_table = s->private;
 876	unsigned int msr_count = msr_table->priv->data.msr_count;
 877	unsigned int precision = 0;
 878	int val, i;
 879
 880	seq_puts(s, "  clock                     rate    precision\n");
 881	seq_puts(s, "---------------------------------------------\n");
 882
 883	for (i = 0 ; i < msr_count ; ++i) {
 884		if (!msr_table[i].name)
 885			continue;
 886
 887		val = meson_measure_best_id(&msr_table[i], &precision);
 888		if (val < 0)
 889			return val;
 890
 891		seq_printf(s, " %-20s %10d    +/-%dHz\n",
 892			   msr_table[i].name, val, precision);
 893	}
 894
 895	return 0;
 896}
 897DEFINE_SHOW_ATTRIBUTE(clk_msr_summary);
 898
 899static struct regmap_config meson_clk_msr_regmap_config = {
 900	.reg_bits = 32,
 901	.val_bits = 32,
 902	.reg_stride = 4,
 903};
 904
 905static int meson_msr_probe(struct platform_device *pdev)
 906{
 907	const struct meson_msr_data *match_data;
 908	struct meson_msr *priv;
 909	struct dentry *root, *clks;
 910	struct resource *res;
 911	void __iomem *base;
 912	int i;
 913
 914	priv = devm_kzalloc(&pdev->dev, sizeof(struct meson_msr),
 915			    GFP_KERNEL);
 916	if (!priv)
 917		return -ENOMEM;
 918
 919	match_data = device_get_match_data(&pdev->dev);
 920	if (!match_data) {
 921		dev_err(&pdev->dev, "failed to get match data\n");
 922		return -ENODEV;
 923	}
 924
 925	priv->data.msr_table = devm_kcalloc(&pdev->dev,
 926					    match_data->msr_count,
 927					    sizeof(struct meson_msr_id),
 928					    GFP_KERNEL);
 929	if (!priv->data.msr_table)
 930		return -ENOMEM;
 931
 932	memcpy(priv->data.msr_table, match_data->msr_table,
 933	       match_data->msr_count * sizeof(struct meson_msr_id));
 934	priv->data.msr_count = match_data->msr_count;
 935
 936	base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
 937	if (IS_ERR(base))
 938		return PTR_ERR(base);
 939
 940	meson_clk_msr_regmap_config.max_register = resource_size(res) - 4;
 941	priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
 942					     &meson_clk_msr_regmap_config);
 943	if (IS_ERR(priv->regmap))
 944		return PTR_ERR(priv->regmap);
 945
 946	priv->data.reg = devm_kzalloc(&pdev->dev, sizeof(struct msr_reg_offset),
 947				      GFP_KERNEL);
 948	if (!priv->data.reg)
 949		return -ENOMEM;
 950
 951	memcpy((void *)priv->data.reg, match_data->reg,
 952	       sizeof(struct msr_reg_offset));
 953
 954	root = debugfs_create_dir("meson-clk-msr", NULL);
 955	clks = debugfs_create_dir("clks", root);
 956
 957	debugfs_create_file("measure_summary", 0444, root,
 958			    priv->data.msr_table, &clk_msr_summary_fops);
 959
 960	for (i = 0 ; i < priv->data.msr_count ; ++i) {
 961		if (!priv->data.msr_table[i].name)
 962			continue;
 963
 964		priv->data.msr_table[i].priv = priv;
 965
 966		debugfs_create_file(priv->data.msr_table[i].name, 0444, clks,
 967				    &priv->data.msr_table[i], &clk_msr_fops);
 968	}
 969
 970	return 0;
 971}
 972
 973static const struct msr_reg_offset msr_reg_offset = {
 974	.duty_val = 0x0,
 975	.freq_ctrl = 0x4,
 976	.duty_ctrl = 0x8,
 977	.freq_val = 0xc,
 978};
 979
 980static const struct meson_msr_data clk_msr_gx_data = {
 981	.msr_table = (void *)clk_msr_gx,
 982	.msr_count = ARRAY_SIZE(clk_msr_gx),
 983	.reg = &msr_reg_offset,
 984};
 985
 986static const struct meson_msr_data clk_msr_m8_data = {
 987	.msr_table = (void *)clk_msr_m8,
 988	.msr_count = ARRAY_SIZE(clk_msr_m8),
 989	.reg = &msr_reg_offset,
 990};
 991
 992static const struct meson_msr_data clk_msr_axg_data = {
 993	.msr_table = (void *)clk_msr_axg,
 994	.msr_count = ARRAY_SIZE(clk_msr_axg),
 995	.reg = &msr_reg_offset,
 996};
 997
 998static const struct meson_msr_data clk_msr_g12a_data = {
 999	.msr_table = (void *)clk_msr_g12a,
1000	.msr_count = ARRAY_SIZE(clk_msr_g12a),
1001	.reg = &msr_reg_offset,
1002};
1003
1004static const struct meson_msr_data clk_msr_sm1_data = {
1005	.msr_table = (void *)clk_msr_sm1,
1006	.msr_count = ARRAY_SIZE(clk_msr_sm1),
1007	.reg = &msr_reg_offset,
1008};
1009
1010static const struct msr_reg_offset msr_reg_offset_v2 = {
1011	.freq_ctrl = 0x0,
1012	.duty_ctrl = 0x4,
1013	.freq_val = 0x8,
1014	.duty_val = 0x18,
1015};
1016
1017static const struct meson_msr_data clk_msr_c3_data = {
1018	.msr_table = (void *)clk_msr_c3,
1019	.msr_count = ARRAY_SIZE(clk_msr_c3),
1020	.reg = &msr_reg_offset_v2,
1021};
1022
1023static const struct meson_msr_data clk_msr_s4_data = {
1024	.msr_table = (void *)clk_msr_s4,
1025	.msr_count = ARRAY_SIZE(clk_msr_s4),
1026	.reg = &msr_reg_offset_v2,
1027};
1028
1029static const struct of_device_id meson_msr_match_table[] = {
1030	{
1031		.compatible = "amlogic,meson-gx-clk-measure",
1032		.data = &clk_msr_gx_data,
1033	},
1034	{
1035		.compatible = "amlogic,meson8-clk-measure",
1036		.data = &clk_msr_m8_data,
1037	},
1038	{
1039		.compatible = "amlogic,meson8b-clk-measure",
1040		.data = &clk_msr_m8_data,
1041	},
1042	{
1043		.compatible = "amlogic,meson-axg-clk-measure",
1044		.data = &clk_msr_axg_data,
1045	},
1046	{
1047		.compatible = "amlogic,meson-g12a-clk-measure",
1048		.data = &clk_msr_g12a_data,
1049	},
1050	{
1051		.compatible = "amlogic,meson-sm1-clk-measure",
1052		.data = &clk_msr_sm1_data,
1053	},
1054	{
1055		.compatible = "amlogic,c3-clk-measure",
1056		.data = &clk_msr_c3_data,
1057	},
1058	{
1059		.compatible = "amlogic,s4-clk-measure",
1060		.data = &clk_msr_s4_data,
1061	},
1062	{ /* sentinel */ }
1063};
1064MODULE_DEVICE_TABLE(of, meson_msr_match_table);
1065
1066static struct platform_driver meson_msr_driver = {
1067	.probe	= meson_msr_probe,
1068	.driver = {
1069		.name		= "meson_msr",
1070		.of_match_table	= meson_msr_match_table,
1071	},
1072};
1073module_platform_driver(meson_msr_driver);
1074MODULE_DESCRIPTION("Amlogic Meson SoC Clock Measure driver");
1075MODULE_LICENSE("GPL v2");