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qla_sup.c
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linux-6.19.14/drivers/scsi/qla2xxx/qla_sup.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * QLogic Fibre Channel HBA Driver 4 * Copyright (c) 2003-2014 QLogic Corporation 5 */ 6#include "qla_def.h" 7 8#include <linux/delay.h> 9#include <linux/slab.h> 10#include <linux/vmalloc.h> 11#include <linux/uaccess.h> 12 13/* 14 * NVRAM support routines 15 */ 16 17/** 18 * qla2x00_lock_nvram_access() - 19 * @ha: HA context 20 */ 21static void 22qla2x00_lock_nvram_access(struct qla_hw_data *ha) 23{ 24 uint16_t data; 25 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 26 27 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) { 28 data = rd_reg_word(®->nvram); 29 while (data & NVR_BUSY) { 30 udelay(100); 31 data = rd_reg_word(®->nvram); 32 } 33 34 /* Lock resource */ 35 wrt_reg_word(®->u.isp2300.host_semaphore, 0x1); 36 rd_reg_word(®->u.isp2300.host_semaphore); 37 udelay(5); 38 data = rd_reg_word(®->u.isp2300.host_semaphore); 39 while ((data & BIT_0) == 0) { 40 /* Lock failed */ 41 udelay(100); 42 wrt_reg_word(®->u.isp2300.host_semaphore, 0x1); 43 rd_reg_word(®->u.isp2300.host_semaphore); 44 udelay(5); 45 data = rd_reg_word(®->u.isp2300.host_semaphore); 46 } 47 } 48} 49 50/** 51 * qla2x00_unlock_nvram_access() - 52 * @ha: HA context 53 */ 54static void 55qla2x00_unlock_nvram_access(struct qla_hw_data *ha) 56{ 57 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 58 59 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) { 60 wrt_reg_word(®->u.isp2300.host_semaphore, 0); 61 rd_reg_word(®->u.isp2300.host_semaphore); 62 } 63} 64 65/** 66 * qla2x00_nv_write() - Prepare for NVRAM read/write operation. 67 * @ha: HA context 68 * @data: Serial interface selector 69 */ 70static void 71qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data) 72{ 73 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 74 75 wrt_reg_word(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE); 76 rd_reg_word(®->nvram); /* PCI Posting. */ 77 NVRAM_DELAY(); 78 wrt_reg_word(®->nvram, data | NVR_SELECT | NVR_CLOCK | 79 NVR_WRT_ENABLE); 80 rd_reg_word(®->nvram); /* PCI Posting. */ 81 NVRAM_DELAY(); 82 wrt_reg_word(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE); 83 rd_reg_word(®->nvram); /* PCI Posting. */ 84 NVRAM_DELAY(); 85} 86 87/** 88 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from 89 * NVRAM. 90 * @ha: HA context 91 * @nv_cmd: NVRAM command 92 * 93 * Bit definitions for NVRAM command: 94 * 95 * Bit 26 = start bit 96 * Bit 25, 24 = opcode 97 * Bit 23-16 = address 98 * Bit 15-0 = write data 99 * 100 * Returns the word read from nvram @addr. 101 */ 102static uint16_t 103qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd) 104{ 105 uint8_t cnt; 106 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 107 uint16_t data = 0; 108 uint16_t reg_data; 109 110 /* Send command to NVRAM. */ 111 nv_cmd <<= 5; 112 for (cnt = 0; cnt < 11; cnt++) { 113 if (nv_cmd & BIT_31) 114 qla2x00_nv_write(ha, NVR_DATA_OUT); 115 else 116 qla2x00_nv_write(ha, 0); 117 nv_cmd <<= 1; 118 } 119 120 /* Read data from NVRAM. */ 121 for (cnt = 0; cnt < 16; cnt++) { 122 wrt_reg_word(®->nvram, NVR_SELECT | NVR_CLOCK); 123 rd_reg_word(®->nvram); /* PCI Posting. */ 124 NVRAM_DELAY(); 125 data <<= 1; 126 reg_data = rd_reg_word(®->nvram); 127 if (reg_data & NVR_DATA_IN) 128 data |= BIT_0; 129 wrt_reg_word(®->nvram, NVR_SELECT); 130 rd_reg_word(®->nvram); /* PCI Posting. */ 131 NVRAM_DELAY(); 132 } 133 134 /* Deselect chip. */ 135 wrt_reg_word(®->nvram, NVR_DESELECT); 136 rd_reg_word(®->nvram); /* PCI Posting. */ 137 NVRAM_DELAY(); 138 139 return data; 140} 141 142 143/** 144 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the 145 * request routine to get the word from NVRAM. 146 * @ha: HA context 147 * @addr: Address in NVRAM to read 148 * 149 * Returns the word read from nvram @addr. 150 */ 151static uint16_t 152qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr) 153{ 154 uint16_t data; 155 uint32_t nv_cmd; 156 157 nv_cmd = addr << 16; 158 nv_cmd |= NV_READ_OP; 159 data = qla2x00_nvram_request(ha, nv_cmd); 160 161 return (data); 162} 163 164/** 165 * qla2x00_nv_deselect() - Deselect NVRAM operations. 166 * @ha: HA context 167 */ 168static void 169qla2x00_nv_deselect(struct qla_hw_data *ha) 170{ 171 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 172 173 wrt_reg_word(®->nvram, NVR_DESELECT); 174 rd_reg_word(®->nvram); /* PCI Posting. */ 175 NVRAM_DELAY(); 176} 177 178/** 179 * qla2x00_write_nvram_word() - Write NVRAM data. 180 * @ha: HA context 181 * @addr: Address in NVRAM to write 182 * @data: word to program 183 */ 184static void 185qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, __le16 data) 186{ 187 int count; 188 uint16_t word; 189 uint32_t nv_cmd, wait_cnt; 190 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 191 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 192 193 qla2x00_nv_write(ha, NVR_DATA_OUT); 194 qla2x00_nv_write(ha, 0); 195 qla2x00_nv_write(ha, 0); 196 197 for (word = 0; word < 8; word++) 198 qla2x00_nv_write(ha, NVR_DATA_OUT); 199 200 qla2x00_nv_deselect(ha); 201 202 /* Write data */ 203 nv_cmd = (addr << 16) | NV_WRITE_OP; 204 nv_cmd |= (__force u16)data; 205 nv_cmd <<= 5; 206 for (count = 0; count < 27; count++) { 207 if (nv_cmd & BIT_31) 208 qla2x00_nv_write(ha, NVR_DATA_OUT); 209 else 210 qla2x00_nv_write(ha, 0); 211 212 nv_cmd <<= 1; 213 } 214 215 qla2x00_nv_deselect(ha); 216 217 /* Wait for NVRAM to become ready */ 218 wrt_reg_word(®->nvram, NVR_SELECT); 219 rd_reg_word(®->nvram); /* PCI Posting. */ 220 wait_cnt = NVR_WAIT_CNT; 221 do { 222 if (!--wait_cnt) { 223 ql_dbg(ql_dbg_user, vha, 0x708d, 224 "NVRAM didn't go ready...\n"); 225 break; 226 } 227 NVRAM_DELAY(); 228 word = rd_reg_word(®->nvram); 229 } while ((word & NVR_DATA_IN) == 0); 230 231 qla2x00_nv_deselect(ha); 232 233 /* Disable writes */ 234 qla2x00_nv_write(ha, NVR_DATA_OUT); 235 for (count = 0; count < 10; count++) 236 qla2x00_nv_write(ha, 0); 237 238 qla2x00_nv_deselect(ha); 239} 240 241static int 242qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr, 243 __le16 data, uint32_t tmo) 244{ 245 int ret, count; 246 uint16_t word; 247 uint32_t nv_cmd; 248 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 249 250 ret = QLA_SUCCESS; 251 252 qla2x00_nv_write(ha, NVR_DATA_OUT); 253 qla2x00_nv_write(ha, 0); 254 qla2x00_nv_write(ha, 0); 255 256 for (word = 0; word < 8; word++) 257 qla2x00_nv_write(ha, NVR_DATA_OUT); 258 259 qla2x00_nv_deselect(ha); 260 261 /* Write data */ 262 nv_cmd = (addr << 16) | NV_WRITE_OP; 263 nv_cmd |= (__force u16)data; 264 nv_cmd <<= 5; 265 for (count = 0; count < 27; count++) { 266 if (nv_cmd & BIT_31) 267 qla2x00_nv_write(ha, NVR_DATA_OUT); 268 else 269 qla2x00_nv_write(ha, 0); 270 271 nv_cmd <<= 1; 272 } 273 274 qla2x00_nv_deselect(ha); 275 276 /* Wait for NVRAM to become ready */ 277 wrt_reg_word(®->nvram, NVR_SELECT); 278 rd_reg_word(®->nvram); /* PCI Posting. */ 279 do { 280 NVRAM_DELAY(); 281 word = rd_reg_word(®->nvram); 282 if (!--tmo) { 283 ret = QLA_FUNCTION_FAILED; 284 break; 285 } 286 } while ((word & NVR_DATA_IN) == 0); 287 288 qla2x00_nv_deselect(ha); 289 290 /* Disable writes */ 291 qla2x00_nv_write(ha, NVR_DATA_OUT); 292 for (count = 0; count < 10; count++) 293 qla2x00_nv_write(ha, 0); 294 295 qla2x00_nv_deselect(ha); 296 297 return ret; 298} 299 300/** 301 * qla2x00_clear_nvram_protection() - 302 * @ha: HA context 303 */ 304static int 305qla2x00_clear_nvram_protection(struct qla_hw_data *ha) 306{ 307 int ret, stat; 308 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 309 uint32_t word, wait_cnt; 310 __le16 wprot, wprot_old; 311 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 312 313 /* Clear NVRAM write protection. */ 314 ret = QLA_FUNCTION_FAILED; 315 316 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base)); 317 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base, 318 cpu_to_le16(0x1234), 100000); 319 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base)); 320 if (stat != QLA_SUCCESS || wprot != cpu_to_le16(0x1234)) { 321 /* Write enable. */ 322 qla2x00_nv_write(ha, NVR_DATA_OUT); 323 qla2x00_nv_write(ha, 0); 324 qla2x00_nv_write(ha, 0); 325 for (word = 0; word < 8; word++) 326 qla2x00_nv_write(ha, NVR_DATA_OUT); 327 328 qla2x00_nv_deselect(ha); 329 330 /* Enable protection register. */ 331 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 332 qla2x00_nv_write(ha, NVR_PR_ENABLE); 333 qla2x00_nv_write(ha, NVR_PR_ENABLE); 334 for (word = 0; word < 8; word++) 335 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); 336 337 qla2x00_nv_deselect(ha); 338 339 /* Clear protection register (ffff is cleared). */ 340 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 341 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 342 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 343 for (word = 0; word < 8; word++) 344 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); 345 346 qla2x00_nv_deselect(ha); 347 348 /* Wait for NVRAM to become ready. */ 349 wrt_reg_word(®->nvram, NVR_SELECT); 350 rd_reg_word(®->nvram); /* PCI Posting. */ 351 wait_cnt = NVR_WAIT_CNT; 352 do { 353 if (!--wait_cnt) { 354 ql_dbg(ql_dbg_user, vha, 0x708e, 355 "NVRAM didn't go ready...\n"); 356 break; 357 } 358 NVRAM_DELAY(); 359 word = rd_reg_word(®->nvram); 360 } while ((word & NVR_DATA_IN) == 0); 361 362 if (wait_cnt) 363 ret = QLA_SUCCESS; 364 } else 365 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old); 366 367 return ret; 368} 369 370static void 371qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat) 372{ 373 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 374 uint32_t word, wait_cnt; 375 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 376 377 if (stat != QLA_SUCCESS) 378 return; 379 380 /* Set NVRAM write protection. */ 381 /* Write enable. */ 382 qla2x00_nv_write(ha, NVR_DATA_OUT); 383 qla2x00_nv_write(ha, 0); 384 qla2x00_nv_write(ha, 0); 385 for (word = 0; word < 8; word++) 386 qla2x00_nv_write(ha, NVR_DATA_OUT); 387 388 qla2x00_nv_deselect(ha); 389 390 /* Enable protection register. */ 391 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 392 qla2x00_nv_write(ha, NVR_PR_ENABLE); 393 qla2x00_nv_write(ha, NVR_PR_ENABLE); 394 for (word = 0; word < 8; word++) 395 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); 396 397 qla2x00_nv_deselect(ha); 398 399 /* Enable protection register. */ 400 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 401 qla2x00_nv_write(ha, NVR_PR_ENABLE); 402 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 403 for (word = 0; word < 8; word++) 404 qla2x00_nv_write(ha, NVR_PR_ENABLE); 405 406 qla2x00_nv_deselect(ha); 407 408 /* Wait for NVRAM to become ready. */ 409 wrt_reg_word(®->nvram, NVR_SELECT); 410 rd_reg_word(®->nvram); /* PCI Posting. */ 411 wait_cnt = NVR_WAIT_CNT; 412 do { 413 if (!--wait_cnt) { 414 ql_dbg(ql_dbg_user, vha, 0x708f, 415 "NVRAM didn't go ready...\n"); 416 break; 417 } 418 NVRAM_DELAY(); 419 word = rd_reg_word(®->nvram); 420 } while ((word & NVR_DATA_IN) == 0); 421} 422 423 424/*****************************************************************************/ 425/* Flash Manipulation Routines */ 426/*****************************************************************************/ 427 428static inline uint32_t 429flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr) 430{ 431 return ha->flash_conf_off + faddr; 432} 433 434static inline uint32_t 435flash_data_addr(struct qla_hw_data *ha, uint32_t faddr) 436{ 437 return ha->flash_data_off + faddr; 438} 439 440static inline uint32_t 441nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr) 442{ 443 return ha->nvram_conf_off + naddr; 444} 445 446static inline uint32_t 447nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr) 448{ 449 return ha->nvram_data_off + naddr; 450} 451 452static int 453qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t *data) 454{ 455 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 456 ulong cnt = 30000; 457 458 wrt_reg_dword(®->flash_addr, addr & ~FARX_DATA_FLAG); 459 460 while (cnt--) { 461 if (rd_reg_dword(®->flash_addr) & FARX_DATA_FLAG) { 462 *data = rd_reg_dword(®->flash_data); 463 return QLA_SUCCESS; 464 } 465 udelay(10); 466 cond_resched(); 467 } 468 469 ql_log(ql_log_warn, pci_get_drvdata(ha->pdev), 0x7090, 470 "Flash read dword at %x timeout.\n", addr); 471 *data = 0xDEADDEAD; 472 return QLA_FUNCTION_TIMEOUT; 473} 474 475int 476qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 477 uint32_t dwords) 478{ 479 ulong i; 480 int ret = QLA_SUCCESS; 481 struct qla_hw_data *ha = vha->hw; 482 483 /* Dword reads to flash. */ 484 faddr = flash_data_addr(ha, faddr); 485 for (i = 0; i < dwords; i++, faddr++, dwptr++) { 486 ret = qla24xx_read_flash_dword(ha, faddr, dwptr); 487 if (ret != QLA_SUCCESS) 488 break; 489 cpu_to_le32s(dwptr); 490 } 491 492 return ret; 493} 494 495static int 496qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data) 497{ 498 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 499 ulong cnt = 500000; 500 501 wrt_reg_dword(®->flash_data, data); 502 wrt_reg_dword(®->flash_addr, addr | FARX_DATA_FLAG); 503 504 while (cnt--) { 505 if (!(rd_reg_dword(®->flash_addr) & FARX_DATA_FLAG)) 506 return QLA_SUCCESS; 507 udelay(10); 508 cond_resched(); 509 } 510 511 ql_log(ql_log_warn, pci_get_drvdata(ha->pdev), 0x7090, 512 "Flash write dword at %x timeout.\n", addr); 513 return QLA_FUNCTION_TIMEOUT; 514} 515 516static void 517qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id, 518 uint8_t *flash_id) 519{ 520 uint32_t faddr, ids = 0; 521 522 *man_id = *flash_id = 0; 523 524 faddr = flash_conf_addr(ha, 0x03ab); 525 if (!qla24xx_read_flash_dword(ha, faddr, &ids)) { 526 *man_id = LSB(ids); 527 *flash_id = MSB(ids); 528 } 529 530 /* Check if man_id and flash_id are valid. */ 531 if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) { 532 /* Read information using 0x9f opcode 533 * Device ID, Mfg ID would be read in the format: 534 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID> 535 * Example: ATMEL 0x00 01 45 1F 536 * Extract MFG and Dev ID from last two bytes. 537 */ 538 faddr = flash_conf_addr(ha, 0x009f); 539 if (!qla24xx_read_flash_dword(ha, faddr, &ids)) { 540 *man_id = LSB(ids); 541 *flash_id = MSB(ids); 542 } 543 } 544} 545 546static int 547qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start) 548{ 549 const char *loc, *locations[] = { "DEF", "PCI" }; 550 uint32_t pcihdr, pcids; 551 uint16_t cnt, chksum; 552 __le16 *wptr; 553 struct qla_hw_data *ha = vha->hw; 554 struct req_que *req = ha->req_q_map[0]; 555 struct qla_flt_location *fltl = (void *)req->ring; 556 uint32_t *dcode = (uint32_t *)req->ring; 557 uint8_t *buf = (void *)req->ring, *bcode, last_image; 558 int rc; 559 560 /* 561 * FLT-location structure resides after the last PCI region. 562 */ 563 564 /* Begin with sane defaults. */ 565 loc = locations[0]; 566 *start = 0; 567 if (IS_QLA24XX_TYPE(ha)) 568 *start = FA_FLASH_LAYOUT_ADDR_24; 569 else if (IS_QLA25XX(ha)) 570 *start = FA_FLASH_LAYOUT_ADDR; 571 else if (IS_QLA81XX(ha)) 572 *start = FA_FLASH_LAYOUT_ADDR_81; 573 else if (IS_P3P_TYPE(ha)) { 574 *start = FA_FLASH_LAYOUT_ADDR_82; 575 goto end; 576 } else if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 577 *start = FA_FLASH_LAYOUT_ADDR_83; 578 goto end; 579 } else if (IS_QLA28XX(ha)) { 580 *start = FA_FLASH_LAYOUT_ADDR_28; 581 goto end; 582 } 583 584 /* Begin with first PCI expansion ROM header. */ 585 pcihdr = 0; 586 do { 587 /* Verify PCI expansion ROM header. */ 588 rc = qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20); 589 if (rc) { 590 ql_log(ql_log_info, vha, 0x016d, 591 "Unable to read PCI Expansion Rom Header (%x).\n", rc); 592 return QLA_FUNCTION_FAILED; 593 } 594 bcode = buf + (pcihdr % 4); 595 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) 596 goto end; 597 598 /* Locate PCI data structure. */ 599 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]); 600 rc = qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20); 601 if (rc) { 602 ql_log(ql_log_info, vha, 0x0179, 603 "Unable to read PCI Data Structure (%x).\n", rc); 604 return QLA_FUNCTION_FAILED; 605 } 606 bcode = buf + (pcihdr % 4); 607 608 /* Validate signature of PCI data structure. */ 609 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' || 610 bcode[0x2] != 'I' || bcode[0x3] != 'R') 611 goto end; 612 613 last_image = bcode[0x15] & BIT_7; 614 615 /* Locate next PCI expansion ROM. */ 616 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512; 617 } while (!last_image); 618 619 /* Now verify FLT-location structure. */ 620 rc = qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, sizeof(*fltl) >> 2); 621 if (rc) { 622 ql_log(ql_log_info, vha, 0x017a, 623 "Unable to read FLT (%x).\n", rc); 624 return QLA_FUNCTION_FAILED; 625 } 626 if (memcmp(fltl->sig, "QFLT", 4)) 627 goto end; 628 629 wptr = (__force __le16 *)req->ring; 630 cnt = sizeof(*fltl) / sizeof(*wptr); 631 for (chksum = 0; cnt--; wptr++) 632 chksum += le16_to_cpu(*wptr); 633 if (chksum) { 634 ql_log(ql_log_fatal, vha, 0x0045, 635 "Inconsistent FLTL detected: checksum=0x%x.\n", chksum); 636 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010e, 637 fltl, sizeof(*fltl)); 638 return QLA_FUNCTION_FAILED; 639 } 640 641 /* Good data. Use specified location. */ 642 loc = locations[1]; 643 *start = (le16_to_cpu(fltl->start_hi) << 16 | 644 le16_to_cpu(fltl->start_lo)) >> 2; 645end: 646 ql_dbg(ql_dbg_init, vha, 0x0046, 647 "FLTL[%s] = 0x%x.\n", 648 loc, *start); 649 return QLA_SUCCESS; 650} 651 652static void 653qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr) 654{ 655 const char *locations[] = { "DEF", "FLT" }, *loc = locations[1]; 656 const uint32_t def_fw[] = 657 { FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 }; 658 const uint32_t def_boot[] = 659 { FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR_81 }; 660 const uint32_t def_vpd_nvram[] = 661 { FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR_81 }; 662 const uint32_t def_vpd0[] = 663 { 0, 0, FA_VPD0_ADDR_81 }; 664 const uint32_t def_vpd1[] = 665 { 0, 0, FA_VPD1_ADDR_81 }; 666 const uint32_t def_nvram0[] = 667 { 0, 0, FA_NVRAM0_ADDR_81 }; 668 const uint32_t def_nvram1[] = 669 { 0, 0, FA_NVRAM1_ADDR_81 }; 670 const uint32_t def_fdt[] = 671 { FA_FLASH_DESCR_ADDR_24, FA_FLASH_DESCR_ADDR, 672 FA_FLASH_DESCR_ADDR_81 }; 673 const uint32_t def_npiv_conf0[] = 674 { FA_NPIV_CONF0_ADDR_24, FA_NPIV_CONF0_ADDR, 675 FA_NPIV_CONF0_ADDR_81 }; 676 const uint32_t def_npiv_conf1[] = 677 { FA_NPIV_CONF1_ADDR_24, FA_NPIV_CONF1_ADDR, 678 FA_NPIV_CONF1_ADDR_81 }; 679 const uint32_t fcp_prio_cfg0[] = 680 { FA_FCP_PRIO0_ADDR, FA_FCP_PRIO0_ADDR_25, 681 0 }; 682 const uint32_t fcp_prio_cfg1[] = 683 { FA_FCP_PRIO1_ADDR, FA_FCP_PRIO1_ADDR_25, 684 0 }; 685 686 struct qla_hw_data *ha = vha->hw; 687 uint32_t def = IS_QLA81XX(ha) ? 2 : IS_QLA25XX(ha) ? 1 : 0; 688 struct qla_flt_header *flt = ha->flt; 689 struct qla_flt_region *region = &flt->region[0]; 690 __le16 *wptr; 691 uint16_t cnt, chksum; 692 uint32_t start; 693 694 /* Assign FCP prio region since older adapters may not have FLT, or 695 FCP prio region in it's FLT. 696 */ 697 ha->flt_region_fcp_prio = (ha->port_no == 0) ? 698 fcp_prio_cfg0[def] : fcp_prio_cfg1[def]; 699 700 ha->flt_region_flt = flt_addr; 701 wptr = (__force __le16 *)ha->flt; 702 ha->isp_ops->read_optrom(vha, flt, flt_addr << 2, 703 (sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE)); 704 705 if (le16_to_cpu(*wptr) == 0xffff) 706 goto no_flash_data; 707 if (flt->version != cpu_to_le16(1)) { 708 ql_log(ql_log_warn, vha, 0x0047, 709 "Unsupported FLT detected: version=0x%x length=0x%x checksum=0x%x.\n", 710 le16_to_cpu(flt->version), le16_to_cpu(flt->length), 711 le16_to_cpu(flt->checksum)); 712 goto no_flash_data; 713 } 714 715 cnt = (sizeof(*flt) + le16_to_cpu(flt->length)) / sizeof(*wptr); 716 for (chksum = 0; cnt--; wptr++) 717 chksum += le16_to_cpu(*wptr); 718 if (chksum) { 719 ql_log(ql_log_fatal, vha, 0x0048, 720 "Inconsistent FLT detected: version=0x%x length=0x%x checksum=0x%x.\n", 721 le16_to_cpu(flt->version), le16_to_cpu(flt->length), 722 le16_to_cpu(flt->checksum)); 723 goto no_flash_data; 724 } 725 726 cnt = le16_to_cpu(flt->length) / sizeof(*region); 727 for ( ; cnt; cnt--, region++) { 728 /* Store addresses as DWORD offsets. */ 729 start = le32_to_cpu(region->start) >> 2; 730 ql_dbg(ql_dbg_init, vha, 0x0049, 731 "FLT[%#x]: start=%#x end=%#x size=%#x.\n", 732 le16_to_cpu(region->code), start, 733 le32_to_cpu(region->end) >> 2, 734 le32_to_cpu(region->size) >> 2); 735 if (region->attribute) 736 ql_log(ql_dbg_init, vha, 0xffff, 737 "Region %x is secure\n", region->code); 738 739 switch (le16_to_cpu(region->code)) { 740 case FLT_REG_FCOE_FW: 741 if (!IS_QLA8031(ha)) 742 break; 743 ha->flt_region_fw = start; 744 break; 745 case FLT_REG_FW: 746 if (IS_QLA8031(ha)) 747 break; 748 ha->flt_region_fw = start; 749 break; 750 case FLT_REG_BOOT_CODE: 751 ha->flt_region_boot = start; 752 break; 753 case FLT_REG_VPD_0: 754 if (IS_QLA8031(ha)) 755 break; 756 ha->flt_region_vpd_nvram = start; 757 if (IS_P3P_TYPE(ha)) 758 break; 759 if (ha->port_no == 0) 760 ha->flt_region_vpd = start; 761 break; 762 case FLT_REG_VPD_1: 763 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha)) 764 break; 765 if (ha->port_no == 1) 766 ha->flt_region_vpd = start; 767 break; 768 case FLT_REG_VPD_2: 769 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 770 break; 771 if (ha->port_no == 2) 772 ha->flt_region_vpd = start; 773 break; 774 case FLT_REG_VPD_3: 775 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 776 break; 777 if (ha->port_no == 3) 778 ha->flt_region_vpd = start; 779 break; 780 case FLT_REG_NVRAM_0: 781 if (IS_QLA8031(ha)) 782 break; 783 if (ha->port_no == 0) 784 ha->flt_region_nvram = start; 785 break; 786 case FLT_REG_NVRAM_1: 787 if (IS_QLA8031(ha)) 788 break; 789 if (ha->port_no == 1) 790 ha->flt_region_nvram = start; 791 break; 792 case FLT_REG_NVRAM_2: 793 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 794 break; 795 if (ha->port_no == 2) 796 ha->flt_region_nvram = start; 797 break; 798 case FLT_REG_NVRAM_3: 799 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 800 break; 801 if (ha->port_no == 3) 802 ha->flt_region_nvram = start; 803 break; 804 case FLT_REG_FDT: 805 ha->flt_region_fdt = start; 806 break; 807 case FLT_REG_NPIV_CONF_0: 808 if (ha->port_no == 0) 809 ha->flt_region_npiv_conf = start; 810 break; 811 case FLT_REG_NPIV_CONF_1: 812 if (ha->port_no == 1) 813 ha->flt_region_npiv_conf = start; 814 break; 815 case FLT_REG_GOLD_FW: 816 ha->flt_region_gold_fw = start; 817 break; 818 case FLT_REG_FCP_PRIO_0: 819 if (ha->port_no == 0) 820 ha->flt_region_fcp_prio = start; 821 break; 822 case FLT_REG_FCP_PRIO_1: 823 if (ha->port_no == 1) 824 ha->flt_region_fcp_prio = start; 825 break; 826 case FLT_REG_BOOT_CODE_82XX: 827 ha->flt_region_boot = start; 828 break; 829 case FLT_REG_BOOT_CODE_8044: 830 if (IS_QLA8044(ha)) 831 ha->flt_region_boot = start; 832 break; 833 case FLT_REG_FW_82XX: 834 ha->flt_region_fw = start; 835 break; 836 case FLT_REG_CNA_FW: 837 if (IS_CNA_CAPABLE(ha)) 838 ha->flt_region_fw = start; 839 break; 840 case FLT_REG_GOLD_FW_82XX: 841 ha->flt_region_gold_fw = start; 842 break; 843 case FLT_REG_BOOTLOAD_82XX: 844 ha->flt_region_bootload = start; 845 break; 846 case FLT_REG_VPD_8XXX: 847 if (IS_CNA_CAPABLE(ha)) 848 ha->flt_region_vpd = start; 849 break; 850 case FLT_REG_FCOE_NVRAM_0: 851 if (!(IS_QLA8031(ha) || IS_QLA8044(ha))) 852 break; 853 if (ha->port_no == 0) 854 ha->flt_region_nvram = start; 855 break; 856 case FLT_REG_FCOE_NVRAM_1: 857 if (!(IS_QLA8031(ha) || IS_QLA8044(ha))) 858 break; 859 if (ha->port_no == 1) 860 ha->flt_region_nvram = start; 861 break; 862 case FLT_REG_IMG_PRI_27XX: 863 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 864 ha->flt_region_img_status_pri = start; 865 break; 866 case FLT_REG_IMG_SEC_27XX: 867 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 868 ha->flt_region_img_status_sec = start; 869 break; 870 case FLT_REG_FW_SEC_27XX: 871 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 872 ha->flt_region_fw_sec = start; 873 break; 874 case FLT_REG_BOOTLOAD_SEC_27XX: 875 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 876 ha->flt_region_boot_sec = start; 877 break; 878 case FLT_REG_AUX_IMG_PRI_28XX: 879 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 880 ha->flt_region_aux_img_status_pri = start; 881 break; 882 case FLT_REG_AUX_IMG_SEC_28XX: 883 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 884 ha->flt_region_aux_img_status_sec = start; 885 break; 886 case FLT_REG_NVRAM_SEC_28XX_0: 887 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 888 if (ha->port_no == 0) 889 ha->flt_region_nvram_sec = start; 890 break; 891 case FLT_REG_NVRAM_SEC_28XX_1: 892 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 893 if (ha->port_no == 1) 894 ha->flt_region_nvram_sec = start; 895 break; 896 case FLT_REG_NVRAM_SEC_28XX_2: 897 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 898 if (ha->port_no == 2) 899 ha->flt_region_nvram_sec = start; 900 break; 901 case FLT_REG_NVRAM_SEC_28XX_3: 902 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 903 if (ha->port_no == 3) 904 ha->flt_region_nvram_sec = start; 905 break; 906 case FLT_REG_VPD_SEC_27XX_0: 907 case FLT_REG_VPD_SEC_28XX_0: 908 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 909 ha->flt_region_vpd_nvram_sec = start; 910 if (ha->port_no == 0) 911 ha->flt_region_vpd_sec = start; 912 } 913 break; 914 case FLT_REG_VPD_SEC_27XX_1: 915 case FLT_REG_VPD_SEC_28XX_1: 916 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 917 if (ha->port_no == 1) 918 ha->flt_region_vpd_sec = start; 919 break; 920 case FLT_REG_VPD_SEC_27XX_2: 921 case FLT_REG_VPD_SEC_28XX_2: 922 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 923 if (ha->port_no == 2) 924 ha->flt_region_vpd_sec = start; 925 break; 926 case FLT_REG_VPD_SEC_27XX_3: 927 case FLT_REG_VPD_SEC_28XX_3: 928 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 929 if (ha->port_no == 3) 930 ha->flt_region_vpd_sec = start; 931 break; 932 } 933 } 934 goto done; 935 936no_flash_data: 937 /* Use hardcoded defaults. */ 938 loc = locations[0]; 939 ha->flt_region_fw = def_fw[def]; 940 ha->flt_region_boot = def_boot[def]; 941 ha->flt_region_vpd_nvram = def_vpd_nvram[def]; 942 ha->flt_region_vpd = (ha->port_no == 0) ? 943 def_vpd0[def] : def_vpd1[def]; 944 ha->flt_region_nvram = (ha->port_no == 0) ? 945 def_nvram0[def] : def_nvram1[def]; 946 ha->flt_region_fdt = def_fdt[def]; 947 ha->flt_region_npiv_conf = (ha->port_no == 0) ? 948 def_npiv_conf0[def] : def_npiv_conf1[def]; 949done: 950 ql_dbg(ql_dbg_init, vha, 0x004a, 951 "FLT[%s]: boot=0x%x fw=0x%x vpd_nvram=0x%x vpd=0x%x nvram=0x%x " 952 "fdt=0x%x flt=0x%x npiv=0x%x fcp_prif_cfg=0x%x.\n", 953 loc, ha->flt_region_boot, ha->flt_region_fw, 954 ha->flt_region_vpd_nvram, ha->flt_region_vpd, ha->flt_region_nvram, 955 ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_npiv_conf, 956 ha->flt_region_fcp_prio); 957} 958 959static void 960qla2xxx_get_fdt_info(scsi_qla_host_t *vha) 961{ 962#define FLASH_BLK_SIZE_4K 0x1000 963#define FLASH_BLK_SIZE_32K 0x8000 964#define FLASH_BLK_SIZE_64K 0x10000 965 const char *loc, *locations[] = { "MID", "FDT" }; 966 struct qla_hw_data *ha = vha->hw; 967 struct req_que *req = ha->req_q_map[0]; 968 uint16_t cnt, chksum; 969 __le16 *wptr = (__force __le16 *)req->ring; 970 struct qla_fdt_layout *fdt = (struct qla_fdt_layout *)req->ring; 971 uint8_t man_id, flash_id; 972 uint16_t mid = 0, fid = 0; 973 974 ha->isp_ops->read_optrom(vha, fdt, ha->flt_region_fdt << 2, 975 OPTROM_BURST_DWORDS); 976 if (le16_to_cpu(*wptr) == 0xffff) 977 goto no_flash_data; 978 if (memcmp(fdt->sig, "QLID", 4)) 979 goto no_flash_data; 980 981 for (cnt = 0, chksum = 0; cnt < sizeof(*fdt) >> 1; cnt++, wptr++) 982 chksum += le16_to_cpu(*wptr); 983 if (chksum) { 984 ql_dbg(ql_dbg_init, vha, 0x004c, 985 "Inconsistent FDT detected:" 986 " checksum=0x%x id=%c version0x%x.\n", chksum, 987 fdt->sig[0], le16_to_cpu(fdt->version)); 988 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0113, 989 fdt, sizeof(*fdt)); 990 goto no_flash_data; 991 } 992 993 loc = locations[1]; 994 mid = le16_to_cpu(fdt->man_id); 995 fid = le16_to_cpu(fdt->id); 996 ha->fdt_wrt_disable = fdt->wrt_disable_bits; 997 ha->fdt_wrt_enable = fdt->wrt_enable_bits; 998 ha->fdt_wrt_sts_reg_cmd = fdt->wrt_sts_reg_cmd; 999 if (IS_QLA8044(ha)) 1000 ha->fdt_erase_cmd = fdt->erase_cmd; 1001 else 1002 ha->fdt_erase_cmd = 1003 flash_conf_addr(ha, 0x0300 | fdt->erase_cmd); 1004 ha->fdt_block_size = le32_to_cpu(fdt->block_size); 1005 if (fdt->unprotect_sec_cmd) { 1006 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 | 1007 fdt->unprotect_sec_cmd); 1008 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ? 1009 flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd) : 1010 flash_conf_addr(ha, 0x0336); 1011 } 1012 goto done; 1013no_flash_data: 1014 loc = locations[0]; 1015 if (IS_P3P_TYPE(ha)) { 1016 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 1017 goto done; 1018 } 1019 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id); 1020 mid = man_id; 1021 fid = flash_id; 1022 ha->fdt_wrt_disable = 0x9c; 1023 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8); 1024 switch (man_id) { 1025 case 0xbf: /* STT flash. */ 1026 if (flash_id == 0x8e) 1027 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 1028 else 1029 ha->fdt_block_size = FLASH_BLK_SIZE_32K; 1030 1031 if (flash_id == 0x80) 1032 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352); 1033 break; 1034 case 0x13: /* ST M25P80. */ 1035 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 1036 break; 1037 case 0x1f: /* Atmel 26DF081A. */ 1038 ha->fdt_block_size = FLASH_BLK_SIZE_4K; 1039 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320); 1040 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339); 1041 ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336); 1042 break; 1043 default: 1044 /* Default to 64 kb sector size. */ 1045 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 1046 break; 1047 } 1048done: 1049 ql_dbg(ql_dbg_init, vha, 0x004d, 1050 "FDT[%s]: (0x%x/0x%x) erase=0x%x " 1051 "pr=%x wrtd=0x%x blk=0x%x.\n", 1052 loc, mid, fid, 1053 ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd, 1054 ha->fdt_wrt_disable, ha->fdt_block_size); 1055 1056} 1057 1058static void 1059qla2xxx_get_idc_param(scsi_qla_host_t *vha) 1060{ 1061#define QLA82XX_IDC_PARAM_ADDR 0x003e885c 1062 __le32 *wptr; 1063 struct qla_hw_data *ha = vha->hw; 1064 struct req_que *req = ha->req_q_map[0]; 1065 1066 if (!(IS_P3P_TYPE(ha))) 1067 return; 1068 1069 wptr = (__force __le32 *)req->ring; 1070 ha->isp_ops->read_optrom(vha, req->ring, QLA82XX_IDC_PARAM_ADDR, 8); 1071 1072 if (*wptr == cpu_to_le32(0xffffffff)) { 1073 ha->fcoe_dev_init_timeout = QLA82XX_ROM_DEV_INIT_TIMEOUT; 1074 ha->fcoe_reset_timeout = QLA82XX_ROM_DRV_RESET_ACK_TIMEOUT; 1075 } else { 1076 ha->fcoe_dev_init_timeout = le32_to_cpu(*wptr); 1077 wptr++; 1078 ha->fcoe_reset_timeout = le32_to_cpu(*wptr); 1079 } 1080 ql_dbg(ql_dbg_init, vha, 0x004e, 1081 "fcoe_dev_init_timeout=%d " 1082 "fcoe_reset_timeout=%d.\n", ha->fcoe_dev_init_timeout, 1083 ha->fcoe_reset_timeout); 1084 return; 1085} 1086 1087int 1088qla2xxx_get_flash_info(scsi_qla_host_t *vha) 1089{ 1090 int ret; 1091 uint32_t flt_addr; 1092 struct qla_hw_data *ha = vha->hw; 1093 1094 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && 1095 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha) && 1096 !IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 1097 return QLA_SUCCESS; 1098 1099 ret = qla2xxx_find_flt_start(vha, &flt_addr); 1100 if (ret != QLA_SUCCESS) 1101 return ret; 1102 1103 qla2xxx_get_flt_info(vha, flt_addr); 1104 qla2xxx_get_fdt_info(vha); 1105 qla2xxx_get_idc_param(vha); 1106 1107 return QLA_SUCCESS; 1108} 1109 1110void 1111qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha) 1112{ 1113#define NPIV_CONFIG_SIZE (16*1024) 1114 void *data; 1115 __le16 *wptr; 1116 uint16_t cnt, chksum; 1117 int i; 1118 struct qla_npiv_header hdr; 1119 struct qla_npiv_entry *entry; 1120 struct qla_hw_data *ha = vha->hw; 1121 1122 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && 1123 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha)) 1124 return; 1125 1126 if (ha->flags.nic_core_reset_hdlr_active) 1127 return; 1128 1129 if (IS_QLA8044(ha)) 1130 return; 1131 1132 ha->isp_ops->read_optrom(vha, &hdr, ha->flt_region_npiv_conf << 2, 1133 sizeof(struct qla_npiv_header)); 1134 if (hdr.version == cpu_to_le16(0xffff)) 1135 return; 1136 if (hdr.version != cpu_to_le16(1)) { 1137 ql_dbg(ql_dbg_user, vha, 0x7090, 1138 "Unsupported NPIV-Config " 1139 "detected: version=0x%x entries=0x%x checksum=0x%x.\n", 1140 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries), 1141 le16_to_cpu(hdr.checksum)); 1142 return; 1143 } 1144 1145 data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL); 1146 if (!data) { 1147 ql_log(ql_log_warn, vha, 0x7091, 1148 "Unable to allocate memory for data.\n"); 1149 return; 1150 } 1151 1152 ha->isp_ops->read_optrom(vha, data, ha->flt_region_npiv_conf << 2, 1153 NPIV_CONFIG_SIZE); 1154 1155 cnt = (sizeof(hdr) + le16_to_cpu(hdr.entries) * sizeof(*entry)) >> 1; 1156 for (wptr = data, chksum = 0; cnt--; wptr++) 1157 chksum += le16_to_cpu(*wptr); 1158 if (chksum) { 1159 ql_dbg(ql_dbg_user, vha, 0x7092, 1160 "Inconsistent NPIV-Config " 1161 "detected: version=0x%x entries=0x%x checksum=0x%x.\n", 1162 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries), 1163 le16_to_cpu(hdr.checksum)); 1164 goto done; 1165 } 1166 1167 entry = data + sizeof(struct qla_npiv_header); 1168 cnt = le16_to_cpu(hdr.entries); 1169 for (i = 0; cnt; cnt--, entry++, i++) { 1170 uint16_t flags; 1171 struct fc_vport_identifiers vid; 1172 struct fc_vport *vport; 1173 1174 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry)); 1175 1176 flags = le16_to_cpu(entry->flags); 1177 if (flags == 0xffff) 1178 continue; 1179 if ((flags & BIT_0) == 0) 1180 continue; 1181 1182 memset(&vid, 0, sizeof(vid)); 1183 vid.roles = FC_PORT_ROLE_FCP_INITIATOR; 1184 vid.vport_type = FC_PORTTYPE_NPIV; 1185 vid.disable = false; 1186 vid.port_name = wwn_to_u64(entry->port_name); 1187 vid.node_name = wwn_to_u64(entry->node_name); 1188 1189 ql_dbg(ql_dbg_user, vha, 0x7093, 1190 "NPIV[%02x]: wwpn=%llx wwnn=%llx vf_id=%#x Q_qos=%#x F_qos=%#x.\n", 1191 cnt, vid.port_name, vid.node_name, 1192 le16_to_cpu(entry->vf_id), 1193 entry->q_qos, entry->f_qos); 1194 1195 if (i < QLA_PRECONFIG_VPORTS) { 1196 vport = fc_vport_create(vha->host, 0, &vid); 1197 if (!vport) 1198 ql_log(ql_log_warn, vha, 0x7094, 1199 "NPIV-Config Failed to create vport [%02x]: wwpn=%llx wwnn=%llx.\n", 1200 cnt, vid.port_name, vid.node_name); 1201 } 1202 } 1203done: 1204 kfree(data); 1205} 1206 1207static int 1208qla24xx_unprotect_flash(scsi_qla_host_t *vha) 1209{ 1210 struct qla_hw_data *ha = vha->hw; 1211 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1212 1213 if (ha->flags.fac_supported) 1214 return qla81xx_fac_do_write_enable(vha, 1); 1215 1216 /* Enable flash write. */ 1217 wrt_reg_dword(®->ctrl_status, 1218 rd_reg_dword(®->ctrl_status) | CSRX_FLASH_ENABLE); 1219 rd_reg_dword(®->ctrl_status); /* PCI Posting. */ 1220 1221 if (!ha->fdt_wrt_disable) 1222 goto done; 1223 1224 /* Disable flash write-protection, first clear SR protection bit */ 1225 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0); 1226 /* Then write zero again to clear remaining SR bits.*/ 1227 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0); 1228done: 1229 return QLA_SUCCESS; 1230} 1231 1232static int 1233qla24xx_protect_flash(scsi_qla_host_t *vha) 1234{ 1235 struct qla_hw_data *ha = vha->hw; 1236 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1237 ulong cnt = 300; 1238 uint32_t faddr, dword; 1239 1240 if (ha->flags.fac_supported) 1241 return qla81xx_fac_do_write_enable(vha, 0); 1242 1243 if (!ha->fdt_wrt_disable) 1244 goto skip_wrt_protect; 1245 1246 /* Enable flash write-protection and wait for completion. */ 1247 faddr = flash_conf_addr(ha, 0x101); 1248 qla24xx_write_flash_dword(ha, faddr, ha->fdt_wrt_disable); 1249 faddr = flash_conf_addr(ha, 0x5); 1250 while (cnt--) { 1251 if (!qla24xx_read_flash_dword(ha, faddr, &dword)) { 1252 if (!(dword & BIT_0)) 1253 break; 1254 } 1255 udelay(10); 1256 } 1257 1258skip_wrt_protect: 1259 /* Disable flash write. */ 1260 wrt_reg_dword(®->ctrl_status, 1261 rd_reg_dword(®->ctrl_status) & ~CSRX_FLASH_ENABLE); 1262 1263 return QLA_SUCCESS; 1264} 1265 1266static int 1267qla24xx_erase_sector(scsi_qla_host_t *vha, uint32_t fdata) 1268{ 1269 struct qla_hw_data *ha = vha->hw; 1270 uint32_t start, finish; 1271 1272 if (ha->flags.fac_supported) { 1273 start = fdata >> 2; 1274 finish = start + (ha->fdt_block_size >> 2) - 1; 1275 return qla81xx_fac_erase_sector(vha, flash_data_addr(ha, 1276 start), flash_data_addr(ha, finish)); 1277 } 1278 1279 return qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd, 1280 (fdata & 0xff00) | ((fdata << 16) & 0xff0000) | 1281 ((fdata >> 16) & 0xff)); 1282} 1283 1284static int 1285qla24xx_write_flash_data(scsi_qla_host_t *vha, __le32 *dwptr, uint32_t faddr, 1286 uint32_t dwords) 1287{ 1288 int ret; 1289 ulong liter; 1290 ulong dburst = OPTROM_BURST_DWORDS; /* burst size in dwords */ 1291 uint32_t sec_mask, rest_addr, fdata; 1292 dma_addr_t optrom_dma; 1293 void *optrom = NULL; 1294 struct qla_hw_data *ha = vha->hw; 1295 1296 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) && 1297 !IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 1298 goto next; 1299 1300 /* Allocate dma buffer for burst write */ 1301 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 1302 &optrom_dma, GFP_KERNEL); 1303 if (!optrom) { 1304 ql_log(ql_log_warn, vha, 0x7095, 1305 "Failed allocate burst (%x bytes)\n", OPTROM_BURST_SIZE); 1306 } 1307 1308next: 1309 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 1310 "Unprotect flash...\n"); 1311 ret = qla24xx_unprotect_flash(vha); 1312 if (ret) { 1313 ql_log(ql_log_warn, vha, 0x7096, 1314 "Failed to unprotect flash.\n"); 1315 goto done; 1316 } 1317 1318 rest_addr = (ha->fdt_block_size >> 2) - 1; 1319 sec_mask = ~rest_addr; 1320 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) { 1321 fdata = (faddr & sec_mask) << 2; 1322 1323 /* Are we at the beginning of a sector? */ 1324 if (!(faddr & rest_addr)) { 1325 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 1326 "Erase sector %#x...\n", faddr); 1327 1328 ret = qla24xx_erase_sector(vha, fdata); 1329 if (ret) { 1330 ql_dbg(ql_dbg_user, vha, 0x7007, 1331 "Failed to erase sector %x.\n", faddr); 1332 break; 1333 } 1334 } 1335 1336 if (optrom) { 1337 /* If smaller than a burst remaining */ 1338 if (dwords - liter < dburst) 1339 dburst = dwords - liter; 1340 1341 /* Copy to dma buffer */ 1342 memcpy(optrom, dwptr, dburst << 2); 1343 1344 /* Burst write */ 1345 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 1346 "Write burst (%#lx dwords)...\n", dburst); 1347 ret = qla2x00_load_ram(vha, optrom_dma, 1348 flash_data_addr(ha, faddr), dburst); 1349 if (!ret) { 1350 liter += dburst - 1; 1351 faddr += dburst - 1; 1352 dwptr += dburst - 1; 1353 continue; 1354 } 1355 1356 ql_log(ql_log_warn, vha, 0x7097, 1357 "Failed burst-write at %x (%p/%#llx)....\n", 1358 flash_data_addr(ha, faddr), optrom, 1359 (u64)optrom_dma); 1360 1361 dma_free_coherent(&ha->pdev->dev, 1362 OPTROM_BURST_SIZE, optrom, optrom_dma); 1363 optrom = NULL; 1364 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 1365 break; 1366 ql_log(ql_log_warn, vha, 0x7098, 1367 "Reverting to slow write...\n"); 1368 } 1369 1370 /* Slow write */ 1371 ret = qla24xx_write_flash_dword(ha, 1372 flash_data_addr(ha, faddr), le32_to_cpu(*dwptr)); 1373 if (ret) { 1374 ql_dbg(ql_dbg_user, vha, 0x7006, 1375 "Failed slow write %x (%x)\n", faddr, *dwptr); 1376 break; 1377 } 1378 } 1379 1380 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 1381 "Protect flash...\n"); 1382 ret = qla24xx_protect_flash(vha); 1383 if (ret) 1384 ql_log(ql_log_warn, vha, 0x7099, 1385 "Failed to protect flash\n"); 1386done: 1387 if (optrom) 1388 dma_free_coherent(&ha->pdev->dev, 1389 OPTROM_BURST_SIZE, optrom, optrom_dma); 1390 1391 return ret; 1392} 1393 1394uint8_t * 1395qla2x00_read_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, 1396 uint32_t bytes) 1397{ 1398 uint32_t i; 1399 __le16 *wptr; 1400 struct qla_hw_data *ha = vha->hw; 1401 1402 /* Word reads to NVRAM via registers. */ 1403 wptr = buf; 1404 qla2x00_lock_nvram_access(ha); 1405 for (i = 0; i < bytes >> 1; i++, naddr++) 1406 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha, 1407 naddr)); 1408 qla2x00_unlock_nvram_access(ha); 1409 1410 return buf; 1411} 1412 1413uint8_t * 1414qla24xx_read_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, 1415 uint32_t bytes) 1416{ 1417 struct qla_hw_data *ha = vha->hw; 1418 uint32_t *dwptr = buf; 1419 uint32_t i; 1420 1421 if (IS_P3P_TYPE(ha)) 1422 return buf; 1423 1424 /* Dword reads to flash. */ 1425 naddr = nvram_data_addr(ha, naddr); 1426 bytes >>= 2; 1427 for (i = 0; i < bytes; i++, naddr++, dwptr++) { 1428 if (qla24xx_read_flash_dword(ha, naddr, dwptr)) 1429 break; 1430 cpu_to_le32s(dwptr); 1431 } 1432 1433 return buf; 1434} 1435 1436int 1437qla2x00_write_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, 1438 uint32_t bytes) 1439{ 1440 int ret, stat; 1441 uint32_t i; 1442 uint16_t *wptr; 1443 unsigned long flags; 1444 struct qla_hw_data *ha = vha->hw; 1445 1446 ret = QLA_SUCCESS; 1447 1448 spin_lock_irqsave(&ha->hardware_lock, flags); 1449 qla2x00_lock_nvram_access(ha); 1450 1451 /* Disable NVRAM write-protection. */ 1452 stat = qla2x00_clear_nvram_protection(ha); 1453 1454 wptr = (uint16_t *)buf; 1455 for (i = 0; i < bytes >> 1; i++, naddr++) { 1456 qla2x00_write_nvram_word(ha, naddr, 1457 cpu_to_le16(*wptr)); 1458 wptr++; 1459 } 1460 1461 /* Enable NVRAM write-protection. */ 1462 qla2x00_set_nvram_protection(ha, stat); 1463 1464 qla2x00_unlock_nvram_access(ha); 1465 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1466 1467 return ret; 1468} 1469 1470int 1471qla24xx_write_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, 1472 uint32_t bytes) 1473{ 1474 struct qla_hw_data *ha = vha->hw; 1475 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1476 __le32 *dwptr = buf; 1477 uint32_t i; 1478 int ret; 1479 1480 ret = QLA_SUCCESS; 1481 1482 if (IS_P3P_TYPE(ha)) 1483 return ret; 1484 1485 /* Enable flash write. */ 1486 wrt_reg_dword(®->ctrl_status, 1487 rd_reg_dword(®->ctrl_status) | CSRX_FLASH_ENABLE); 1488 rd_reg_dword(®->ctrl_status); /* PCI Posting. */ 1489 1490 /* Disable NVRAM write-protection. */ 1491 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0); 1492 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0); 1493 1494 /* Dword writes to flash. */ 1495 naddr = nvram_data_addr(ha, naddr); 1496 bytes >>= 2; 1497 for (i = 0; i < bytes; i++, naddr++, dwptr++) { 1498 if (qla24xx_write_flash_dword(ha, naddr, le32_to_cpu(*dwptr))) { 1499 ql_dbg(ql_dbg_user, vha, 0x709a, 1500 "Unable to program nvram address=%x data=%x.\n", 1501 naddr, *dwptr); 1502 break; 1503 } 1504 } 1505 1506 /* Enable NVRAM write-protection. */ 1507 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c); 1508 1509 /* Disable flash write. */ 1510 wrt_reg_dword(®->ctrl_status, 1511 rd_reg_dword(®->ctrl_status) & ~CSRX_FLASH_ENABLE); 1512 rd_reg_dword(®->ctrl_status); /* PCI Posting. */ 1513 1514 return ret; 1515} 1516 1517uint8_t * 1518qla25xx_read_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, 1519 uint32_t bytes) 1520{ 1521 struct qla_hw_data *ha = vha->hw; 1522 uint32_t *dwptr = buf; 1523 uint32_t i; 1524 1525 /* Dword reads to flash. */ 1526 naddr = flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr); 1527 bytes >>= 2; 1528 for (i = 0; i < bytes; i++, naddr++, dwptr++) { 1529 if (qla24xx_read_flash_dword(ha, naddr, dwptr)) 1530 break; 1531 1532 cpu_to_le32s(dwptr); 1533 } 1534 1535 return buf; 1536} 1537 1538#define RMW_BUFFER_SIZE (64 * 1024) 1539int 1540qla25xx_write_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, 1541 uint32_t bytes) 1542{ 1543 struct qla_hw_data *ha = vha->hw; 1544 uint8_t *dbuf = vmalloc(RMW_BUFFER_SIZE); 1545 1546 if (!dbuf) 1547 return QLA_MEMORY_ALLOC_FAILED; 1548 ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2, 1549 RMW_BUFFER_SIZE); 1550 memcpy(dbuf + (naddr << 2), buf, bytes); 1551 ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2, 1552 RMW_BUFFER_SIZE); 1553 vfree(dbuf); 1554 1555 return QLA_SUCCESS; 1556} 1557 1558static inline void 1559qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags) 1560{ 1561 if (IS_QLA2322(ha)) { 1562 /* Flip all colors. */ 1563 if (ha->beacon_color_state == QLA_LED_ALL_ON) { 1564 /* Turn off. */ 1565 ha->beacon_color_state = 0; 1566 *pflags = GPIO_LED_ALL_OFF; 1567 } else { 1568 /* Turn on. */ 1569 ha->beacon_color_state = QLA_LED_ALL_ON; 1570 *pflags = GPIO_LED_RGA_ON; 1571 } 1572 } else { 1573 /* Flip green led only. */ 1574 if (ha->beacon_color_state == QLA_LED_GRN_ON) { 1575 /* Turn off. */ 1576 ha->beacon_color_state = 0; 1577 *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF; 1578 } else { 1579 /* Turn on. */ 1580 ha->beacon_color_state = QLA_LED_GRN_ON; 1581 *pflags = GPIO_LED_GREEN_ON_AMBER_OFF; 1582 } 1583 } 1584} 1585 1586#define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r)) 1587 1588void 1589qla2x00_beacon_blink(struct scsi_qla_host *vha) 1590{ 1591 uint16_t gpio_enable; 1592 uint16_t gpio_data; 1593 uint16_t led_color = 0; 1594 unsigned long flags; 1595 struct qla_hw_data *ha = vha->hw; 1596 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1597 1598 if (IS_P3P_TYPE(ha)) 1599 return; 1600 1601 spin_lock_irqsave(&ha->hardware_lock, flags); 1602 1603 /* Save the Original GPIOE. */ 1604 if (ha->pio_address) { 1605 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe)); 1606 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod)); 1607 } else { 1608 gpio_enable = rd_reg_word(®->gpioe); 1609 gpio_data = rd_reg_word(®->gpiod); 1610 } 1611 1612 /* Set the modified gpio_enable values */ 1613 gpio_enable |= GPIO_LED_MASK; 1614 1615 if (ha->pio_address) { 1616 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable); 1617 } else { 1618 wrt_reg_word(®->gpioe, gpio_enable); 1619 rd_reg_word(®->gpioe); 1620 } 1621 1622 qla2x00_flip_colors(ha, &led_color); 1623 1624 /* Clear out any previously set LED color. */ 1625 gpio_data &= ~GPIO_LED_MASK; 1626 1627 /* Set the new input LED color to GPIOD. */ 1628 gpio_data |= led_color; 1629 1630 /* Set the modified gpio_data values */ 1631 if (ha->pio_address) { 1632 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data); 1633 } else { 1634 wrt_reg_word(®->gpiod, gpio_data); 1635 rd_reg_word(®->gpiod); 1636 } 1637 1638 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1639} 1640 1641int 1642qla2x00_beacon_on(struct scsi_qla_host *vha) 1643{ 1644 uint16_t gpio_enable; 1645 uint16_t gpio_data; 1646 unsigned long flags; 1647 struct qla_hw_data *ha = vha->hw; 1648 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1649 1650 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; 1651 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7; 1652 1653 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) { 1654 ql_log(ql_log_warn, vha, 0x709b, 1655 "Unable to update fw options (beacon on).\n"); 1656 return QLA_FUNCTION_FAILED; 1657 } 1658 1659 /* Turn off LEDs. */ 1660 spin_lock_irqsave(&ha->hardware_lock, flags); 1661 if (ha->pio_address) { 1662 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe)); 1663 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod)); 1664 } else { 1665 gpio_enable = rd_reg_word(®->gpioe); 1666 gpio_data = rd_reg_word(®->gpiod); 1667 } 1668 gpio_enable |= GPIO_LED_MASK; 1669 1670 /* Set the modified gpio_enable values. */ 1671 if (ha->pio_address) { 1672 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable); 1673 } else { 1674 wrt_reg_word(®->gpioe, gpio_enable); 1675 rd_reg_word(®->gpioe); 1676 } 1677 1678 /* Clear out previously set LED colour. */ 1679 gpio_data &= ~GPIO_LED_MASK; 1680 if (ha->pio_address) { 1681 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data); 1682 } else { 1683 wrt_reg_word(®->gpiod, gpio_data); 1684 rd_reg_word(®->gpiod); 1685 } 1686 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1687 1688 /* 1689 * Let the per HBA timer kick off the blinking process based on 1690 * the following flags. No need to do anything else now. 1691 */ 1692 ha->beacon_blink_led = 1; 1693 ha->beacon_color_state = 0; 1694 1695 return QLA_SUCCESS; 1696} 1697 1698int 1699qla2x00_beacon_off(struct scsi_qla_host *vha) 1700{ 1701 int rval = QLA_SUCCESS; 1702 struct qla_hw_data *ha = vha->hw; 1703 1704 ha->beacon_blink_led = 0; 1705 1706 /* Set the on flag so when it gets flipped it will be off. */ 1707 if (IS_QLA2322(ha)) 1708 ha->beacon_color_state = QLA_LED_ALL_ON; 1709 else 1710 ha->beacon_color_state = QLA_LED_GRN_ON; 1711 1712 ha->isp_ops->beacon_blink(vha); /* This turns green LED off */ 1713 1714 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; 1715 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7; 1716 1717 rval = qla2x00_set_fw_options(vha, ha->fw_options); 1718 if (rval != QLA_SUCCESS) 1719 ql_log(ql_log_warn, vha, 0x709c, 1720 "Unable to update fw options (beacon off).\n"); 1721 return rval; 1722} 1723 1724 1725static inline void 1726qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags) 1727{ 1728 /* Flip all colors. */ 1729 if (ha->beacon_color_state == QLA_LED_ALL_ON) { 1730 /* Turn off. */ 1731 ha->beacon_color_state = 0; 1732 *pflags = 0; 1733 } else { 1734 /* Turn on. */ 1735 ha->beacon_color_state = QLA_LED_ALL_ON; 1736 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON; 1737 } 1738} 1739 1740void 1741qla24xx_beacon_blink(struct scsi_qla_host *vha) 1742{ 1743 uint16_t led_color = 0; 1744 uint32_t gpio_data; 1745 unsigned long flags; 1746 struct qla_hw_data *ha = vha->hw; 1747 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1748 1749 /* Save the Original GPIOD. */ 1750 spin_lock_irqsave(&ha->hardware_lock, flags); 1751 gpio_data = rd_reg_dword(®->gpiod); 1752 1753 /* Enable the gpio_data reg for update. */ 1754 gpio_data |= GPDX_LED_UPDATE_MASK; 1755 1756 wrt_reg_dword(®->gpiod, gpio_data); 1757 gpio_data = rd_reg_dword(®->gpiod); 1758 1759 /* Set the color bits. */ 1760 qla24xx_flip_colors(ha, &led_color); 1761 1762 /* Clear out any previously set LED color. */ 1763 gpio_data &= ~GPDX_LED_COLOR_MASK; 1764 1765 /* Set the new input LED color to GPIOD. */ 1766 gpio_data |= led_color; 1767 1768 /* Set the modified gpio_data values. */ 1769 wrt_reg_dword(®->gpiod, gpio_data); 1770 gpio_data = rd_reg_dword(®->gpiod); 1771 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1772} 1773 1774static uint32_t 1775qla83xx_select_led_port(struct qla_hw_data *ha) 1776{ 1777 uint32_t led_select_value = 0; 1778 1779 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 1780 goto out; 1781 1782 if (ha->port_no == 0) 1783 led_select_value = QLA83XX_LED_PORT0; 1784 else 1785 led_select_value = QLA83XX_LED_PORT1; 1786 1787out: 1788 return led_select_value; 1789} 1790 1791void 1792qla83xx_beacon_blink(struct scsi_qla_host *vha) 1793{ 1794 uint32_t led_select_value; 1795 struct qla_hw_data *ha = vha->hw; 1796 uint16_t led_cfg[6]; 1797 uint16_t orig_led_cfg[6]; 1798 uint32_t led_10_value, led_43_value; 1799 1800 if (!IS_QLA83XX(ha) && !IS_QLA81XX(ha) && !IS_QLA27XX(ha) && 1801 !IS_QLA28XX(ha)) 1802 return; 1803 1804 if (!ha->beacon_blink_led) 1805 return; 1806 1807 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 1808 qla2x00_write_ram_word(vha, 0x1003, 0x40000230); 1809 qla2x00_write_ram_word(vha, 0x1004, 0x40000230); 1810 } else if (IS_QLA2031(ha)) { 1811 led_select_value = qla83xx_select_led_port(ha); 1812 1813 qla83xx_wr_reg(vha, led_select_value, 0x40000230); 1814 qla83xx_wr_reg(vha, led_select_value + 4, 0x40000230); 1815 } else if (IS_QLA8031(ha)) { 1816 led_select_value = qla83xx_select_led_port(ha); 1817 1818 qla83xx_rd_reg(vha, led_select_value, &led_10_value); 1819 qla83xx_rd_reg(vha, led_select_value + 0x10, &led_43_value); 1820 qla83xx_wr_reg(vha, led_select_value, 0x01f44000); 1821 msleep(500); 1822 qla83xx_wr_reg(vha, led_select_value, 0x400001f4); 1823 msleep(1000); 1824 qla83xx_wr_reg(vha, led_select_value, led_10_value); 1825 qla83xx_wr_reg(vha, led_select_value + 0x10, led_43_value); 1826 } else if (IS_QLA81XX(ha)) { 1827 int rval; 1828 1829 /* Save Current */ 1830 rval = qla81xx_get_led_config(vha, orig_led_cfg); 1831 /* Do the blink */ 1832 if (rval == QLA_SUCCESS) { 1833 if (IS_QLA81XX(ha)) { 1834 led_cfg[0] = 0x4000; 1835 led_cfg[1] = 0x2000; 1836 led_cfg[2] = 0; 1837 led_cfg[3] = 0; 1838 led_cfg[4] = 0; 1839 led_cfg[5] = 0; 1840 } else { 1841 led_cfg[0] = 0x4000; 1842 led_cfg[1] = 0x4000; 1843 led_cfg[2] = 0x4000; 1844 led_cfg[3] = 0x2000; 1845 led_cfg[4] = 0; 1846 led_cfg[5] = 0x2000; 1847 } 1848 rval = qla81xx_set_led_config(vha, led_cfg); 1849 msleep(1000); 1850 if (IS_QLA81XX(ha)) { 1851 led_cfg[0] = 0x4000; 1852 led_cfg[1] = 0x2000; 1853 led_cfg[2] = 0; 1854 } else { 1855 led_cfg[0] = 0x4000; 1856 led_cfg[1] = 0x2000; 1857 led_cfg[2] = 0x4000; 1858 led_cfg[3] = 0x4000; 1859 led_cfg[4] = 0; 1860 led_cfg[5] = 0x2000; 1861 } 1862 rval = qla81xx_set_led_config(vha, led_cfg); 1863 } 1864 /* On exit, restore original (presumes no status change) */ 1865 qla81xx_set_led_config(vha, orig_led_cfg); 1866 } 1867} 1868 1869int 1870qla24xx_beacon_on(struct scsi_qla_host *vha) 1871{ 1872 uint32_t gpio_data; 1873 unsigned long flags; 1874 struct qla_hw_data *ha = vha->hw; 1875 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1876 1877 if (IS_P3P_TYPE(ha)) 1878 return QLA_SUCCESS; 1879 1880 if (IS_QLA8031(ha) || IS_QLA81XX(ha)) 1881 goto skip_gpio; /* let blink handle it */ 1882 1883 if (ha->beacon_blink_led == 0) { 1884 /* Enable firmware for update */ 1885 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL; 1886 1887 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) 1888 return QLA_FUNCTION_FAILED; 1889 1890 if (qla2x00_get_fw_options(vha, ha->fw_options) != 1891 QLA_SUCCESS) { 1892 ql_log(ql_log_warn, vha, 0x7009, 1893 "Unable to update fw options (beacon on).\n"); 1894 return QLA_FUNCTION_FAILED; 1895 } 1896 1897 if (IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 1898 goto skip_gpio; 1899 1900 spin_lock_irqsave(&ha->hardware_lock, flags); 1901 gpio_data = rd_reg_dword(®->gpiod); 1902 1903 /* Enable the gpio_data reg for update. */ 1904 gpio_data |= GPDX_LED_UPDATE_MASK; 1905 wrt_reg_dword(®->gpiod, gpio_data); 1906 rd_reg_dword(®->gpiod); 1907 1908 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1909 } 1910 1911 /* So all colors blink together. */ 1912 ha->beacon_color_state = 0; 1913 1914skip_gpio: 1915 /* Let the per HBA timer kick off the blinking process. */ 1916 ha->beacon_blink_led = 1; 1917 1918 return QLA_SUCCESS; 1919} 1920 1921int 1922qla24xx_beacon_off(struct scsi_qla_host *vha) 1923{ 1924 uint32_t gpio_data; 1925 unsigned long flags; 1926 struct qla_hw_data *ha = vha->hw; 1927 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1928 1929 if (IS_P3P_TYPE(ha)) 1930 return QLA_SUCCESS; 1931 1932 if (!ha->flags.fw_started) 1933 return QLA_SUCCESS; 1934 1935 ha->beacon_blink_led = 0; 1936 1937 if (IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 1938 goto set_fw_options; 1939 1940 if (IS_QLA8031(ha) || IS_QLA81XX(ha)) 1941 return QLA_SUCCESS; 1942 1943 ha->beacon_color_state = QLA_LED_ALL_ON; 1944 1945 ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */ 1946 1947 /* Give control back to firmware. */ 1948 spin_lock_irqsave(&ha->hardware_lock, flags); 1949 gpio_data = rd_reg_dword(®->gpiod); 1950 1951 /* Disable the gpio_data reg for update. */ 1952 gpio_data &= ~GPDX_LED_UPDATE_MASK; 1953 wrt_reg_dword(®->gpiod, gpio_data); 1954 rd_reg_dword(®->gpiod); 1955 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1956 1957set_fw_options: 1958 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL; 1959 1960 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) { 1961 ql_log(ql_log_warn, vha, 0x704d, 1962 "Unable to update fw options (beacon on).\n"); 1963 return QLA_FUNCTION_FAILED; 1964 } 1965 1966 if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) { 1967 ql_log(ql_log_warn, vha, 0x704e, 1968 "Unable to update fw options (beacon on).\n"); 1969 return QLA_FUNCTION_FAILED; 1970 } 1971 1972 return QLA_SUCCESS; 1973} 1974 1975 1976/* 1977 * Flash support routines 1978 */ 1979 1980/** 1981 * qla2x00_flash_enable() - Setup flash for reading and writing. 1982 * @ha: HA context 1983 */ 1984static void 1985qla2x00_flash_enable(struct qla_hw_data *ha) 1986{ 1987 uint16_t data; 1988 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1989 1990 data = rd_reg_word(®->ctrl_status); 1991 data |= CSR_FLASH_ENABLE; 1992 wrt_reg_word(®->ctrl_status, data); 1993 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 1994} 1995 1996/** 1997 * qla2x00_flash_disable() - Disable flash and allow RISC to run. 1998 * @ha: HA context 1999 */ 2000static void 2001qla2x00_flash_disable(struct qla_hw_data *ha) 2002{ 2003 uint16_t data; 2004 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2005 2006 data = rd_reg_word(®->ctrl_status); 2007 data &= ~(CSR_FLASH_ENABLE); 2008 wrt_reg_word(®->ctrl_status, data); 2009 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2010} 2011 2012/** 2013 * qla2x00_read_flash_byte() - Reads a byte from flash 2014 * @ha: HA context 2015 * @addr: Address in flash to read 2016 * 2017 * A word is read from the chip, but, only the lower byte is valid. 2018 * 2019 * Returns the byte read from flash @addr. 2020 */ 2021static uint8_t 2022qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr) 2023{ 2024 uint16_t data; 2025 uint16_t bank_select; 2026 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2027 2028 bank_select = rd_reg_word(®->ctrl_status); 2029 2030 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 2031 /* Specify 64K address range: */ 2032 /* clear out Module Select and Flash Address bits [19:16]. */ 2033 bank_select &= ~0xf8; 2034 bank_select |= addr >> 12 & 0xf0; 2035 bank_select |= CSR_FLASH_64K_BANK; 2036 wrt_reg_word(®->ctrl_status, bank_select); 2037 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2038 2039 wrt_reg_word(®->flash_address, (uint16_t)addr); 2040 data = rd_reg_word(®->flash_data); 2041 2042 return (uint8_t)data; 2043 } 2044 2045 /* Setup bit 16 of flash address. */ 2046 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) { 2047 bank_select |= CSR_FLASH_64K_BANK; 2048 wrt_reg_word(®->ctrl_status, bank_select); 2049 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2050 } else if (((addr & BIT_16) == 0) && 2051 (bank_select & CSR_FLASH_64K_BANK)) { 2052 bank_select &= ~(CSR_FLASH_64K_BANK); 2053 wrt_reg_word(®->ctrl_status, bank_select); 2054 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2055 } 2056 2057 /* Always perform IO mapped accesses to the FLASH registers. */ 2058 if (ha->pio_address) { 2059 uint16_t data2; 2060 2061 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr); 2062 do { 2063 data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data)); 2064 barrier(); 2065 cpu_relax(); 2066 data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data)); 2067 } while (data != data2); 2068 } else { 2069 wrt_reg_word(®->flash_address, (uint16_t)addr); 2070 data = qla2x00_debounce_register(®->flash_data); 2071 } 2072 2073 return (uint8_t)data; 2074} 2075 2076/** 2077 * qla2x00_write_flash_byte() - Write a byte to flash 2078 * @ha: HA context 2079 * @addr: Address in flash to write 2080 * @data: Data to write 2081 */ 2082static void 2083qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data) 2084{ 2085 uint16_t bank_select; 2086 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2087 2088 bank_select = rd_reg_word(®->ctrl_status); 2089 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 2090 /* Specify 64K address range: */ 2091 /* clear out Module Select and Flash Address bits [19:16]. */ 2092 bank_select &= ~0xf8; 2093 bank_select |= addr >> 12 & 0xf0; 2094 bank_select |= CSR_FLASH_64K_BANK; 2095 wrt_reg_word(®->ctrl_status, bank_select); 2096 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2097 2098 wrt_reg_word(®->flash_address, (uint16_t)addr); 2099 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2100 wrt_reg_word(®->flash_data, (uint16_t)data); 2101 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2102 2103 return; 2104 } 2105 2106 /* Setup bit 16 of flash address. */ 2107 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) { 2108 bank_select |= CSR_FLASH_64K_BANK; 2109 wrt_reg_word(®->ctrl_status, bank_select); 2110 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2111 } else if (((addr & BIT_16) == 0) && 2112 (bank_select & CSR_FLASH_64K_BANK)) { 2113 bank_select &= ~(CSR_FLASH_64K_BANK); 2114 wrt_reg_word(®->ctrl_status, bank_select); 2115 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2116 } 2117 2118 /* Always perform IO mapped accesses to the FLASH registers. */ 2119 if (ha->pio_address) { 2120 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr); 2121 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data); 2122 } else { 2123 wrt_reg_word(®->flash_address, (uint16_t)addr); 2124 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2125 wrt_reg_word(®->flash_data, (uint16_t)data); 2126 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2127 } 2128} 2129 2130/** 2131 * qla2x00_poll_flash() - Polls flash for completion. 2132 * @ha: HA context 2133 * @addr: Address in flash to poll 2134 * @poll_data: Data to be polled 2135 * @man_id: Flash manufacturer ID 2136 * @flash_id: Flash ID 2137 * 2138 * This function polls the device until bit 7 of what is read matches data 2139 * bit 7 or until data bit 5 becomes a 1. If that happens, the flash ROM timed 2140 * out (a fatal error). The flash book recommends reading bit 7 again after 2141 * reading bit 5 as a 1. 2142 * 2143 * Returns 0 on success, else non-zero. 2144 */ 2145static int 2146qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data, 2147 uint8_t man_id, uint8_t flash_id) 2148{ 2149 int status; 2150 uint8_t flash_data; 2151 uint32_t cnt; 2152 2153 status = 1; 2154 2155 /* Wait for 30 seconds for command to finish. */ 2156 poll_data &= BIT_7; 2157 for (cnt = 3000000; cnt; cnt--) { 2158 flash_data = qla2x00_read_flash_byte(ha, addr); 2159 if ((flash_data & BIT_7) == poll_data) { 2160 status = 0; 2161 break; 2162 } 2163 2164 if (man_id != 0x40 && man_id != 0xda) { 2165 if ((flash_data & BIT_5) && cnt > 2) 2166 cnt = 2; 2167 } 2168 udelay(10); 2169 barrier(); 2170 cond_resched(); 2171 } 2172 return status; 2173} 2174 2175/** 2176 * qla2x00_program_flash_address() - Programs a flash address 2177 * @ha: HA context 2178 * @addr: Address in flash to program 2179 * @data: Data to be written in flash 2180 * @man_id: Flash manufacturer ID 2181 * @flash_id: Flash ID 2182 * 2183 * Returns 0 on success, else non-zero. 2184 */ 2185static int 2186qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr, 2187 uint8_t data, uint8_t man_id, uint8_t flash_id) 2188{ 2189 /* Write Program Command Sequence. */ 2190 if (IS_OEM_001(ha)) { 2191 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); 2192 qla2x00_write_flash_byte(ha, 0x555, 0x55); 2193 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0); 2194 qla2x00_write_flash_byte(ha, addr, data); 2195 } else { 2196 if (man_id == 0xda && flash_id == 0xc1) { 2197 qla2x00_write_flash_byte(ha, addr, data); 2198 if (addr & 0x7e) 2199 return 0; 2200 } else { 2201 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2202 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2203 qla2x00_write_flash_byte(ha, 0x5555, 0xa0); 2204 qla2x00_write_flash_byte(ha, addr, data); 2205 } 2206 } 2207 2208 udelay(150); 2209 2210 /* Wait for write to complete. */ 2211 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id); 2212} 2213 2214/** 2215 * qla2x00_erase_flash() - Erase the flash. 2216 * @ha: HA context 2217 * @man_id: Flash manufacturer ID 2218 * @flash_id: Flash ID 2219 * 2220 * Returns 0 on success, else non-zero. 2221 */ 2222static int 2223qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id) 2224{ 2225 /* Individual Sector Erase Command Sequence */ 2226 if (IS_OEM_001(ha)) { 2227 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); 2228 qla2x00_write_flash_byte(ha, 0x555, 0x55); 2229 qla2x00_write_flash_byte(ha, 0xaaa, 0x80); 2230 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); 2231 qla2x00_write_flash_byte(ha, 0x555, 0x55); 2232 qla2x00_write_flash_byte(ha, 0xaaa, 0x10); 2233 } else { 2234 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2235 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2236 qla2x00_write_flash_byte(ha, 0x5555, 0x80); 2237 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2238 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2239 qla2x00_write_flash_byte(ha, 0x5555, 0x10); 2240 } 2241 2242 udelay(150); 2243 2244 /* Wait for erase to complete. */ 2245 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id); 2246} 2247 2248/** 2249 * qla2x00_erase_flash_sector() - Erase a flash sector. 2250 * @ha: HA context 2251 * @addr: Flash sector to erase 2252 * @sec_mask: Sector address mask 2253 * @man_id: Flash manufacturer ID 2254 * @flash_id: Flash ID 2255 * 2256 * Returns 0 on success, else non-zero. 2257 */ 2258static int 2259qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr, 2260 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id) 2261{ 2262 /* Individual Sector Erase Command Sequence */ 2263 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2264 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2265 qla2x00_write_flash_byte(ha, 0x5555, 0x80); 2266 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2267 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2268 if (man_id == 0x1f && flash_id == 0x13) 2269 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10); 2270 else 2271 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30); 2272 2273 udelay(150); 2274 2275 /* Wait for erase to complete. */ 2276 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id); 2277} 2278 2279/** 2280 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip. 2281 * @ha: host adapter 2282 * @man_id: Flash manufacturer ID 2283 * @flash_id: Flash ID 2284 */ 2285static void 2286qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id, 2287 uint8_t *flash_id) 2288{ 2289 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2290 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2291 qla2x00_write_flash_byte(ha, 0x5555, 0x90); 2292 *man_id = qla2x00_read_flash_byte(ha, 0x0000); 2293 *flash_id = qla2x00_read_flash_byte(ha, 0x0001); 2294 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2295 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2296 qla2x00_write_flash_byte(ha, 0x5555, 0xf0); 2297} 2298 2299static void 2300qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf, 2301 uint32_t saddr, uint32_t length) 2302{ 2303 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2304 uint32_t midpoint, ilength; 2305 uint8_t data; 2306 2307 midpoint = length / 2; 2308 2309 wrt_reg_word(®->nvram, 0); 2310 rd_reg_word(®->nvram); 2311 for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) { 2312 if (ilength == midpoint) { 2313 wrt_reg_word(®->nvram, NVR_SELECT); 2314 rd_reg_word(®->nvram); 2315 } 2316 data = qla2x00_read_flash_byte(ha, saddr); 2317 if (saddr % 100) 2318 udelay(10); 2319 *tmp_buf = data; 2320 cond_resched(); 2321 } 2322} 2323 2324static inline void 2325qla2x00_suspend_hba(struct scsi_qla_host *vha) 2326{ 2327 int cnt; 2328 unsigned long flags; 2329 struct qla_hw_data *ha = vha->hw; 2330 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2331 2332 /* Suspend HBA. */ 2333 scsi_block_requests(vha->host); 2334 ha->isp_ops->disable_intrs(ha); 2335 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2336 2337 /* Pause RISC. */ 2338 spin_lock_irqsave(&ha->hardware_lock, flags); 2339 wrt_reg_word(®->hccr, HCCR_PAUSE_RISC); 2340 rd_reg_word(®->hccr); 2341 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { 2342 for (cnt = 0; cnt < 30000; cnt++) { 2343 if ((rd_reg_word(®->hccr) & HCCR_RISC_PAUSE) != 0) 2344 break; 2345 udelay(100); 2346 } 2347 } else { 2348 udelay(10); 2349 } 2350 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2351} 2352 2353static inline void 2354qla2x00_resume_hba(struct scsi_qla_host *vha) 2355{ 2356 struct qla_hw_data *ha = vha->hw; 2357 2358 /* Resume HBA. */ 2359 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2360 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 2361 qla2xxx_wake_dpc(vha); 2362 qla2x00_wait_for_chip_reset(vha); 2363 scsi_unblock_requests(vha->host); 2364} 2365 2366void * 2367qla2x00_read_optrom_data(struct scsi_qla_host *vha, void *buf, 2368 uint32_t offset, uint32_t length) 2369{ 2370 uint32_t addr, midpoint; 2371 uint8_t *data; 2372 struct qla_hw_data *ha = vha->hw; 2373 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2374 2375 /* Suspend HBA. */ 2376 qla2x00_suspend_hba(vha); 2377 2378 /* Go with read. */ 2379 midpoint = ha->optrom_size / 2; 2380 2381 qla2x00_flash_enable(ha); 2382 wrt_reg_word(®->nvram, 0); 2383 rd_reg_word(®->nvram); /* PCI Posting. */ 2384 for (addr = offset, data = buf; addr < length; addr++, data++) { 2385 if (addr == midpoint) { 2386 wrt_reg_word(®->nvram, NVR_SELECT); 2387 rd_reg_word(®->nvram); /* PCI Posting. */ 2388 } 2389 2390 *data = qla2x00_read_flash_byte(ha, addr); 2391 } 2392 qla2x00_flash_disable(ha); 2393 2394 /* Resume HBA. */ 2395 qla2x00_resume_hba(vha); 2396 2397 return buf; 2398} 2399 2400int 2401qla2x00_write_optrom_data(struct scsi_qla_host *vha, void *buf, 2402 uint32_t offset, uint32_t length) 2403{ 2404 2405 int rval; 2406 uint8_t man_id, flash_id, sec_number, *data; 2407 uint16_t wd; 2408 uint32_t addr, liter, sec_mask, rest_addr; 2409 struct qla_hw_data *ha = vha->hw; 2410 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2411 2412 /* Suspend HBA. */ 2413 qla2x00_suspend_hba(vha); 2414 2415 rval = QLA_SUCCESS; 2416 sec_number = 0; 2417 2418 /* Reset ISP chip. */ 2419 wrt_reg_word(®->ctrl_status, CSR_ISP_SOFT_RESET); 2420 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); 2421 2422 /* Go with write. */ 2423 qla2x00_flash_enable(ha); 2424 do { /* Loop once to provide quick error exit */ 2425 /* Structure of flash memory based on manufacturer */ 2426 if (IS_OEM_001(ha)) { 2427 /* OEM variant with special flash part. */ 2428 man_id = flash_id = 0; 2429 rest_addr = 0xffff; 2430 sec_mask = 0x10000; 2431 goto update_flash; 2432 } 2433 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id); 2434 switch (man_id) { 2435 case 0x20: /* ST flash. */ 2436 if (flash_id == 0xd2 || flash_id == 0xe3) { 2437 /* 2438 * ST m29w008at part - 64kb sector size with 2439 * 32kb,8kb,8kb,16kb sectors at memory address 2440 * 0xf0000. 2441 */ 2442 rest_addr = 0xffff; 2443 sec_mask = 0x10000; 2444 break; 2445 } 2446 /* 2447 * ST m29w010b part - 16kb sector size 2448 * Default to 16kb sectors 2449 */ 2450 rest_addr = 0x3fff; 2451 sec_mask = 0x1c000; 2452 break; 2453 case 0x40: /* Mostel flash. */ 2454 /* Mostel v29c51001 part - 512 byte sector size. */ 2455 rest_addr = 0x1ff; 2456 sec_mask = 0x1fe00; 2457 break; 2458 case 0xbf: /* SST flash. */ 2459 /* SST39sf10 part - 4kb sector size. */ 2460 rest_addr = 0xfff; 2461 sec_mask = 0x1f000; 2462 break; 2463 case 0xda: /* Winbond flash. */ 2464 /* Winbond W29EE011 part - 256 byte sector size. */ 2465 rest_addr = 0x7f; 2466 sec_mask = 0x1ff80; 2467 break; 2468 case 0xc2: /* Macronix flash. */ 2469 /* 64k sector size. */ 2470 if (flash_id == 0x38 || flash_id == 0x4f) { 2471 rest_addr = 0xffff; 2472 sec_mask = 0x10000; 2473 break; 2474 } 2475 fallthrough; 2476 2477 case 0x1f: /* Atmel flash. */ 2478 /* 512k sector size. */ 2479 if (flash_id == 0x13) { 2480 rest_addr = 0x7fffffff; 2481 sec_mask = 0x80000000; 2482 break; 2483 } 2484 fallthrough; 2485 2486 case 0x01: /* AMD flash. */ 2487 if (flash_id == 0x38 || flash_id == 0x40 || 2488 flash_id == 0x4f) { 2489 /* Am29LV081 part - 64kb sector size. */ 2490 /* Am29LV002BT part - 64kb sector size. */ 2491 rest_addr = 0xffff; 2492 sec_mask = 0x10000; 2493 break; 2494 } else if (flash_id == 0x3e) { 2495 /* 2496 * Am29LV008b part - 64kb sector size with 2497 * 32kb,8kb,8kb,16kb sector at memory address 2498 * h0xf0000. 2499 */ 2500 rest_addr = 0xffff; 2501 sec_mask = 0x10000; 2502 break; 2503 } else if (flash_id == 0x20 || flash_id == 0x6e) { 2504 /* 2505 * Am29LV010 part or AM29f010 - 16kb sector 2506 * size. 2507 */ 2508 rest_addr = 0x3fff; 2509 sec_mask = 0x1c000; 2510 break; 2511 } else if (flash_id == 0x6d) { 2512 /* Am29LV001 part - 8kb sector size. */ 2513 rest_addr = 0x1fff; 2514 sec_mask = 0x1e000; 2515 break; 2516 } 2517 fallthrough; 2518 default: 2519 /* Default to 16 kb sector size. */ 2520 rest_addr = 0x3fff; 2521 sec_mask = 0x1c000; 2522 break; 2523 } 2524 2525update_flash: 2526 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 2527 if (qla2x00_erase_flash(ha, man_id, flash_id)) { 2528 rval = QLA_FUNCTION_FAILED; 2529 break; 2530 } 2531 } 2532 2533 for (addr = offset, liter = 0; liter < length; liter++, 2534 addr++) { 2535 data = buf + liter; 2536 /* Are we at the beginning of a sector? */ 2537 if ((addr & rest_addr) == 0) { 2538 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 2539 if (addr >= 0x10000UL) { 2540 if (((addr >> 12) & 0xf0) && 2541 ((man_id == 0x01 && 2542 flash_id == 0x3e) || 2543 (man_id == 0x20 && 2544 flash_id == 0xd2))) { 2545 sec_number++; 2546 if (sec_number == 1) { 2547 rest_addr = 2548 0x7fff; 2549 sec_mask = 2550 0x18000; 2551 } else if ( 2552 sec_number == 2 || 2553 sec_number == 3) { 2554 rest_addr = 2555 0x1fff; 2556 sec_mask = 2557 0x1e000; 2558 } else if ( 2559 sec_number == 4) { 2560 rest_addr = 2561 0x3fff; 2562 sec_mask = 2563 0x1c000; 2564 } 2565 } 2566 } 2567 } else if (addr == ha->optrom_size / 2) { 2568 wrt_reg_word(®->nvram, NVR_SELECT); 2569 rd_reg_word(®->nvram); 2570 } 2571 2572 if (flash_id == 0xda && man_id == 0xc1) { 2573 qla2x00_write_flash_byte(ha, 0x5555, 2574 0xaa); 2575 qla2x00_write_flash_byte(ha, 0x2aaa, 2576 0x55); 2577 qla2x00_write_flash_byte(ha, 0x5555, 2578 0xa0); 2579 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) { 2580 /* Then erase it */ 2581 if (qla2x00_erase_flash_sector(ha, 2582 addr, sec_mask, man_id, 2583 flash_id)) { 2584 rval = QLA_FUNCTION_FAILED; 2585 break; 2586 } 2587 if (man_id == 0x01 && flash_id == 0x6d) 2588 sec_number++; 2589 } 2590 } 2591 2592 if (man_id == 0x01 && flash_id == 0x6d) { 2593 if (sec_number == 1 && 2594 addr == (rest_addr - 1)) { 2595 rest_addr = 0x0fff; 2596 sec_mask = 0x1f000; 2597 } else if (sec_number == 3 && (addr & 0x7ffe)) { 2598 rest_addr = 0x3fff; 2599 sec_mask = 0x1c000; 2600 } 2601 } 2602 2603 if (qla2x00_program_flash_address(ha, addr, *data, 2604 man_id, flash_id)) { 2605 rval = QLA_FUNCTION_FAILED; 2606 break; 2607 } 2608 cond_resched(); 2609 } 2610 } while (0); 2611 qla2x00_flash_disable(ha); 2612 2613 /* Resume HBA. */ 2614 qla2x00_resume_hba(vha); 2615 2616 return rval; 2617} 2618 2619void * 2620qla24xx_read_optrom_data(struct scsi_qla_host *vha, void *buf, 2621 uint32_t offset, uint32_t length) 2622{ 2623 struct qla_hw_data *ha = vha->hw; 2624 int rc; 2625 2626 /* Suspend HBA. */ 2627 scsi_block_requests(vha->host); 2628 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2629 2630 /* Go with read. */ 2631 rc = qla24xx_read_flash_data(vha, buf, offset >> 2, length >> 2); 2632 if (rc) { 2633 ql_log(ql_log_info, vha, 0x01a0, 2634 "Unable to perform optrom read(%x).\n", rc); 2635 } 2636 2637 /* Resume HBA. */ 2638 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2639 scsi_unblock_requests(vha->host); 2640 2641 return buf; 2642} 2643 2644static int 2645qla28xx_extract_sfub_and_verify(struct scsi_qla_host *vha, __le32 *buf, 2646 uint32_t len, uint32_t buf_size_without_sfub, uint8_t *sfub_buf) 2647{ 2648 uint32_t check_sum = 0; 2649 __le32 *p; 2650 int i; 2651 2652 p = buf + buf_size_without_sfub; 2653 2654 /* Extract SFUB from end of file */ 2655 memcpy(sfub_buf, (uint8_t *)p, 2656 sizeof(struct secure_flash_update_block)); 2657 2658 for (i = 0; i < (sizeof(struct secure_flash_update_block) >> 2); i++) 2659 check_sum += le32_to_cpu(p[i]); 2660 2661 check_sum = (~check_sum) + 1; 2662 2663 if (check_sum != le32_to_cpu(p[i])) { 2664 ql_log(ql_log_warn, vha, 0x7097, 2665 "SFUB checksum failed, 0x%x, 0x%x\n", 2666 check_sum, le32_to_cpu(p[i])); 2667 return QLA_COMMAND_ERROR; 2668 } 2669 2670 return QLA_SUCCESS; 2671} 2672 2673static int 2674qla28xx_get_flash_region(struct scsi_qla_host *vha, uint32_t start, 2675 struct qla_flt_region *region) 2676{ 2677 struct qla_hw_data *ha = vha->hw; 2678 struct qla_flt_header *flt = ha->flt; 2679 struct qla_flt_region *flt_reg = &flt->region[0]; 2680 uint16_t cnt; 2681 int rval = QLA_FUNCTION_FAILED; 2682 2683 if (!ha->flt) 2684 return QLA_FUNCTION_FAILED; 2685 2686 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region); 2687 for (; cnt; cnt--, flt_reg++) { 2688 if (le32_to_cpu(flt_reg->start) == start) { 2689 memcpy((uint8_t *)region, flt_reg, 2690 sizeof(struct qla_flt_region)); 2691 rval = QLA_SUCCESS; 2692 break; 2693 } 2694 } 2695 2696 return rval; 2697} 2698 2699static int 2700qla28xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 2701 uint32_t dwords) 2702{ 2703 struct qla_hw_data *ha = vha->hw; 2704 ulong liter; 2705 ulong dburst = OPTROM_BURST_DWORDS; /* burst size in dwords */ 2706 uint32_t sec_mask, rest_addr, fdata; 2707 void *optrom = NULL; 2708 dma_addr_t optrom_dma; 2709 int rval, ret; 2710 struct secure_flash_update_block *sfub; 2711 dma_addr_t sfub_dma; 2712 uint32_t offset = faddr << 2; 2713 uint32_t buf_size_without_sfub = 0; 2714 struct qla_flt_region region; 2715 bool reset_to_rom = false; 2716 uint32_t risc_size, risc_attr = 0; 2717 __be32 *fw_array = NULL; 2718 2719 /* Retrieve region info - must be a start address passed in */ 2720 rval = qla28xx_get_flash_region(vha, offset, ®ion); 2721 2722 if (rval != QLA_SUCCESS) { 2723 ql_log(ql_log_warn, vha, 0xffff, 2724 "Invalid address %x - not a region start address\n", 2725 offset); 2726 goto done; 2727 } 2728 2729 /* Allocate dma buffer for burst write */ 2730 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 2731 &optrom_dma, GFP_KERNEL); 2732 if (!optrom) { 2733 ql_log(ql_log_warn, vha, 0x7095, 2734 "Failed allocate burst (%x bytes)\n", OPTROM_BURST_SIZE); 2735 rval = QLA_COMMAND_ERROR; 2736 goto done; 2737 } 2738 2739 /* 2740 * If adapter supports secure flash and region is secure 2741 * extract secure flash update block (SFUB) and verify 2742 */ 2743 if (ha->flags.secure_adapter && region.attribute) { 2744 2745 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2746 "Region %x is secure\n", le16_to_cpu(region.code)); 2747 2748 switch (le16_to_cpu(region.code)) { 2749 case FLT_REG_FW: 2750 case FLT_REG_FW_SEC_27XX: 2751 case FLT_REG_MPI_PRI_28XX: 2752 case FLT_REG_MPI_SEC_28XX: 2753 fw_array = (__force __be32 *)dwptr; 2754 2755 /* 1st fw array */ 2756 risc_size = be32_to_cpu(fw_array[3]); 2757 risc_attr = be32_to_cpu(fw_array[9]); 2758 2759 buf_size_without_sfub = risc_size; 2760 fw_array += risc_size; 2761 2762 /* 2nd fw array */ 2763 risc_size = be32_to_cpu(fw_array[3]); 2764 2765 buf_size_without_sfub += risc_size; 2766 fw_array += risc_size; 2767 2768 /* 1st dump template */ 2769 risc_size = be32_to_cpu(fw_array[2]); 2770 2771 /* skip header and ignore checksum */ 2772 buf_size_without_sfub += risc_size; 2773 fw_array += risc_size; 2774 2775 if (risc_attr & BIT_9) { 2776 /* 2nd dump template */ 2777 risc_size = be32_to_cpu(fw_array[2]); 2778 2779 /* skip header and ignore checksum */ 2780 buf_size_without_sfub += risc_size; 2781 fw_array += risc_size; 2782 } 2783 break; 2784 2785 case FLT_REG_PEP_PRI_28XX: 2786 case FLT_REG_PEP_SEC_28XX: 2787 fw_array = (__force __be32 *)dwptr; 2788 2789 /* 1st fw array */ 2790 risc_size = be32_to_cpu(fw_array[3]); 2791 risc_attr = be32_to_cpu(fw_array[9]); 2792 2793 buf_size_without_sfub = risc_size; 2794 fw_array += risc_size; 2795 break; 2796 2797 default: 2798 ql_log(ql_log_warn + ql_dbg_verbose, vha, 2799 0xffff, "Secure region %x not supported\n", 2800 le16_to_cpu(region.code)); 2801 rval = QLA_COMMAND_ERROR; 2802 goto done; 2803 } 2804 2805 sfub = dma_alloc_coherent(&ha->pdev->dev, 2806 sizeof(struct secure_flash_update_block), &sfub_dma, 2807 GFP_KERNEL); 2808 if (!sfub) { 2809 ql_log(ql_log_warn, vha, 0xffff, 2810 "Unable to allocate memory for SFUB\n"); 2811 rval = QLA_COMMAND_ERROR; 2812 goto done; 2813 } 2814 2815 rval = qla28xx_extract_sfub_and_verify(vha, (__le32 *)dwptr, 2816 dwords, buf_size_without_sfub, (uint8_t *)sfub); 2817 2818 if (rval != QLA_SUCCESS) 2819 goto done; 2820 2821 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2822 "SFUB extract and verify successful\n"); 2823 } 2824 2825 rest_addr = (ha->fdt_block_size >> 2) - 1; 2826 sec_mask = ~rest_addr; 2827 2828 /* Lock semaphore */ 2829 rval = qla81xx_fac_semaphore_access(vha, FAC_SEMAPHORE_LOCK); 2830 if (rval != QLA_SUCCESS) { 2831 ql_log(ql_log_warn, vha, 0xffff, 2832 "Unable to lock flash semaphore."); 2833 goto done; 2834 } 2835 2836 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 2837 "Unprotect flash...\n"); 2838 rval = qla24xx_unprotect_flash(vha); 2839 if (rval) { 2840 qla81xx_fac_semaphore_access(vha, FAC_SEMAPHORE_UNLOCK); 2841 ql_log(ql_log_warn, vha, 0x7096, "Failed unprotect flash\n"); 2842 goto done; 2843 } 2844 2845 for (liter = 0; liter < dwords; liter++, faddr++) { 2846 fdata = (faddr & sec_mask) << 2; 2847 2848 /* If start of sector */ 2849 if (!(faddr & rest_addr)) { 2850 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 2851 "Erase sector %#x...\n", faddr); 2852 rval = qla24xx_erase_sector(vha, fdata); 2853 if (rval) { 2854 ql_dbg(ql_dbg_user, vha, 0x7007, 2855 "Failed erase sector %#x\n", faddr); 2856 goto write_protect; 2857 } 2858 } 2859 } 2860 2861 if (ha->flags.secure_adapter) { 2862 /* 2863 * If adapter supports secure flash but FW doesn't, 2864 * disable write protect, release semaphore and reset 2865 * chip to execute ROM code in order to update region securely 2866 */ 2867 if (!ha->flags.secure_fw) { 2868 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2869 "Disable Write and Release Semaphore."); 2870 rval = qla24xx_protect_flash(vha); 2871 if (rval != QLA_SUCCESS) { 2872 qla81xx_fac_semaphore_access(vha, 2873 FAC_SEMAPHORE_UNLOCK); 2874 ql_log(ql_log_warn, vha, 0xffff, 2875 "Unable to protect flash."); 2876 goto done; 2877 } 2878 2879 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2880 "Reset chip to ROM."); 2881 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 2882 set_bit(ISP_ABORT_TO_ROM, &vha->dpc_flags); 2883 qla2xxx_wake_dpc(vha); 2884 rval = qla2x00_wait_for_chip_reset(vha); 2885 if (rval != QLA_SUCCESS) { 2886 ql_log(ql_log_warn, vha, 0xffff, 2887 "Unable to reset to ROM code."); 2888 goto done; 2889 } 2890 reset_to_rom = true; 2891 ha->flags.fac_supported = 0; 2892 2893 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2894 "Lock Semaphore"); 2895 rval = qla2xxx_write_remote_register(vha, 2896 FLASH_SEMAPHORE_REGISTER_ADDR, 0x00020002); 2897 if (rval != QLA_SUCCESS) { 2898 ql_log(ql_log_warn, vha, 0xffff, 2899 "Unable to lock flash semaphore."); 2900 goto done; 2901 } 2902 2903 /* Unprotect flash */ 2904 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2905 "Enable Write."); 2906 rval = qla2x00_write_ram_word(vha, 0x7ffd0101, 0); 2907 if (rval) { 2908 ql_log(ql_log_warn, vha, 0x7096, 2909 "Failed unprotect flash\n"); 2910 goto done; 2911 } 2912 } 2913 2914 /* If region is secure, send Secure Flash MB Cmd */ 2915 if (region.attribute && buf_size_without_sfub) { 2916 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2917 "Sending Secure Flash MB Cmd\n"); 2918 rval = qla28xx_secure_flash_update(vha, 0, 2919 le16_to_cpu(region.code), 2920 buf_size_without_sfub, sfub_dma, 2921 sizeof(struct secure_flash_update_block) >> 2); 2922 if (rval != QLA_SUCCESS) { 2923 ql_log(ql_log_warn, vha, 0xffff, 2924 "Secure Flash MB Cmd failed %x.", rval); 2925 goto write_protect; 2926 } 2927 } 2928 2929 } 2930 2931 /* re-init flash offset */ 2932 faddr = offset >> 2; 2933 2934 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) { 2935 fdata = (faddr & sec_mask) << 2; 2936 2937 /* If smaller than a burst remaining */ 2938 if (dwords - liter < dburst) 2939 dburst = dwords - liter; 2940 2941 /* Copy to dma buffer */ 2942 memcpy(optrom, dwptr, dburst << 2); 2943 2944 /* Burst write */ 2945 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 2946 "Write burst (%#lx dwords)...\n", dburst); 2947 rval = qla2x00_load_ram(vha, optrom_dma, 2948 flash_data_addr(ha, faddr), dburst); 2949 if (rval != QLA_SUCCESS) { 2950 ql_log(ql_log_warn, vha, 0x7097, 2951 "Failed burst write at %x (%p/%#llx)...\n", 2952 flash_data_addr(ha, faddr), optrom, 2953 (u64)optrom_dma); 2954 break; 2955 } 2956 2957 liter += dburst - 1; 2958 faddr += dburst - 1; 2959 dwptr += dburst - 1; 2960 } 2961 2962write_protect: 2963 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 2964 "Protect flash...\n"); 2965 ret = qla24xx_protect_flash(vha); 2966 if (ret) { 2967 qla81xx_fac_semaphore_access(vha, FAC_SEMAPHORE_UNLOCK); 2968 ql_log(ql_log_warn, vha, 0x7099, 2969 "Failed protect flash\n"); 2970 rval = QLA_COMMAND_ERROR; 2971 } 2972 2973 if (reset_to_rom == true) { 2974 /* Schedule DPC to restart the RISC */ 2975 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 2976 qla2xxx_wake_dpc(vha); 2977 2978 ret = qla2x00_wait_for_hba_online(vha); 2979 if (ret != QLA_SUCCESS) { 2980 ql_log(ql_log_warn, vha, 0xffff, 2981 "Adapter did not come out of reset\n"); 2982 rval = QLA_COMMAND_ERROR; 2983 } 2984 } 2985 2986done: 2987 if (optrom) 2988 dma_free_coherent(&ha->pdev->dev, 2989 OPTROM_BURST_SIZE, optrom, optrom_dma); 2990 2991 return rval; 2992} 2993 2994int 2995qla24xx_write_optrom_data(struct scsi_qla_host *vha, void *buf, 2996 uint32_t offset, uint32_t length) 2997{ 2998 int rval; 2999 struct qla_hw_data *ha = vha->hw; 3000 3001 /* Suspend HBA. */ 3002 scsi_block_requests(vha->host); 3003 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 3004 3005 /* Go with write. */ 3006 if (IS_QLA28XX(ha)) 3007 rval = qla28xx_write_flash_data(vha, buf, offset >> 2, 3008 length >> 2); 3009 else 3010 rval = qla24xx_write_flash_data(vha, buf, offset >> 2, 3011 length >> 2); 3012 3013 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 3014 scsi_unblock_requests(vha->host); 3015 3016 return rval; 3017} 3018 3019void * 3020qla25xx_read_optrom_data(struct scsi_qla_host *vha, void *buf, 3021 uint32_t offset, uint32_t length) 3022{ 3023 int rval; 3024 dma_addr_t optrom_dma; 3025 void *optrom; 3026 uint8_t *pbuf; 3027 uint32_t faddr, left, burst; 3028 struct qla_hw_data *ha = vha->hw; 3029 3030 if (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || 3031 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 3032 goto try_fast; 3033 if (offset & 0xfff) 3034 goto slow_read; 3035 if (length < OPTROM_BURST_SIZE) 3036 goto slow_read; 3037 3038try_fast: 3039 if (offset & 0xff) 3040 goto slow_read; 3041 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 3042 &optrom_dma, GFP_KERNEL); 3043 if (!optrom) { 3044 ql_log(ql_log_warn, vha, 0x00cc, 3045 "Unable to allocate memory for optrom burst read (%x KB).\n", 3046 OPTROM_BURST_SIZE / 1024); 3047 goto slow_read; 3048 } 3049 3050 pbuf = buf; 3051 faddr = offset >> 2; 3052 left = length >> 2; 3053 burst = OPTROM_BURST_DWORDS; 3054 while (left != 0) { 3055 if (burst > left) 3056 burst = left; 3057 3058 rval = qla2x00_dump_ram(vha, optrom_dma, 3059 flash_data_addr(ha, faddr), burst); 3060 if (rval) { 3061 ql_log(ql_log_warn, vha, 0x00f5, 3062 "Unable to burst-read optrom segment (%x/%x/%llx).\n", 3063 rval, flash_data_addr(ha, faddr), 3064 (unsigned long long)optrom_dma); 3065 ql_log(ql_log_warn, vha, 0x00f6, 3066 "Reverting to slow-read.\n"); 3067 3068 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 3069 optrom, optrom_dma); 3070 goto slow_read; 3071 } 3072 3073 memcpy(pbuf, optrom, burst * 4); 3074 3075 left -= burst; 3076 faddr += burst; 3077 pbuf += burst * 4; 3078 } 3079 3080 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom, 3081 optrom_dma); 3082 3083 return buf; 3084 3085slow_read: 3086 return qla24xx_read_optrom_data(vha, buf, offset, length); 3087} 3088 3089/** 3090 * qla2x00_get_fcode_version() - Determine an FCODE image's version. 3091 * @ha: HA context 3092 * @pcids: Pointer to the FCODE PCI data structure 3093 * 3094 * The process of retrieving the FCODE version information is at best 3095 * described as interesting. 3096 * 3097 * Within the first 100h bytes of the image an ASCII string is present 3098 * which contains several pieces of information including the FCODE 3099 * version. Unfortunately it seems the only reliable way to retrieve 3100 * the version is by scanning for another sentinel within the string, 3101 * the FCODE build date: 3102 * 3103 * ... 2.00.02 10/17/02 ... 3104 * 3105 * Returns QLA_SUCCESS on successful retrieval of version. 3106 */ 3107static void 3108qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids) 3109{ 3110 int ret = QLA_FUNCTION_FAILED; 3111 uint32_t istart, iend, iter, vend; 3112 uint8_t do_next, rbyte, *vbyte; 3113 3114 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 3115 3116 /* Skip the PCI data structure. */ 3117 istart = pcids + 3118 ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) | 3119 qla2x00_read_flash_byte(ha, pcids + 0x0A)); 3120 iend = istart + 0x100; 3121 do { 3122 /* Scan for the sentinel date string...eeewww. */ 3123 do_next = 0; 3124 iter = istart; 3125 while ((iter < iend) && !do_next) { 3126 iter++; 3127 if (qla2x00_read_flash_byte(ha, iter) == '/') { 3128 if (qla2x00_read_flash_byte(ha, iter + 2) == 3129 '/') 3130 do_next++; 3131 else if (qla2x00_read_flash_byte(ha, 3132 iter + 3) == '/') 3133 do_next++; 3134 } 3135 } 3136 if (!do_next) 3137 break; 3138 3139 /* Backtrack to previous ' ' (space). */ 3140 do_next = 0; 3141 while ((iter > istart) && !do_next) { 3142 iter--; 3143 if (qla2x00_read_flash_byte(ha, iter) == ' ') 3144 do_next++; 3145 } 3146 if (!do_next) 3147 break; 3148 3149 /* 3150 * Mark end of version tag, and find previous ' ' (space) or 3151 * string length (recent FCODE images -- major hack ahead!!!). 3152 */ 3153 vend = iter - 1; 3154 do_next = 0; 3155 while ((iter > istart) && !do_next) { 3156 iter--; 3157 rbyte = qla2x00_read_flash_byte(ha, iter); 3158 if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10) 3159 do_next++; 3160 } 3161 if (!do_next) 3162 break; 3163 3164 /* Mark beginning of version tag, and copy data. */ 3165 iter++; 3166 if ((vend - iter) && 3167 ((vend - iter) < sizeof(ha->fcode_revision))) { 3168 vbyte = ha->fcode_revision; 3169 while (iter <= vend) { 3170 *vbyte++ = qla2x00_read_flash_byte(ha, iter); 3171 iter++; 3172 } 3173 ret = QLA_SUCCESS; 3174 } 3175 } while (0); 3176 3177 if (ret != QLA_SUCCESS) 3178 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 3179} 3180 3181int 3182qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf) 3183{ 3184 int ret = QLA_SUCCESS; 3185 uint8_t code_type, last_image; 3186 uint32_t pcihdr, pcids; 3187 uint8_t *dbyte; 3188 uint16_t *dcode; 3189 struct qla_hw_data *ha = vha->hw; 3190 3191 if (!ha->pio_address || !mbuf) 3192 return QLA_FUNCTION_FAILED; 3193 3194 memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); 3195 memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); 3196 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 3197 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3198 3199 qla2x00_flash_enable(ha); 3200 3201 /* Begin with first PCI expansion ROM header. */ 3202 pcihdr = 0; 3203 last_image = 1; 3204 do { 3205 /* Verify PCI expansion ROM header. */ 3206 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 || 3207 qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) { 3208 /* No signature */ 3209 ql_log(ql_log_fatal, vha, 0x0050, 3210 "No matching ROM signature.\n"); 3211 ret = QLA_FUNCTION_FAILED; 3212 break; 3213 } 3214 3215 /* Locate PCI data structure. */ 3216 pcids = pcihdr + 3217 ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) | 3218 qla2x00_read_flash_byte(ha, pcihdr + 0x18)); 3219 3220 /* Validate signature of PCI data structure. */ 3221 if (qla2x00_read_flash_byte(ha, pcids) != 'P' || 3222 qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' || 3223 qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' || 3224 qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') { 3225 /* Incorrect header. */ 3226 ql_log(ql_log_fatal, vha, 0x0051, 3227 "PCI data struct not found pcir_adr=%x.\n", pcids); 3228 ret = QLA_FUNCTION_FAILED; 3229 break; 3230 } 3231 3232 /* Read version */ 3233 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14); 3234 switch (code_type) { 3235 case ROM_CODE_TYPE_BIOS: 3236 /* Intel x86, PC-AT compatible. */ 3237 ha->bios_revision[0] = 3238 qla2x00_read_flash_byte(ha, pcids + 0x12); 3239 ha->bios_revision[1] = 3240 qla2x00_read_flash_byte(ha, pcids + 0x13); 3241 ql_dbg(ql_dbg_init, vha, 0x0052, 3242 "Read BIOS %d.%d.\n", 3243 ha->bios_revision[1], ha->bios_revision[0]); 3244 break; 3245 case ROM_CODE_TYPE_FCODE: 3246 /* Open Firmware standard for PCI (FCode). */ 3247 /* Eeeewww... */ 3248 qla2x00_get_fcode_version(ha, pcids); 3249 break; 3250 case ROM_CODE_TYPE_EFI: 3251 /* Extensible Firmware Interface (EFI). */ 3252 ha->efi_revision[0] = 3253 qla2x00_read_flash_byte(ha, pcids + 0x12); 3254 ha->efi_revision[1] = 3255 qla2x00_read_flash_byte(ha, pcids + 0x13); 3256 ql_dbg(ql_dbg_init, vha, 0x0053, 3257 "Read EFI %d.%d.\n", 3258 ha->efi_revision[1], ha->efi_revision[0]); 3259 break; 3260 default: 3261 ql_log(ql_log_warn, vha, 0x0054, 3262 "Unrecognized code type %x at pcids %x.\n", 3263 code_type, pcids); 3264 break; 3265 } 3266 3267 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7; 3268 3269 /* Locate next PCI expansion ROM. */ 3270 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) | 3271 qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512; 3272 } while (!last_image); 3273 3274 if (IS_QLA2322(ha)) { 3275 /* Read firmware image information. */ 3276 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3277 dbyte = mbuf; 3278 memset(dbyte, 0, 8); 3279 dcode = (uint16_t *)dbyte; 3280 3281 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10, 3282 8); 3283 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010a, 3284 "Dumping fw " 3285 "ver from flash:.\n"); 3286 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010b, 3287 dbyte, 32); 3288 3289 if ((dcode[0] == 0xffff && dcode[1] == 0xffff && 3290 dcode[2] == 0xffff && dcode[3] == 0xffff) || 3291 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 && 3292 dcode[3] == 0)) { 3293 ql_log(ql_log_warn, vha, 0x0057, 3294 "Unrecognized fw revision at %x.\n", 3295 ha->flt_region_fw * 4); 3296 } else { 3297 /* values are in big endian */ 3298 ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1]; 3299 ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3]; 3300 ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5]; 3301 ql_dbg(ql_dbg_init, vha, 0x0058, 3302 "FW Version: " 3303 "%d.%d.%d.\n", ha->fw_revision[0], 3304 ha->fw_revision[1], ha->fw_revision[2]); 3305 } 3306 } 3307 3308 qla2x00_flash_disable(ha); 3309 3310 return ret; 3311} 3312 3313int 3314qla82xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf) 3315{ 3316 int ret = QLA_SUCCESS; 3317 uint32_t pcihdr, pcids; 3318 uint32_t *dcode = mbuf; 3319 uint8_t *bcode = mbuf; 3320 uint8_t code_type, last_image; 3321 struct qla_hw_data *ha = vha->hw; 3322 3323 if (!mbuf) 3324 return QLA_FUNCTION_FAILED; 3325 3326 memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); 3327 memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); 3328 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 3329 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3330 3331 /* Begin with first PCI expansion ROM header. */ 3332 pcihdr = ha->flt_region_boot << 2; 3333 last_image = 1; 3334 do { 3335 /* Verify PCI expansion ROM header. */ 3336 ha->isp_ops->read_optrom(vha, dcode, pcihdr, 0x20 * 4); 3337 bcode = mbuf + (pcihdr % 4); 3338 if (memcmp(bcode, "\x55\xaa", 2)) { 3339 /* No signature */ 3340 ql_log(ql_log_fatal, vha, 0x0154, 3341 "No matching ROM signature.\n"); 3342 ret = QLA_FUNCTION_FAILED; 3343 break; 3344 } 3345 3346 /* Locate PCI data structure. */ 3347 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]); 3348 3349 ha->isp_ops->read_optrom(vha, dcode, pcids, 0x20 * 4); 3350 bcode = mbuf + (pcihdr % 4); 3351 3352 /* Validate signature of PCI data structure. */ 3353 if (memcmp(bcode, "PCIR", 4)) { 3354 /* Incorrect header. */ 3355 ql_log(ql_log_fatal, vha, 0x0155, 3356 "PCI data struct not found pcir_adr=%x.\n", pcids); 3357 ret = QLA_FUNCTION_FAILED; 3358 break; 3359 } 3360 3361 /* Read version */ 3362 code_type = bcode[0x14]; 3363 switch (code_type) { 3364 case ROM_CODE_TYPE_BIOS: 3365 /* Intel x86, PC-AT compatible. */ 3366 ha->bios_revision[0] = bcode[0x12]; 3367 ha->bios_revision[1] = bcode[0x13]; 3368 ql_dbg(ql_dbg_init, vha, 0x0156, 3369 "Read BIOS %d.%d.\n", 3370 ha->bios_revision[1], ha->bios_revision[0]); 3371 break; 3372 case ROM_CODE_TYPE_FCODE: 3373 /* Open Firmware standard for PCI (FCode). */ 3374 ha->fcode_revision[0] = bcode[0x12]; 3375 ha->fcode_revision[1] = bcode[0x13]; 3376 ql_dbg(ql_dbg_init, vha, 0x0157, 3377 "Read FCODE %d.%d.\n", 3378 ha->fcode_revision[1], ha->fcode_revision[0]); 3379 break; 3380 case ROM_CODE_TYPE_EFI: 3381 /* Extensible Firmware Interface (EFI). */ 3382 ha->efi_revision[0] = bcode[0x12]; 3383 ha->efi_revision[1] = bcode[0x13]; 3384 ql_dbg(ql_dbg_init, vha, 0x0158, 3385 "Read EFI %d.%d.\n", 3386 ha->efi_revision[1], ha->efi_revision[0]); 3387 break; 3388 default: 3389 ql_log(ql_log_warn, vha, 0x0159, 3390 "Unrecognized code type %x at pcids %x.\n", 3391 code_type, pcids); 3392 break; 3393 } 3394 3395 last_image = bcode[0x15] & BIT_7; 3396 3397 /* Locate next PCI expansion ROM. */ 3398 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512; 3399 } while (!last_image); 3400 3401 /* Read firmware image information. */ 3402 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3403 dcode = mbuf; 3404 ha->isp_ops->read_optrom(vha, dcode, ha->flt_region_fw << 2, 0x20); 3405 bcode = mbuf + (pcihdr % 4); 3406 3407 /* Validate signature of PCI data structure. */ 3408 if (bcode[0x0] == 0x3 && bcode[0x1] == 0x0 && 3409 bcode[0x2] == 0x40 && bcode[0x3] == 0x40) { 3410 ha->fw_revision[0] = bcode[0x4]; 3411 ha->fw_revision[1] = bcode[0x5]; 3412 ha->fw_revision[2] = bcode[0x6]; 3413 ql_dbg(ql_dbg_init, vha, 0x0153, 3414 "Firmware revision %d.%d.%d\n", 3415 ha->fw_revision[0], ha->fw_revision[1], 3416 ha->fw_revision[2]); 3417 } 3418 3419 return ret; 3420} 3421 3422int 3423qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf) 3424{ 3425 int ret = QLA_SUCCESS; 3426 uint32_t pcihdr = 0, pcids = 0; 3427 uint32_t *dcode = mbuf; 3428 uint8_t *bcode = mbuf; 3429 uint8_t code_type, last_image; 3430 int i; 3431 struct qla_hw_data *ha = vha->hw; 3432 uint32_t faddr = 0; 3433 struct active_regions active_regions = { }; 3434 3435 if (IS_P3P_TYPE(ha)) 3436 return QLA_SUCCESS; 3437 3438 if (!mbuf) 3439 return QLA_FUNCTION_FAILED; 3440 3441 memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); 3442 memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); 3443 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 3444 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3445 3446 pcihdr = ha->flt_region_boot << 2; 3447 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 3448 qla27xx_get_active_image(vha, &active_regions); 3449 if (active_regions.global == QLA27XX_SECONDARY_IMAGE) { 3450 pcihdr = ha->flt_region_boot_sec << 2; 3451 } 3452 } 3453 3454 do { 3455 /* Verify PCI expansion ROM header. */ 3456 ret = qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20); 3457 if (ret) { 3458 ql_log(ql_log_info, vha, 0x017d, 3459 "Unable to read PCI EXP Rom Header(%x).\n", ret); 3460 return QLA_FUNCTION_FAILED; 3461 } 3462 3463 bcode = mbuf + (pcihdr % 4); 3464 if (memcmp(bcode, "\x55\xaa", 2)) { 3465 /* No signature */ 3466 ql_log(ql_log_fatal, vha, 0x0059, 3467 "No matching ROM signature.\n"); 3468 return QLA_FUNCTION_FAILED; 3469 } 3470 3471 /* Locate PCI data structure. */ 3472 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]); 3473 3474 ret = qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20); 3475 if (ret) { 3476 ql_log(ql_log_info, vha, 0x018e, 3477 "Unable to read PCI Data Structure (%x).\n", ret); 3478 return QLA_FUNCTION_FAILED; 3479 } 3480 3481 bcode = mbuf + (pcihdr % 4); 3482 3483 /* Validate signature of PCI data structure. */ 3484 if (memcmp(bcode, "PCIR", 4)) { 3485 /* Incorrect header. */ 3486 ql_log(ql_log_fatal, vha, 0x005a, 3487 "PCI data struct not found pcir_adr=%x.\n", pcids); 3488 ql_dump_buffer(ql_dbg_init, vha, 0x0059, dcode, 32); 3489 return QLA_FUNCTION_FAILED; 3490 } 3491 3492 /* Read version */ 3493 code_type = bcode[0x14]; 3494 switch (code_type) { 3495 case ROM_CODE_TYPE_BIOS: 3496 /* Intel x86, PC-AT compatible. */ 3497 ha->bios_revision[0] = bcode[0x12]; 3498 ha->bios_revision[1] = bcode[0x13]; 3499 ql_dbg(ql_dbg_init, vha, 0x005b, 3500 "Read BIOS %d.%d.\n", 3501 ha->bios_revision[1], ha->bios_revision[0]); 3502 break; 3503 case ROM_CODE_TYPE_FCODE: 3504 /* Open Firmware standard for PCI (FCode). */ 3505 ha->fcode_revision[0] = bcode[0x12]; 3506 ha->fcode_revision[1] = bcode[0x13]; 3507 ql_dbg(ql_dbg_init, vha, 0x005c, 3508 "Read FCODE %d.%d.\n", 3509 ha->fcode_revision[1], ha->fcode_revision[0]); 3510 break; 3511 case ROM_CODE_TYPE_EFI: 3512 /* Extensible Firmware Interface (EFI). */ 3513 ha->efi_revision[0] = bcode[0x12]; 3514 ha->efi_revision[1] = bcode[0x13]; 3515 ql_dbg(ql_dbg_init, vha, 0x005d, 3516 "Read EFI %d.%d.\n", 3517 ha->efi_revision[1], ha->efi_revision[0]); 3518 break; 3519 default: 3520 ql_log(ql_log_warn, vha, 0x005e, 3521 "Unrecognized code type %x at pcids %x.\n", 3522 code_type, pcids); 3523 break; 3524 } 3525 3526 last_image = bcode[0x15] & BIT_7; 3527 3528 /* Locate next PCI expansion ROM. */ 3529 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512; 3530 } while (!last_image); 3531 3532 /* Read firmware image information. */ 3533 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3534 faddr = ha->flt_region_fw; 3535 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 3536 qla27xx_get_active_image(vha, &active_regions); 3537 if (active_regions.global == QLA27XX_SECONDARY_IMAGE) 3538 faddr = ha->flt_region_fw_sec; 3539 } 3540 3541 ret = qla24xx_read_flash_data(vha, dcode, faddr, 8); 3542 if (ret) { 3543 ql_log(ql_log_info, vha, 0x019e, 3544 "Unable to read FW version (%x).\n", ret); 3545 return ret; 3546 } else { 3547 if (qla24xx_risc_firmware_invalid(dcode)) { 3548 ql_log(ql_log_warn, vha, 0x005f, 3549 "Unrecognized fw revision at %x.\n", 3550 ha->flt_region_fw * 4); 3551 ql_dump_buffer(ql_dbg_init, vha, 0x005f, dcode, 32); 3552 } else { 3553 for (i = 0; i < 4; i++) 3554 ha->fw_revision[i] = 3555 be32_to_cpu((__force __be32)dcode[4+i]); 3556 ql_dbg(ql_dbg_init, vha, 0x0060, 3557 "Firmware revision (flash) %u.%u.%u (%x).\n", 3558 ha->fw_revision[0], ha->fw_revision[1], 3559 ha->fw_revision[2], ha->fw_revision[3]); 3560 } 3561 } 3562 3563 /* Check for golden firmware and get version if available */ 3564 if (!IS_QLA81XX(ha)) { 3565 /* Golden firmware is not present in non 81XX adapters */ 3566 return ret; 3567 } 3568 3569 memset(ha->gold_fw_version, 0, sizeof(ha->gold_fw_version)); 3570 faddr = ha->flt_region_gold_fw; 3571 ret = qla24xx_read_flash_data(vha, dcode, ha->flt_region_gold_fw, 8); 3572 if (ret) { 3573 ql_log(ql_log_info, vha, 0x019f, 3574 "Unable to read Gold FW version (%x).\n", ret); 3575 return ret; 3576 } else { 3577 if (qla24xx_risc_firmware_invalid(dcode)) { 3578 ql_log(ql_log_warn, vha, 0x0056, 3579 "Unrecognized golden fw at %#x.\n", faddr); 3580 ql_dump_buffer(ql_dbg_init, vha, 0x0056, dcode, 32); 3581 return QLA_FUNCTION_FAILED; 3582 } 3583 3584 for (i = 0; i < 4; i++) 3585 ha->gold_fw_version[i] = 3586 be32_to_cpu((__force __be32)dcode[4+i]); 3587 } 3588 return ret; 3589} 3590 3591static int 3592qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end) 3593{ 3594 if (pos >= end || *pos != 0x82) 3595 return 0; 3596 3597 pos += 3 + pos[1]; 3598 if (pos >= end || *pos != 0x90) 3599 return 0; 3600 3601 pos += 3 + pos[1]; 3602 if (pos >= end || *pos != 0x78) 3603 return 0; 3604 3605 return 1; 3606} 3607 3608int 3609qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size) 3610{ 3611 struct qla_hw_data *ha = vha->hw; 3612 uint8_t *pos = ha->vpd; 3613 uint8_t *end = pos + ha->vpd_size; 3614 int len = 0; 3615 3616 if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end)) 3617 return 0; 3618 3619 while (pos < end && *pos != 0x78) { 3620 len = (*pos == 0x82) ? pos[1] : pos[2]; 3621 3622 if (!strncmp(pos, key, strlen(key))) 3623 break; 3624 3625 if (*pos != 0x90 && *pos != 0x91) 3626 pos += len; 3627 3628 pos += 3; 3629 } 3630 3631 if (pos < end - len && *pos != 0x78) 3632 return scnprintf(str, size, "%.*s", len, pos + 3); 3633 3634 return 0; 3635} 3636 3637int 3638qla24xx_read_fcp_prio_cfg(scsi_qla_host_t *vha) 3639{ 3640 int len, max_len; 3641 uint32_t fcp_prio_addr; 3642 struct qla_hw_data *ha = vha->hw; 3643 3644 if (!ha->fcp_prio_cfg) { 3645 ha->fcp_prio_cfg = vmalloc(FCP_PRIO_CFG_SIZE); 3646 if (!ha->fcp_prio_cfg) { 3647 ql_log(ql_log_warn, vha, 0x00d5, 3648 "Unable to allocate memory for fcp priority data (%x).\n", 3649 FCP_PRIO_CFG_SIZE); 3650 return QLA_FUNCTION_FAILED; 3651 } 3652 } 3653 memset(ha->fcp_prio_cfg, 0, FCP_PRIO_CFG_SIZE); 3654 3655 fcp_prio_addr = ha->flt_region_fcp_prio; 3656 3657 /* first read the fcp priority data header from flash */ 3658 ha->isp_ops->read_optrom(vha, ha->fcp_prio_cfg, 3659 fcp_prio_addr << 2, FCP_PRIO_CFG_HDR_SIZE); 3660 3661 if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 0)) 3662 goto fail; 3663 3664 /* read remaining FCP CMD config data from flash */ 3665 fcp_prio_addr += (FCP_PRIO_CFG_HDR_SIZE >> 2); 3666 len = ha->fcp_prio_cfg->num_entries * sizeof(struct qla_fcp_prio_entry); 3667 max_len = FCP_PRIO_CFG_SIZE - FCP_PRIO_CFG_HDR_SIZE; 3668 3669 ha->isp_ops->read_optrom(vha, &ha->fcp_prio_cfg->entry[0], 3670 fcp_prio_addr << 2, (len < max_len ? len : max_len)); 3671 3672 /* revalidate the entire FCP priority config data, including entries */ 3673 if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 1)) 3674 goto fail; 3675 3676 ha->flags.fcp_prio_enabled = 1; 3677 return QLA_SUCCESS; 3678fail: 3679 vfree(ha->fcp_prio_cfg); 3680 ha->fcp_prio_cfg = NULL; 3681 return QLA_FUNCTION_FAILED; 3682}
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