qla_os.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * QLogic Fibre Channel HBA Driver
   4 * Copyright (c)  2003-2014 QLogic Corporation
   5 */
   6#include "qla_def.h"
   7
   8#include <linux/bitfield.h>
   9#include <linux/moduleparam.h>
  10#include <linux/vmalloc.h>
  11#include <linux/delay.h>
  12#include <linux/kthread.h>
  13#include <linux/mutex.h>
  14#include <linux/kobject.h>
  15#include <linux/slab.h>
  16#include <linux/refcount.h>
  17#include <linux/crash_dump.h>
  18#include <linux/trace_events.h>
  19#include <linux/trace.h>
  20#include <linux/irq.h>
  21
  22#include <scsi/scsi_tcq.h>
  23#include <scsi/scsicam.h>
  24#include <scsi/scsi_transport.h>
  25#include <scsi/scsi_transport_fc.h>
  26
  27#include "qla_target.h"
  28
  29/*
  30 * Driver version
  31 */
  32char qla2x00_version_str[40];
  33
  34static int apidev_major;
  35
  36/*
  37 * SRB allocation cache
  38 */
  39struct kmem_cache *srb_cachep;
  40
  41static struct trace_array *qla_trc_array;
  42
  43int ql2xfulldump_on_mpifail;
  44module_param(ql2xfulldump_on_mpifail, int, S_IRUGO | S_IWUSR);
  45MODULE_PARM_DESC(ql2xfulldump_on_mpifail,
  46		 "Set this to take full dump on MPI hang.");
  47
  48int ql2xenforce_iocb_limit = 2;
  49module_param(ql2xenforce_iocb_limit, int, S_IRUGO | S_IWUSR);
  50MODULE_PARM_DESC(ql2xenforce_iocb_limit,
  51		 "Enforce IOCB throttling, to avoid FW congestion. (default: 2) "
  52		 "1: track usage per queue, 2: track usage per adapter");
  53
  54/*
  55 * CT6 CTX allocation cache
  56 */
  57static struct kmem_cache *ctx_cachep;
  58/*
  59 * error level for logging
  60 */
  61uint ql_errlev = 0x8001;
  62
  63int ql2xsecenable;
  64module_param(ql2xsecenable, int, S_IRUGO);
  65MODULE_PARM_DESC(ql2xsecenable,
  66	"Enable/disable security. 0(Default) - Security disabled. 1 - Security enabled.");
  67
  68static int ql2xenableclass2;
  69module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
  70MODULE_PARM_DESC(ql2xenableclass2,
  71		"Specify if Class 2 operations are supported from the very "
  72		"beginning. Default is 0 - class 2 not supported.");
  73
  74
  75int ql2xlogintimeout = 20;
  76module_param(ql2xlogintimeout, int, S_IRUGO);
  77MODULE_PARM_DESC(ql2xlogintimeout,
  78		"Login timeout value in seconds.");
  79
  80int qlport_down_retry;
  81module_param(qlport_down_retry, int, S_IRUGO);
  82MODULE_PARM_DESC(qlport_down_retry,
  83		"Maximum number of command retries to a port that returns "
  84		"a PORT-DOWN status.");
  85
  86int ql2xplogiabsentdevice;
  87module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
  88MODULE_PARM_DESC(ql2xplogiabsentdevice,
  89		"Option to enable PLOGI to devices that are not present after "
  90		"a Fabric scan.  This is needed for several broken switches. "
  91		"Default is 0 - no PLOGI. 1 - perform PLOGI.");
  92
  93int ql2xloginretrycount;
  94module_param(ql2xloginretrycount, int, S_IRUGO);
  95MODULE_PARM_DESC(ql2xloginretrycount,
  96		"Specify an alternate value for the NVRAM login retry count.");
  97
  98int ql2xallocfwdump = 1;
  99module_param(ql2xallocfwdump, int, S_IRUGO);
 100MODULE_PARM_DESC(ql2xallocfwdump,
 101		"Option to enable allocation of memory for a firmware dump "
 102		"during HBA initialization.  Memory allocation requirements "
 103		"vary by ISP type.  Default is 1 - allocate memory.");
 104
 105int ql2xextended_error_logging;
 106module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
 107module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
 108MODULE_PARM_DESC(ql2xextended_error_logging,
 109		"Option to enable extended error logging,\n"
 110		"\t\tDefault is 0 - no logging.  0x40000000 - Module Init & Probe.\n"
 111		"\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
 112		"\t\t0x08000000 - IO tracing.    0x04000000 - DPC Thread.\n"
 113		"\t\t0x02000000 - Async events.  0x01000000 - Timer routines.\n"
 114		"\t\t0x00800000 - User space.    0x00400000 - Task Management.\n"
 115		"\t\t0x00200000 - AER/EEH.       0x00100000 - Multi Q.\n"
 116		"\t\t0x00080000 - P3P Specific.  0x00040000 - Virtual Port.\n"
 117		"\t\t0x00020000 - Buffer Dump.   0x00010000 - Misc.\n"
 118		"\t\t0x00008000 - Verbose.       0x00004000 - Target.\n"
 119		"\t\t0x00002000 - Target Mgmt.   0x00001000 - Target TMF.\n"
 120		"\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
 121		"\t\t0x1e400000 - Preferred value for capturing essential "
 122		"debug information (equivalent to old "
 123		"ql2xextended_error_logging=1).\n"
 124		"\t\tDo LOGICAL OR of the value to enable more than one level");
 125
 126int ql2xextended_error_logging_ktrace = 1;
 127module_param(ql2xextended_error_logging_ktrace, int, S_IRUGO|S_IWUSR);
 128MODULE_PARM_DESC(ql2xextended_error_logging_ktrace,
 129		"Same BIT definition as ql2xextended_error_logging, but used to control logging to kernel trace buffer (default=1).\n");
 130
 131int ql2xshiftctondsd = 6;
 132module_param(ql2xshiftctondsd, int, S_IRUGO);
 133MODULE_PARM_DESC(ql2xshiftctondsd,
 134		"Set to control shifting of command type processing "
 135		"based on total number of SG elements.");
 136
 137int ql2xfdmienable = 1;
 138module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
 139module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
 140MODULE_PARM_DESC(ql2xfdmienable,
 141		"Enables FDMI registrations. "
 142		"0 - no FDMI registrations. "
 143		"1 - provide FDMI registrations (default).");
 144
 145#define MAX_Q_DEPTH	64
 146static int ql2xmaxqdepth = MAX_Q_DEPTH;
 147module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
 148MODULE_PARM_DESC(ql2xmaxqdepth,
 149		"Maximum queue depth to set for each LUN. "
 150		"Default is 64.");
 151
 152int ql2xenabledif = 2;
 153module_param(ql2xenabledif, int, S_IRUGO);
 154MODULE_PARM_DESC(ql2xenabledif,
 155		" Enable T10-CRC-DIF:\n"
 156		" Default is 2.\n"
 157		"  0 -- No DIF Support\n"
 158		"  1 -- Enable DIF for all types\n"
 159		"  2 -- Enable DIF for all types, except Type 0.\n");
 160
 161#if (IS_ENABLED(CONFIG_NVME_FC))
 162int ql2xnvmeenable = 1;
 163#else
 164int ql2xnvmeenable;
 165#endif
 166module_param(ql2xnvmeenable, int, 0644);
 167MODULE_PARM_DESC(ql2xnvmeenable,
 168    "Enables NVME support. "
 169    "0 - no NVMe.  Default is Y");
 170
 171int ql2xenablehba_err_chk = 2;
 172module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
 173MODULE_PARM_DESC(ql2xenablehba_err_chk,
 174		" Enable T10-CRC-DIF Error isolation by HBA:\n"
 175		" Default is 2.\n"
 176		"  0 -- Error isolation disabled\n"
 177		"  1 -- Error isolation enabled only for DIX Type 0\n"
 178		"  2 -- Error isolation enabled for all Types\n");
 179
 180int ql2xmqsupport = 1;
 181module_param(ql2xmqsupport, int, S_IRUGO);
 182MODULE_PARM_DESC(ql2xmqsupport,
 183		"Enable on demand multiple queue pairs support "
 184		"Default is 1 for supported. "
 185		"Set it to 0 to turn off mq qpair support.");
 186
 187int ql2xfwloadbin;
 188module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
 189module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
 190MODULE_PARM_DESC(ql2xfwloadbin,
 191		"Option to specify location from which to load ISP firmware:.\n"
 192		" 2 -- load firmware via the request_firmware() (hotplug).\n"
 193		"      interface.\n"
 194		" 1 -- load firmware from flash.\n"
 195		" 0 -- use default semantics.\n");
 196
 197int ql2xdbwr = 1;
 198module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
 199MODULE_PARM_DESC(ql2xdbwr,
 200		"Option to specify scheme for request queue posting.\n"
 201		" 0 -- Regular doorbell.\n"
 202		" 1 -- CAMRAM doorbell (faster).\n");
 203
 204int ql2xgffidenable;
 205module_param(ql2xgffidenable, int, S_IRUGO);
 206MODULE_PARM_DESC(ql2xgffidenable,
 207		"Enables GFF_ID checks of port type. "
 208		"Default is 0 - Do not use GFF_ID information.");
 209
 210int ql2xasynctmfenable = 1;
 211module_param(ql2xasynctmfenable, int, S_IRUGO);
 212MODULE_PARM_DESC(ql2xasynctmfenable,
 213		"Enables issue of TM IOCBs asynchronously via IOCB mechanism"
 214		"Default is 1 - Issue TM IOCBs via mailbox mechanism.");
 215
 216int ql2xdontresethba;
 217module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
 218MODULE_PARM_DESC(ql2xdontresethba,
 219		"Option to specify reset behaviour.\n"
 220		" 0 (Default) -- Reset on failure.\n"
 221		" 1 -- Do not reset on failure.\n");
 222
 223uint64_t ql2xmaxlun = MAX_LUNS;
 224module_param(ql2xmaxlun, ullong, S_IRUGO);
 225MODULE_PARM_DESC(ql2xmaxlun,
 226		"Defines the maximum LU number to register with the SCSI "
 227		"midlayer. Default is 65535.");
 228
 229int ql2xmdcapmask = 0x1F;
 230module_param(ql2xmdcapmask, int, S_IRUGO);
 231MODULE_PARM_DESC(ql2xmdcapmask,
 232		"Set the Minidump driver capture mask level. "
 233		"Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
 234
 235int ql2xmdenable = 1;
 236module_param(ql2xmdenable, int, S_IRUGO);
 237MODULE_PARM_DESC(ql2xmdenable,
 238		"Enable/disable MiniDump. "
 239		"0 - MiniDump disabled. "
 240		"1 (Default) - MiniDump enabled.");
 241
 242int ql2xexlogins;
 243module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
 244MODULE_PARM_DESC(ql2xexlogins,
 245		 "Number of extended Logins. "
 246		 "0 (Default)- Disabled.");
 247
 248int ql2xexchoffld = 1024;
 249module_param(ql2xexchoffld, uint, 0644);
 250MODULE_PARM_DESC(ql2xexchoffld,
 251	"Number of target exchanges.");
 252
 253int ql2xiniexchg = 1024;
 254module_param(ql2xiniexchg, uint, 0644);
 255MODULE_PARM_DESC(ql2xiniexchg,
 256	"Number of initiator exchanges.");
 257
 258int ql2xfwholdabts;
 259module_param(ql2xfwholdabts, int, S_IRUGO);
 260MODULE_PARM_DESC(ql2xfwholdabts,
 261		"Allow FW to hold status IOCB until ABTS rsp received. "
 262		"0 (Default) Do not set fw option. "
 263		"1 - Set fw option to hold ABTS.");
 264
 265int ql2xmvasynctoatio = 1;
 266module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
 267MODULE_PARM_DESC(ql2xmvasynctoatio,
 268		"Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
 269		"0 (Default). Do not move IOCBs"
 270		"1 - Move IOCBs.");
 271
 272int ql2xautodetectsfp = 1;
 273module_param(ql2xautodetectsfp, int, 0444);
 274MODULE_PARM_DESC(ql2xautodetectsfp,
 275		 "Detect SFP range and set appropriate distance.\n"
 276		 "1 (Default): Enable\n");
 277
 278int ql2xenablemsix = 1;
 279module_param(ql2xenablemsix, int, 0444);
 280MODULE_PARM_DESC(ql2xenablemsix,
 281		 "Set to enable MSI or MSI-X interrupt mechanism.\n"
 282		 " Default is 1, enable MSI-X interrupt mechanism.\n"
 283		 " 0 -- enable traditional pin-based mechanism.\n"
 284		 " 1 -- enable MSI-X interrupt mechanism.\n"
 285		 " 2 -- enable MSI interrupt mechanism.\n");
 286
 287int qla2xuseresexchforels;
 288module_param(qla2xuseresexchforels, int, 0444);
 289MODULE_PARM_DESC(qla2xuseresexchforels,
 290		 "Reserve 1/2 of emergency exchanges for ELS.\n"
 291		 " 0 (default): disabled");
 292
 293static int ql2xprotmask;
 294module_param(ql2xprotmask, int, 0644);
 295MODULE_PARM_DESC(ql2xprotmask,
 296		 "Override DIF/DIX protection capabilities mask\n"
 297		 "Default is 0 which sets protection mask based on "
 298		 "capabilities reported by HBA firmware.\n");
 299
 300static int ql2xprotguard;
 301module_param(ql2xprotguard, int, 0644);
 302MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n"
 303		 "  0 -- Let HBA firmware decide\n"
 304		 "  1 -- Force T10 CRC\n"
 305		 "  2 -- Force IP checksum\n");
 306
 307int ql2xdifbundlinginternalbuffers;
 308module_param(ql2xdifbundlinginternalbuffers, int, 0644);
 309MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers,
 310    "Force using internal buffers for DIF information\n"
 311    "0 (Default). Based on check.\n"
 312    "1 Force using internal buffers\n");
 313
 314int ql2xsmartsan;
 315module_param(ql2xsmartsan, int, 0444);
 316module_param_named(smartsan, ql2xsmartsan, int, 0444);
 317MODULE_PARM_DESC(ql2xsmartsan,
 318		"Send SmartSAN Management Attributes for FDMI Registration."
 319		" Default is 0 - No SmartSAN registration,"
 320		" 1 - Register SmartSAN Management Attributes.");
 321
 322int ql2xrdpenable;
 323module_param(ql2xrdpenable, int, 0444);
 324module_param_named(rdpenable, ql2xrdpenable, int, 0444);
 325MODULE_PARM_DESC(ql2xrdpenable,
 326		"Enables RDP responses. "
 327		"0 - no RDP responses (default). "
 328		"1 - provide RDP responses.");
 329int ql2xabts_wait_nvme = 1;
 330module_param(ql2xabts_wait_nvme, int, 0444);
 331MODULE_PARM_DESC(ql2xabts_wait_nvme,
 332		 "To wait for ABTS response on I/O timeouts for NVMe. (default: 1)");
 333
 334
 335static u32 ql2xdelay_before_pci_error_handling = 5;
 336module_param(ql2xdelay_before_pci_error_handling, uint, 0644);
 337MODULE_PARM_DESC(ql2xdelay_before_pci_error_handling,
 338	"Number of seconds delayed before qla begin PCI error self-handling (default: 5).\n");
 339
 340static void qla2x00_clear_drv_active(struct qla_hw_data *);
 341static void qla2x00_free_device(scsi_qla_host_t *);
 342static void qla2xxx_map_queues(struct Scsi_Host *shost);
 343static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
 344
 345u32 ql2xnvme_queues = DEF_NVME_HW_QUEUES;
 346module_param(ql2xnvme_queues, uint, S_IRUGO);
 347MODULE_PARM_DESC(ql2xnvme_queues,
 348	"Number of NVMe Queues that can be configured.\n"
 349	"Final value will be min(ql2xnvme_queues, num_cpus,num_chip_queues)\n"
 350	"1 - Minimum number of queues supported\n"
 351	"8 - Default value");
 352
 353int ql2xfc2target = 1;
 354module_param(ql2xfc2target, int, 0444);
 355MODULE_PARM_DESC(qla2xfc2target,
 356		  "Enables FC2 Target support. "
 357		  "0 - FC2 Target support is disabled. "
 358		  "1 - FC2 Target support is enabled (default).");
 359
 360static struct scsi_transport_template *qla2xxx_transport_template = NULL;
 361struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
 362
 363/* TODO Convert to inlines
 364 *
 365 * Timer routines
 366 */
 367
 368__inline__ void
 369qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval)
 370{
 371	timer_setup(&vha->timer, qla2x00_timer, 0);
 372	vha->timer.expires = jiffies + interval * HZ;
 373	add_timer(&vha->timer);
 374	vha->timer_active = 1;
 375}
 376
 377static inline void
 378qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
 379{
 380	/* Currently used for 82XX only. */
 381	if (vha->device_flags & DFLG_DEV_FAILED) {
 382		ql_dbg(ql_dbg_timer, vha, 0x600d,
 383		    "Device in a failed state, returning.\n");
 384		return;
 385	}
 386
 387	mod_timer(&vha->timer, jiffies + interval * HZ);
 388}
 389
 390static __inline__ void
 391qla2x00_stop_timer(scsi_qla_host_t *vha)
 392{
 393	timer_delete_sync(&vha->timer);
 394	vha->timer_active = 0;
 395}
 396
 397static int qla2x00_do_dpc(void *data);
 398
 399static void qla2x00_rst_aen(scsi_qla_host_t *);
 400
 401static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
 402	struct req_que **, struct rsp_que **);
 403static void qla2x00_free_fw_dump(struct qla_hw_data *);
 404static void qla2x00_mem_free(struct qla_hw_data *);
 405int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
 406	struct qla_qpair *qpair);
 407
 408/* -------------------------------------------------------------------------- */
 409static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
 410    struct rsp_que *rsp)
 411{
 412	struct qla_hw_data *ha = vha->hw;
 413
 414	rsp->qpair = ha->base_qpair;
 415	rsp->req = req;
 416	ha->base_qpair->hw = ha;
 417	ha->base_qpair->req = req;
 418	ha->base_qpair->rsp = rsp;
 419	ha->base_qpair->vha = vha;
 420	ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
 421	ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
 422	ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
 423	ha->base_qpair->srb_mempool = ha->srb_mempool;
 424	INIT_LIST_HEAD(&ha->base_qpair->hints_list);
 425	INIT_LIST_HEAD(&ha->base_qpair->dsd_list);
 426	ha->base_qpair->enable_class_2 = ql2xenableclass2;
 427	/* init qpair to this cpu. Will adjust at run time. */
 428	qla_cpu_update(rsp->qpair, raw_smp_processor_id());
 429	ha->base_qpair->pdev = ha->pdev;
 430
 431	if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha))
 432		ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
 433}
 434
 435static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
 436				struct rsp_que *rsp)
 437{
 438	scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 439
 440	ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *),
 441				GFP_KERNEL);
 442	if (!ha->req_q_map) {
 443		ql_log(ql_log_fatal, vha, 0x003b,
 444		    "Unable to allocate memory for request queue ptrs.\n");
 445		goto fail_req_map;
 446	}
 447
 448	ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *),
 449				GFP_KERNEL);
 450	if (!ha->rsp_q_map) {
 451		ql_log(ql_log_fatal, vha, 0x003c,
 452		    "Unable to allocate memory for response queue ptrs.\n");
 453		goto fail_rsp_map;
 454	}
 455
 456	ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
 457	if (ha->base_qpair == NULL) {
 458		ql_log(ql_log_warn, vha, 0x00e0,
 459		    "Failed to allocate base queue pair memory.\n");
 460		goto fail_base_qpair;
 461	}
 462
 463	qla_init_base_qpair(vha, req, rsp);
 464
 465	if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) {
 466		ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
 467			GFP_KERNEL);
 468		if (!ha->queue_pair_map) {
 469			ql_log(ql_log_fatal, vha, 0x0180,
 470			    "Unable to allocate memory for queue pair ptrs.\n");
 471			goto fail_qpair_map;
 472		}
 473		if (qla_mapq_alloc_qp_cpu_map(ha) != 0) {
 474			kfree(ha->queue_pair_map);
 475			ha->queue_pair_map = NULL;
 476			goto fail_qpair_map;
 477		}
 478	}
 479
 480	/*
 481	 * Make sure we record at least the request and response queue zero in
 482	 * case we need to free them if part of the probe fails.
 483	 */
 484	ha->rsp_q_map[0] = rsp;
 485	ha->req_q_map[0] = req;
 486	set_bit(0, ha->rsp_qid_map);
 487	set_bit(0, ha->req_qid_map);
 488	return 0;
 489
 490fail_qpair_map:
 491	kfree(ha->base_qpair);
 492	ha->base_qpair = NULL;
 493fail_base_qpair:
 494	kfree(ha->rsp_q_map);
 495	ha->rsp_q_map = NULL;
 496fail_rsp_map:
 497	kfree(ha->req_q_map);
 498	ha->req_q_map = NULL;
 499fail_req_map:
 500	return -ENOMEM;
 501}
 502
 503static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
 504{
 505	if (IS_QLAFX00(ha)) {
 506		if (req && req->ring_fx00)
 507			dma_free_coherent(&ha->pdev->dev,
 508			    (req->length_fx00 + 1) * sizeof(request_t),
 509			    req->ring_fx00, req->dma_fx00);
 510	} else if (req && req->ring)
 511		dma_free_coherent(&ha->pdev->dev,
 512		(req->length + 1) * sizeof(request_t),
 513		req->ring, req->dma);
 514
 515	if (req)
 516		kfree(req->outstanding_cmds);
 517
 518	kfree(req);
 519}
 520
 521static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
 522{
 523	if (IS_QLAFX00(ha)) {
 524		if (rsp && rsp->ring_fx00)
 525			dma_free_coherent(&ha->pdev->dev,
 526			    (rsp->length_fx00 + 1) * sizeof(request_t),
 527			    rsp->ring_fx00, rsp->dma_fx00);
 528	} else if (rsp && rsp->ring) {
 529		dma_free_coherent(&ha->pdev->dev,
 530		(rsp->length + 1) * sizeof(response_t),
 531		rsp->ring, rsp->dma);
 532	}
 533	kfree(rsp);
 534}
 535
 536static void qla2x00_free_queues(struct qla_hw_data *ha)
 537{
 538	struct req_que *req;
 539	struct rsp_que *rsp;
 540	int cnt;
 541	unsigned long flags;
 542
 543	if (ha->queue_pair_map) {
 544		kfree(ha->queue_pair_map);
 545		ha->queue_pair_map = NULL;
 546	}
 547	if (ha->base_qpair) {
 548		kfree(ha->base_qpair);
 549		ha->base_qpair = NULL;
 550	}
 551
 552	qla_mapq_free_qp_cpu_map(ha);
 553	spin_lock_irqsave(&ha->hardware_lock, flags);
 554	for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
 555		if (!test_bit(cnt, ha->req_qid_map))
 556			continue;
 557
 558		req = ha->req_q_map[cnt];
 559		clear_bit(cnt, ha->req_qid_map);
 560		ha->req_q_map[cnt] = NULL;
 561
 562		spin_unlock_irqrestore(&ha->hardware_lock, flags);
 563		qla2x00_free_req_que(ha, req);
 564		spin_lock_irqsave(&ha->hardware_lock, flags);
 565	}
 566	spin_unlock_irqrestore(&ha->hardware_lock, flags);
 567
 568	kfree(ha->req_q_map);
 569	ha->req_q_map = NULL;
 570
 571
 572	spin_lock_irqsave(&ha->hardware_lock, flags);
 573	for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
 574		if (!test_bit(cnt, ha->rsp_qid_map))
 575			continue;
 576
 577		rsp = ha->rsp_q_map[cnt];
 578		clear_bit(cnt, ha->rsp_qid_map);
 579		ha->rsp_q_map[cnt] =  NULL;
 580		spin_unlock_irqrestore(&ha->hardware_lock, flags);
 581		qla2x00_free_rsp_que(ha, rsp);
 582		spin_lock_irqsave(&ha->hardware_lock, flags);
 583	}
 584	spin_unlock_irqrestore(&ha->hardware_lock, flags);
 585
 586	kfree(ha->rsp_q_map);
 587	ha->rsp_q_map = NULL;
 588}
 589
 590static char *
 591qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
 592{
 593	struct qla_hw_data *ha = vha->hw;
 594	static const char *const pci_bus_modes[] = {
 595		"33", "66", "100", "133",
 596	};
 597	uint16_t pci_bus;
 598
 599	pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
 600	if (pci_bus) {
 601		snprintf(str, str_len, "PCI-X (%s MHz)",
 602			 pci_bus_modes[pci_bus]);
 603	} else {
 604		pci_bus = (ha->pci_attr & BIT_8) >> 8;
 605		snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]);
 606	}
 607
 608	return str;
 609}
 610
 611static char *
 612qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
 613{
 614	static const char *const pci_bus_modes[] = {
 615		"33", "66", "100", "133",
 616	};
 617	struct qla_hw_data *ha = vha->hw;
 618	uint32_t pci_bus;
 619
 620	if (pci_is_pcie(ha->pdev)) {
 621		uint32_t lstat, lspeed, lwidth;
 622		const char *speed_str;
 623
 624		pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
 625		lspeed = FIELD_GET(PCI_EXP_LNKCAP_SLS, lstat);
 626		lwidth = FIELD_GET(PCI_EXP_LNKCAP_MLW, lstat);
 627
 628		switch (lspeed) {
 629		case 1:
 630			speed_str = "2.5GT/s";
 631			break;
 632		case 2:
 633			speed_str = "5.0GT/s";
 634			break;
 635		case 3:
 636			speed_str = "8.0GT/s";
 637			break;
 638		case 4:
 639			speed_str = "16.0GT/s";
 640			break;
 641		default:
 642			speed_str = "<unknown>";
 643			break;
 644		}
 645		snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth);
 646
 647		return str;
 648	}
 649
 650	pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
 651	if (pci_bus == 0 || pci_bus == 8)
 652		snprintf(str, str_len, "PCI (%s MHz)",
 653			 pci_bus_modes[pci_bus >> 3]);
 654	else
 655		snprintf(str, str_len, "PCI-X Mode %d (%s MHz)",
 656			 pci_bus & 4 ? 2 : 1,
 657			 pci_bus_modes[pci_bus & 3]);
 658
 659	return str;
 660}
 661
 662static char *
 663qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
 664{
 665	char un_str[10];
 666	struct qla_hw_data *ha = vha->hw;
 667
 668	snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
 669	    ha->fw_minor_version, ha->fw_subminor_version);
 670
 671	if (ha->fw_attributes & BIT_9) {
 672		strcat(str, "FLX");
 673		return (str);
 674	}
 675
 676	switch (ha->fw_attributes & 0xFF) {
 677	case 0x7:
 678		strcat(str, "EF");
 679		break;
 680	case 0x17:
 681		strcat(str, "TP");
 682		break;
 683	case 0x37:
 684		strcat(str, "IP");
 685		break;
 686	case 0x77:
 687		strcat(str, "VI");
 688		break;
 689	default:
 690		sprintf(un_str, "(%x)", ha->fw_attributes);
 691		strcat(str, un_str);
 692		break;
 693	}
 694	if (ha->fw_attributes & 0x100)
 695		strcat(str, "X");
 696
 697	return (str);
 698}
 699
 700static char *
 701qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
 702{
 703	struct qla_hw_data *ha = vha->hw;
 704
 705	snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
 706	    ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
 707	return str;
 708}
 709
 710void qla2x00_sp_free_dma(srb_t *sp)
 711{
 712	struct qla_hw_data *ha = sp->vha->hw;
 713	struct scsi_cmnd *cmd = GET_CMD_SP(sp);
 714
 715	if (sp->flags & SRB_DMA_VALID) {
 716		scsi_dma_unmap(cmd);
 717		sp->flags &= ~SRB_DMA_VALID;
 718	}
 719
 720	if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
 721		dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
 722		    scsi_prot_sg_count(cmd), cmd->sc_data_direction);
 723		sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
 724	}
 725
 726	if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
 727		/* List assured to be having elements */
 728		qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx);
 729		sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
 730	}
 731
 732	if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
 733		struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
 734
 735		dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
 736		sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
 737	}
 738
 739	if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
 740		struct ct6_dsd *ctx1 = &sp->u.scmd.ct6_ctx;
 741
 742		dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
 743		    ctx1->fcp_cmnd_dma);
 744		list_splice(&ctx1->dsd_list, &sp->qpair->dsd_list);
 745		sp->qpair->dsd_inuse -= ctx1->dsd_use_cnt;
 746		sp->qpair->dsd_avail += ctx1->dsd_use_cnt;
 747	}
 748
 749	if (sp->flags & SRB_GOT_BUF)
 750		qla_put_buf(sp->qpair, &sp->u.scmd.buf_dsc);
 751}
 752
 753void qla2x00_sp_compl(srb_t *sp, int res)
 754{
 755	struct scsi_cmnd *cmd = GET_CMD_SP(sp);
 756	struct completion *comp = sp->comp;
 757
 758	/* kref: INIT */
 759	kref_put(&sp->cmd_kref, qla2x00_sp_release);
 760	cmd->result = res;
 761	sp->type = 0;
 762	scsi_done(cmd);
 763	if (comp)
 764		complete(comp);
 765}
 766
 767void qla2xxx_qpair_sp_free_dma(srb_t *sp)
 768{
 769	struct scsi_cmnd *cmd = GET_CMD_SP(sp);
 770	struct qla_hw_data *ha = sp->fcport->vha->hw;
 771
 772	if (sp->flags & SRB_DMA_VALID) {
 773		scsi_dma_unmap(cmd);
 774		sp->flags &= ~SRB_DMA_VALID;
 775	}
 776
 777	if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
 778		dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
 779		    scsi_prot_sg_count(cmd), cmd->sc_data_direction);
 780		sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
 781	}
 782
 783	if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
 784		/* List assured to be having elements */
 785		qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx);
 786		sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
 787	}
 788
 789	if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) {
 790		struct crc_context *difctx = sp->u.scmd.crc_ctx;
 791		struct dsd_dma *dif_dsd, *nxt_dsd;
 792
 793		list_for_each_entry_safe(dif_dsd, nxt_dsd,
 794		    &difctx->ldif_dma_hndl_list, list) {
 795			list_del(&dif_dsd->list);
 796			dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr,
 797			    dif_dsd->dsd_list_dma);
 798			kfree(dif_dsd);
 799			difctx->no_dif_bundl--;
 800		}
 801
 802		list_for_each_entry_safe(dif_dsd, nxt_dsd,
 803		    &difctx->ldif_dsd_list, list) {
 804			list_del(&dif_dsd->list);
 805			dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr,
 806			    dif_dsd->dsd_list_dma);
 807			kfree(dif_dsd);
 808			difctx->no_ldif_dsd--;
 809		}
 810
 811		if (difctx->no_ldif_dsd) {
 812			ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
 813			    "%s: difctx->no_ldif_dsd=%x\n",
 814			    __func__, difctx->no_ldif_dsd);
 815		}
 816
 817		if (difctx->no_dif_bundl) {
 818			ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
 819			    "%s: difctx->no_dif_bundl=%x\n",
 820			    __func__, difctx->no_dif_bundl);
 821		}
 822		sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID;
 823	}
 824
 825	if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
 826		struct ct6_dsd *ctx1 = &sp->u.scmd.ct6_ctx;
 827
 828		dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
 829		    ctx1->fcp_cmnd_dma);
 830		list_splice(&ctx1->dsd_list, &sp->qpair->dsd_list);
 831		sp->qpair->dsd_inuse -= ctx1->dsd_use_cnt;
 832		sp->qpair->dsd_avail += ctx1->dsd_use_cnt;
 833		sp->flags &= ~SRB_FCP_CMND_DMA_VALID;
 834	}
 835
 836	if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
 837		struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
 838
 839		dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
 840		sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
 841	}
 842
 843	if (sp->flags & SRB_GOT_BUF)
 844		qla_put_buf(sp->qpair, &sp->u.scmd.buf_dsc);
 845}
 846
 847void qla2xxx_qpair_sp_compl(srb_t *sp, int res)
 848{
 849	struct scsi_cmnd *cmd = GET_CMD_SP(sp);
 850	struct completion *comp = sp->comp;
 851
 852	/* ref: INIT */
 853	kref_put(&sp->cmd_kref, qla2x00_sp_release);
 854	cmd->result = res;
 855	sp->type = 0;
 856	scsi_done(cmd);
 857	if (comp)
 858		complete(comp);
 859}
 860
 861static int
 862qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
 863{
 864	scsi_qla_host_t *vha = shost_priv(host);
 865	fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
 866	struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
 867	struct qla_hw_data *ha = vha->hw;
 868	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
 869	srb_t *sp;
 870	int rval;
 871
 872	if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) ||
 873	    WARN_ON_ONCE(!rport)) {
 874		cmd->result = DID_NO_CONNECT << 16;
 875		goto qc24_fail_command;
 876	}
 877
 878	if (ha->mqenable) {
 879		uint32_t tag;
 880		uint16_t hwq;
 881		struct qla_qpair *qpair = NULL;
 882
 883		tag = blk_mq_unique_tag(scsi_cmd_to_rq(cmd));
 884		hwq = blk_mq_unique_tag_to_hwq(tag);
 885		qpair = ha->queue_pair_map[hwq];
 886
 887		if (qpair)
 888			return qla2xxx_mqueuecommand(host, cmd, qpair);
 889	}
 890
 891	if (ha->flags.eeh_busy) {
 892		if (ha->flags.pci_channel_io_perm_failure) {
 893			ql_dbg(ql_dbg_aer, vha, 0x9010,
 894			    "PCI Channel IO permanent failure, exiting "
 895			    "cmd=%p.\n", cmd);
 896			cmd->result = DID_NO_CONNECT << 16;
 897		} else {
 898			ql_dbg(ql_dbg_aer, vha, 0x9011,
 899			    "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
 900			cmd->result = DID_REQUEUE << 16;
 901		}
 902		goto qc24_fail_command;
 903	}
 904
 905	rval = fc_remote_port_chkready(rport);
 906	if (rval) {
 907		cmd->result = rval;
 908		ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
 909		    "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
 910		    cmd, rval);
 911		goto qc24_fail_command;
 912	}
 913
 914	if (!vha->flags.difdix_supported &&
 915		scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
 916			ql_dbg(ql_dbg_io, vha, 0x3004,
 917			    "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
 918			    cmd);
 919			cmd->result = DID_NO_CONNECT << 16;
 920			goto qc24_fail_command;
 921	}
 922
 923	if (!fcport || fcport->deleted) {
 924		cmd->result = DID_IMM_RETRY << 16;
 925		goto qc24_fail_command;
 926	}
 927
 928	if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) {
 929		if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
 930			atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
 931			ql_dbg(ql_dbg_io, vha, 0x3005,
 932			    "Returning DNC, fcport_state=%d loop_state=%d.\n",
 933			    atomic_read(&fcport->state),
 934			    atomic_read(&base_vha->loop_state));
 935			cmd->result = DID_NO_CONNECT << 16;
 936			goto qc24_fail_command;
 937		}
 938		goto qc24_target_busy;
 939	}
 940
 941	/*
 942	 * Return target busy if we've received a non-zero retry_delay_timer
 943	 * in a FCP_RSP.
 944	 */
 945	if (fcport->retry_delay_timestamp == 0) {
 946		/* retry delay not set */
 947	} else if (time_after(jiffies, fcport->retry_delay_timestamp))
 948		fcport->retry_delay_timestamp = 0;
 949	else
 950		goto qc24_target_busy;
 951
 952	sp = scsi_cmd_priv(cmd);
 953	/* ref: INIT */
 954	qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport);
 955
 956	sp->u.scmd.cmd = cmd;
 957	sp->type = SRB_SCSI_CMD;
 958	sp->free = qla2x00_sp_free_dma;
 959	sp->done = qla2x00_sp_compl;
 960
 961	rval = ha->isp_ops->start_scsi(sp);
 962	if (rval != QLA_SUCCESS) {
 963		ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
 964		    "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
 965		goto qc24_host_busy_free_sp;
 966	}
 967
 968	return 0;
 969
 970qc24_host_busy_free_sp:
 971	/* ref: INIT */
 972	kref_put(&sp->cmd_kref, qla2x00_sp_release);
 973
 974qc24_target_busy:
 975	return SCSI_MLQUEUE_TARGET_BUSY;
 976
 977qc24_fail_command:
 978	scsi_done(cmd);
 979
 980	return 0;
 981}
 982
 983/* For MQ supported I/O */
 984int
 985qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
 986    struct qla_qpair *qpair)
 987{
 988	scsi_qla_host_t *vha = shost_priv(host);
 989	fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
 990	struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
 991	struct qla_hw_data *ha = vha->hw;
 992	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
 993	srb_t *sp;
 994	int rval;
 995
 996	rval = rport ? fc_remote_port_chkready(rport) : (DID_NO_CONNECT << 16);
 997	if (rval) {
 998		cmd->result = rval;
 999		ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
1000		    "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
1001		    cmd, rval);
1002		goto qc24_fail_command;
1003	}
1004
1005	if (!qpair->online) {
1006		ql_dbg(ql_dbg_io, vha, 0x3077,
1007		       "qpair not online. eeh_busy=%d.\n", ha->flags.eeh_busy);
1008		cmd->result = DID_NO_CONNECT << 16;
1009		goto qc24_fail_command;
1010	}
1011
1012	if (!fcport || fcport->deleted) {
1013		cmd->result = DID_IMM_RETRY << 16;
1014		goto qc24_fail_command;
1015	}
1016
1017	if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) {
1018		if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
1019			atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
1020			ql_dbg(ql_dbg_io, vha, 0x3077,
1021			    "Returning DNC, fcport_state=%d loop_state=%d.\n",
1022			    atomic_read(&fcport->state),
1023			    atomic_read(&base_vha->loop_state));
1024			cmd->result = DID_NO_CONNECT << 16;
1025			goto qc24_fail_command;
1026		}
1027		goto qc24_target_busy;
1028	}
1029
1030	/*
1031	 * Return target busy if we've received a non-zero retry_delay_timer
1032	 * in a FCP_RSP.
1033	 */
1034	if (fcport->retry_delay_timestamp == 0) {
1035		/* retry delay not set */
1036	} else if (time_after(jiffies, fcport->retry_delay_timestamp))
1037		fcport->retry_delay_timestamp = 0;
1038	else
1039		goto qc24_target_busy;
1040
1041	sp = scsi_cmd_priv(cmd);
1042	/* ref: INIT */
1043	qla2xxx_init_sp(sp, vha, qpair, fcport);
1044
1045	sp->u.scmd.cmd = cmd;
1046	sp->type = SRB_SCSI_CMD;
1047	sp->free = qla2xxx_qpair_sp_free_dma;
1048	sp->done = qla2xxx_qpair_sp_compl;
1049
1050	rval = ha->isp_ops->start_scsi_mq(sp);
1051	if (rval != QLA_SUCCESS) {
1052		ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1053		    "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
1054		goto qc24_host_busy_free_sp;
1055	}
1056
1057	return 0;
1058
1059qc24_host_busy_free_sp:
1060	/* ref: INIT */
1061	kref_put(&sp->cmd_kref, qla2x00_sp_release);
1062
1063qc24_target_busy:
1064	return SCSI_MLQUEUE_TARGET_BUSY;
1065
1066qc24_fail_command:
1067	scsi_done(cmd);
1068
1069	return 0;
1070}
1071
1072/*
1073 * qla2x00_wait_for_hba_online
1074 *    Wait till the HBA is online after going through
1075 *    <= MAX_RETRIES_OF_ISP_ABORT  or
1076 *    finally HBA is disabled ie marked offline
1077 *
1078 * Input:
1079 *     ha - pointer to host adapter structure
1080 *
1081 * Note:
1082 *    Does context switching-Release SPIN_LOCK
1083 *    (if any) before calling this routine.
1084 *
1085 * Return:
1086 *    Success (Adapter is online) : 0
1087 *    Failed  (Adapter is offline/disabled) : 1
1088 */
1089int
1090qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1091{
1092	int		return_status;
1093	unsigned long	wait_online;
1094	struct qla_hw_data *ha = vha->hw;
1095	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1096
1097	wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1098	while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1099	    test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1100	    test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1101	    ha->dpc_active) && time_before(jiffies, wait_online)) {
1102
1103		msleep(1000);
1104	}
1105	if (base_vha->flags.online)
1106		return_status = QLA_SUCCESS;
1107	else
1108		return_status = QLA_FUNCTION_FAILED;
1109
1110	return (return_status);
1111}
1112
1113static inline int test_fcport_count(scsi_qla_host_t *vha)
1114{
1115	struct qla_hw_data *ha = vha->hw;
1116	unsigned long flags;
1117	int res;
1118	/* Return 0 = sleep, x=wake */
1119
1120	spin_lock_irqsave(&ha->tgt.sess_lock, flags);
1121	ql_dbg(ql_dbg_init, vha, 0x00ec,
1122	    "tgt %p, fcport_count=%d\n",
1123	    vha, vha->fcport_count);
1124	res = (vha->fcport_count == 0);
1125	if  (res) {
1126		struct fc_port *fcport;
1127
1128		list_for_each_entry(fcport, &vha->vp_fcports, list) {
1129			if (fcport->deleted != QLA_SESS_DELETED) {
1130				/* session(s) may not be fully logged in
1131				 * (ie fcport_count=0), but session
1132				 * deletion thread(s) may be inflight.
1133				 */
1134
1135				res = 0;
1136				break;
1137			}
1138		}
1139	}
1140	spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1141
1142	return res;
1143}
1144
1145/*
1146 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1147 * it has dependency on UNLOADING flag to stop device discovery
1148 */
1149void
1150qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1151{
1152	u8 i;
1153
1154	qla2x00_mark_all_devices_lost(vha);
1155
1156	for (i = 0; i < 10; i++) {
1157		if (wait_event_timeout(vha->fcport_waitQ,
1158		    test_fcport_count(vha), HZ) > 0)
1159			break;
1160	}
1161
1162	flush_workqueue(vha->hw->wq);
1163}
1164
1165/*
1166 * qla2x00_wait_for_hba_ready
1167 * Wait till the HBA is ready before doing driver unload
1168 *
1169 * Input:
1170 *     ha - pointer to host adapter structure
1171 *
1172 * Note:
1173 *    Does context switching-Release SPIN_LOCK
1174 *    (if any) before calling this routine.
1175 *
1176 */
1177static void
1178qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
1179{
1180	struct qla_hw_data *ha = vha->hw;
1181	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1182
1183	while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1184		ha->flags.mbox_busy) ||
1185	       test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1186	       test_bit(FX00_TARGET_SCAN, &vha->dpc_flags) ||
1187	       (vha->scan.scan_flags & SF_SCANNING)) {
1188		if (test_bit(UNLOADING, &base_vha->dpc_flags))
1189			break;
1190		msleep(1000);
1191	}
1192}
1193
1194int
1195qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1196{
1197	int		return_status;
1198	unsigned long	wait_reset;
1199	struct qla_hw_data *ha = vha->hw;
1200	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1201
1202	wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1203	while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1204	    test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1205	    test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1206	    ha->dpc_active) && time_before(jiffies, wait_reset)) {
1207
1208		msleep(1000);
1209
1210		if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1211		    ha->flags.chip_reset_done)
1212			break;
1213	}
1214	if (ha->flags.chip_reset_done)
1215		return_status = QLA_SUCCESS;
1216	else
1217		return_status = QLA_FUNCTION_FAILED;
1218
1219	return return_status;
1220}
1221
1222/**************************************************************************
1223* qla2xxx_eh_abort
1224*
1225* Description:
1226*    The abort function will abort the specified command.
1227*
1228* Input:
1229*    cmd = Linux SCSI command packet to be aborted.
1230*
1231* Returns:
1232*    Either SUCCESS or FAILED.
1233*
1234* Note:
1235*    Only return FAILED if command not returned by firmware.
1236**************************************************************************/
1237static int
1238qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1239{
1240	scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1241	DECLARE_COMPLETION_ONSTACK(comp);
1242	srb_t *sp;
1243	int ret;
1244	unsigned int id;
1245	uint64_t lun;
1246	int rval;
1247	struct qla_hw_data *ha = vha->hw;
1248	uint32_t ratov_j;
1249	struct qla_qpair *qpair;
1250	unsigned long flags;
1251	int fast_fail_status = SUCCESS;
1252
1253	if (qla2x00_isp_reg_stat(ha)) {
1254		ql_log(ql_log_info, vha, 0x8042,
1255		    "PCI/Register disconnect, exiting.\n");
1256		qla_pci_set_eeh_busy(vha);
1257		return FAILED;
1258	}
1259
1260	/* Save any FAST_IO_FAIL value to return later if abort succeeds */
1261	ret = fc_block_scsi_eh(cmd);
1262	if (ret != 0)
1263		fast_fail_status = ret;
1264
1265	sp = scsi_cmd_priv(cmd);
1266	qpair = sp->qpair;
1267
1268	vha->cmd_timeout_cnt++;
1269
1270	if ((sp->fcport && sp->fcport->deleted) || !qpair)
1271		return fast_fail_status != SUCCESS ? fast_fail_status : FAILED;
1272
1273	spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1274	sp->comp = &comp;
1275	spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1276
1277
1278	id = cmd->device->id;
1279	lun = cmd->device->lun;
1280
1281	ql_dbg(ql_dbg_taskm, vha, 0x8002,
1282	    "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1283	    vha->host_no, id, lun, sp, cmd, sp->handle);
1284
1285	/*
1286	 * Abort will release the original Command/sp from FW. Let the
1287	 * original command call scsi_done. In return, he will wakeup
1288	 * this sleeping thread.
1289	 */
1290	rval = ha->isp_ops->abort_command(sp);
1291
1292	ql_dbg(ql_dbg_taskm, vha, 0x8003,
1293	       "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval);
1294
1295	/* Wait for the command completion. */
1296	ratov_j = ha->r_a_tov / 10 * 4;
1297	ratov_j = secs_to_jiffies(ratov_j);
1298	switch (rval) {
1299	case QLA_SUCCESS:
1300		if (!wait_for_completion_timeout(&comp, ratov_j)) {
1301			ql_dbg(ql_dbg_taskm, vha, 0xffff,
1302			    "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
1303			    __func__, ha->r_a_tov/10);
1304			ret = FAILED;
1305		} else {
1306			ret = fast_fail_status;
1307		}
1308		break;
1309	default:
1310		ret = FAILED;
1311		break;
1312	}
1313
1314	sp->comp = NULL;
1315
1316	ql_log(ql_log_info, vha, 0x801c,
1317	    "Abort command issued nexus=%ld:%d:%llu -- %x.\n",
1318	    vha->host_no, id, lun, ret);
1319
1320	return ret;
1321}
1322
1323#define ABORT_POLLING_PERIOD	1000
1324#define ABORT_WAIT_ITER		((2 * 1000) / (ABORT_POLLING_PERIOD))
1325
1326/*
1327 * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED.
1328 */
1329static int
1330__qla2x00_eh_wait_for_pending_commands(struct qla_qpair *qpair, unsigned int t,
1331				       uint64_t l, enum nexus_wait_type type)
1332{
1333	int cnt, match, status;
1334	unsigned long flags;
1335	scsi_qla_host_t *vha = qpair->vha;
1336	struct req_que *req = qpair->req;
1337	srb_t *sp;
1338	struct scsi_cmnd *cmd;
1339	unsigned long wait_iter = ABORT_WAIT_ITER;
1340	bool found;
1341	struct qla_hw_data *ha = vha->hw;
1342
1343	status = QLA_SUCCESS;
1344
1345	while (wait_iter--) {
1346		found = false;
1347
1348		spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1349		for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1350			sp = req->outstanding_cmds[cnt];
1351			if (!sp)
1352				continue;
1353			if (sp->type != SRB_SCSI_CMD)
1354				continue;
1355			if (vha->vp_idx != sp->vha->vp_idx)
1356				continue;
1357			match = 0;
1358			cmd = GET_CMD_SP(sp);
1359			switch (type) {
1360			case WAIT_HOST:
1361				match = 1;
1362				break;
1363			case WAIT_TARGET:
1364				if (sp->fcport)
1365					match = sp->fcport->d_id.b24 == t;
1366				else
1367					match = 0;
1368				break;
1369			case WAIT_LUN:
1370				if (sp->fcport)
1371					match = (sp->fcport->d_id.b24 == t &&
1372						cmd->device->lun == l);
1373				else
1374					match = 0;
1375				break;
1376			}
1377			if (!match)
1378				continue;
1379
1380			spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1381
1382			if (unlikely(pci_channel_offline(ha->pdev)) ||
1383			    ha->flags.eeh_busy) {
1384				ql_dbg(ql_dbg_taskm, vha, 0x8005,
1385				    "Return:eh_wait.\n");
1386				return status;
1387			}
1388
1389			/*
1390			 * SRB_SCSI_CMD is still in the outstanding_cmds array.
1391			 * it means scsi_done has not called. Wait for it to
1392			 * clear from outstanding_cmds.
1393			 */
1394			msleep(ABORT_POLLING_PERIOD);
1395			spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1396			found = true;
1397		}
1398		spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1399
1400		if (!found)
1401			break;
1402	}
1403
1404	if (wait_iter == -1)
1405		status = QLA_FUNCTION_FAILED;
1406
1407	return status;
1408}
1409
1410int
1411qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
1412				     uint64_t l, enum nexus_wait_type type)
1413{
1414	struct qla_qpair *qpair;
1415	struct qla_hw_data *ha = vha->hw;
1416	int i, status = QLA_SUCCESS;
1417
1418	status = __qla2x00_eh_wait_for_pending_commands(ha->base_qpair, t, l,
1419							type);
1420	for (i = 0; status == QLA_SUCCESS && i < ha->max_qpairs; i++) {
1421		qpair = ha->queue_pair_map[i];
1422		if (!qpair)
1423			continue;
1424		status = __qla2x00_eh_wait_for_pending_commands(qpair, t, l,
1425								type);
1426	}
1427	return status;
1428}
1429
1430static char *reset_errors[] = {
1431	"HBA not online",
1432	"HBA not ready",
1433	"Task management failed",
1434	"Waiting for command completions",
1435};
1436
1437static int
1438qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1439{
1440	struct scsi_device *sdev = cmd->device;
1441	scsi_qla_host_t *vha = shost_priv(sdev->host);
1442	struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1443	fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1444	struct qla_hw_data *ha = vha->hw;
1445	int err;
1446
1447	if (qla2x00_isp_reg_stat(ha)) {
1448		ql_log(ql_log_info, vha, 0x803e,
1449		    "PCI/Register disconnect, exiting.\n");
1450		qla_pci_set_eeh_busy(vha);
1451		return FAILED;
1452	}
1453
1454	if (!fcport) {
1455		return FAILED;
1456	}
1457
1458	err = fc_block_rport(rport);
1459	if (err != 0)
1460		return err;
1461
1462	if (fcport->deleted)
1463		return FAILED;
1464
1465	ql_log(ql_log_info, vha, 0x8009,
1466	    "DEVICE RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", vha->host_no,
1467	    sdev->id, sdev->lun, cmd);
1468
1469	err = 0;
1470	if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1471		ql_log(ql_log_warn, vha, 0x800a,
1472		    "Wait for hba online failed for cmd=%p.\n", cmd);
1473		goto eh_reset_failed;
1474	}
1475	err = 2;
1476	if (ha->isp_ops->lun_reset(fcport, sdev->lun, 1)
1477		!= QLA_SUCCESS) {
1478		ql_log(ql_log_warn, vha, 0x800c,
1479		    "do_reset failed for cmd=%p.\n", cmd);
1480		goto eh_reset_failed;
1481	}
1482	err = 3;
1483	if (qla2x00_eh_wait_for_pending_commands(vha, fcport->d_id.b24,
1484						 cmd->device->lun,
1485						 WAIT_LUN) != QLA_SUCCESS) {
1486		ql_log(ql_log_warn, vha, 0x800d,
1487		    "wait for pending cmds failed for cmd=%p.\n", cmd);
1488		goto eh_reset_failed;
1489	}
1490
1491	ql_log(ql_log_info, vha, 0x800e,
1492	    "DEVICE RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n",
1493	    vha->host_no, sdev->id, sdev->lun, cmd);
1494
1495	return SUCCESS;
1496
1497eh_reset_failed:
1498	ql_log(ql_log_info, vha, 0x800f,
1499	    "DEVICE RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n",
1500	    reset_errors[err], vha->host_no, sdev->id, sdev->lun,
1501	    cmd);
1502	vha->reset_cmd_err_cnt++;
1503	return FAILED;
1504}
1505
1506static int
1507qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1508{
1509	struct scsi_device *sdev = cmd->device;
1510	struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1511	scsi_qla_host_t *vha = shost_priv(rport_to_shost(rport));
1512	struct qla_hw_data *ha = vha->hw;
1513	fc_port_t *fcport = *(fc_port_t **)rport->dd_data;
1514	int err;
1515
1516	if (qla2x00_isp_reg_stat(ha)) {
1517		ql_log(ql_log_info, vha, 0x803f,
1518		    "PCI/Register disconnect, exiting.\n");
1519		qla_pci_set_eeh_busy(vha);
1520		return FAILED;
1521	}
1522
1523	if (!fcport) {
1524		return FAILED;
1525	}
1526
1527	err = fc_block_rport(rport);
1528	if (err != 0)
1529		return err;
1530
1531	if (fcport->deleted)
1532		return FAILED;
1533
1534	ql_log(ql_log_info, vha, 0x8009,
1535	    "TARGET RESET ISSUED nexus=%ld:%d cmd=%p.\n", vha->host_no,
1536	    sdev->id, cmd);
1537
1538	err = 0;
1539	if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1540		ql_log(ql_log_warn, vha, 0x800a,
1541		    "Wait for hba online failed for cmd=%p.\n", cmd);
1542		goto eh_reset_failed;
1543	}
1544	err = 2;
1545	if (ha->isp_ops->target_reset(fcport, 0, 0) != QLA_SUCCESS) {
1546		ql_log(ql_log_warn, vha, 0x800c,
1547		    "target_reset failed for cmd=%p.\n", cmd);
1548		goto eh_reset_failed;
1549	}
1550	err = 3;
1551	if (qla2x00_eh_wait_for_pending_commands(vha, fcport->d_id.b24, 0,
1552						 WAIT_TARGET) != QLA_SUCCESS) {
1553		ql_log(ql_log_warn, vha, 0x800d,
1554		    "wait for pending cmds failed for cmd=%p.\n", cmd);
1555		goto eh_reset_failed;
1556	}
1557
1558	ql_log(ql_log_info, vha, 0x800e,
1559	    "TARGET RESET SUCCEEDED nexus:%ld:%d cmd=%p.\n",
1560	    vha->host_no, sdev->id, cmd);
1561
1562	return SUCCESS;
1563
1564eh_reset_failed:
1565	ql_log(ql_log_info, vha, 0x800f,
1566	    "TARGET RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n",
1567	    reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1568	    cmd);
1569	vha->reset_cmd_err_cnt++;
1570	return FAILED;
1571}
1572
1573/**************************************************************************
1574* qla2xxx_eh_bus_reset
1575*
1576* Description:
1577*    The bus reset function will reset the bus and abort any executing
1578*    commands.
1579*
1580* Input:
1581*    cmd = Linux SCSI command packet of the command that cause the
1582*          bus reset.
1583*
1584* Returns:
1585*    SUCCESS/FAILURE (defined as macro in scsi.h).
1586*
1587**************************************************************************/
1588static int
1589qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1590{
1591	scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1592	int ret = FAILED;
1593	unsigned int id;
1594	uint64_t lun;
1595	struct qla_hw_data *ha = vha->hw;
1596
1597	if (qla2x00_isp_reg_stat(ha)) {
1598		ql_log(ql_log_info, vha, 0x8040,
1599		    "PCI/Register disconnect, exiting.\n");
1600		qla_pci_set_eeh_busy(vha);
1601		return FAILED;
1602	}
1603
1604	id = cmd->device->id;
1605	lun = cmd->device->lun;
1606
1607	if (qla2x00_chip_is_down(vha))
1608		return ret;
1609
1610	ql_log(ql_log_info, vha, 0x8012,
1611	    "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1612
1613	if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1614		ql_log(ql_log_fatal, vha, 0x8013,
1615		    "Wait for hba online failed board disabled.\n");
1616		goto eh_bus_reset_done;
1617	}
1618
1619	if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1620		ret = SUCCESS;
1621
1622	if (ret == FAILED)
1623		goto eh_bus_reset_done;
1624
1625	/* Flush outstanding commands. */
1626	if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
1627	    QLA_SUCCESS) {
1628		ql_log(ql_log_warn, vha, 0x8014,
1629		    "Wait for pending commands failed.\n");
1630		ret = FAILED;
1631	}
1632
1633eh_bus_reset_done:
1634	ql_log(ql_log_warn, vha, 0x802b,
1635	    "BUS RESET %s nexus=%ld:%d:%llu.\n",
1636	    (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1637
1638	return ret;
1639}
1640
1641/**************************************************************************
1642* qla2xxx_eh_host_reset
1643*
1644* Description:
1645*    The reset function will reset the Adapter.
1646*
1647* Input:
1648*      cmd = Linux SCSI command packet of the command that cause the
1649*            adapter reset.
1650*
1651* Returns:
1652*      Either SUCCESS or FAILED.
1653*
1654* Note:
1655**************************************************************************/
1656static int
1657qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1658{
1659	scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1660	struct qla_hw_data *ha = vha->hw;
1661	int ret = FAILED;
1662	unsigned int id;
1663	uint64_t lun;
1664	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1665
1666	if (qla2x00_isp_reg_stat(ha)) {
1667		ql_log(ql_log_info, vha, 0x8041,
1668		    "PCI/Register disconnect, exiting.\n");
1669		qla_pci_set_eeh_busy(vha);
1670		return SUCCESS;
1671	}
1672
1673	id = cmd->device->id;
1674	lun = cmd->device->lun;
1675
1676	ql_log(ql_log_info, vha, 0x8018,
1677	    "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1678
1679	/*
1680	 * No point in issuing another reset if one is active.  Also do not
1681	 * attempt a reset if we are updating flash.
1682	 */
1683	if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
1684		goto eh_host_reset_lock;
1685
1686	if (vha != base_vha) {
1687		if (qla2x00_vp_abort_isp(vha))
1688			goto eh_host_reset_lock;
1689	} else {
1690		if (IS_P3P_TYPE(vha->hw)) {
1691			if (!qla82xx_fcoe_ctx_reset(vha)) {
1692				/* Ctx reset success */
1693				ret = SUCCESS;
1694				goto eh_host_reset_lock;
1695			}
1696			/* fall thru if ctx reset failed */
1697		}
1698		if (ha->wq)
1699			flush_workqueue(ha->wq);
1700
1701		set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1702		if (ha->isp_ops->abort_isp(base_vha)) {
1703			clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1704			/* failed. schedule dpc to try */
1705			set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1706
1707			if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1708				ql_log(ql_log_warn, vha, 0x802a,
1709				    "wait for hba online failed.\n");
1710				goto eh_host_reset_lock;
1711			}
1712		}
1713		clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1714	}
1715
1716	/* Waiting for command to be returned to OS.*/
1717	if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
1718		QLA_SUCCESS)
1719		ret = SUCCESS;
1720
1721eh_host_reset_lock:
1722	ql_log(ql_log_info, vha, 0x8017,
1723	    "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
1724	    (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1725
1726	return ret;
1727}
1728
1729/*
1730* qla2x00_loop_reset
1731*      Issue loop reset.
1732*
1733* Input:
1734*      ha = adapter block pointer.
1735*
1736* Returns:
1737*      0 = success
1738*/
1739int
1740qla2x00_loop_reset(scsi_qla_host_t *vha)
1741{
1742	int ret;
1743	struct qla_hw_data *ha = vha->hw;
1744
1745	if (IS_QLAFX00(ha))
1746		return QLA_SUCCESS;
1747
1748	if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
1749		atomic_set(&vha->loop_state, LOOP_DOWN);
1750		atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1751		qla2x00_mark_all_devices_lost(vha);
1752		ret = qla2x00_full_login_lip(vha);
1753		if (ret != QLA_SUCCESS) {
1754			ql_dbg(ql_dbg_taskm, vha, 0x802d,
1755			    "full_login_lip=%d.\n", ret);
1756		}
1757	}
1758
1759	if (ha->flags.enable_lip_reset) {
1760		ret = qla2x00_lip_reset(vha);
1761		if (ret != QLA_SUCCESS)
1762			ql_dbg(ql_dbg_taskm, vha, 0x802e,
1763			    "lip_reset failed (%d).\n", ret);
1764	}
1765
1766	/* Issue marker command only when we are going to start the I/O */
1767	vha->marker_needed = 1;
1768
1769	return QLA_SUCCESS;
1770}
1771
1772/*
1773 * The caller must ensure that no completion interrupts will happen
1774 * while this function is in progress.
1775 */
1776static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res,
1777			      unsigned long *flags)
1778	__releases(qp->qp_lock_ptr)
1779	__acquires(qp->qp_lock_ptr)
1780{
1781	DECLARE_COMPLETION_ONSTACK(comp);
1782	scsi_qla_host_t *vha = qp->vha;
1783	struct qla_hw_data *ha = vha->hw;
1784	struct scsi_cmnd *cmd = GET_CMD_SP(sp);
1785	int rval;
1786	bool ret_cmd;
1787	uint32_t ratov_j;
1788
1789	lockdep_assert_held(qp->qp_lock_ptr);
1790
1791	if (qla2x00_chip_is_down(vha)) {
1792		sp->done(sp, res);
1793		return;
1794	}
1795
1796	if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS ||
1797	    (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy &&
1798	     !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
1799	     !qla2x00_isp_reg_stat(ha))) {
1800		if (sp->comp) {
1801			sp->done(sp, res);
1802			return;
1803		}
1804
1805		sp->comp = &comp;
1806		spin_unlock_irqrestore(qp->qp_lock_ptr, *flags);
1807
1808		rval = ha->isp_ops->abort_command(sp);
1809		/* Wait for command completion. */
1810		ret_cmd = false;
1811		ratov_j = ha->r_a_tov / 10 * 4;
1812		ratov_j = secs_to_jiffies(ratov_j);
1813		switch (rval) {
1814		case QLA_SUCCESS:
1815			if (wait_for_completion_timeout(&comp, ratov_j)) {
1816				ql_dbg(ql_dbg_taskm, vha, 0xffff,
1817				    "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
1818				    __func__, ha->r_a_tov/10);
1819				ret_cmd = true;
1820			}
1821			/* else FW return SP to driver */
1822			break;
1823		default:
1824			ret_cmd = true;
1825			break;
1826		}
1827
1828		spin_lock_irqsave(qp->qp_lock_ptr, *flags);
1829		switch (sp->type) {
1830		case SRB_SCSI_CMD:
1831			if (ret_cmd && blk_mq_request_started(scsi_cmd_to_rq(cmd)))
1832				sp->done(sp, res);
1833			break;
1834		default:
1835			if (ret_cmd)
1836				sp->done(sp, res);
1837			break;
1838		}
1839	} else {
1840		sp->done(sp, res);
1841	}
1842}
1843
1844/*
1845 * The caller must ensure that no completion interrupts will happen
1846 * while this function is in progress.
1847 */
1848static void
1849__qla2x00_abort_all_cmds(struct qla_qpair *qp, int res)
1850{
1851	int cnt;
1852	unsigned long flags;
1853	srb_t *sp;
1854	scsi_qla_host_t *vha = qp->vha;
1855	struct qla_hw_data *ha = vha->hw;
1856	struct req_que *req;
1857	struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1858	struct qla_tgt_cmd *cmd;
1859
1860	if (!ha->req_q_map)
1861		return;
1862	spin_lock_irqsave(qp->qp_lock_ptr, flags);
1863	req = qp->req;
1864	for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1865		sp = req->outstanding_cmds[cnt];
1866		if (sp) {
1867			switch (sp->cmd_type) {
1868			case TYPE_SRB:
1869				qla2x00_abort_srb(qp, sp, res, &flags);
1870				break;
1871			case TYPE_TGT_CMD:
1872				if (!vha->hw->tgt.tgt_ops || !tgt ||
1873				    qla_ini_mode_enabled(vha)) {
1874					ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003,
1875					    "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1876					    vha->dpc_flags);
1877					continue;
1878				}
1879				cmd = (struct qla_tgt_cmd *)sp;
1880
1881				if (cmd->sg_mapped)
1882					qlt_unmap_sg(vha, cmd);
1883
1884				if (cmd->state == QLA_TGT_STATE_NEED_DATA) {
1885					cmd->aborted = 1;
1886					cmd->write_data_transferred = 0;
1887					cmd->state = QLA_TGT_STATE_DATA_IN;
1888					ha->tgt.tgt_ops->handle_data(cmd);
1889				} else {
1890					ha->tgt.tgt_ops->free_cmd(cmd);
1891				}
1892				break;
1893			case TYPE_TGT_TMCMD:
1894				/*
1895				 * Currently, only ABTS response gets on the
1896				 * outstanding_cmds[]
1897				 */
1898				qlt_free_ul_mcmd(ha,
1899					(struct qla_tgt_mgmt_cmd *) sp);
1900				break;
1901			default:
1902				break;
1903			}
1904			req->outstanding_cmds[cnt] = NULL;
1905		}
1906	}
1907	spin_unlock_irqrestore(qp->qp_lock_ptr, flags);
1908}
1909
1910/*
1911 * The caller must ensure that no completion interrupts will happen
1912 * while this function is in progress.
1913 */
1914void
1915qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1916{
1917	int que;
1918	struct qla_hw_data *ha = vha->hw;
1919
1920	/* Continue only if initialization complete. */
1921	if (!ha->base_qpair)
1922		return;
1923	__qla2x00_abort_all_cmds(ha->base_qpair, res);
1924
1925	if (!ha->queue_pair_map)
1926		return;
1927	for (que = 0; que < ha->max_qpairs; que++) {
1928		if (!ha->queue_pair_map[que])
1929			continue;
1930
1931		__qla2x00_abort_all_cmds(ha->queue_pair_map[que], res);
1932	}
1933}
1934
1935static int
1936qla2xxx_sdev_init(struct scsi_device *sdev)
1937{
1938	struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1939
1940	if (!rport || fc_remote_port_chkready(rport))
1941		return -ENXIO;
1942
1943	sdev->hostdata = *(fc_port_t **)rport->dd_data;
1944
1945	return 0;
1946}
1947
1948static int
1949qla2xxx_sdev_configure(struct scsi_device *sdev, struct queue_limits *lim)
1950{
1951	scsi_qla_host_t *vha = shost_priv(sdev->host);
1952	struct req_que *req = vha->req;
1953
1954	scsi_change_queue_depth(sdev, req->max_q_depth);
1955	return 0;
1956}
1957
1958static void
1959qla2xxx_sdev_destroy(struct scsi_device *sdev)
1960{
1961	sdev->hostdata = NULL;
1962}
1963
1964/**
1965 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1966 * @ha: HA context
1967 *
1968 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1969 * supported addressing method.
1970 */
1971static void
1972qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1973{
1974	/* Assume a 32bit DMA mask. */
1975	ha->flags.enable_64bit_addressing = 0;
1976
1977	if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1978		/* Any upper-dword bits set? */
1979		if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
1980		    !dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1981			/* Ok, a 64bit DMA mask is applicable. */
1982			ha->flags.enable_64bit_addressing = 1;
1983			ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1984			ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
1985			return;
1986		}
1987	}
1988
1989	dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1990	dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1991}
1992
1993static void
1994qla2x00_enable_intrs(struct qla_hw_data *ha)
1995{
1996	unsigned long flags = 0;
1997	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1998
1999	spin_lock_irqsave(&ha->hardware_lock, flags);
2000	ha->interrupts_on = 1;
2001	/* enable risc and host interrupts */
2002	wrt_reg_word(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
2003	rd_reg_word(&reg->ictrl);
2004	spin_unlock_irqrestore(&ha->hardware_lock, flags);
2005
2006}
2007
2008static void
2009qla2x00_disable_intrs(struct qla_hw_data *ha)
2010{
2011	unsigned long flags = 0;
2012	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2013
2014	spin_lock_irqsave(&ha->hardware_lock, flags);
2015	ha->interrupts_on = 0;
2016	/* disable risc and host interrupts */
2017	wrt_reg_word(&reg->ictrl, 0);
2018	rd_reg_word(&reg->ictrl);
2019	spin_unlock_irqrestore(&ha->hardware_lock, flags);
2020}
2021
2022static void
2023qla24xx_enable_intrs(struct qla_hw_data *ha)
2024{
2025	unsigned long flags = 0;
2026	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2027
2028	spin_lock_irqsave(&ha->hardware_lock, flags);
2029	ha->interrupts_on = 1;
2030	wrt_reg_dword(&reg->ictrl, ICRX_EN_RISC_INT);
2031	rd_reg_dword(&reg->ictrl);
2032	spin_unlock_irqrestore(&ha->hardware_lock, flags);
2033}
2034
2035static void
2036qla24xx_disable_intrs(struct qla_hw_data *ha)
2037{
2038	unsigned long flags = 0;
2039	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2040
2041	if (IS_NOPOLLING_TYPE(ha))
2042		return;
2043	spin_lock_irqsave(&ha->hardware_lock, flags);
2044	ha->interrupts_on = 0;
2045	wrt_reg_dword(&reg->ictrl, 0);
2046	rd_reg_dword(&reg->ictrl);
2047	spin_unlock_irqrestore(&ha->hardware_lock, flags);
2048}
2049
2050static int
2051qla2x00_iospace_config(struct qla_hw_data *ha)
2052{
2053	resource_size_t pio;
2054	uint16_t msix;
2055
2056	if (pci_request_selected_regions(ha->pdev, ha->bars,
2057	    QLA2XXX_DRIVER_NAME)) {
2058		ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
2059		    "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2060		    pci_name(ha->pdev));
2061		goto iospace_error_exit;
2062	}
2063	if (!(ha->bars & 1))
2064		goto skip_pio;
2065
2066	/* We only need PIO for Flash operations on ISP2312 v2 chips. */
2067	pio = pci_resource_start(ha->pdev, 0);
2068	if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
2069		if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2070			ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
2071			    "Invalid pci I/O region size (%s).\n",
2072			    pci_name(ha->pdev));
2073			pio = 0;
2074		}
2075	} else {
2076		ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
2077		    "Region #0 no a PIO resource (%s).\n",
2078		    pci_name(ha->pdev));
2079		pio = 0;
2080	}
2081	ha->pio_address = pio;
2082	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
2083	    "PIO address=%llu.\n",
2084	    (unsigned long long)ha->pio_address);
2085
2086skip_pio:
2087	/* Use MMIO operations for all accesses. */
2088	if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
2089		ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
2090		    "Region #1 not an MMIO resource (%s), aborting.\n",
2091		    pci_name(ha->pdev));
2092		goto iospace_error_exit;
2093	}
2094	if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
2095		ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
2096		    "Invalid PCI mem region size (%s), aborting.\n",
2097		    pci_name(ha->pdev));
2098		goto iospace_error_exit;
2099	}
2100
2101	ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
2102	if (!ha->iobase) {
2103		ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
2104		    "Cannot remap MMIO (%s), aborting.\n",
2105		    pci_name(ha->pdev));
2106		goto iospace_error_exit;
2107	}
2108
2109	/* Determine queue resources */
2110	ha->max_req_queues = ha->max_rsp_queues = 1;
2111	ha->msix_count = QLA_BASE_VECTORS;
2112
2113	/* Check if FW supports MQ or not */
2114	if (!(ha->fw_attributes & BIT_6))
2115		goto mqiobase_exit;
2116
2117	if (!ql2xmqsupport || !ql2xnvmeenable ||
2118	    (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
2119		goto mqiobase_exit;
2120
2121	ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
2122			pci_resource_len(ha->pdev, 3));
2123	if (ha->mqiobase) {
2124		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
2125		    "MQIO Base=%p.\n", ha->mqiobase);
2126		/* Read MSIX vector size of the board */
2127		pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
2128		ha->msix_count = msix + 1;
2129		/* Max queues are bounded by available msix vectors */
2130		/* MB interrupt uses 1 vector */
2131		ha->max_req_queues = ha->msix_count - 1;
2132		ha->max_rsp_queues = ha->max_req_queues;
2133		/* Queue pairs is the max value minus the base queue pair */
2134		ha->max_qpairs = ha->max_rsp_queues - 1;
2135		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
2136		    "Max no of queues pairs: %d.\n", ha->max_qpairs);
2137
2138		ql_log_pci(ql_log_info, ha->pdev, 0x001a,
2139		    "MSI-X vector count: %d.\n", ha->msix_count);
2140	} else
2141		ql_log_pci(ql_log_info, ha->pdev, 0x001b,
2142		    "BAR 3 not enabled.\n");
2143
2144mqiobase_exit:
2145	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
2146	    "MSIX Count: %d.\n", ha->msix_count);
2147	return (0);
2148
2149iospace_error_exit:
2150	return (-ENOMEM);
2151}
2152
2153
2154static int
2155qla83xx_iospace_config(struct qla_hw_data *ha)
2156{
2157	uint16_t msix;
2158
2159	if (pci_request_selected_regions(ha->pdev, ha->bars,
2160	    QLA2XXX_DRIVER_NAME)) {
2161		ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2162		    "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2163		    pci_name(ha->pdev));
2164
2165		goto iospace_error_exit;
2166	}
2167
2168	/* Use MMIO operations for all accesses. */
2169	if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2170		ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2171		    "Invalid pci I/O region size (%s).\n",
2172		    pci_name(ha->pdev));
2173		goto iospace_error_exit;
2174	}
2175	if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2176		ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2177		    "Invalid PCI mem region size (%s), aborting\n",
2178			pci_name(ha->pdev));
2179		goto iospace_error_exit;
2180	}
2181
2182	ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2183	if (!ha->iobase) {
2184		ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2185		    "Cannot remap MMIO (%s), aborting.\n",
2186		    pci_name(ha->pdev));
2187		goto iospace_error_exit;
2188	}
2189
2190	/* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2191	/* 83XX 26XX always use MQ type access for queues
2192	 * - mbar 2, a.k.a region 4 */
2193	ha->max_req_queues = ha->max_rsp_queues = 1;
2194	ha->msix_count = QLA_BASE_VECTORS;
2195	ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2196			pci_resource_len(ha->pdev, 4));
2197
2198	if (!ha->mqiobase) {
2199		ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2200		    "BAR2/region4 not enabled\n");
2201		goto mqiobase_exit;
2202	}
2203
2204	ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2205			pci_resource_len(ha->pdev, 2));
2206	if (ha->msixbase) {
2207		/* Read MSIX vector size of the board */
2208		pci_read_config_word(ha->pdev,
2209		    QLA_83XX_PCI_MSIX_CONTROL, &msix);
2210		ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE)  + 1;
2211		/*
2212		 * By default, driver uses at least two msix vectors
2213		 * (default & rspq)
2214		 */
2215		if (ql2xmqsupport || ql2xnvmeenable) {
2216			/* MB interrupt uses 1 vector */
2217			ha->max_req_queues = ha->msix_count - 1;
2218
2219			/* ATIOQ needs 1 vector. That's 1 less QPair */
2220			if (QLA_TGT_MODE_ENABLED())
2221				ha->max_req_queues--;
2222
2223			ha->max_rsp_queues = ha->max_req_queues;
2224
2225			/* Queue pairs is the max value minus
2226			 * the base queue pair */
2227			ha->max_qpairs = ha->max_req_queues - 1;
2228			ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
2229			    "Max no of queues pairs: %d.\n", ha->max_qpairs);
2230		}
2231		ql_log_pci(ql_log_info, ha->pdev, 0x011c,
2232		    "MSI-X vector count: %d.\n", ha->msix_count);
2233	} else
2234		ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2235		    "BAR 1 not enabled.\n");
2236
2237mqiobase_exit:
2238	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
2239	    "MSIX Count: %d.\n", ha->msix_count);
2240	return 0;
2241
2242iospace_error_exit:
2243	return -ENOMEM;
2244}
2245
2246static struct isp_operations qla2100_isp_ops = {
2247	.pci_config		= qla2100_pci_config,
2248	.reset_chip		= qla2x00_reset_chip,
2249	.chip_diag		= qla2x00_chip_diag,
2250	.config_rings		= qla2x00_config_rings,
2251	.reset_adapter		= qla2x00_reset_adapter,
2252	.nvram_config		= qla2x00_nvram_config,
2253	.update_fw_options	= qla2x00_update_fw_options,
2254	.load_risc		= qla2x00_load_risc,
2255	.pci_info_str		= qla2x00_pci_info_str,
2256	.fw_version_str		= qla2x00_fw_version_str,
2257	.intr_handler		= qla2100_intr_handler,
2258	.enable_intrs		= qla2x00_enable_intrs,
2259	.disable_intrs		= qla2x00_disable_intrs,
2260	.abort_command		= qla2x00_abort_command,
2261	.target_reset		= qla2x00_abort_target,
2262	.lun_reset		= qla2x00_lun_reset,
2263	.fabric_login		= qla2x00_login_fabric,
2264	.fabric_logout		= qla2x00_fabric_logout,
2265	.calc_req_entries	= qla2x00_calc_iocbs_32,
2266	.build_iocbs		= qla2x00_build_scsi_iocbs_32,
2267	.prep_ms_iocb		= qla2x00_prep_ms_iocb,
2268	.prep_ms_fdmi_iocb	= qla2x00_prep_ms_fdmi_iocb,
2269	.read_nvram		= qla2x00_read_nvram_data,
2270	.write_nvram		= qla2x00_write_nvram_data,
2271	.fw_dump		= qla2100_fw_dump,
2272	.beacon_on		= NULL,
2273	.beacon_off		= NULL,
2274	.beacon_blink		= NULL,
2275	.read_optrom		= qla2x00_read_optrom_data,
2276	.write_optrom		= qla2x00_write_optrom_data,
2277	.get_flash_version	= qla2x00_get_flash_version,
2278	.start_scsi		= qla2x00_start_scsi,
2279	.start_scsi_mq          = NULL,
2280	.abort_isp		= qla2x00_abort_isp,
2281	.iospace_config     	= qla2x00_iospace_config,
2282	.initialize_adapter	= qla2x00_initialize_adapter,
2283};
2284
2285static struct isp_operations qla2300_isp_ops = {
2286	.pci_config		= qla2300_pci_config,
2287	.reset_chip		= qla2x00_reset_chip,
2288	.chip_diag		= qla2x00_chip_diag,
2289	.config_rings		= qla2x00_config_rings,
2290	.reset_adapter		= qla2x00_reset_adapter,
2291	.nvram_config		= qla2x00_nvram_config,
2292	.update_fw_options	= qla2x00_update_fw_options,
2293	.load_risc		= qla2x00_load_risc,
2294	.pci_info_str		= qla2x00_pci_info_str,
2295	.fw_version_str		= qla2x00_fw_version_str,
2296	.intr_handler		= qla2300_intr_handler,
2297	.enable_intrs		= qla2x00_enable_intrs,
2298	.disable_intrs		= qla2x00_disable_intrs,
2299	.abort_command		= qla2x00_abort_command,
2300	.target_reset		= qla2x00_abort_target,
2301	.lun_reset		= qla2x00_lun_reset,
2302	.fabric_login		= qla2x00_login_fabric,
2303	.fabric_logout		= qla2x00_fabric_logout,
2304	.calc_req_entries	= qla2x00_calc_iocbs_32,
2305	.build_iocbs		= qla2x00_build_scsi_iocbs_32,
2306	.prep_ms_iocb		= qla2x00_prep_ms_iocb,
2307	.prep_ms_fdmi_iocb	= qla2x00_prep_ms_fdmi_iocb,
2308	.read_nvram		= qla2x00_read_nvram_data,
2309	.write_nvram		= qla2x00_write_nvram_data,
2310	.fw_dump		= qla2300_fw_dump,
2311	.beacon_on		= qla2x00_beacon_on,
2312	.beacon_off		= qla2x00_beacon_off,
2313	.beacon_blink		= qla2x00_beacon_blink,
2314	.read_optrom		= qla2x00_read_optrom_data,
2315	.write_optrom		= qla2x00_write_optrom_data,
2316	.get_flash_version	= qla2x00_get_flash_version,
2317	.start_scsi		= qla2x00_start_scsi,
2318	.start_scsi_mq          = NULL,
2319	.abort_isp		= qla2x00_abort_isp,
2320	.iospace_config		= qla2x00_iospace_config,
2321	.initialize_adapter	= qla2x00_initialize_adapter,
2322};
2323
2324static struct isp_operations qla24xx_isp_ops = {
2325	.pci_config		= qla24xx_pci_config,
2326	.reset_chip		= qla24xx_reset_chip,
2327	.chip_diag		= qla24xx_chip_diag,
2328	.config_rings		= qla24xx_config_rings,
2329	.reset_adapter		= qla24xx_reset_adapter,
2330	.nvram_config		= qla24xx_nvram_config,
2331	.update_fw_options	= qla24xx_update_fw_options,
2332	.load_risc		= qla24xx_load_risc,
2333	.pci_info_str		= qla24xx_pci_info_str,
2334	.fw_version_str		= qla24xx_fw_version_str,
2335	.intr_handler		= qla24xx_intr_handler,
2336	.enable_intrs		= qla24xx_enable_intrs,
2337	.disable_intrs		= qla24xx_disable_intrs,
2338	.abort_command		= qla24xx_abort_command,
2339	.target_reset		= qla24xx_abort_target,
2340	.lun_reset		= qla24xx_lun_reset,
2341	.fabric_login		= qla24xx_login_fabric,
2342	.fabric_logout		= qla24xx_fabric_logout,
2343	.calc_req_entries	= NULL,
2344	.build_iocbs		= NULL,
2345	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
2346	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
2347	.read_nvram		= qla24xx_read_nvram_data,
2348	.write_nvram		= qla24xx_write_nvram_data,
2349	.fw_dump		= qla24xx_fw_dump,
2350	.beacon_on		= qla24xx_beacon_on,
2351	.beacon_off		= qla24xx_beacon_off,
2352	.beacon_blink		= qla24xx_beacon_blink,
2353	.read_optrom		= qla24xx_read_optrom_data,
2354	.write_optrom		= qla24xx_write_optrom_data,
2355	.get_flash_version	= qla24xx_get_flash_version,
2356	.start_scsi		= qla24xx_start_scsi,
2357	.start_scsi_mq          = NULL,
2358	.abort_isp		= qla2x00_abort_isp,
2359	.iospace_config		= qla2x00_iospace_config,
2360	.initialize_adapter	= qla2x00_initialize_adapter,
2361};
2362
2363static struct isp_operations qla25xx_isp_ops = {
2364	.pci_config		= qla25xx_pci_config,
2365	.reset_chip		= qla24xx_reset_chip,
2366	.chip_diag		= qla24xx_chip_diag,
2367	.config_rings		= qla24xx_config_rings,
2368	.reset_adapter		= qla24xx_reset_adapter,
2369	.nvram_config		= qla24xx_nvram_config,
2370	.update_fw_options	= qla24xx_update_fw_options,
2371	.load_risc		= qla24xx_load_risc,
2372	.pci_info_str		= qla24xx_pci_info_str,
2373	.fw_version_str		= qla24xx_fw_version_str,
2374	.intr_handler		= qla24xx_intr_handler,
2375	.enable_intrs		= qla24xx_enable_intrs,
2376	.disable_intrs		= qla24xx_disable_intrs,
2377	.abort_command		= qla24xx_abort_command,
2378	.target_reset		= qla24xx_abort_target,
2379	.lun_reset		= qla24xx_lun_reset,
2380	.fabric_login		= qla24xx_login_fabric,
2381	.fabric_logout		= qla24xx_fabric_logout,
2382	.calc_req_entries	= NULL,
2383	.build_iocbs		= NULL,
2384	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
2385	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
2386	.read_nvram		= qla25xx_read_nvram_data,
2387	.write_nvram		= qla25xx_write_nvram_data,
2388	.fw_dump		= qla25xx_fw_dump,
2389	.beacon_on		= qla24xx_beacon_on,
2390	.beacon_off		= qla24xx_beacon_off,
2391	.beacon_blink		= qla24xx_beacon_blink,
2392	.read_optrom		= qla25xx_read_optrom_data,
2393	.write_optrom		= qla24xx_write_optrom_data,
2394	.get_flash_version	= qla24xx_get_flash_version,
2395	.start_scsi		= qla24xx_dif_start_scsi,
2396	.start_scsi_mq          = qla2xxx_dif_start_scsi_mq,
2397	.abort_isp		= qla2x00_abort_isp,
2398	.iospace_config		= qla2x00_iospace_config,
2399	.initialize_adapter	= qla2x00_initialize_adapter,
2400};
2401
2402static struct isp_operations qla81xx_isp_ops = {
2403	.pci_config		= qla25xx_pci_config,
2404	.reset_chip		= qla24xx_reset_chip,
2405	.chip_diag		= qla24xx_chip_diag,
2406	.config_rings		= qla24xx_config_rings,
2407	.reset_adapter		= qla24xx_reset_adapter,
2408	.nvram_config		= qla81xx_nvram_config,
2409	.update_fw_options	= qla24xx_update_fw_options,
2410	.load_risc		= qla81xx_load_risc,
2411	.pci_info_str		= qla24xx_pci_info_str,
2412	.fw_version_str		= qla24xx_fw_version_str,
2413	.intr_handler		= qla24xx_intr_handler,
2414	.enable_intrs		= qla24xx_enable_intrs,
2415	.disable_intrs		= qla24xx_disable_intrs,
2416	.abort_command		= qla24xx_abort_command,
2417	.target_reset		= qla24xx_abort_target,
2418	.lun_reset		= qla24xx_lun_reset,
2419	.fabric_login		= qla24xx_login_fabric,
2420	.fabric_logout		= qla24xx_fabric_logout,
2421	.calc_req_entries	= NULL,
2422	.build_iocbs		= NULL,
2423	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
2424	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
2425	.read_nvram		= NULL,
2426	.write_nvram		= NULL,
2427	.fw_dump		= qla81xx_fw_dump,
2428	.beacon_on		= qla24xx_beacon_on,
2429	.beacon_off		= qla24xx_beacon_off,
2430	.beacon_blink		= qla83xx_beacon_blink,
2431	.read_optrom		= qla25xx_read_optrom_data,
2432	.write_optrom		= qla24xx_write_optrom_data,
2433	.get_flash_version	= qla24xx_get_flash_version,
2434	.start_scsi		= qla24xx_dif_start_scsi,
2435	.start_scsi_mq          = qla2xxx_dif_start_scsi_mq,
2436	.abort_isp		= qla2x00_abort_isp,
2437	.iospace_config		= qla2x00_iospace_config,
2438	.initialize_adapter	= qla2x00_initialize_adapter,
2439};
2440
2441static struct isp_operations qla82xx_isp_ops = {
2442	.pci_config		= qla82xx_pci_config,
2443	.reset_chip		= qla82xx_reset_chip,
2444	.chip_diag		= qla24xx_chip_diag,
2445	.config_rings		= qla82xx_config_rings,
2446	.reset_adapter		= qla24xx_reset_adapter,
2447	.nvram_config		= qla81xx_nvram_config,
2448	.update_fw_options	= qla24xx_update_fw_options,
2449	.load_risc		= qla82xx_load_risc,
2450	.pci_info_str		= qla24xx_pci_info_str,
2451	.fw_version_str		= qla24xx_fw_version_str,
2452	.intr_handler		= qla82xx_intr_handler,
2453	.enable_intrs		= qla82xx_enable_intrs,
2454	.disable_intrs		= qla82xx_disable_intrs,
2455	.abort_command		= qla24xx_abort_command,
2456	.target_reset		= qla24xx_abort_target,
2457	.lun_reset		= qla24xx_lun_reset,
2458	.fabric_login		= qla24xx_login_fabric,
2459	.fabric_logout		= qla24xx_fabric_logout,
2460	.calc_req_entries	= NULL,
2461	.build_iocbs		= NULL,
2462	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
2463	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
2464	.read_nvram		= qla24xx_read_nvram_data,
2465	.write_nvram		= qla24xx_write_nvram_data,
2466	.fw_dump		= qla82xx_fw_dump,
2467	.beacon_on		= qla82xx_beacon_on,
2468	.beacon_off		= qla82xx_beacon_off,
2469	.beacon_blink		= NULL,
2470	.read_optrom		= qla82xx_read_optrom_data,
2471	.write_optrom		= qla82xx_write_optrom_data,
2472	.get_flash_version	= qla82xx_get_flash_version,
2473	.start_scsi             = qla82xx_start_scsi,
2474	.start_scsi_mq          = NULL,
2475	.abort_isp		= qla82xx_abort_isp,
2476	.iospace_config     	= qla82xx_iospace_config,
2477	.initialize_adapter	= qla2x00_initialize_adapter,
2478};
2479
2480static struct isp_operations qla8044_isp_ops = {
2481	.pci_config		= qla82xx_pci_config,
2482	.reset_chip		= qla82xx_reset_chip,
2483	.chip_diag		= qla24xx_chip_diag,
2484	.config_rings		= qla82xx_config_rings,
2485	.reset_adapter		= qla24xx_reset_adapter,
2486	.nvram_config		= qla81xx_nvram_config,
2487	.update_fw_options	= qla24xx_update_fw_options,
2488	.load_risc		= qla82xx_load_risc,
2489	.pci_info_str		= qla24xx_pci_info_str,
2490	.fw_version_str		= qla24xx_fw_version_str,
2491	.intr_handler		= qla8044_intr_handler,
2492	.enable_intrs		= qla82xx_enable_intrs,
2493	.disable_intrs		= qla82xx_disable_intrs,
2494	.abort_command		= qla24xx_abort_command,
2495	.target_reset		= qla24xx_abort_target,
2496	.lun_reset		= qla24xx_lun_reset,
2497	.fabric_login		= qla24xx_login_fabric,
2498	.fabric_logout		= qla24xx_fabric_logout,
2499	.calc_req_entries	= NULL,
2500	.build_iocbs		= NULL,
2501	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
2502	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
2503	.read_nvram		= NULL,
2504	.write_nvram		= NULL,
2505	.fw_dump		= qla8044_fw_dump,
2506	.beacon_on		= qla82xx_beacon_on,
2507	.beacon_off		= qla82xx_beacon_off,
2508	.beacon_blink		= NULL,
2509	.read_optrom		= qla8044_read_optrom_data,
2510	.write_optrom		= qla8044_write_optrom_data,
2511	.get_flash_version	= qla82xx_get_flash_version,
2512	.start_scsi             = qla82xx_start_scsi,
2513	.start_scsi_mq          = NULL,
2514	.abort_isp		= qla8044_abort_isp,
2515	.iospace_config		= qla82xx_iospace_config,
2516	.initialize_adapter	= qla2x00_initialize_adapter,
2517};
2518
2519static struct isp_operations qla83xx_isp_ops = {
2520	.pci_config		= qla25xx_pci_config,
2521	.reset_chip		= qla24xx_reset_chip,
2522	.chip_diag		= qla24xx_chip_diag,
2523	.config_rings		= qla24xx_config_rings,
2524	.reset_adapter		= qla24xx_reset_adapter,
2525	.nvram_config		= qla81xx_nvram_config,
2526	.update_fw_options	= qla24xx_update_fw_options,
2527	.load_risc		= qla81xx_load_risc,
2528	.pci_info_str		= qla24xx_pci_info_str,
2529	.fw_version_str		= qla24xx_fw_version_str,
2530	.intr_handler		= qla24xx_intr_handler,
2531	.enable_intrs		= qla24xx_enable_intrs,
2532	.disable_intrs		= qla24xx_disable_intrs,
2533	.abort_command		= qla24xx_abort_command,
2534	.target_reset		= qla24xx_abort_target,
2535	.lun_reset		= qla24xx_lun_reset,
2536	.fabric_login		= qla24xx_login_fabric,
2537	.fabric_logout		= qla24xx_fabric_logout,
2538	.calc_req_entries	= NULL,
2539	.build_iocbs		= NULL,
2540	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
2541	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
2542	.read_nvram		= NULL,
2543	.write_nvram		= NULL,
2544	.fw_dump		= qla83xx_fw_dump,
2545	.beacon_on		= qla24xx_beacon_on,
2546	.beacon_off		= qla24xx_beacon_off,
2547	.beacon_blink		= qla83xx_beacon_blink,
2548	.read_optrom		= qla25xx_read_optrom_data,
2549	.write_optrom		= qla24xx_write_optrom_data,
2550	.get_flash_version	= qla24xx_get_flash_version,
2551	.start_scsi		= qla24xx_dif_start_scsi,
2552	.start_scsi_mq          = qla2xxx_dif_start_scsi_mq,
2553	.abort_isp		= qla2x00_abort_isp,
2554	.iospace_config		= qla83xx_iospace_config,
2555	.initialize_adapter	= qla2x00_initialize_adapter,
2556};
2557
2558static struct isp_operations qlafx00_isp_ops = {
2559	.pci_config		= qlafx00_pci_config,
2560	.reset_chip		= qlafx00_soft_reset,
2561	.chip_diag		= qlafx00_chip_diag,
2562	.config_rings		= qlafx00_config_rings,
2563	.reset_adapter		= qlafx00_soft_reset,
2564	.nvram_config		= NULL,
2565	.update_fw_options	= NULL,
2566	.load_risc		= NULL,
2567	.pci_info_str		= qlafx00_pci_info_str,
2568	.fw_version_str		= qlafx00_fw_version_str,
2569	.intr_handler		= qlafx00_intr_handler,
2570	.enable_intrs		= qlafx00_enable_intrs,
2571	.disable_intrs		= qlafx00_disable_intrs,
2572	.abort_command		= qla24xx_async_abort_command,
2573	.target_reset		= qlafx00_abort_target,
2574	.lun_reset		= qlafx00_lun_reset,
2575	.fabric_login		= NULL,
2576	.fabric_logout		= NULL,
2577	.calc_req_entries	= NULL,
2578	.build_iocbs		= NULL,
2579	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
2580	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
2581	.read_nvram		= qla24xx_read_nvram_data,
2582	.write_nvram		= qla24xx_write_nvram_data,
2583	.fw_dump		= NULL,
2584	.beacon_on		= qla24xx_beacon_on,
2585	.beacon_off		= qla24xx_beacon_off,
2586	.beacon_blink		= NULL,
2587	.read_optrom		= qla24xx_read_optrom_data,
2588	.write_optrom		= qla24xx_write_optrom_data,
2589	.get_flash_version	= qla24xx_get_flash_version,
2590	.start_scsi		= qlafx00_start_scsi,
2591	.start_scsi_mq          = NULL,
2592	.abort_isp		= qlafx00_abort_isp,
2593	.iospace_config		= qlafx00_iospace_config,
2594	.initialize_adapter	= qlafx00_initialize_adapter,
2595};
2596
2597static struct isp_operations qla27xx_isp_ops = {
2598	.pci_config		= qla25xx_pci_config,
2599	.reset_chip		= qla24xx_reset_chip,
2600	.chip_diag		= qla24xx_chip_diag,
2601	.config_rings		= qla24xx_config_rings,
2602	.reset_adapter		= qla24xx_reset_adapter,
2603	.nvram_config		= qla81xx_nvram_config,
2604	.update_fw_options	= qla24xx_update_fw_options,
2605	.load_risc		= qla81xx_load_risc,
2606	.pci_info_str		= qla24xx_pci_info_str,
2607	.fw_version_str		= qla24xx_fw_version_str,
2608	.intr_handler		= qla24xx_intr_handler,
2609	.enable_intrs		= qla24xx_enable_intrs,
2610	.disable_intrs		= qla24xx_disable_intrs,
2611	.abort_command		= qla24xx_abort_command,
2612	.target_reset		= qla24xx_abort_target,
2613	.lun_reset		= qla24xx_lun_reset,
2614	.fabric_login		= qla24xx_login_fabric,
2615	.fabric_logout		= qla24xx_fabric_logout,
2616	.calc_req_entries	= NULL,
2617	.build_iocbs		= NULL,
2618	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
2619	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
2620	.read_nvram		= NULL,
2621	.write_nvram		= NULL,
2622	.fw_dump		= qla27xx_fwdump,
2623	.mpi_fw_dump		= qla27xx_mpi_fwdump,
2624	.beacon_on		= qla24xx_beacon_on,
2625	.beacon_off		= qla24xx_beacon_off,
2626	.beacon_blink		= qla83xx_beacon_blink,
2627	.read_optrom		= qla25xx_read_optrom_data,
2628	.write_optrom		= qla24xx_write_optrom_data,
2629	.get_flash_version	= qla24xx_get_flash_version,
2630	.start_scsi		= qla24xx_dif_start_scsi,
2631	.start_scsi_mq          = qla2xxx_dif_start_scsi_mq,
2632	.abort_isp		= qla2x00_abort_isp,
2633	.iospace_config		= qla83xx_iospace_config,
2634	.initialize_adapter	= qla2x00_initialize_adapter,
2635};
2636
2637static inline void
2638qla2x00_set_isp_flags(struct qla_hw_data *ha)
2639{
2640	ha->device_type = DT_EXTENDED_IDS;
2641	switch (ha->pdev->device) {
2642	case PCI_DEVICE_ID_QLOGIC_ISP2100:
2643		ha->isp_type |= DT_ISP2100;
2644		ha->device_type &= ~DT_EXTENDED_IDS;
2645		ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2646		break;
2647	case PCI_DEVICE_ID_QLOGIC_ISP2200:
2648		ha->isp_type |= DT_ISP2200;
2649		ha->device_type &= ~DT_EXTENDED_IDS;
2650		ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2651		break;
2652	case PCI_DEVICE_ID_QLOGIC_ISP2300:
2653		ha->isp_type |= DT_ISP2300;
2654		ha->device_type |= DT_ZIO_SUPPORTED;
2655		ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2656		break;
2657	case PCI_DEVICE_ID_QLOGIC_ISP2312:
2658		ha->isp_type |= DT_ISP2312;
2659		ha->device_type |= DT_ZIO_SUPPORTED;
2660		ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2661		break;
2662	case PCI_DEVICE_ID_QLOGIC_ISP2322:
2663		ha->isp_type |= DT_ISP2322;
2664		ha->device_type |= DT_ZIO_SUPPORTED;
2665		if (ha->pdev->subsystem_vendor == 0x1028 &&
2666		    ha->pdev->subsystem_device == 0x0170)
2667			ha->device_type |= DT_OEM_001;
2668		ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2669		break;
2670	case PCI_DEVICE_ID_QLOGIC_ISP6312:
2671		ha->isp_type |= DT_ISP6312;
2672		ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2673		break;
2674	case PCI_DEVICE_ID_QLOGIC_ISP6322:
2675		ha->isp_type |= DT_ISP6322;
2676		ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2677		break;
2678	case PCI_DEVICE_ID_QLOGIC_ISP2422:
2679		ha->isp_type |= DT_ISP2422;
2680		ha->device_type |= DT_ZIO_SUPPORTED;
2681		ha->device_type |= DT_FWI2;
2682		ha->device_type |= DT_IIDMA;
2683		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2684		break;
2685	case PCI_DEVICE_ID_QLOGIC_ISP2432:
2686		ha->isp_type |= DT_ISP2432;
2687		ha->device_type |= DT_ZIO_SUPPORTED;
2688		ha->device_type |= DT_FWI2;
2689		ha->device_type |= DT_IIDMA;
2690		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2691		break;
2692	case PCI_DEVICE_ID_QLOGIC_ISP8432:
2693		ha->isp_type |= DT_ISP8432;
2694		ha->device_type |= DT_ZIO_SUPPORTED;
2695		ha->device_type |= DT_FWI2;
2696		ha->device_type |= DT_IIDMA;
2697		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2698		break;
2699	case PCI_DEVICE_ID_QLOGIC_ISP5422:
2700		ha->isp_type |= DT_ISP5422;
2701		ha->device_type |= DT_FWI2;
2702		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2703		break;
2704	case PCI_DEVICE_ID_QLOGIC_ISP5432:
2705		ha->isp_type |= DT_ISP5432;
2706		ha->device_type |= DT_FWI2;
2707		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2708		break;
2709	case PCI_DEVICE_ID_QLOGIC_ISP2532:
2710		ha->isp_type |= DT_ISP2532;
2711		ha->device_type |= DT_ZIO_SUPPORTED;
2712		ha->device_type |= DT_FWI2;
2713		ha->device_type |= DT_IIDMA;
2714		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2715		break;
2716	case PCI_DEVICE_ID_QLOGIC_ISP8001:
2717		ha->isp_type |= DT_ISP8001;
2718		ha->device_type |= DT_ZIO_SUPPORTED;
2719		ha->device_type |= DT_FWI2;
2720		ha->device_type |= DT_IIDMA;
2721		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2722		break;
2723	case PCI_DEVICE_ID_QLOGIC_ISP8021:
2724		ha->isp_type |= DT_ISP8021;
2725		ha->device_type |= DT_ZIO_SUPPORTED;
2726		ha->device_type |= DT_FWI2;
2727		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2728		/* Initialize 82XX ISP flags */
2729		qla82xx_init_flags(ha);
2730		break;
2731	 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2732		ha->isp_type |= DT_ISP8044;
2733		ha->device_type |= DT_ZIO_SUPPORTED;
2734		ha->device_type |= DT_FWI2;
2735		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2736		/* Initialize 82XX ISP flags */
2737		qla82xx_init_flags(ha);
2738		break;
2739	case PCI_DEVICE_ID_QLOGIC_ISP2031:
2740		ha->isp_type |= DT_ISP2031;
2741		ha->device_type |= DT_ZIO_SUPPORTED;
2742		ha->device_type |= DT_FWI2;
2743		ha->device_type |= DT_IIDMA;
2744		ha->device_type |= DT_T10_PI;
2745		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2746		break;
2747	case PCI_DEVICE_ID_QLOGIC_ISP8031:
2748		ha->isp_type |= DT_ISP8031;
2749		ha->device_type |= DT_ZIO_SUPPORTED;
2750		ha->device_type |= DT_FWI2;
2751		ha->device_type |= DT_IIDMA;
2752		ha->device_type |= DT_T10_PI;
2753		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2754		break;
2755	case PCI_DEVICE_ID_QLOGIC_ISPF001:
2756		ha->isp_type |= DT_ISPFX00;
2757		break;
2758	case PCI_DEVICE_ID_QLOGIC_ISP2071:
2759		ha->isp_type |= DT_ISP2071;
2760		ha->device_type |= DT_ZIO_SUPPORTED;
2761		ha->device_type |= DT_FWI2;
2762		ha->device_type |= DT_IIDMA;
2763		ha->device_type |= DT_T10_PI;
2764		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2765		break;
2766	case PCI_DEVICE_ID_QLOGIC_ISP2271:
2767		ha->isp_type |= DT_ISP2271;
2768		ha->device_type |= DT_ZIO_SUPPORTED;
2769		ha->device_type |= DT_FWI2;
2770		ha->device_type |= DT_IIDMA;
2771		ha->device_type |= DT_T10_PI;
2772		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2773		break;
2774	case PCI_DEVICE_ID_QLOGIC_ISP2261:
2775		ha->isp_type |= DT_ISP2261;
2776		ha->device_type |= DT_ZIO_SUPPORTED;
2777		ha->device_type |= DT_FWI2;
2778		ha->device_type |= DT_IIDMA;
2779		ha->device_type |= DT_T10_PI;
2780		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2781		break;
2782	case PCI_DEVICE_ID_QLOGIC_ISP2081:
2783	case PCI_DEVICE_ID_QLOGIC_ISP2089:
2784		ha->isp_type |= DT_ISP2081;
2785		ha->device_type |= DT_ZIO_SUPPORTED;
2786		ha->device_type |= DT_FWI2;
2787		ha->device_type |= DT_IIDMA;
2788		ha->device_type |= DT_T10_PI;
2789		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2790		break;
2791	case PCI_DEVICE_ID_QLOGIC_ISP2281:
2792	case PCI_DEVICE_ID_QLOGIC_ISP2289:
2793		ha->isp_type |= DT_ISP2281;
2794		ha->device_type |= DT_ZIO_SUPPORTED;
2795		ha->device_type |= DT_FWI2;
2796		ha->device_type |= DT_IIDMA;
2797		ha->device_type |= DT_T10_PI;
2798		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2799		break;
2800	}
2801
2802	if (IS_QLA82XX(ha))
2803		ha->port_no = ha->portnum & 1;
2804	else {
2805		/* Get adapter physical port no from interrupt pin register. */
2806		pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2807		if (IS_QLA25XX(ha) || IS_QLA2031(ha) ||
2808		    IS_QLA27XX(ha) || IS_QLA28XX(ha))
2809			ha->port_no--;
2810		else
2811			ha->port_no = !(ha->port_no & 1);
2812	}
2813
2814	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
2815	    "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
2816	    ha->device_type, ha->port_no, ha->fw_srisc_address);
2817}
2818
2819static void
2820qla2xxx_scan_start(struct Scsi_Host *shost)
2821{
2822	scsi_qla_host_t *vha = shost_priv(shost);
2823
2824	if (vha->hw->flags.running_gold_fw)
2825		return;
2826
2827	set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2828	set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2829	set_bit(RSCN_UPDATE, &vha->dpc_flags);
2830	set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
2831}
2832
2833static int
2834qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2835{
2836	scsi_qla_host_t *vha = shost_priv(shost);
2837
2838	if (test_bit(UNLOADING, &vha->dpc_flags))
2839		return 1;
2840	if (!vha->host)
2841		return 1;
2842	if (time > vha->hw->loop_reset_delay * HZ)
2843		return 1;
2844
2845	return atomic_read(&vha->loop_state) == LOOP_READY;
2846}
2847
2848static void qla_heartbeat_work_fn(struct work_struct *work)
2849{
2850	struct qla_hw_data *ha = container_of(work,
2851		struct qla_hw_data, heartbeat_work);
2852	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2853
2854	if (!ha->flags.mbox_busy && base_vha->flags.init_done)
2855		qla_no_op_mb(base_vha);
2856}
2857
2858static void qla2x00_iocb_work_fn(struct work_struct *work)
2859{
2860	struct scsi_qla_host *vha = container_of(work,
2861		struct scsi_qla_host, iocb_work);
2862	struct qla_hw_data *ha = vha->hw;
2863	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2864	int i = 2;
2865	unsigned long flags;
2866
2867	if (test_bit(UNLOADING, &base_vha->dpc_flags))
2868		return;
2869
2870	while (!list_empty(&vha->work_list) && i > 0) {
2871		qla2x00_do_work(vha);
2872		i--;
2873	}
2874
2875	spin_lock_irqsave(&vha->work_lock, flags);
2876	clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags);
2877	spin_unlock_irqrestore(&vha->work_lock, flags);
2878}
2879
2880static void
2881qla_trace_init(void)
2882{
2883	qla_trc_array = trace_array_get_by_name("qla2xxx", NULL);
2884	if (!qla_trc_array) {
2885		ql_log(ql_log_fatal, NULL, 0x0001,
2886		       "Unable to create qla2xxx trace instance, instance logging will be disabled.\n");
2887		return;
2888	}
2889
2890	QLA_TRACE_ENABLE(qla_trc_array);
2891}
2892
2893static void
2894qla_trace_uninit(void)
2895{
2896	if (!qla_trc_array)
2897		return;
2898	trace_array_put(qla_trc_array);
2899}
2900
2901/*
2902 * PCI driver interface
2903 */
2904static int
2905qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
2906{
2907	int	ret = -ENODEV;
2908	struct Scsi_Host *host;
2909	scsi_qla_host_t *base_vha = NULL;
2910	struct qla_hw_data *ha;
2911	char pci_info[30];
2912	char fw_str[30], wq_name[30];
2913	struct scsi_host_template *sht;
2914	int bars, mem_only = 0;
2915	uint16_t req_length = 0, rsp_length = 0;
2916	struct req_que *req = NULL;
2917	struct rsp_que *rsp = NULL;
2918	int i;
2919
2920	bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
2921	sht = &qla2xxx_driver_template;
2922	if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
2923	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
2924	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
2925	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
2926	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
2927	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
2928	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
2929	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2930	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2931	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
2932	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
2933	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2934	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2935	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2936	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 ||
2937	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 ||
2938	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 ||
2939	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 ||
2940	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) {
2941		bars = pci_select_bars(pdev, IORESOURCE_MEM);
2942		mem_only = 1;
2943		ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2944		    "Mem only adapter.\n");
2945	}
2946	ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2947	    "Bars=%d.\n", bars);
2948
2949	if (mem_only) {
2950		if (pci_enable_device_mem(pdev))
2951			return ret;
2952	} else {
2953		if (pci_enable_device(pdev))
2954			return ret;
2955	}
2956
2957	if (is_kdump_kernel()) {
2958		ql2xmqsupport = 0;
2959		ql2xallocfwdump = 0;
2960	}
2961
2962	ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2963	if (!ha) {
2964		ql_log_pci(ql_log_fatal, pdev, 0x0009,
2965		    "Unable to allocate memory for ha.\n");
2966		goto disable_device;
2967	}
2968	ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2969	    "Memory allocated for ha=%p.\n", ha);
2970	ha->pdev = pdev;
2971	INIT_LIST_HEAD(&ha->tgt.q_full_list);
2972	spin_lock_init(&ha->tgt.q_full_lock);
2973	spin_lock_init(&ha->tgt.sess_lock);
2974	spin_lock_init(&ha->tgt.atio_lock);
2975
2976	spin_lock_init(&ha->sadb_lock);
2977	INIT_LIST_HEAD(&ha->sadb_tx_index_list);
2978	INIT_LIST_HEAD(&ha->sadb_rx_index_list);
2979
2980	spin_lock_init(&ha->sadb_fp_lock);
2981
2982	if (qla_edif_sadb_build_free_pool(ha)) {
2983		kfree(ha);
2984		goto  disable_device;
2985	}
2986
2987	atomic_set(&ha->nvme_active_aen_cnt, 0);
2988
2989	/* Clear our data area */
2990	ha->bars = bars;
2991	ha->mem_only = mem_only;
2992	spin_lock_init(&ha->hardware_lock);
2993	spin_lock_init(&ha->vport_slock);
2994	mutex_init(&ha->selflogin_lock);
2995	mutex_init(&ha->optrom_mutex);
2996
2997	/* Set ISP-type information. */
2998	qla2x00_set_isp_flags(ha);
2999
3000	/* Set EEH reset type to fundamental if required by hba */
3001	if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
3002	    IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
3003		pdev->needs_freset = 1;
3004
3005	ha->prev_topology = 0;
3006	ha->init_cb_size = sizeof(init_cb_t);
3007	ha->link_data_rate = PORT_SPEED_UNKNOWN;
3008	ha->optrom_size = OPTROM_SIZE_2300;
3009	ha->max_exchg = FW_MAX_EXCHANGES_CNT;
3010	atomic_set(&ha->num_pend_mbx_stage1, 0);
3011	atomic_set(&ha->num_pend_mbx_stage2, 0);
3012	atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD);
3013	ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD;
3014	INIT_LIST_HEAD(&ha->tmf_pending);
3015	INIT_LIST_HEAD(&ha->tmf_active);
3016
3017	/* Assign ISP specific operations. */
3018	if (IS_QLA2100(ha)) {
3019		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
3020		ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
3021		req_length = REQUEST_ENTRY_CNT_2100;
3022		rsp_length = RESPONSE_ENTRY_CNT_2100;
3023		ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
3024		ha->gid_list_info_size = 4;
3025		ha->flash_conf_off = ~0;
3026		ha->flash_data_off = ~0;
3027		ha->nvram_conf_off = ~0;
3028		ha->nvram_data_off = ~0;
3029		ha->isp_ops = &qla2100_isp_ops;
3030	} else if (IS_QLA2200(ha)) {
3031		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
3032		ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
3033		req_length = REQUEST_ENTRY_CNT_2200;
3034		rsp_length = RESPONSE_ENTRY_CNT_2100;
3035		ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
3036		ha->gid_list_info_size = 4;
3037		ha->flash_conf_off = ~0;
3038		ha->flash_data_off = ~0;
3039		ha->nvram_conf_off = ~0;
3040		ha->nvram_data_off = ~0;
3041		ha->isp_ops = &qla2100_isp_ops;
3042	} else if (IS_QLA23XX(ha)) {
3043		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
3044		ha->mbx_count = MAILBOX_REGISTER_COUNT;
3045		req_length = REQUEST_ENTRY_CNT_2200;
3046		rsp_length = RESPONSE_ENTRY_CNT_2300;
3047		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3048		ha->gid_list_info_size = 6;
3049		if (IS_QLA2322(ha) || IS_QLA6322(ha))
3050			ha->optrom_size = OPTROM_SIZE_2322;
3051		ha->flash_conf_off = ~0;
3052		ha->flash_data_off = ~0;
3053		ha->nvram_conf_off = ~0;
3054		ha->nvram_data_off = ~0;
3055		ha->isp_ops = &qla2300_isp_ops;
3056	} else if (IS_QLA24XX_TYPE(ha)) {
3057		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3058		ha->mbx_count = MAILBOX_REGISTER_COUNT;
3059		req_length = REQUEST_ENTRY_CNT_24XX;
3060		rsp_length = RESPONSE_ENTRY_CNT_2300;
3061		ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3062		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3063		ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
3064		ha->gid_list_info_size = 8;
3065		ha->optrom_size = OPTROM_SIZE_24XX;
3066		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
3067		ha->isp_ops = &qla24xx_isp_ops;
3068		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3069		ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3070		ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3071		ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3072	} else if (IS_QLA25XX(ha)) {
3073		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3074		ha->mbx_count = MAILBOX_REGISTER_COUNT;
3075		req_length = REQUEST_ENTRY_CNT_24XX;
3076		rsp_length = RESPONSE_ENTRY_CNT_2300;
3077		ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3078		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3079		ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
3080		ha->gid_list_info_size = 8;
3081		ha->optrom_size = OPTROM_SIZE_25XX;
3082		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3083		ha->isp_ops = &qla25xx_isp_ops;
3084		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3085		ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3086		ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3087		ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3088	} else if (IS_QLA81XX(ha)) {
3089		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3090		ha->mbx_count = MAILBOX_REGISTER_COUNT;
3091		req_length = REQUEST_ENTRY_CNT_24XX;
3092		rsp_length = RESPONSE_ENTRY_CNT_2300;
3093		ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3094		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3095		ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3096		ha->gid_list_info_size = 8;
3097		ha->optrom_size = OPTROM_SIZE_81XX;
3098		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3099		ha->isp_ops = &qla81xx_isp_ops;
3100		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3101		ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3102		ha->nvram_conf_off = ~0;
3103		ha->nvram_data_off = ~0;
3104	} else if (IS_QLA82XX(ha)) {
3105		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3106		ha->mbx_count = MAILBOX_REGISTER_COUNT;
3107		req_length = REQUEST_ENTRY_CNT_82XX;
3108		rsp_length = RESPONSE_ENTRY_CNT_82XX;
3109		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3110		ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3111		ha->gid_list_info_size = 8;
3112		ha->optrom_size = OPTROM_SIZE_82XX;
3113		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3114		ha->isp_ops = &qla82xx_isp_ops;
3115		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3116		ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3117		ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3118		ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3119	} else if (IS_QLA8044(ha)) {
3120		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3121		ha->mbx_count = MAILBOX_REGISTER_COUNT;
3122		req_length = REQUEST_ENTRY_CNT_82XX;
3123		rsp_length = RESPONSE_ENTRY_CNT_82XX;
3124		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3125		ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3126		ha->gid_list_info_size = 8;
3127		ha->optrom_size = OPTROM_SIZE_83XX;
3128		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3129		ha->isp_ops = &qla8044_isp_ops;
3130		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3131		ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3132		ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3133		ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3134	} else if (IS_QLA83XX(ha)) {
3135		ha->portnum = PCI_FUNC(ha->pdev->devfn);
3136		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3137		ha->mbx_count = MAILBOX_REGISTER_COUNT;
3138		req_length = REQUEST_ENTRY_CNT_83XX;
3139		rsp_length = RESPONSE_ENTRY_CNT_83XX;
3140		ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3141		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3142		ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3143		ha->gid_list_info_size = 8;
3144		ha->optrom_size = OPTROM_SIZE_83XX;
3145		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3146		ha->isp_ops = &qla83xx_isp_ops;
3147		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3148		ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3149		ha->nvram_conf_off = ~0;
3150		ha->nvram_data_off = ~0;
3151	}  else if (IS_QLAFX00(ha)) {
3152		ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
3153		ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
3154		ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
3155		req_length = REQUEST_ENTRY_CNT_FX00;
3156		rsp_length = RESPONSE_ENTRY_CNT_FX00;
3157		ha->isp_ops = &qlafx00_isp_ops;
3158		ha->port_down_retry_count = 30; /* default value */
3159		ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
3160		ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
3161		ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
3162		ha->mr.fw_hbt_en = 1;
3163		ha->mr.host_info_resend = false;
3164		ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
3165	} else if (IS_QLA27XX(ha)) {
3166		ha->portnum = PCI_FUNC(ha->pdev->devfn);
3167		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3168		ha->mbx_count = MAILBOX_REGISTER_COUNT;
3169		req_length = REQUEST_ENTRY_CNT_83XX;
3170		rsp_length = RESPONSE_ENTRY_CNT_83XX;
3171		ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3172		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3173		ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3174		ha->gid_list_info_size = 8;
3175		ha->optrom_size = OPTROM_SIZE_83XX;
3176		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3177		ha->isp_ops = &qla27xx_isp_ops;
3178		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3179		ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3180		ha->nvram_conf_off = ~0;
3181		ha->nvram_data_off = ~0;
3182	} else if (IS_QLA28XX(ha)) {
3183		ha->portnum = PCI_FUNC(ha->pdev->devfn);
3184		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3185		ha->mbx_count = MAILBOX_REGISTER_COUNT;
3186		req_length = REQUEST_ENTRY_CNT_83XX;
3187		rsp_length = RESPONSE_ENTRY_CNT_83XX;
3188		ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3189		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3190		ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3191		ha->gid_list_info_size = 8;
3192		ha->optrom_size = OPTROM_SIZE_28XX;
3193		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3194		ha->isp_ops = &qla27xx_isp_ops;
3195		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX;
3196		ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX;
3197		ha->nvram_conf_off = ~0;
3198		ha->nvram_data_off = ~0;
3199	}
3200
3201	ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
3202	    "mbx_count=%d, req_length=%d, "
3203	    "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
3204	    "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
3205	    "max_fibre_devices=%d.\n",
3206	    ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
3207	    ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
3208	    ha->nvram_npiv_size, ha->max_fibre_devices);
3209	ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
3210	    "isp_ops=%p, flash_conf_off=%d, "
3211	    "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
3212	    ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
3213	    ha->nvram_conf_off, ha->nvram_data_off);
3214
3215	/* Configure PCI I/O space */
3216	ret = ha->isp_ops->iospace_config(ha);
3217	if (ret)
3218		goto iospace_config_failed;
3219
3220	ql_log_pci(ql_log_info, pdev, 0x001d,
3221	    "Found an ISP%04X irq %d iobase 0x%p.\n",
3222	    pdev->device, pdev->irq, ha->iobase);
3223	mutex_init(&ha->vport_lock);
3224	mutex_init(&ha->mq_lock);
3225	init_completion(&ha->mbx_cmd_comp);
3226	complete(&ha->mbx_cmd_comp);
3227	init_completion(&ha->mbx_intr_comp);
3228	init_completion(&ha->dcbx_comp);
3229	init_completion(&ha->lb_portup_comp);
3230
3231	set_bit(0, (unsigned long *) ha->vp_idx_map);
3232
3233	qla2x00_config_dma_addressing(ha);
3234	ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
3235	    "64 Bit addressing is %s.\n",
3236	    ha->flags.enable_64bit_addressing ? "enable" :
3237	    "disable");
3238	ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
3239	if (ret) {
3240		ql_log_pci(ql_log_fatal, pdev, 0x0031,
3241		    "Failed to allocate memory for adapter, aborting.\n");
3242
3243		goto probe_hw_failed;
3244	}
3245
3246	req->max_q_depth = MAX_Q_DEPTH;
3247	if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
3248		req->max_q_depth = ql2xmaxqdepth;
3249
3250
3251	base_vha = qla2x00_create_host(sht, ha);
3252	if (!base_vha) {
3253		ret = -ENOMEM;
3254		goto probe_hw_failed;
3255	}
3256
3257	pci_set_drvdata(pdev, base_vha);
3258	set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3259
3260	host = base_vha->host;
3261	base_vha->req = req;
3262	if (IS_QLA2XXX_MIDTYPE(ha))
3263		base_vha->mgmt_svr_loop_id =
3264			qla2x00_reserve_mgmt_server_loop_id(base_vha);
3265	else
3266		base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3267						base_vha->vp_idx;
3268
3269	/* Setup fcport template structure. */
3270	ha->mr.fcport.vha = base_vha;
3271	ha->mr.fcport.port_type = FCT_UNKNOWN;
3272	ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3273	qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3274	ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3275	ha->mr.fcport.scan_state = 1;
3276
3277	qla2xxx_reset_stats(host, QLA2XX_HW_ERROR | QLA2XX_SHT_LNK_DWN |
3278			    QLA2XX_INT_ERR | QLA2XX_CMD_TIMEOUT |
3279			    QLA2XX_RESET_CMD_ERR | QLA2XX_TGT_SHT_LNK_DOWN);
3280
3281	/* Set the SG table size based on ISP type */
3282	if (!IS_FWI2_CAPABLE(ha)) {
3283		if (IS_QLA2100(ha))
3284			host->sg_tablesize = 32;
3285	} else {
3286		if (!IS_QLA82XX(ha))
3287			host->sg_tablesize = QLA_SG_ALL;
3288	}
3289	host->max_id = ha->max_fibre_devices;
3290	host->cmd_per_lun = 3;
3291	host->unique_id = host->host_no;
3292
3293	if (ql2xenabledif && ql2xenabledif != 2) {
3294		ql_log(ql_log_warn, base_vha, 0x302d,
3295		       "Invalid value for ql2xenabledif, resetting it to default (2)\n");
3296		ql2xenabledif = 2;
3297	}
3298
3299	if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
3300		host->max_cmd_len = 32;
3301	else
3302		host->max_cmd_len = MAX_CMDSZ;
3303	host->max_channel = MAX_BUSES - 1;
3304	/* Older HBAs support only 16-bit LUNs */
3305	if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3306	    ql2xmaxlun > 0xffff)
3307		host->max_lun = 0xffff;
3308	else
3309		host->max_lun = ql2xmaxlun;
3310	host->transportt = qla2xxx_transport_template;
3311	sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
3312
3313	ql_dbg(ql_dbg_init, base_vha, 0x0033,
3314	    "max_id=%d this_id=%d "
3315	    "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
3316	    "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
3317	    host->this_id, host->cmd_per_lun, host->unique_id,
3318	    host->max_cmd_len, host->max_channel, host->max_lun,
3319	    host->transportt, sht->vendor_id);
3320
3321	INIT_WORK(&ha->heartbeat_work, qla_heartbeat_work_fn);
3322
3323	/* Set up the irqs */
3324	ret = qla2x00_request_irqs(ha, rsp);
3325	if (ret)
3326		goto probe_failed;
3327
3328	/* Alloc arrays of request and response ring ptrs */
3329	ret = qla2x00_alloc_queues(ha, req, rsp);
3330	if (ret) {
3331		ql_log(ql_log_fatal, base_vha, 0x003d,
3332		    "Failed to allocate memory for queue pointers..."
3333		    "aborting.\n");
3334		ret = -ENODEV;
3335		goto probe_failed;
3336	}
3337
3338	if (ha->mqenable) {
3339		/* number of hardware queues supported by blk/scsi-mq*/
3340		host->nr_hw_queues = ha->max_qpairs;
3341
3342		ql_dbg(ql_dbg_init, base_vha, 0x0192,
3343			"blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
3344	} else {
3345		if (ql2xnvmeenable) {
3346			host->nr_hw_queues = ha->max_qpairs;
3347			ql_dbg(ql_dbg_init, base_vha, 0x0194,
3348			    "FC-NVMe support is enabled, HW queues=%d\n",
3349			    host->nr_hw_queues);
3350		} else {
3351			ql_dbg(ql_dbg_init, base_vha, 0x0193,
3352			    "blk/scsi-mq disabled.\n");
3353		}
3354	}
3355
3356	qlt_probe_one_stage1(base_vha, ha);
3357
3358	pci_save_state(pdev);
3359
3360	/* Assign back pointers */
3361	rsp->req = req;
3362	req->rsp = rsp;
3363
3364	if (IS_QLAFX00(ha)) {
3365		ha->rsp_q_map[0] = rsp;
3366		ha->req_q_map[0] = req;
3367		set_bit(0, ha->req_qid_map);
3368		set_bit(0, ha->rsp_qid_map);
3369	}
3370
3371	/* FWI2-capable only. */
3372	req->req_q_in = &ha->iobase->isp24.req_q_in;
3373	req->req_q_out = &ha->iobase->isp24.req_q_out;
3374	rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3375	rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
3376	if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
3377	    IS_QLA28XX(ha)) {
3378		req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3379		req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3380		rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3381		rsp->rsp_q_out =  &ha->mqiobase->isp25mq.rsp_q_out;
3382	}
3383
3384	if (IS_QLAFX00(ha)) {
3385		req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3386		req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3387		rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3388		rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3389	}
3390
3391	if (IS_P3P_TYPE(ha)) {
3392		req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3393		rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3394		rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3395	}
3396
3397	ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3398	    "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3399	    ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3400	ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3401	    "req->req_q_in=%p req->req_q_out=%p "
3402	    "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3403	    req->req_q_in, req->req_q_out,
3404	    rsp->rsp_q_in, rsp->rsp_q_out);
3405	ql_dbg(ql_dbg_init, base_vha, 0x003e,
3406	    "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3407	    ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3408	ql_dbg(ql_dbg_init, base_vha, 0x003f,
3409	    "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3410	    req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
3411
3412	ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM | WQ_PERCPU, 0);
3413	if (unlikely(!ha->wq)) {
3414		ret = -ENOMEM;
3415		goto probe_failed;
3416	}
3417
3418	if (ha->isp_ops->initialize_adapter(base_vha)) {
3419		ql_log(ql_log_fatal, base_vha, 0x00d6,
3420		    "Failed to initialize adapter - Adapter flags %x.\n",
3421		    base_vha->device_flags);
3422
3423		if (IS_QLA82XX(ha)) {
3424			qla82xx_idc_lock(ha);
3425			qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3426				QLA8XXX_DEV_FAILED);
3427			qla82xx_idc_unlock(ha);
3428			ql_log(ql_log_fatal, base_vha, 0x00d7,
3429			    "HW State: FAILED.\n");
3430		} else if (IS_QLA8044(ha)) {
3431			qla8044_idc_lock(ha);
3432			qla8044_wr_direct(base_vha,
3433				QLA8044_CRB_DEV_STATE_INDEX,
3434				QLA8XXX_DEV_FAILED);
3435			qla8044_idc_unlock(ha);
3436			ql_log(ql_log_fatal, base_vha, 0x0150,
3437			    "HW State: FAILED.\n");
3438		}
3439
3440		ret = -ENODEV;
3441		goto probe_failed;
3442	}
3443
3444	if (IS_QLAFX00(ha))
3445		host->can_queue = QLAFX00_MAX_CANQUEUE;
3446	else
3447		host->can_queue = req->num_outstanding_cmds - 10;
3448
3449	ql_dbg(ql_dbg_init, base_vha, 0x0032,
3450	    "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3451	    host->can_queue, base_vha->req,
3452	    base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3453
3454	/* Check if FW supports MQ or not for ISP25xx */
3455	if (IS_QLA25XX(ha) && !(ha->fw_attributes & BIT_6))
3456		ha->mqenable = 0;
3457
3458	if (ha->mqenable) {
3459		bool startit = !!(host->active_mode & MODE_INITIATOR);
3460
3461		/* Create start of day qpairs for Block MQ */
3462		for (i = 0; i < ha->max_qpairs; i++)
3463			qla2xxx_create_qpair(base_vha, 5, 0, startit);
3464	}
3465	qla_init_iocb_limit(base_vha);
3466
3467	if (ha->flags.running_gold_fw)
3468		goto skip_dpc;
3469
3470	/*
3471	 * Startup the kernel thread for this host adapter
3472	 */
3473	ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
3474	    "%s_dpc", base_vha->host_str);
3475	if (IS_ERR(ha->dpc_thread)) {
3476		ql_log(ql_log_fatal, base_vha, 0x00ed,
3477		    "Failed to start DPC thread.\n");
3478		ret = PTR_ERR(ha->dpc_thread);
3479		ha->dpc_thread = NULL;
3480		goto probe_failed;
3481	}
3482	ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3483	    "DPC thread started successfully.\n");
3484
3485	/*
3486	 * If we're not coming up in initiator mode, we might sit for
3487	 * a while without waking up the dpc thread, which leads to a
3488	 * stuck process warning.  So just kick the dpc once here and
3489	 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3490	 */
3491	qla2xxx_wake_dpc(base_vha);
3492
3493	INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3494
3495	if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3496		sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3497		ha->dpc_lp_wq =
3498			alloc_ordered_workqueue("%s", WQ_MEM_RECLAIM, wq_name);
3499		INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3500
3501		sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3502		ha->dpc_hp_wq =
3503			alloc_ordered_workqueue("%s", WQ_MEM_RECLAIM, wq_name);
3504		INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3505		INIT_WORK(&ha->idc_state_handler,
3506		    qla83xx_idc_state_handler_work);
3507		INIT_WORK(&ha->nic_core_unrecoverable,
3508		    qla83xx_nic_core_unrecoverable_work);
3509	}
3510
3511skip_dpc:
3512	list_add_tail(&base_vha->list, &ha->vp_list);
3513	base_vha->host->irq = ha->pdev->irq;
3514
3515	/* Initialized the timer */
3516	qla2x00_start_timer(base_vha, WATCH_INTERVAL);
3517	ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3518	    "Started qla2x00_timer with "
3519	    "interval=%d.\n", WATCH_INTERVAL);
3520	ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3521	    "Detected hba at address=%p.\n",
3522	    ha);
3523
3524	if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
3525		if (ha->fw_attributes & BIT_4) {
3526			int prot = 0, guard;
3527
3528			base_vha->flags.difdix_supported = 1;
3529			ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3530			    "Registering for DIF/DIX type 1 and 3 protection.\n");
3531			if (ql2xprotmask)
3532				scsi_host_set_prot(host, ql2xprotmask);
3533			else
3534				scsi_host_set_prot(host,
3535				    prot | SHOST_DIF_TYPE1_PROTECTION
3536				    | SHOST_DIF_TYPE2_PROTECTION
3537				    | SHOST_DIF_TYPE3_PROTECTION
3538				    | SHOST_DIX_TYPE1_PROTECTION
3539				    | SHOST_DIX_TYPE2_PROTECTION
3540				    | SHOST_DIX_TYPE3_PROTECTION);
3541
3542			guard = SHOST_DIX_GUARD_CRC;
3543
3544			if (IS_PI_IPGUARD_CAPABLE(ha) &&
3545			    (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3546				guard |= SHOST_DIX_GUARD_IP;
3547
3548			if (ql2xprotguard)
3549				scsi_host_set_guard(host, ql2xprotguard);
3550			else
3551				scsi_host_set_guard(host, guard);
3552		} else
3553			base_vha->flags.difdix_supported = 0;
3554	}
3555
3556	ha->isp_ops->enable_intrs(ha);
3557
3558	if (IS_QLAFX00(ha)) {
3559		ret = qlafx00_fx_disc(base_vha,
3560			&base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3561		host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3562		    QLA_SG_ALL : 128;
3563	}
3564
3565	if (IS_T10_PI_CAPABLE(base_vha->hw))
3566		host->dma_alignment = 0x7;
3567
3568	ret = scsi_add_host(host, &pdev->dev);
3569	if (ret)
3570		goto probe_failed;
3571
3572	base_vha->flags.init_done = 1;
3573	base_vha->flags.online = 1;
3574	ha->prev_minidump_failed = 0;
3575
3576	ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3577	    "Init done and hba is online.\n");
3578
3579	if (qla_ini_mode_enabled(base_vha) ||
3580		qla_dual_mode_enabled(base_vha))
3581		scsi_scan_host(host);
3582	else
3583		ql_log(ql_log_info, base_vha, 0x0122,
3584			"skipping scsi_scan_host() for non-initiator port\n");
3585
3586	qla2x00_alloc_sysfs_attr(base_vha);
3587
3588	if (IS_QLAFX00(ha)) {
3589		ret = qlafx00_fx_disc(base_vha,
3590			&base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3591
3592		/* Register system information */
3593		ret =  qlafx00_fx_disc(base_vha,
3594			&base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3595	}
3596
3597	qla2x00_init_host_attr(base_vha);
3598
3599	qla2x00_dfs_setup(base_vha);
3600
3601	ql_log(ql_log_info, base_vha, 0x00fb,
3602	    "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
3603	ql_log(ql_log_info, base_vha, 0x00fc,
3604	    "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3605	    pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info,
3606						       sizeof(pci_info)),
3607	    pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3608	    base_vha->host_no,
3609	    ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
3610
3611	qlt_add_target(ha, base_vha);
3612
3613	clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3614
3615	if (test_bit(UNLOADING, &base_vha->dpc_flags))
3616		return -ENODEV;
3617
3618	return 0;
3619
3620probe_failed:
3621	qla_enode_stop(base_vha);
3622	qla_edb_stop(base_vha);
3623	vfree(base_vha->scan.l);
3624	if (base_vha->gnl.l) {
3625		dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3626				base_vha->gnl.l, base_vha->gnl.ldma);
3627		base_vha->gnl.l = NULL;
3628	}
3629
3630	if (base_vha->timer_active)
3631		qla2x00_stop_timer(base_vha);
3632	base_vha->flags.online = 0;
3633	if (ha->dpc_thread) {
3634		struct task_struct *t = ha->dpc_thread;
3635
3636		ha->dpc_thread = NULL;
3637		kthread_stop(t);
3638	}
3639
3640	qla2x00_free_device(base_vha);
3641	scsi_host_put(base_vha->host);
3642	/*
3643	 * Need to NULL out local req/rsp after
3644	 * qla2x00_free_device => qla2x00_free_queues frees
3645	 * what these are pointing to. Or else we'll
3646	 * fall over below in qla2x00_free_req/rsp_que.
3647	 */
3648	req = NULL;
3649	rsp = NULL;
3650
3651probe_hw_failed:
3652	qla2x00_mem_free(ha);
3653	qla2x00_free_req_que(ha, req);
3654	qla2x00_free_rsp_que(ha, rsp);
3655	qla2x00_clear_drv_active(ha);
3656
3657iospace_config_failed:
3658	if (IS_P3P_TYPE(ha)) {
3659		if (!ha->nx_pcibase)
3660			iounmap((device_reg_t *)ha->nx_pcibase);
3661		if (!ql2xdbwr)
3662			iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3663	} else {
3664		if (ha->iobase)
3665			iounmap(ha->iobase);
3666		if (ha->cregbase)
3667			iounmap(ha->cregbase);
3668	}
3669	pci_release_selected_regions(ha->pdev, ha->bars);
3670	kfree(ha);
3671
3672disable_device:
3673	pci_disable_device(pdev);
3674	return ret;
3675}
3676
3677static void __qla_set_remove_flag(scsi_qla_host_t *base_vha)
3678{
3679	scsi_qla_host_t *vp;
3680	unsigned long flags;
3681	struct qla_hw_data *ha;
3682
3683	if (!base_vha)
3684		return;
3685
3686	ha = base_vha->hw;
3687
3688	spin_lock_irqsave(&ha->vport_slock, flags);
3689	list_for_each_entry(vp, &ha->vp_list, list)
3690		set_bit(PFLG_DRIVER_REMOVING, &vp->pci_flags);
3691
3692	/*
3693	 * Indicate device removal to prevent future board_disable
3694	 * and wait until any pending board_disable has completed.
3695	 */
3696	set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3697	spin_unlock_irqrestore(&ha->vport_slock, flags);
3698}
3699
3700static void
3701qla2x00_shutdown(struct pci_dev *pdev)
3702{
3703	scsi_qla_host_t *vha;
3704	struct qla_hw_data  *ha;
3705
3706	vha = pci_get_drvdata(pdev);
3707	ha = vha->hw;
3708
3709	ql_log(ql_log_info, vha, 0xfffa,
3710		"Adapter shutdown\n");
3711
3712	/*
3713	 * Prevent future board_disable and wait
3714	 * until any pending board_disable has completed.
3715	 */
3716	__qla_set_remove_flag(vha);
3717	cancel_work_sync(&ha->board_disable);
3718
3719	if (!atomic_read(&pdev->enable_cnt))
3720		return;
3721
3722	/* Notify ISPFX00 firmware */
3723	if (IS_QLAFX00(ha))
3724		qlafx00_driver_shutdown(vha, 20);
3725
3726	/* Turn-off FCE trace */
3727	if (ha->flags.fce_enabled) {
3728		qla2x00_disable_fce_trace(vha, NULL, NULL);
3729		ha->flags.fce_enabled = 0;
3730	}
3731
3732	/* Turn-off EFT trace */
3733	if (ha->eft)
3734		qla2x00_disable_eft_trace(vha);
3735
3736	if (IS_QLA25XX(ha) ||  IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3737	    IS_QLA28XX(ha)) {
3738		if (ha->flags.fw_started)
3739			qla2x00_abort_isp_cleanup(vha);
3740	} else {
3741		/* Stop currently executing firmware. */
3742		qla2x00_try_to_stop_firmware(vha);
3743	}
3744
3745	/* Disable timer */
3746	if (vha->timer_active)
3747		qla2x00_stop_timer(vha);
3748
3749	/* Turn adapter off line */
3750	vha->flags.online = 0;
3751
3752	/* turn-off interrupts on the card */
3753	if (ha->interrupts_on) {
3754		vha->flags.init_done = 0;
3755		ha->isp_ops->disable_intrs(ha);
3756	}
3757
3758	qla2x00_free_irqs(vha);
3759
3760	qla2x00_free_fw_dump(ha);
3761
3762	pci_disable_device(pdev);
3763	ql_log(ql_log_info, vha, 0xfffe,
3764		"Adapter shutdown successfully.\n");
3765}
3766
3767/* Deletes all the virtual ports for a given ha */
3768static void
3769qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
3770{
3771	scsi_qla_host_t *vha;
3772	unsigned long flags;
3773
3774	mutex_lock(&ha->vport_lock);
3775	while (ha->cur_vport_count) {
3776		spin_lock_irqsave(&ha->vport_slock, flags);
3777
3778		BUG_ON(base_vha->list.next == &ha->vp_list);
3779		/* This assumes first entry in ha->vp_list is always base vha */
3780		vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
3781		scsi_host_get(vha->host);
3782
3783		spin_unlock_irqrestore(&ha->vport_slock, flags);
3784		mutex_unlock(&ha->vport_lock);
3785
3786		qla_nvme_delete(vha);
3787
3788		fc_vport_terminate(vha->fc_vport);
3789		scsi_host_put(vha->host);
3790
3791		mutex_lock(&ha->vport_lock);
3792	}
3793	mutex_unlock(&ha->vport_lock);
3794}
3795
3796/* Stops all deferred work threads */
3797static void
3798qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3799{
3800	/* Cancel all work and destroy DPC workqueues */
3801	if (ha->dpc_lp_wq) {
3802		cancel_work_sync(&ha->idc_aen);
3803		destroy_workqueue(ha->dpc_lp_wq);
3804		ha->dpc_lp_wq = NULL;
3805	}
3806
3807	if (ha->dpc_hp_wq) {
3808		cancel_work_sync(&ha->nic_core_reset);
3809		cancel_work_sync(&ha->idc_state_handler);
3810		cancel_work_sync(&ha->nic_core_unrecoverable);
3811		destroy_workqueue(ha->dpc_hp_wq);
3812		ha->dpc_hp_wq = NULL;
3813	}
3814
3815	/* Kill the kernel thread for this host */
3816	if (ha->dpc_thread) {
3817		struct task_struct *t = ha->dpc_thread;
3818
3819		/*
3820		 * qla2xxx_wake_dpc checks for ->dpc_thread
3821		 * so we need to zero it out.
3822		 */
3823		ha->dpc_thread = NULL;
3824		kthread_stop(t);
3825	}
3826}
3827
3828static void
3829qla2x00_unmap_iobases(struct qla_hw_data *ha)
3830{
3831	if (IS_QLA82XX(ha)) {
3832
3833		iounmap((device_reg_t *)ha->nx_pcibase);
3834		if (!ql2xdbwr)
3835			iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3836	} else {
3837		if (ha->iobase)
3838			iounmap(ha->iobase);
3839
3840		if (ha->cregbase)
3841			iounmap(ha->cregbase);
3842
3843		if (ha->mqiobase)
3844			iounmap(ha->mqiobase);
3845
3846		if (ha->msixbase)
3847			iounmap(ha->msixbase);
3848	}
3849}
3850
3851static void
3852qla2x00_clear_drv_active(struct qla_hw_data *ha)
3853{
3854	if (IS_QLA8044(ha)) {
3855		qla8044_idc_lock(ha);
3856		qla8044_clear_drv_active(ha);
3857		qla8044_idc_unlock(ha);
3858	} else if (IS_QLA82XX(ha)) {
3859		qla82xx_idc_lock(ha);
3860		qla82xx_clear_drv_active(ha);
3861		qla82xx_idc_unlock(ha);
3862	}
3863}
3864
3865static void
3866qla2x00_remove_one(struct pci_dev *pdev)
3867{
3868	scsi_qla_host_t *base_vha;
3869	struct qla_hw_data  *ha;
3870
3871	base_vha = pci_get_drvdata(pdev);
3872	ha = base_vha->hw;
3873	ql_log(ql_log_info, base_vha, 0xb079,
3874	    "Removing driver\n");
3875	__qla_set_remove_flag(base_vha);
3876	cancel_work_sync(&ha->board_disable);
3877
3878	/*
3879	 * If the PCI device is disabled then there was a PCI-disconnect and
3880	 * qla2x00_disable_board_on_pci_error has taken care of most of the
3881	 * resources.
3882	 */
3883	if (!atomic_read(&pdev->enable_cnt)) {
3884		dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3885		    base_vha->gnl.l, base_vha->gnl.ldma);
3886		base_vha->gnl.l = NULL;
3887		scsi_host_put(base_vha->host);
3888		kfree(ha);
3889		pci_set_drvdata(pdev, NULL);
3890		return;
3891	}
3892	qla2x00_wait_for_hba_ready(base_vha);
3893
3894	/*
3895	 * if UNLOADING flag is already set, then continue unload,
3896	 * where it was set first.
3897	 */
3898	if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags))
3899		return;
3900
3901	if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3902	    IS_QLA28XX(ha)) {
3903		if (ha->flags.fw_started)
3904			qla2x00_abort_isp_cleanup(base_vha);
3905	} else if (!IS_QLAFX00(ha)) {
3906		if (IS_QLA8031(ha)) {
3907			ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3908			    "Clearing fcoe driver presence.\n");
3909			if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3910				ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3911				    "Error while clearing DRV-Presence.\n");
3912		}
3913
3914		qla2x00_try_to_stop_firmware(base_vha);
3915	}
3916
3917	qla2x00_wait_for_sess_deletion(base_vha);
3918
3919	qla_nvme_delete(base_vha);
3920
3921	dma_free_coherent(&ha->pdev->dev,
3922		base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
3923
3924	base_vha->gnl.l = NULL;
3925	qla_enode_stop(base_vha);
3926	qla_edb_stop(base_vha);
3927
3928	vfree(base_vha->scan.l);
3929
3930	if (IS_QLAFX00(ha))
3931		qlafx00_driver_shutdown(base_vha, 20);
3932
3933	qla2x00_delete_all_vps(ha, base_vha);
3934
3935	qla2x00_dfs_remove(base_vha);
3936
3937	qla84xx_put_chip(base_vha);
3938
3939	/* Disable timer */
3940	if (base_vha->timer_active)
3941		qla2x00_stop_timer(base_vha);
3942
3943	base_vha->flags.online = 0;
3944
3945	/* free DMA memory */
3946	if (ha->exlogin_buf)
3947		qla2x00_free_exlogin_buffer(ha);
3948
3949	/* free DMA memory */
3950	if (ha->exchoffld_buf)
3951		qla2x00_free_exchoffld_buffer(ha);
3952
3953	qla2x00_destroy_deferred_work(ha);
3954
3955	qlt_remove_target(ha, base_vha);
3956
3957	qla2x00_free_sysfs_attr(base_vha, true);
3958
3959	fc_remove_host(base_vha->host);
3960
3961	scsi_remove_host(base_vha->host);
3962
3963	qla2x00_free_device(base_vha);
3964
3965	qla2x00_clear_drv_active(ha);
3966
3967	scsi_host_put(base_vha->host);
3968
3969	qla2x00_unmap_iobases(ha);
3970
3971	pci_release_selected_regions(ha->pdev, ha->bars);
3972	kfree(ha);
3973
3974	pci_disable_device(pdev);
3975}
3976
3977static inline void
3978qla24xx_free_purex_list(struct purex_list *list)
3979{
3980	struct purex_item *item, *next;
3981	ulong flags;
3982
3983	spin_lock_irqsave(&list->lock, flags);
3984	list_for_each_entry_safe(item, next, &list->head, list) {
3985		list_del(&item->list);
3986		if (item == &item->vha->default_item)
3987			continue;
3988		kfree(item);
3989	}
3990	spin_unlock_irqrestore(&list->lock, flags);
3991}
3992
3993static void
3994qla2x00_free_device(scsi_qla_host_t *vha)
3995{
3996	struct qla_hw_data *ha = vha->hw;
3997
3998	qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3999
4000	/* Disable timer */
4001	if (vha->timer_active)
4002		qla2x00_stop_timer(vha);
4003
4004	qla25xx_delete_queues(vha);
4005	vha->flags.online = 0;
4006
4007	/* turn-off interrupts on the card */
4008	if (ha->interrupts_on) {
4009		vha->flags.init_done = 0;
4010		ha->isp_ops->disable_intrs(ha);
4011	}
4012
4013	qla2x00_free_fcports(vha);
4014
4015	qla2x00_free_irqs(vha);
4016
4017	/* Flush the work queue and remove it */
4018	if (ha->wq) {
4019		destroy_workqueue(ha->wq);
4020		ha->wq = NULL;
4021	}
4022
4023
4024	qla24xx_free_purex_list(&vha->purex_list);
4025
4026	qla2x00_mem_free(ha);
4027
4028	qla82xx_md_free(vha);
4029
4030	qla_edif_sadb_release_free_pool(ha);
4031	qla_edif_sadb_release(ha);
4032
4033	qla2x00_free_queues(ha);
4034}
4035
4036void qla2x00_free_fcports(struct scsi_qla_host *vha)
4037{
4038	fc_port_t *fcport, *tfcport;
4039
4040	list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list)
4041		qla2x00_free_fcport(fcport);
4042}
4043
4044static inline void
4045qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport)
4046{
4047	int now;
4048
4049	if (!fcport->rport)
4050		return;
4051
4052	if (fcport->rport) {
4053		ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
4054		    "%s %8phN. rport %p roles %x\n",
4055		    __func__, fcport->port_name, fcport->rport,
4056		    fcport->rport->roles);
4057		fc_remote_port_delete(fcport->rport);
4058	}
4059	qlt_do_generation_tick(vha, &now);
4060}
4061
4062/*
4063 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
4064 *
4065 * Input: ha = adapter block pointer.  fcport = port structure pointer.
4066 *
4067 * Return: None.
4068 *
4069 * Context:
4070 */
4071void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
4072    int do_login)
4073{
4074	if (IS_QLAFX00(vha->hw)) {
4075		qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
4076		qla2x00_schedule_rport_del(vha, fcport);
4077		return;
4078	}
4079
4080	if (atomic_read(&fcport->state) == FCS_ONLINE &&
4081	    vha->vp_idx == fcport->vha->vp_idx) {
4082		qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
4083		qla2x00_schedule_rport_del(vha, fcport);
4084	}
4085
4086	/*
4087	 * We may need to retry the login, so don't change the state of the
4088	 * port but do the retries.
4089	 */
4090	if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
4091		qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
4092
4093	if (!do_login)
4094		return;
4095
4096	set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4097}
4098
4099void
4100qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha)
4101{
4102	fc_port_t *fcport;
4103
4104	ql_dbg(ql_dbg_disc, vha, 0x20f1,
4105	    "Mark all dev lost\n");
4106
4107	list_for_each_entry(fcport, &vha->vp_fcports, list) {
4108		if (ql2xfc2target &&
4109		    fcport->loop_id != FC_NO_LOOP_ID &&
4110		    (fcport->flags & FCF_FCP2_DEVICE) &&
4111		    fcport->port_type == FCT_TARGET &&
4112		    !qla2x00_reset_active(vha)) {
4113			ql_dbg(ql_dbg_disc, vha, 0x211a,
4114			       "Delaying session delete for FCP2 flags 0x%x port_type = 0x%x port_id=%06x %phC",
4115			       fcport->flags, fcport->port_type,
4116			       fcport->d_id.b24, fcport->port_name);
4117			continue;
4118		}
4119		fcport->scan_state = 0;
4120		qlt_schedule_sess_for_deletion(fcport);
4121	}
4122}
4123
4124static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha)
4125{
4126	int i;
4127
4128	if (IS_FWI2_CAPABLE(ha))
4129		return;
4130
4131	for (i = 0; i < SNS_FIRST_LOOP_ID; i++)
4132		set_bit(i, ha->loop_id_map);
4133	set_bit(MANAGEMENT_SERVER, ha->loop_id_map);
4134	set_bit(BROADCAST, ha->loop_id_map);
4135}
4136
4137/*
4138* qla2x00_mem_alloc
4139*      Allocates adapter memory.
4140*
4141* Returns:
4142*      0  = success.
4143*      !0  = failure.
4144*/
4145static int
4146qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
4147	struct req_que **req, struct rsp_que **rsp)
4148{
4149	char	name[16];
4150	int rc;
4151
4152	if (QLA_TGT_MODE_ENABLED() || EDIF_CAP(ha)) {
4153		ha->vp_map = kcalloc(MAX_MULTI_ID_FABRIC, sizeof(struct qla_vp_map), GFP_KERNEL);
4154		if (!ha->vp_map)
4155			goto fail;
4156	}
4157
4158	ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
4159		&ha->init_cb_dma, GFP_KERNEL);
4160	if (!ha->init_cb)
4161		goto fail_free_vp_map;
4162
4163	rc = btree_init32(&ha->host_map);
4164	if (rc)
4165		goto fail_free_init_cb;
4166
4167	if (qlt_mem_alloc(ha) < 0)
4168		goto fail_free_btree;
4169
4170	ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
4171		qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
4172	if (!ha->gid_list)
4173		goto fail_free_tgt_mem;
4174
4175	ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
4176	if (!ha->srb_mempool)
4177		goto fail_free_gid_list;
4178
4179	if (IS_P3P_TYPE(ha) || IS_QLA27XX(ha) || (ql2xsecenable && IS_QLA28XX(ha))) {
4180		/* Allocate cache for CT6 Ctx. */
4181		if (!ctx_cachep) {
4182			ctx_cachep = kmem_cache_create("qla2xxx_ctx",
4183				sizeof(struct ct6_dsd), 0,
4184				SLAB_HWCACHE_ALIGN, NULL);
4185			if (!ctx_cachep)
4186				goto fail_free_srb_mempool;
4187		}
4188		ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
4189			ctx_cachep);
4190		if (!ha->ctx_mempool)
4191			goto fail_free_srb_mempool;
4192		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
4193		    "ctx_cachep=%p ctx_mempool=%p.\n",
4194		    ctx_cachep, ha->ctx_mempool);
4195	}
4196
4197	/* Get memory for cached NVRAM */
4198	ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
4199	if (!ha->nvram)
4200		goto fail_free_ctx_mempool;
4201
4202	snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
4203		ha->pdev->device);
4204	ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4205		DMA_POOL_SIZE, 8, 0);
4206	if (!ha->s_dma_pool)
4207		goto fail_free_nvram;
4208
4209	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
4210	    "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
4211	    ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
4212
4213	if (IS_P3P_TYPE(ha) || ql2xenabledif || (IS_QLA28XX(ha) && ql2xsecenable)) {
4214		ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4215			DSD_LIST_DMA_POOL_SIZE, 8, 0);
4216		if (!ha->dl_dma_pool) {
4217			ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
4218			    "Failed to allocate memory for dl_dma_pool.\n");
4219			goto fail_s_dma_pool;
4220		}
4221
4222		ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4223			FCP_CMND_DMA_POOL_SIZE, 8, 0);
4224		if (!ha->fcp_cmnd_dma_pool) {
4225			ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
4226			    "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
4227			goto fail_dl_dma_pool;
4228		}
4229
4230		if (ql2xenabledif) {
4231			u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE;
4232			struct dsd_dma *dsd, *nxt;
4233			uint i;
4234			/* Creata a DMA pool of buffers for DIF bundling */
4235			ha->dif_bundl_pool = dma_pool_create(name,
4236			    &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0);
4237			if (!ha->dif_bundl_pool) {
4238				ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4239				    "%s: failed create dif_bundl_pool\n",
4240				    __func__);
4241				goto fail_dif_bundl_dma_pool;
4242			}
4243
4244			INIT_LIST_HEAD(&ha->pool.good.head);
4245			INIT_LIST_HEAD(&ha->pool.unusable.head);
4246			ha->pool.good.count = 0;
4247			ha->pool.unusable.count = 0;
4248			for (i = 0; i < 128; i++) {
4249				dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC);
4250				if (!dsd) {
4251					ql_dbg_pci(ql_dbg_init, ha->pdev,
4252					    0xe0ee, "%s: failed alloc dsd\n",
4253					    __func__);
4254					return -ENOMEM;
4255				}
4256				ha->dif_bundle_kallocs++;
4257
4258				dsd->dsd_addr = dma_pool_alloc(
4259				    ha->dif_bundl_pool, GFP_ATOMIC,
4260				    &dsd->dsd_list_dma);
4261				if (!dsd->dsd_addr) {
4262					ql_dbg_pci(ql_dbg_init, ha->pdev,
4263					    0xe0ee,
4264					    "%s: failed alloc ->dsd_addr\n",
4265					    __func__);
4266					kfree(dsd);
4267					ha->dif_bundle_kallocs--;
4268					continue;
4269				}
4270				ha->dif_bundle_dma_allocs++;
4271
4272				/*
4273				 * if DMA buffer crosses 4G boundary,
4274				 * put it on bad list
4275				 */
4276				if (MSD(dsd->dsd_list_dma) ^
4277				    MSD(dsd->dsd_list_dma + bufsize)) {
4278					list_add_tail(&dsd->list,
4279					    &ha->pool.unusable.head);
4280					ha->pool.unusable.count++;
4281				} else {
4282					list_add_tail(&dsd->list,
4283					    &ha->pool.good.head);
4284					ha->pool.good.count++;
4285				}
4286			}
4287
4288			/* return the good ones back to the pool */
4289			list_for_each_entry_safe(dsd, nxt,
4290			    &ha->pool.good.head, list) {
4291				list_del(&dsd->list);
4292				dma_pool_free(ha->dif_bundl_pool,
4293				    dsd->dsd_addr, dsd->dsd_list_dma);
4294				ha->dif_bundle_dma_allocs--;
4295				kfree(dsd);
4296				ha->dif_bundle_kallocs--;
4297			}
4298
4299			ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4300			    "%s: dif dma pool (good=%u unusable=%u)\n",
4301			    __func__, ha->pool.good.count,
4302			    ha->pool.unusable.count);
4303		}
4304
4305		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
4306		    "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n",
4307		    ha->dl_dma_pool, ha->fcp_cmnd_dma_pool,
4308		    ha->dif_bundl_pool);
4309	}
4310
4311	/* Allocate memory for SNS commands */
4312	if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
4313	/* Get consistent memory allocated for SNS commands */
4314		ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
4315		sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
4316		if (!ha->sns_cmd)
4317			goto fail_dma_pool;
4318		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
4319		    "sns_cmd: %p.\n", ha->sns_cmd);
4320	} else {
4321	/* Get consistent memory allocated for MS IOCB */
4322		ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4323			&ha->ms_iocb_dma);
4324		if (!ha->ms_iocb)
4325			goto fail_dma_pool;
4326	/* Get consistent memory allocated for CT SNS commands */
4327		ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
4328			sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
4329		if (!ha->ct_sns)
4330			goto fail_free_ms_iocb;
4331		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
4332		    "ms_iocb=%p ct_sns=%p.\n",
4333		    ha->ms_iocb, ha->ct_sns);
4334	}
4335
4336	/* Allocate memory for request ring */
4337	*req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
4338	if (!*req) {
4339		ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
4340		    "Failed to allocate memory for req.\n");
4341		goto fail_req;
4342	}
4343	(*req)->length = req_len;
4344	(*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
4345		((*req)->length + 1) * sizeof(request_t),
4346		&(*req)->dma, GFP_KERNEL);
4347	if (!(*req)->ring) {
4348		ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
4349		    "Failed to allocate memory for req_ring.\n");
4350		goto fail_req_ring;
4351	}
4352	/* Allocate memory for response ring */
4353	*rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
4354	if (!*rsp) {
4355		ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
4356		    "Failed to allocate memory for rsp.\n");
4357		goto fail_rsp;
4358	}
4359	(*rsp)->hw = ha;
4360	(*rsp)->length = rsp_len;
4361	(*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
4362		((*rsp)->length + 1) * sizeof(response_t),
4363		&(*rsp)->dma, GFP_KERNEL);
4364	if (!(*rsp)->ring) {
4365		ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
4366		    "Failed to allocate memory for rsp_ring.\n");
4367		goto fail_rsp_ring;
4368	}
4369	(*req)->rsp = *rsp;
4370	(*rsp)->req = *req;
4371	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
4372	    "req=%p req->length=%d req->ring=%p rsp=%p "
4373	    "rsp->length=%d rsp->ring=%p.\n",
4374	    *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
4375	    (*rsp)->ring);
4376	/* Allocate memory for NVRAM data for vports */
4377	if (ha->nvram_npiv_size) {
4378		ha->npiv_info = kcalloc(ha->nvram_npiv_size,
4379					sizeof(struct qla_npiv_entry),
4380					GFP_KERNEL);
4381		if (!ha->npiv_info) {
4382			ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
4383			    "Failed to allocate memory for npiv_info.\n");
4384			goto fail_npiv_info;
4385		}
4386	} else
4387		ha->npiv_info = NULL;
4388
4389	/* Get consistent memory allocated for EX-INIT-CB. */
4390	if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
4391	    IS_QLA28XX(ha)) {
4392		ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4393		    &ha->ex_init_cb_dma);
4394		if (!ha->ex_init_cb)
4395			goto fail_ex_init_cb;
4396		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4397		    "ex_init_cb=%p.\n", ha->ex_init_cb);
4398	}
4399
4400	/* Get consistent memory allocated for Special Features-CB. */
4401	if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
4402		ha->sf_init_cb = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL,
4403						&ha->sf_init_cb_dma);
4404		if (!ha->sf_init_cb)
4405			goto fail_sf_init_cb;
4406		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0199,
4407			   "sf_init_cb=%p.\n", ha->sf_init_cb);
4408	}
4409
4410
4411	/* Get consistent memory allocated for Async Port-Database. */
4412	if (!IS_FWI2_CAPABLE(ha)) {
4413		ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4414			&ha->async_pd_dma);
4415		if (!ha->async_pd)
4416			goto fail_async_pd;
4417		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4418		    "async_pd=%p.\n", ha->async_pd);
4419	}
4420
4421	INIT_LIST_HEAD(&ha->vp_list);
4422
4423	/* Allocate memory for our loop_id bitmap */
4424	ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE),
4425				  sizeof(long),
4426				  GFP_KERNEL);
4427	if (!ha->loop_id_map)
4428		goto fail_loop_id_map;
4429	else {
4430		qla2x00_set_reserved_loop_ids(ha);
4431		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
4432		    "loop_id_map=%p.\n", ha->loop_id_map);
4433	}
4434
4435	ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4436	    SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4437	if (!ha->sfp_data) {
4438		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4439		    "Unable to allocate memory for SFP read-data.\n");
4440		goto fail_sfp_data;
4441	}
4442
4443	ha->flt = dma_alloc_coherent(&ha->pdev->dev,
4444	    sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma,
4445	    GFP_KERNEL);
4446	if (!ha->flt) {
4447		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4448		    "Unable to allocate memory for FLT.\n");
4449		goto fail_flt_buffer;
4450	}
4451
4452	/* allocate the purex dma pool */
4453	ha->purex_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4454	    ELS_MAX_PAYLOAD, 8, 0);
4455
4456	if (!ha->purex_dma_pool) {
4457		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4458		    "Unable to allocate purex_dma_pool.\n");
4459		goto fail_flt;
4460	}
4461
4462	ha->elsrej.size = sizeof(struct fc_els_ls_rjt) + 16;
4463	ha->elsrej.c = dma_alloc_coherent(&ha->pdev->dev,
4464					  ha->elsrej.size,
4465					  &ha->elsrej.cdma,
4466					  GFP_KERNEL);
4467	if (!ha->elsrej.c) {
4468		ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff,
4469		    "Alloc failed for els reject cmd.\n");
4470		goto fail_elsrej;
4471	}
4472	ha->elsrej.c->er_cmd = ELS_LS_RJT;
4473	ha->elsrej.c->er_reason = ELS_RJT_LOGIC;
4474	ha->elsrej.c->er_explan = ELS_EXPL_UNAB_DATA;
4475
4476	ha->lsrjt.size = sizeof(struct fcnvme_ls_rjt);
4477	ha->lsrjt.c = dma_alloc_coherent(&ha->pdev->dev, ha->lsrjt.size,
4478			&ha->lsrjt.cdma, GFP_KERNEL);
4479	if (!ha->lsrjt.c) {
4480		ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff,
4481			   "Alloc failed for nvme fc reject cmd.\n");
4482		goto fail_lsrjt;
4483	}
4484
4485	return 0;
4486
4487fail_lsrjt:
4488	dma_free_coherent(&ha->pdev->dev, ha->elsrej.size,
4489			  ha->elsrej.c, ha->elsrej.cdma);
4490fail_elsrej:
4491	dma_pool_destroy(ha->purex_dma_pool);
4492fail_flt:
4493	dma_free_coherent(&ha->pdev->dev, sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE,
4494	    ha->flt, ha->flt_dma);
4495
4496fail_flt_buffer:
4497	dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4498	    ha->sfp_data, ha->sfp_data_dma);
4499fail_sfp_data:
4500	kfree(ha->loop_id_map);
4501fail_loop_id_map:
4502	dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4503fail_async_pd:
4504	dma_pool_free(ha->s_dma_pool, ha->sf_init_cb, ha->sf_init_cb_dma);
4505fail_sf_init_cb:
4506	dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
4507fail_ex_init_cb:
4508	kfree(ha->npiv_info);
4509fail_npiv_info:
4510	dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4511		sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4512	(*rsp)->ring = NULL;
4513	(*rsp)->dma = 0;
4514fail_rsp_ring:
4515	kfree(*rsp);
4516	*rsp = NULL;
4517fail_rsp:
4518	dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4519		sizeof(request_t), (*req)->ring, (*req)->dma);
4520	(*req)->ring = NULL;
4521	(*req)->dma = 0;
4522fail_req_ring:
4523	kfree(*req);
4524	*req = NULL;
4525fail_req:
4526	dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4527		ha->ct_sns, ha->ct_sns_dma);
4528	ha->ct_sns = NULL;
4529	ha->ct_sns_dma = 0;
4530fail_free_ms_iocb:
4531	dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4532	ha->ms_iocb = NULL;
4533	ha->ms_iocb_dma = 0;
4534
4535	if (ha->sns_cmd)
4536		dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4537		    ha->sns_cmd, ha->sns_cmd_dma);
4538fail_dma_pool:
4539	if (ql2xenabledif) {
4540		struct dsd_dma *dsd, *nxt;
4541
4542		list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4543		    list) {
4544			list_del(&dsd->list);
4545			dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4546			    dsd->dsd_list_dma);
4547			ha->dif_bundle_dma_allocs--;
4548			kfree(dsd);
4549			ha->dif_bundle_kallocs--;
4550			ha->pool.unusable.count--;
4551		}
4552		dma_pool_destroy(ha->dif_bundl_pool);
4553		ha->dif_bundl_pool = NULL;
4554	}
4555
4556fail_dif_bundl_dma_pool:
4557	if (IS_QLA82XX(ha) || ql2xenabledif) {
4558		dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4559		ha->fcp_cmnd_dma_pool = NULL;
4560	}
4561fail_dl_dma_pool:
4562	if (IS_QLA82XX(ha) || ql2xenabledif) {
4563		dma_pool_destroy(ha->dl_dma_pool);
4564		ha->dl_dma_pool = NULL;
4565	}
4566fail_s_dma_pool:
4567	dma_pool_destroy(ha->s_dma_pool);
4568	ha->s_dma_pool = NULL;
4569fail_free_nvram:
4570	kfree(ha->nvram);
4571	ha->nvram = NULL;
4572fail_free_ctx_mempool:
4573	mempool_destroy(ha->ctx_mempool);
4574	ha->ctx_mempool = NULL;
4575fail_free_srb_mempool:
4576	mempool_destroy(ha->srb_mempool);
4577	ha->srb_mempool = NULL;
4578fail_free_gid_list:
4579	dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4580	ha->gid_list,
4581	ha->gid_list_dma);
4582	ha->gid_list = NULL;
4583	ha->gid_list_dma = 0;
4584fail_free_tgt_mem:
4585	qlt_mem_free(ha);
4586fail_free_btree:
4587	btree_destroy32(&ha->host_map);
4588fail_free_init_cb:
4589	dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4590	ha->init_cb_dma);
4591	ha->init_cb = NULL;
4592	ha->init_cb_dma = 0;
4593fail_free_vp_map:
4594	kfree(ha->vp_map);
4595	ha->vp_map = NULL;
4596fail:
4597	ql_log(ql_log_fatal, NULL, 0x0030,
4598	    "Memory allocation failure.\n");
4599	return -ENOMEM;
4600}
4601
4602int
4603qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4604{
4605	int rval;
4606	uint16_t	size, max_cnt;
4607	uint32_t temp;
4608	struct qla_hw_data *ha = vha->hw;
4609
4610	/* Return if we don't need to alloacate any extended logins */
4611	if (ql2xexlogins <= MAX_FIBRE_DEVICES_2400)
4612		return QLA_SUCCESS;
4613
4614	if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4615		return QLA_SUCCESS;
4616
4617	ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4618	max_cnt = 0;
4619	rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4620	if (rval != QLA_SUCCESS) {
4621		ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4622		    "Failed to get exlogin status.\n");
4623		return rval;
4624	}
4625
4626	temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
4627	temp *= size;
4628
4629	if (temp != ha->exlogin_size) {
4630		qla2x00_free_exlogin_buffer(ha);
4631		ha->exlogin_size = temp;
4632
4633		ql_log(ql_log_info, vha, 0xd024,
4634		    "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4635		    max_cnt, size, temp);
4636
4637		ql_log(ql_log_info, vha, 0xd025,
4638		    "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4639
4640		/* Get consistent memory for extended logins */
4641		ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4642			ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4643		if (!ha->exlogin_buf) {
4644			ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
4645		    "Failed to allocate memory for exlogin_buf_dma.\n");
4646			return -ENOMEM;
4647		}
4648	}
4649
4650	/* Now configure the dma buffer */
4651	rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4652	if (rval) {
4653		ql_log(ql_log_fatal, vha, 0xd033,
4654		    "Setup extended login buffer  ****FAILED****.\n");
4655		qla2x00_free_exlogin_buffer(ha);
4656	}
4657
4658	return rval;
4659}
4660
4661/*
4662* qla2x00_free_exlogin_buffer
4663*
4664* Input:
4665*	ha = adapter block pointer
4666*/
4667void
4668qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4669{
4670	if (ha->exlogin_buf) {
4671		dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4672		    ha->exlogin_buf, ha->exlogin_buf_dma);
4673		ha->exlogin_buf = NULL;
4674		ha->exlogin_size = 0;
4675	}
4676}
4677
4678static void
4679qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4680{
4681	u32 temp;
4682	struct init_cb_81xx *icb = (struct init_cb_81xx *)vha->hw->init_cb;
4683	*ret_cnt = FW_DEF_EXCHANGES_CNT;
4684
4685	if (max_cnt > vha->hw->max_exchg)
4686		max_cnt = vha->hw->max_exchg;
4687
4688	if (qla_ini_mode_enabled(vha)) {
4689		if (vha->ql2xiniexchg > max_cnt)
4690			vha->ql2xiniexchg = max_cnt;
4691
4692		if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4693			*ret_cnt = vha->ql2xiniexchg;
4694
4695	} else if (qla_tgt_mode_enabled(vha)) {
4696		if (vha->ql2xexchoffld > max_cnt) {
4697			vha->ql2xexchoffld = max_cnt;
4698			icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4699		}
4700
4701		if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4702			*ret_cnt = vha->ql2xexchoffld;
4703	} else if (qla_dual_mode_enabled(vha)) {
4704		temp = vha->ql2xiniexchg + vha->ql2xexchoffld;
4705		if (temp > max_cnt) {
4706			vha->ql2xiniexchg -= (temp - max_cnt)/2;
4707			vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
4708			temp = max_cnt;
4709			icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4710		}
4711
4712		if (temp > FW_DEF_EXCHANGES_CNT)
4713			*ret_cnt = temp;
4714	}
4715}
4716
4717int
4718qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4719{
4720	int rval;
4721	u16	size, max_cnt;
4722	u32 actual_cnt, totsz;
4723	struct qla_hw_data *ha = vha->hw;
4724
4725	if (!ha->flags.exchoffld_enabled)
4726		return QLA_SUCCESS;
4727
4728	if (!IS_EXCHG_OFFLD_CAPABLE(ha))
4729		return QLA_SUCCESS;
4730
4731	max_cnt = 0;
4732	rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4733	if (rval != QLA_SUCCESS) {
4734		ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4735		    "Failed to get exlogin status.\n");
4736		return rval;
4737	}
4738
4739	qla2x00_number_of_exch(vha, &actual_cnt, max_cnt);
4740	ql_log(ql_log_info, vha, 0xd014,
4741	    "Actual exchange offload count: %d.\n", actual_cnt);
4742
4743	totsz = actual_cnt * size;
4744
4745	if (totsz != ha->exchoffld_size) {
4746		qla2x00_free_exchoffld_buffer(ha);
4747		if (actual_cnt <= FW_DEF_EXCHANGES_CNT) {
4748			ha->exchoffld_size = 0;
4749			ha->flags.exchoffld_enabled = 0;
4750			return QLA_SUCCESS;
4751		}
4752
4753		ha->exchoffld_size = totsz;
4754
4755		ql_log(ql_log_info, vha, 0xd016,
4756		    "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n",
4757		    max_cnt, actual_cnt, size, totsz);
4758
4759		ql_log(ql_log_info, vha, 0xd017,
4760		    "Exchange Buffers requested size = 0x%x\n",
4761		    ha->exchoffld_size);
4762
4763		/* Get consistent memory for extended logins */
4764		ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4765			ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4766		if (!ha->exchoffld_buf) {
4767			ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4768			"Failed to allocate memory for Exchange Offload.\n");
4769
4770			if (ha->max_exchg >
4771			    (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) {
4772				ha->max_exchg -= REDUCE_EXCHANGES_CNT;
4773			} else if (ha->max_exchg >
4774			    (FW_DEF_EXCHANGES_CNT + 512)) {
4775				ha->max_exchg -= 512;
4776			} else {
4777				ha->flags.exchoffld_enabled = 0;
4778				ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4779				    "Disabling Exchange offload due to lack of memory\n");
4780			}
4781			ha->exchoffld_size = 0;
4782
4783			return -ENOMEM;
4784		}
4785	} else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) {
4786		/* pathological case */
4787		qla2x00_free_exchoffld_buffer(ha);
4788		ha->exchoffld_size = 0;
4789		ha->flags.exchoffld_enabled = 0;
4790		ql_log(ql_log_info, vha, 0xd016,
4791		    "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n",
4792		    ha->exchoffld_size, actual_cnt, size, totsz);
4793		return 0;
4794	}
4795
4796	/* Now configure the dma buffer */
4797	rval = qla_set_exchoffld_mem_cfg(vha);
4798	if (rval) {
4799		ql_log(ql_log_fatal, vha, 0xd02e,
4800		    "Setup exchange offload buffer ****FAILED****.\n");
4801		qla2x00_free_exchoffld_buffer(ha);
4802	} else {
4803		/* re-adjust number of target exchange */
4804		struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4805
4806		if (qla_ini_mode_enabled(vha))
4807			icb->exchange_count = 0;
4808		else
4809			icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4810	}
4811
4812	return rval;
4813}
4814
4815/*
4816* qla2x00_free_exchoffld_buffer
4817*
4818* Input:
4819*	ha = adapter block pointer
4820*/
4821void
4822qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4823{
4824	if (ha->exchoffld_buf) {
4825		dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4826		    ha->exchoffld_buf, ha->exchoffld_buf_dma);
4827		ha->exchoffld_buf = NULL;
4828		ha->exchoffld_size = 0;
4829	}
4830}
4831
4832/*
4833* qla2x00_free_fw_dump
4834*	Frees fw dump stuff.
4835*
4836* Input:
4837*	ha = adapter block pointer
4838*/
4839static void
4840qla2x00_free_fw_dump(struct qla_hw_data *ha)
4841{
4842	struct fwdt *fwdt = ha->fwdt;
4843	uint j;
4844
4845	if (ha->fce)
4846		dma_free_coherent(&ha->pdev->dev,
4847		    FCE_SIZE, ha->fce, ha->fce_dma);
4848
4849	if (ha->eft)
4850		dma_free_coherent(&ha->pdev->dev,
4851		    EFT_SIZE, ha->eft, ha->eft_dma);
4852
4853	vfree(ha->fw_dump);
4854
4855	ha->fce = NULL;
4856	ha->fce_dma = 0;
4857	ha->flags.fce_enabled = 0;
4858	ha->eft = NULL;
4859	ha->eft_dma = 0;
4860	ha->fw_dumped = false;
4861	ha->fw_dump_cap_flags = 0;
4862	ha->fw_dump_reading = 0;
4863	ha->fw_dump = NULL;
4864	ha->fw_dump_len = 0;
4865
4866	for (j = 0; j < 2; j++, fwdt++) {
4867		vfree(fwdt->template);
4868		fwdt->template = NULL;
4869		fwdt->length = 0;
4870	}
4871}
4872
4873/*
4874* qla2x00_mem_free
4875*      Frees all adapter allocated memory.
4876*
4877* Input:
4878*      ha = adapter block pointer.
4879*/
4880static void
4881qla2x00_mem_free(struct qla_hw_data *ha)
4882{
4883	qla2x00_free_fw_dump(ha);
4884
4885	if (ha->mctp_dump)
4886		dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4887		    ha->mctp_dump_dma);
4888	ha->mctp_dump = NULL;
4889
4890	mempool_destroy(ha->srb_mempool);
4891	ha->srb_mempool = NULL;
4892
4893	if (ha->dcbx_tlv)
4894		dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4895		    ha->dcbx_tlv, ha->dcbx_tlv_dma);
4896	ha->dcbx_tlv = NULL;
4897
4898	if (ha->xgmac_data)
4899		dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4900		    ha->xgmac_data, ha->xgmac_data_dma);
4901	ha->xgmac_data = NULL;
4902
4903	if (ha->sns_cmd)
4904		dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4905		ha->sns_cmd, ha->sns_cmd_dma);
4906	ha->sns_cmd = NULL;
4907	ha->sns_cmd_dma = 0;
4908
4909	if (ha->ct_sns)
4910		dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4911		ha->ct_sns, ha->ct_sns_dma);
4912	ha->ct_sns = NULL;
4913	ha->ct_sns_dma = 0;
4914
4915	if (ha->sfp_data)
4916		dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
4917		    ha->sfp_data_dma);
4918	ha->sfp_data = NULL;
4919
4920	if (ha->flt)
4921		dma_free_coherent(&ha->pdev->dev,
4922		    sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE,
4923		    ha->flt, ha->flt_dma);
4924	ha->flt = NULL;
4925	ha->flt_dma = 0;
4926
4927	if (ha->ms_iocb)
4928		dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4929	ha->ms_iocb = NULL;
4930	ha->ms_iocb_dma = 0;
4931
4932	if (ha->sf_init_cb)
4933		dma_pool_free(ha->s_dma_pool,
4934			      ha->sf_init_cb, ha->sf_init_cb_dma);
4935
4936	if (ha->ex_init_cb)
4937		dma_pool_free(ha->s_dma_pool,
4938			ha->ex_init_cb, ha->ex_init_cb_dma);
4939	ha->ex_init_cb = NULL;
4940	ha->ex_init_cb_dma = 0;
4941
4942	if (ha->async_pd)
4943		dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4944	ha->async_pd = NULL;
4945	ha->async_pd_dma = 0;
4946
4947	dma_pool_destroy(ha->s_dma_pool);
4948	ha->s_dma_pool = NULL;
4949
4950	if (ha->gid_list)
4951		dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4952		ha->gid_list, ha->gid_list_dma);
4953	ha->gid_list = NULL;
4954	ha->gid_list_dma = 0;
4955
4956	if (ha->base_qpair && !list_empty(&ha->base_qpair->dsd_list)) {
4957		struct dsd_dma *dsd_ptr, *tdsd_ptr;
4958
4959		/* clean up allocated prev pool */
4960		list_for_each_entry_safe(dsd_ptr, tdsd_ptr,
4961					 &ha->base_qpair->dsd_list, list) {
4962			dma_pool_free(ha->dl_dma_pool, dsd_ptr->dsd_addr,
4963				      dsd_ptr->dsd_list_dma);
4964			list_del(&dsd_ptr->list);
4965			kfree(dsd_ptr);
4966		}
4967	}
4968
4969	dma_pool_destroy(ha->dl_dma_pool);
4970	ha->dl_dma_pool = NULL;
4971
4972	dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4973	ha->fcp_cmnd_dma_pool = NULL;
4974
4975	mempool_destroy(ha->ctx_mempool);
4976	ha->ctx_mempool = NULL;
4977
4978	if (ql2xenabledif && ha->dif_bundl_pool) {
4979		struct dsd_dma *dsd, *nxt;
4980
4981		list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4982					 list) {
4983			list_del(&dsd->list);
4984			dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4985				      dsd->dsd_list_dma);
4986			ha->dif_bundle_dma_allocs--;
4987			kfree(dsd);
4988			ha->dif_bundle_kallocs--;
4989			ha->pool.unusable.count--;
4990		}
4991		list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) {
4992			list_del(&dsd->list);
4993			dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4994				      dsd->dsd_list_dma);
4995			ha->dif_bundle_dma_allocs--;
4996			kfree(dsd);
4997			ha->dif_bundle_kallocs--;
4998		}
4999	}
5000
5001	dma_pool_destroy(ha->dif_bundl_pool);
5002	ha->dif_bundl_pool = NULL;
5003
5004	qlt_mem_free(ha);
5005	qla_remove_hostmap(ha);
5006
5007	if (ha->init_cb)
5008		dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
5009			ha->init_cb, ha->init_cb_dma);
5010
5011	dma_pool_destroy(ha->purex_dma_pool);
5012	ha->purex_dma_pool = NULL;
5013
5014	if (ha->elsrej.c) {
5015		dma_free_coherent(&ha->pdev->dev, ha->elsrej.size,
5016		    ha->elsrej.c, ha->elsrej.cdma);
5017		ha->elsrej.c = NULL;
5018	}
5019
5020	if (ha->lsrjt.c) {
5021		dma_free_coherent(&ha->pdev->dev, ha->lsrjt.size, ha->lsrjt.c,
5022				  ha->lsrjt.cdma);
5023		ha->lsrjt.c = NULL;
5024	}
5025
5026	ha->init_cb = NULL;
5027	ha->init_cb_dma = 0;
5028
5029	vfree(ha->optrom_buffer);
5030	ha->optrom_buffer = NULL;
5031	kfree(ha->nvram);
5032	ha->nvram = NULL;
5033	kfree(ha->npiv_info);
5034	ha->npiv_info = NULL;
5035	kfree(ha->swl);
5036	ha->swl = NULL;
5037	kfree(ha->loop_id_map);
5038	ha->sf_init_cb = NULL;
5039	ha->sf_init_cb_dma = 0;
5040	ha->loop_id_map = NULL;
5041
5042	kfree(ha->vp_map);
5043	ha->vp_map = NULL;
5044}
5045
5046struct scsi_qla_host *qla2x00_create_host(const struct scsi_host_template *sht,
5047					  struct qla_hw_data *ha)
5048{
5049	struct Scsi_Host *host;
5050	struct scsi_qla_host *vha = NULL;
5051
5052	host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
5053	if (!host) {
5054		ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
5055		    "Failed to allocate host from the scsi layer, aborting.\n");
5056		return NULL;
5057	}
5058
5059	/* Clear our data area */
5060	vha = shost_priv(host);
5061	memset(vha, 0, sizeof(scsi_qla_host_t));
5062
5063	vha->host = host;
5064	vha->host_no = host->host_no;
5065	vha->hw = ha;
5066
5067	vha->qlini_mode = ql2x_ini_mode;
5068	vha->ql2xexchoffld = ql2xexchoffld;
5069	vha->ql2xiniexchg = ql2xiniexchg;
5070
5071	INIT_LIST_HEAD(&vha->vp_fcports);
5072	INIT_LIST_HEAD(&vha->work_list);
5073	INIT_LIST_HEAD(&vha->list);
5074	INIT_LIST_HEAD(&vha->qla_cmd_list);
5075	INIT_LIST_HEAD(&vha->logo_list);
5076	INIT_LIST_HEAD(&vha->plogi_ack_list);
5077	INIT_LIST_HEAD(&vha->qp_list);
5078	INIT_LIST_HEAD(&vha->gnl.fcports);
5079	INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn);
5080
5081	INIT_LIST_HEAD(&vha->purex_list.head);
5082	spin_lock_init(&vha->purex_list.lock);
5083
5084	spin_lock_init(&vha->work_lock);
5085	spin_lock_init(&vha->cmd_list_lock);
5086	init_waitqueue_head(&vha->fcport_waitQ);
5087	init_waitqueue_head(&vha->vref_waitq);
5088	qla_enode_init(vha);
5089	qla_edb_init(vha);
5090
5091
5092	vha->gnl.size = sizeof(struct get_name_list_extended) *
5093			(ha->max_loop_id + 1);
5094	vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
5095	    vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
5096	if (!vha->gnl.l) {
5097		ql_log(ql_log_fatal, vha, 0xd04a,
5098		    "Alloc failed for name list.\n");
5099		scsi_host_put(vha->host);
5100		return NULL;
5101	}
5102
5103	/* todo: what about ext login? */
5104	vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp);
5105	vha->scan.l = vmalloc(vha->scan.size);
5106	if (!vha->scan.l) {
5107		ql_log(ql_log_fatal, vha, 0xd04a,
5108		    "Alloc failed for scan database.\n");
5109		dma_free_coherent(&ha->pdev->dev, vha->gnl.size,
5110		    vha->gnl.l, vha->gnl.ldma);
5111		vha->gnl.l = NULL;
5112		scsi_host_put(vha->host);
5113		return NULL;
5114	}
5115	INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn);
5116
5117	snprintf(vha->host_str, sizeof(vha->host_str), "%s_%lu",
5118		 QLA2XXX_DRIVER_NAME, vha->host_no);
5119	ql_dbg(ql_dbg_init, vha, 0x0041,
5120	    "Allocated the host=%p hw=%p vha=%p dev_name=%s",
5121	    vha->host, vha->hw, vha,
5122	    dev_name(&(ha->pdev->dev)));
5123
5124	return vha;
5125}
5126
5127struct qla_work_evt *
5128qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
5129{
5130	struct qla_work_evt *e;
5131
5132	if (test_bit(UNLOADING, &vha->dpc_flags))
5133		return NULL;
5134
5135	if (qla_vha_mark_busy(vha))
5136		return NULL;
5137
5138	e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
5139	if (!e) {
5140		QLA_VHA_MARK_NOT_BUSY(vha);
5141		return NULL;
5142	}
5143
5144	INIT_LIST_HEAD(&e->list);
5145	e->type = type;
5146	e->flags = QLA_EVT_FLAG_FREE;
5147	return e;
5148}
5149
5150int
5151qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
5152{
5153	unsigned long flags;
5154	bool q = false;
5155
5156	spin_lock_irqsave(&vha->work_lock, flags);
5157	list_add_tail(&e->list, &vha->work_list);
5158
5159	if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
5160		q = true;
5161
5162	spin_unlock_irqrestore(&vha->work_lock, flags);
5163
5164	if (q)
5165		queue_work(vha->hw->wq, &vha->iocb_work);
5166
5167	return QLA_SUCCESS;
5168}
5169
5170int
5171qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
5172    u32 data)
5173{
5174	struct qla_work_evt *e;
5175
5176	e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
5177	if (!e)
5178		return QLA_FUNCTION_FAILED;
5179
5180	e->u.aen.code = code;
5181	e->u.aen.data = data;
5182	return qla2x00_post_work(vha, e);
5183}
5184
5185int
5186qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
5187{
5188	struct qla_work_evt *e;
5189
5190	e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
5191	if (!e)
5192		return QLA_FUNCTION_FAILED;
5193
5194	memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
5195	return qla2x00_post_work(vha, e);
5196}
5197
5198#define qla2x00_post_async_work(name, type)	\
5199int qla2x00_post_async_##name##_work(		\
5200    struct scsi_qla_host *vha,			\
5201    fc_port_t *fcport, uint16_t *data)		\
5202{						\
5203	struct qla_work_evt *e;			\
5204						\
5205	e = qla2x00_alloc_work(vha, type);	\
5206	if (!e)					\
5207		return QLA_FUNCTION_FAILED;	\
5208						\
5209	e->u.logio.fcport = fcport;		\
5210	if (data) {				\
5211		e->u.logio.data[0] = data[0];	\
5212		e->u.logio.data[1] = data[1];	\
5213	}					\
5214	fcport->flags |= FCF_ASYNC_ACTIVE;	\
5215	return qla2x00_post_work(vha, e);	\
5216}
5217
5218qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
5219qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
5220qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
5221qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO);
5222qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE);
5223
5224int
5225qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
5226{
5227	struct qla_work_evt *e;
5228
5229	e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
5230	if (!e)
5231		return QLA_FUNCTION_FAILED;
5232
5233	e->u.uevent.code = code;
5234	return qla2x00_post_work(vha, e);
5235}
5236
5237static void
5238qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
5239{
5240	char event_string[40];
5241	char *envp[] = { event_string, NULL };
5242
5243	switch (code) {
5244	case QLA_UEVENT_CODE_FW_DUMP:
5245		snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu",
5246		    vha->host_no);
5247		break;
5248	default:
5249		/* do nothing */
5250		break;
5251	}
5252	kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
5253}
5254
5255int
5256qlafx00_post_aenfx_work(struct scsi_qla_host *vha,  uint32_t evtcode,
5257			uint32_t *data, int cnt)
5258{
5259	struct qla_work_evt *e;
5260
5261	e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
5262	if (!e)
5263		return QLA_FUNCTION_FAILED;
5264
5265	e->u.aenfx.evtcode = evtcode;
5266	e->u.aenfx.count = cnt;
5267	memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
5268	return qla2x00_post_work(vha, e);
5269}
5270
5271void qla24xx_sched_upd_fcport(fc_port_t *fcport)
5272{
5273	unsigned long flags;
5274
5275	if (IS_SW_RESV_ADDR(fcport->d_id))
5276		return;
5277
5278	spin_lock_irqsave(&fcport->vha->work_lock, flags);
5279	if (fcport->disc_state == DSC_UPD_FCPORT) {
5280		spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5281		return;
5282	}
5283	fcport->jiffies_at_registration = jiffies;
5284	fcport->sec_since_registration = 0;
5285	fcport->next_disc_state = DSC_DELETED;
5286	qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT);
5287	spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5288
5289	queue_work(system_dfl_wq, &fcport->reg_work);
5290}
5291
5292static
5293void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
5294{
5295	unsigned long flags;
5296	fc_port_t *fcport =  NULL, *tfcp;
5297	struct qlt_plogi_ack_t *pla =
5298	    (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
5299	uint8_t free_fcport = 0;
5300
5301	ql_dbg(ql_dbg_disc, vha, 0xffff,
5302	    "%s %d %8phC enter\n",
5303	    __func__, __LINE__, e->u.new_sess.port_name);
5304
5305	spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5306	fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
5307	if (fcport) {
5308		fcport->d_id = e->u.new_sess.id;
5309		if (pla) {
5310			fcport->fw_login_state = DSC_LS_PLOGI_PEND;
5311			memcpy(fcport->node_name,
5312			    pla->iocb.u.isp24.u.plogi.node_name,
5313			    WWN_SIZE);
5314			qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
5315			/* we took an extra ref_count to prevent PLOGI ACK when
5316			 * fcport/sess has not been created.
5317			 */
5318			pla->ref_count--;
5319		}
5320	} else {
5321		spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5322		fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
5323		if (fcport) {
5324			fcport->d_id = e->u.new_sess.id;
5325			fcport->flags |= FCF_FABRIC_DEVICE;
5326			fcport->fw_login_state = DSC_LS_PLOGI_PEND;
5327			fcport->tgt_short_link_down_cnt = 0;
5328
5329			memcpy(fcport->port_name, e->u.new_sess.port_name,
5330			    WWN_SIZE);
5331
5332			fcport->fc4_type = e->u.new_sess.fc4_type;
5333			if (NVME_PRIORITY(vha->hw, fcport))
5334				fcport->do_prli_nvme = 1;
5335			else
5336				fcport->do_prli_nvme = 0;
5337
5338			if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N) {
5339				fcport->dm_login_expire = jiffies +
5340					QLA_N2N_WAIT_TIME * HZ;
5341				fcport->fc4_type = FS_FC4TYPE_FCP;
5342				fcport->n2n_flag = 1;
5343				if (vha->flags.nvme_enabled)
5344					fcport->fc4_type |= FS_FC4TYPE_NVME;
5345			}
5346
5347		} else {
5348			ql_dbg(ql_dbg_disc, vha, 0xffff,
5349				   "%s %8phC mem alloc fail.\n",
5350				   __func__, e->u.new_sess.port_name);
5351
5352			if (pla) {
5353				list_del(&pla->list);
5354				kmem_cache_free(qla_tgt_plogi_cachep, pla);
5355			}
5356			return;
5357		}
5358
5359		spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5360		/* search again to make sure no one else got ahead */
5361		tfcp = qla2x00_find_fcport_by_wwpn(vha,
5362		    e->u.new_sess.port_name, 1);
5363		if (tfcp) {
5364			/* should rarily happen */
5365			ql_dbg(ql_dbg_disc, vha, 0xffff,
5366			    "%s %8phC found existing fcport b4 add. DS %d LS %d\n",
5367			    __func__, tfcp->port_name, tfcp->disc_state,
5368			    tfcp->fw_login_state);
5369
5370			free_fcport = 1;
5371		} else {
5372			list_add_tail(&fcport->list, &vha->vp_fcports);
5373
5374		}
5375		if (pla) {
5376			qlt_plogi_ack_link(vha, pla, fcport,
5377			    QLT_PLOGI_LINK_SAME_WWN);
5378			pla->ref_count--;
5379		}
5380	}
5381	spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5382
5383	if (fcport) {
5384		fcport->id_changed = 1;
5385		fcport->scan_state = QLA_FCPORT_FOUND;
5386		fcport->chip_reset = vha->hw->base_qpair->chip_reset;
5387		memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE);
5388
5389		if (pla) {
5390			if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) {
5391				u16 wd3_lo;
5392
5393				fcport->fw_login_state = DSC_LS_PRLI_PEND;
5394				fcport->local = 0;
5395				fcport->loop_id =
5396					le16_to_cpu(
5397					    pla->iocb.u.isp24.nport_handle);
5398				fcport->fw_login_state = DSC_LS_PRLI_PEND;
5399				wd3_lo =
5400				    le16_to_cpu(
5401					pla->iocb.u.isp24.u.prli.wd3_lo);
5402
5403				if (wd3_lo & BIT_7)
5404					fcport->conf_compl_supported = 1;
5405
5406				if ((wd3_lo & BIT_4) == 0)
5407					fcport->port_type = FCT_INITIATOR;
5408				else
5409					fcport->port_type = FCT_TARGET;
5410			}
5411			qlt_plogi_ack_unref(vha, pla);
5412		} else {
5413			fc_port_t *dfcp = NULL;
5414
5415			spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5416			tfcp = qla2x00_find_fcport_by_nportid(vha,
5417			    &e->u.new_sess.id, 1);
5418			if (tfcp && (tfcp != fcport)) {
5419				/*
5420				 * We have a conflict fcport with same NportID.
5421				 */
5422				ql_dbg(ql_dbg_disc, vha, 0xffff,
5423				    "%s %8phC found conflict b4 add. DS %d LS %d\n",
5424				    __func__, tfcp->port_name, tfcp->disc_state,
5425				    tfcp->fw_login_state);
5426
5427				switch (tfcp->disc_state) {
5428				case DSC_DELETED:
5429					break;
5430				case DSC_DELETE_PEND:
5431					fcport->login_pause = 1;
5432					tfcp->conflict = fcport;
5433					break;
5434				default:
5435					fcport->login_pause = 1;
5436					tfcp->conflict = fcport;
5437					dfcp = tfcp;
5438					break;
5439				}
5440			}
5441			spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5442			if (dfcp)
5443				qlt_schedule_sess_for_deletion(tfcp);
5444
5445			if (N2N_TOPO(vha->hw)) {
5446				fcport->flags &= ~FCF_FABRIC_DEVICE;
5447				fcport->keep_nport_handle = 1;
5448				if (vha->flags.nvme_enabled) {
5449					fcport->fc4_type =
5450					    (FS_FC4TYPE_NVME | FS_FC4TYPE_FCP);
5451					fcport->n2n_flag = 1;
5452				}
5453				fcport->fw_login_state = 0;
5454
5455				schedule_delayed_work(&vha->scan.scan_work, 5);
5456			} else {
5457				qla24xx_fcport_handle_login(vha, fcport);
5458			}
5459		}
5460	}
5461
5462	if (free_fcport) {
5463		qla2x00_free_fcport(fcport);
5464		if (pla) {
5465			list_del(&pla->list);
5466			kmem_cache_free(qla_tgt_plogi_cachep, pla);
5467		}
5468	}
5469}
5470
5471static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e)
5472{
5473	struct srb *sp = e->u.iosb.sp;
5474	int rval;
5475
5476	rval = qla2x00_start_sp(sp);
5477	if (rval != QLA_SUCCESS) {
5478		ql_dbg(ql_dbg_disc, vha, 0x2043,
5479		    "%s: %s: Re-issue IOCB failed (%d).\n",
5480		    __func__, sp->name, rval);
5481		qla24xx_sp_unmap(vha, sp);
5482	}
5483}
5484
5485void
5486qla2x00_do_work(struct scsi_qla_host *vha)
5487{
5488	struct qla_work_evt *e, *tmp;
5489	unsigned long flags;
5490	LIST_HEAD(work);
5491	int rc;
5492
5493	spin_lock_irqsave(&vha->work_lock, flags);
5494	list_splice_init(&vha->work_list, &work);
5495	spin_unlock_irqrestore(&vha->work_lock, flags);
5496
5497	list_for_each_entry_safe(e, tmp, &work, list) {
5498		rc = QLA_SUCCESS;
5499		switch (e->type) {
5500		case QLA_EVT_AEN:
5501			fc_host_post_event(vha->host, fc_get_event_number(),
5502			    e->u.aen.code, e->u.aen.data);
5503			break;
5504		case QLA_EVT_IDC_ACK:
5505			qla81xx_idc_ack(vha, e->u.idc_ack.mb);
5506			break;
5507		case QLA_EVT_ASYNC_LOGIN:
5508			qla2x00_async_login(vha, e->u.logio.fcport,
5509			    e->u.logio.data);
5510			break;
5511		case QLA_EVT_ASYNC_LOGOUT:
5512			rc = qla2x00_async_logout(vha, e->u.logio.fcport);
5513			break;
5514		case QLA_EVT_ASYNC_ADISC:
5515			qla2x00_async_adisc(vha, e->u.logio.fcport,
5516			    e->u.logio.data);
5517			break;
5518		case QLA_EVT_UEVENT:
5519			qla2x00_uevent_emit(vha, e->u.uevent.code);
5520			break;
5521		case QLA_EVT_AENFX:
5522			qlafx00_process_aen(vha, e);
5523			break;
5524		case QLA_EVT_UNMAP:
5525			qla24xx_sp_unmap(vha, e->u.iosb.sp);
5526			break;
5527		case QLA_EVT_RELOGIN:
5528			qla2x00_relogin(vha);
5529			break;
5530		case QLA_EVT_NEW_SESS:
5531			qla24xx_create_new_sess(vha, e);
5532			break;
5533		case QLA_EVT_GPDB:
5534			qla24xx_async_gpdb(vha, e->u.fcport.fcport,
5535			    e->u.fcport.opt);
5536			break;
5537		case QLA_EVT_PRLI:
5538			qla24xx_async_prli(vha, e->u.fcport.fcport);
5539			break;
5540		case QLA_EVT_GPSC:
5541			qla24xx_async_gpsc(vha, e->u.fcport.fcport);
5542			break;
5543		case QLA_EVT_GNL:
5544			qla24xx_async_gnl(vha, e->u.fcport.fcport);
5545			break;
5546		case QLA_EVT_NACK:
5547			qla24xx_do_nack_work(vha, e);
5548			break;
5549		case QLA_EVT_ASYNC_PRLO:
5550			rc = qla2x00_async_prlo(vha, e->u.logio.fcport);
5551			break;
5552		case QLA_EVT_ASYNC_PRLO_DONE:
5553			qla2x00_async_prlo_done(vha, e->u.logio.fcport,
5554			    e->u.logio.data);
5555			break;
5556		case QLA_EVT_SCAN_CMD:
5557			qla_fab_async_scan(vha, e->u.iosb.sp);
5558			break;
5559		case QLA_EVT_SCAN_FINISH:
5560			qla_fab_scan_finish(vha, e->u.iosb.sp);
5561			break;
5562		case QLA_EVT_GFPNID:
5563			qla24xx_async_gfpnid(vha, e->u.fcport.fcport);
5564			break;
5565		case QLA_EVT_SP_RETRY:
5566			qla_sp_retry(vha, e);
5567			break;
5568		case QLA_EVT_IIDMA:
5569			qla_do_iidma_work(vha, e->u.fcport.fcport);
5570			break;
5571		case QLA_EVT_ELS_PLOGI:
5572			qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI,
5573			    e->u.fcport.fcport);
5574			break;
5575		case QLA_EVT_SA_REPLACE:
5576			rc = qla24xx_issue_sa_replace_iocb(vha, e);
5577			break;
5578		}
5579
5580		if (rc == EAGAIN) {
5581			/* put 'work' at head of 'vha->work_list' */
5582			spin_lock_irqsave(&vha->work_lock, flags);
5583			list_splice(&work, &vha->work_list);
5584			spin_unlock_irqrestore(&vha->work_lock, flags);
5585			break;
5586		}
5587		list_del_init(&e->list);
5588		if (e->flags & QLA_EVT_FLAG_FREE)
5589			kfree(e);
5590
5591		/* For each work completed decrement vha ref count */
5592		QLA_VHA_MARK_NOT_BUSY(vha);
5593	}
5594}
5595
5596int qla24xx_post_relogin_work(struct scsi_qla_host *vha)
5597{
5598	struct qla_work_evt *e;
5599
5600	e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN);
5601
5602	if (!e) {
5603		set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5604		return QLA_FUNCTION_FAILED;
5605	}
5606
5607	return qla2x00_post_work(vha, e);
5608}
5609
5610/* Relogins all the fcports of a vport
5611 * Context: dpc thread
5612 */
5613void qla2x00_relogin(struct scsi_qla_host *vha)
5614{
5615	fc_port_t       *fcport;
5616	int status, relogin_needed = 0;
5617	struct event_arg ea;
5618
5619	list_for_each_entry(fcport, &vha->vp_fcports, list) {
5620		/*
5621		 * If the port is not ONLINE then try to login
5622		 * to it if we haven't run out of retries.
5623		 */
5624		if (atomic_read(&fcport->state) != FCS_ONLINE &&
5625		    fcport->login_retry) {
5626			if (fcport->scan_state != QLA_FCPORT_FOUND ||
5627			    fcport->disc_state == DSC_LOGIN_AUTH_PEND ||
5628			    fcport->disc_state == DSC_LOGIN_COMPLETE)
5629				continue;
5630
5631			if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) ||
5632				fcport->disc_state == DSC_DELETE_PEND) {
5633				relogin_needed = 1;
5634			} else {
5635				if (vha->hw->current_topology != ISP_CFG_NL) {
5636					memset(&ea, 0, sizeof(ea));
5637					ea.fcport = fcport;
5638					qla24xx_handle_relogin_event(vha, &ea);
5639				} else if (vha->hw->current_topology ==
5640					 ISP_CFG_NL &&
5641					IS_QLA2XXX_MIDTYPE(vha->hw)) {
5642					(void)qla24xx_fcport_handle_login(vha,
5643									fcport);
5644				} else if (vha->hw->current_topology ==
5645				    ISP_CFG_NL) {
5646					fcport->login_retry--;
5647					status =
5648					    qla2x00_local_device_login(vha,
5649						fcport);
5650					if (status == QLA_SUCCESS) {
5651						fcport->old_loop_id =
5652						    fcport->loop_id;
5653						ql_dbg(ql_dbg_disc, vha, 0x2003,
5654						    "Port login OK: logged in ID 0x%x.\n",
5655						    fcport->loop_id);
5656						qla2x00_update_fcport
5657							(vha, fcport);
5658					} else if (status == 1) {
5659						set_bit(RELOGIN_NEEDED,
5660						    &vha->dpc_flags);
5661						/* retry the login again */
5662						ql_dbg(ql_dbg_disc, vha, 0x2007,
5663						    "Retrying %d login again loop_id 0x%x.\n",
5664						    fcport->login_retry,
5665						    fcport->loop_id);
5666					} else {
5667						fcport->login_retry = 0;
5668					}
5669
5670					if (fcport->login_retry == 0 &&
5671					    status != QLA_SUCCESS)
5672						qla2x00_clear_loop_id(fcport);
5673				}
5674			}
5675		}
5676		if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5677			break;
5678	}
5679
5680	if (relogin_needed)
5681		set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5682
5683	ql_dbg(ql_dbg_disc, vha, 0x400e,
5684	    "Relogin end.\n");
5685}
5686
5687/* Schedule work on any of the dpc-workqueues */
5688void
5689qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
5690{
5691	struct qla_hw_data *ha = base_vha->hw;
5692
5693	switch (work_code) {
5694	case MBA_IDC_AEN: /* 0x8200 */
5695		if (ha->dpc_lp_wq)
5696			queue_work(ha->dpc_lp_wq, &ha->idc_aen);
5697		break;
5698
5699	case QLA83XX_NIC_CORE_RESET: /* 0x1 */
5700		if (!ha->flags.nic_core_reset_hdlr_active) {
5701			if (ha->dpc_hp_wq)
5702				queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
5703		} else
5704			ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
5705			    "NIC Core reset is already active. Skip "
5706			    "scheduling it again.\n");
5707		break;
5708	case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
5709		if (ha->dpc_hp_wq)
5710			queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
5711		break;
5712	case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
5713		if (ha->dpc_hp_wq)
5714			queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
5715		break;
5716	default:
5717		ql_log(ql_log_warn, base_vha, 0xb05f,
5718		    "Unknown work-code=0x%x.\n", work_code);
5719	}
5720
5721	return;
5722}
5723
5724/* Work: Perform NIC Core Unrecoverable state handling */
5725void
5726qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
5727{
5728	struct qla_hw_data *ha =
5729		container_of(work, struct qla_hw_data, nic_core_unrecoverable);
5730	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5731	uint32_t dev_state = 0;
5732
5733	qla83xx_idc_lock(base_vha, 0);
5734	qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5735	qla83xx_reset_ownership(base_vha);
5736	if (ha->flags.nic_core_reset_owner) {
5737		ha->flags.nic_core_reset_owner = 0;
5738		qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5739		    QLA8XXX_DEV_FAILED);
5740		ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
5741		qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5742	}
5743	qla83xx_idc_unlock(base_vha, 0);
5744}
5745
5746/* Work: Execute IDC state handler */
5747void
5748qla83xx_idc_state_handler_work(struct work_struct *work)
5749{
5750	struct qla_hw_data *ha =
5751		container_of(work, struct qla_hw_data, idc_state_handler);
5752	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5753	uint32_t dev_state = 0;
5754
5755	qla83xx_idc_lock(base_vha, 0);
5756	qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5757	if (dev_state == QLA8XXX_DEV_FAILED ||
5758			dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
5759		qla83xx_idc_state_handler(base_vha);
5760	qla83xx_idc_unlock(base_vha, 0);
5761}
5762
5763static int
5764qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
5765{
5766	int rval = QLA_SUCCESS;
5767	unsigned long heart_beat_wait = jiffies + (1 * HZ);
5768	uint32_t heart_beat_counter1, heart_beat_counter2;
5769
5770	do {
5771		if (time_after(jiffies, heart_beat_wait)) {
5772			ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
5773			    "Nic Core f/w is not alive.\n");
5774			rval = QLA_FUNCTION_FAILED;
5775			break;
5776		}
5777
5778		qla83xx_idc_lock(base_vha, 0);
5779		qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5780		    &heart_beat_counter1);
5781		qla83xx_idc_unlock(base_vha, 0);
5782		msleep(100);
5783		qla83xx_idc_lock(base_vha, 0);
5784		qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5785		    &heart_beat_counter2);
5786		qla83xx_idc_unlock(base_vha, 0);
5787	} while (heart_beat_counter1 == heart_beat_counter2);
5788
5789	return rval;
5790}
5791
5792/* Work: Perform NIC Core Reset handling */
5793void
5794qla83xx_nic_core_reset_work(struct work_struct *work)
5795{
5796	struct qla_hw_data *ha =
5797		container_of(work, struct qla_hw_data, nic_core_reset);
5798	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5799	uint32_t dev_state = 0;
5800
5801	if (IS_QLA2031(ha)) {
5802		if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
5803			ql_log(ql_log_warn, base_vha, 0xb081,
5804			    "Failed to dump mctp\n");
5805		return;
5806	}
5807
5808	if (!ha->flags.nic_core_reset_hdlr_active) {
5809		if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
5810			qla83xx_idc_lock(base_vha, 0);
5811			qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5812			    &dev_state);
5813			qla83xx_idc_unlock(base_vha, 0);
5814			if (dev_state != QLA8XXX_DEV_NEED_RESET) {
5815				ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
5816				    "Nic Core f/w is alive.\n");
5817				return;
5818			}
5819		}
5820
5821		ha->flags.nic_core_reset_hdlr_active = 1;
5822		if (qla83xx_nic_core_reset(base_vha)) {
5823			/* NIC Core reset failed. */
5824			ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
5825			    "NIC Core reset failed.\n");
5826		}
5827		ha->flags.nic_core_reset_hdlr_active = 0;
5828	}
5829}
5830
5831/* Work: Handle 8200 IDC aens */
5832void
5833qla83xx_service_idc_aen(struct work_struct *work)
5834{
5835	struct qla_hw_data *ha =
5836		container_of(work, struct qla_hw_data, idc_aen);
5837	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5838	uint32_t dev_state, idc_control;
5839
5840	qla83xx_idc_lock(base_vha, 0);
5841	qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5842	qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
5843	qla83xx_idc_unlock(base_vha, 0);
5844	if (dev_state == QLA8XXX_DEV_NEED_RESET) {
5845		if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
5846			ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
5847			    "Application requested NIC Core Reset.\n");
5848			qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5849		} else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
5850		    QLA_SUCCESS) {
5851			ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
5852			    "Other protocol driver requested NIC Core Reset.\n");
5853			qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5854		}
5855	} else if (dev_state == QLA8XXX_DEV_FAILED ||
5856			dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5857		qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5858	}
5859}
5860
5861/*
5862 * Control the frequency of IDC lock retries
5863 */
5864#define QLA83XX_WAIT_LOGIC_MS	100
5865
5866static int
5867qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5868{
5869	int rval;
5870	uint32_t data;
5871	uint32_t idc_lck_rcvry_stage_mask = 0x3;
5872	uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5873	struct qla_hw_data *ha = base_vha->hw;
5874
5875	ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5876	    "Trying force recovery of the IDC lock.\n");
5877
5878	rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5879	if (rval)
5880		return rval;
5881
5882	if ((data & idc_lck_rcvry_stage_mask) > 0) {
5883		return QLA_SUCCESS;
5884	} else {
5885		data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5886		rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5887		    data);
5888		if (rval)
5889			return rval;
5890
5891		msleep(200);
5892
5893		rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5894		    &data);
5895		if (rval)
5896			return rval;
5897
5898		if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5899			data &= (IDC_LOCK_RECOVERY_STAGE2 |
5900					~(idc_lck_rcvry_stage_mask));
5901			rval = qla83xx_wr_reg(base_vha,
5902			    QLA83XX_IDC_LOCK_RECOVERY, data);
5903			if (rval)
5904				return rval;
5905
5906			/* Forcefully perform IDC UnLock */
5907			rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5908			    &data);
5909			if (rval)
5910				return rval;
5911			/* Clear lock-id by setting 0xff */
5912			rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5913			    0xff);
5914			if (rval)
5915				return rval;
5916			/* Clear lock-recovery by setting 0x0 */
5917			rval = qla83xx_wr_reg(base_vha,
5918			    QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5919			if (rval)
5920				return rval;
5921		} else
5922			return QLA_SUCCESS;
5923	}
5924
5925	return rval;
5926}
5927
5928static int
5929qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5930{
5931	int rval = QLA_SUCCESS;
5932	uint32_t o_drv_lockid, n_drv_lockid;
5933	unsigned long lock_recovery_timeout;
5934
5935	lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5936retry_lockid:
5937	rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5938	if (rval)
5939		goto exit;
5940
5941	/* MAX wait time before forcing IDC Lock recovery = 2 secs */
5942	if (time_after_eq(jiffies, lock_recovery_timeout)) {
5943		if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5944			return QLA_SUCCESS;
5945		else
5946			return QLA_FUNCTION_FAILED;
5947	}
5948
5949	rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5950	if (rval)
5951		goto exit;
5952
5953	if (o_drv_lockid == n_drv_lockid) {
5954		msleep(QLA83XX_WAIT_LOGIC_MS);
5955		goto retry_lockid;
5956	} else
5957		return QLA_SUCCESS;
5958
5959exit:
5960	return rval;
5961}
5962
5963/*
5964 * Context: task, can sleep
5965 */
5966void
5967qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5968{
5969	uint32_t data;
5970	uint32_t lock_owner;
5971	struct qla_hw_data *ha = base_vha->hw;
5972
5973	might_sleep();
5974
5975	/* IDC-lock implementation using driver-lock/lock-id remote registers */
5976retry_lock:
5977	if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5978	    == QLA_SUCCESS) {
5979		if (data) {
5980			/* Setting lock-id to our function-number */
5981			qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5982			    ha->portnum);
5983		} else {
5984			qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5985			    &lock_owner);
5986			ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
5987			    "Failed to acquire IDC lock, acquired by %d, "
5988			    "retrying...\n", lock_owner);
5989
5990			/* Retry/Perform IDC-Lock recovery */
5991			if (qla83xx_idc_lock_recovery(base_vha)
5992			    == QLA_SUCCESS) {
5993				msleep(QLA83XX_WAIT_LOGIC_MS);
5994				goto retry_lock;
5995			} else
5996				ql_log(ql_log_warn, base_vha, 0xb075,
5997				    "IDC Lock recovery FAILED.\n");
5998		}
5999
6000	}
6001
6002	return;
6003}
6004
6005static bool
6006qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host *vha,
6007	struct purex_entry_24xx *purex)
6008{
6009	char fwstr[16];
6010	u32 sid = purex->s_id[2] << 16 | purex->s_id[1] << 8 | purex->s_id[0];
6011	struct port_database_24xx *pdb;
6012
6013	/* Domain Controller is always logged-out. */
6014	/* if RDP request is not from Domain Controller: */
6015	if (sid != 0xfffc01)
6016		return false;
6017
6018	ql_dbg(ql_dbg_init, vha, 0x0181, "%s: s_id=%#x\n", __func__, sid);
6019
6020	pdb = kzalloc(sizeof(*pdb), GFP_KERNEL);
6021	if (!pdb) {
6022		ql_dbg(ql_dbg_init, vha, 0x0181,
6023		    "%s: Failed allocate pdb\n", __func__);
6024	} else if (qla24xx_get_port_database(vha,
6025				le16_to_cpu(purex->nport_handle), pdb)) {
6026		ql_dbg(ql_dbg_init, vha, 0x0181,
6027		    "%s: Failed get pdb sid=%x\n", __func__, sid);
6028	} else if (pdb->current_login_state != PDS_PLOGI_COMPLETE &&
6029	    pdb->current_login_state != PDS_PRLI_COMPLETE) {
6030		ql_dbg(ql_dbg_init, vha, 0x0181,
6031		    "%s: Port not logged in sid=%#x\n", __func__, sid);
6032	} else {
6033		/* RDP request is from logged in port */
6034		kfree(pdb);
6035		return false;
6036	}
6037	kfree(pdb);
6038
6039	vha->hw->isp_ops->fw_version_str(vha, fwstr, sizeof(fwstr));
6040	fwstr[strcspn(fwstr, " ")] = 0;
6041	/* if FW version allows RDP response length upto 2048 bytes: */
6042	if (strcmp(fwstr, "8.09.00") > 0 || strcmp(fwstr, "8.05.65") == 0)
6043		return false;
6044
6045	ql_dbg(ql_dbg_init, vha, 0x0181, "%s: fw=%s\n", __func__, fwstr);
6046
6047	/* RDP response length is to be reduced to maximum 256 bytes */
6048	return true;
6049}
6050
6051/*
6052 * Function Name: qla24xx_process_purex_iocb
6053 *
6054 * Description:
6055 * Prepare a RDP response and send to Fabric switch
6056 *
6057 * PARAMETERS:
6058 * vha:	SCSI qla host
6059 * purex: RDP request received by HBA
6060 */
6061void qla24xx_process_purex_rdp(struct scsi_qla_host *vha,
6062			       struct purex_item *item)
6063{
6064	struct qla_hw_data *ha = vha->hw;
6065	struct purex_entry_24xx *purex =
6066	    (struct purex_entry_24xx *)&item->iocb;
6067	dma_addr_t rsp_els_dma;
6068	dma_addr_t rsp_payload_dma;
6069	dma_addr_t stat_dma;
6070	dma_addr_t sfp_dma;
6071	struct els_entry_24xx *rsp_els = NULL;
6072	struct rdp_rsp_payload *rsp_payload = NULL;
6073	struct link_statistics *stat = NULL;
6074	uint8_t *sfp = NULL;
6075	uint16_t sfp_flags = 0;
6076	uint rsp_payload_length = sizeof(*rsp_payload);
6077	int rval;
6078
6079	ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0180,
6080	    "%s: Enter\n", __func__);
6081
6082	ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0181,
6083	    "-------- ELS REQ -------\n");
6084	ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0182,
6085	    purex, sizeof(*purex));
6086
6087	if (qla25xx_rdp_rsp_reduce_size(vha, purex)) {
6088		rsp_payload_length =
6089		    offsetof(typeof(*rsp_payload), optical_elmt_desc);
6090		ql_dbg(ql_dbg_init, vha, 0x0181,
6091		    "Reducing RSP payload length to %u bytes...\n",
6092		    rsp_payload_length);
6093	}
6094
6095	rsp_els = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_els),
6096	    &rsp_els_dma, GFP_KERNEL);
6097	if (!rsp_els) {
6098		ql_log(ql_log_warn, vha, 0x0183,
6099		    "Failed allocate dma buffer ELS RSP.\n");
6100		goto dealloc;
6101	}
6102
6103	rsp_payload = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_payload),
6104	    &rsp_payload_dma, GFP_KERNEL);
6105	if (!rsp_payload) {
6106		ql_log(ql_log_warn, vha, 0x0184,
6107		    "Failed allocate dma buffer ELS RSP payload.\n");
6108		goto dealloc;
6109	}
6110
6111	sfp = dma_alloc_coherent(&ha->pdev->dev, SFP_RTDI_LEN,
6112	    &sfp_dma, GFP_KERNEL);
6113
6114	stat = dma_alloc_coherent(&ha->pdev->dev, sizeof(*stat),
6115	    &stat_dma, GFP_KERNEL);
6116
6117	/* Prepare Response IOCB */
6118	rsp_els->entry_type = ELS_IOCB_TYPE;
6119	rsp_els->entry_count = 1;
6120	rsp_els->sys_define = 0;
6121	rsp_els->entry_status = 0;
6122	rsp_els->handle = 0;
6123	rsp_els->nport_handle = purex->nport_handle;
6124	rsp_els->tx_dsd_count = cpu_to_le16(1);
6125	rsp_els->vp_index = purex->vp_idx;
6126	rsp_els->sof_type = EST_SOFI3;
6127	rsp_els->rx_xchg_address = purex->rx_xchg_addr;
6128	rsp_els->rx_dsd_count = 0;
6129	rsp_els->opcode = purex->els_frame_payload[0];
6130
6131	rsp_els->d_id[0] = purex->s_id[0];
6132	rsp_els->d_id[1] = purex->s_id[1];
6133	rsp_els->d_id[2] = purex->s_id[2];
6134
6135	rsp_els->control_flags = cpu_to_le16(EPD_ELS_ACC);
6136	rsp_els->rx_byte_count = 0;
6137	rsp_els->tx_byte_count = cpu_to_le32(rsp_payload_length);
6138
6139	put_unaligned_le64(rsp_payload_dma, &rsp_els->tx_address);
6140	rsp_els->tx_len = rsp_els->tx_byte_count;
6141
6142	rsp_els->rx_address = 0;
6143	rsp_els->rx_len = 0;
6144
6145	/* Prepare Response Payload */
6146	rsp_payload->hdr.cmd = cpu_to_be32(0x2 << 24); /* LS_ACC */
6147	rsp_payload->hdr.len = cpu_to_be32(le32_to_cpu(rsp_els->tx_byte_count) -
6148					   sizeof(rsp_payload->hdr));
6149
6150	/* Link service Request Info Descriptor */
6151	rsp_payload->ls_req_info_desc.desc_tag = cpu_to_be32(0x1);
6152	rsp_payload->ls_req_info_desc.desc_len =
6153	    cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc));
6154	rsp_payload->ls_req_info_desc.req_payload_word_0 =
6155	    cpu_to_be32p((uint32_t *)purex->els_frame_payload);
6156
6157	/* Link service Request Info Descriptor 2 */
6158	rsp_payload->ls_req_info_desc2.desc_tag = cpu_to_be32(0x1);
6159	rsp_payload->ls_req_info_desc2.desc_len =
6160	    cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc2));
6161	rsp_payload->ls_req_info_desc2.req_payload_word_0 =
6162	    cpu_to_be32p((uint32_t *)purex->els_frame_payload);
6163
6164
6165	rsp_payload->sfp_diag_desc.desc_tag = cpu_to_be32(0x10000);
6166	rsp_payload->sfp_diag_desc.desc_len =
6167		cpu_to_be32(RDP_DESC_LEN(rsp_payload->sfp_diag_desc));
6168
6169	if (sfp) {
6170		/* SFP Flags */
6171		memset(sfp, 0, SFP_RTDI_LEN);
6172		rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x7, 2, 0);
6173		if (!rval) {
6174			/* SFP Flags bits 3-0: Port Tx Laser Type */
6175			if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5))
6176				sfp_flags |= BIT_0; /* short wave */
6177			else if (sfp[0] & BIT_1)
6178				sfp_flags |= BIT_1; /* long wave 1310nm */
6179			else if (sfp[1] & BIT_4)
6180				sfp_flags |= BIT_1|BIT_0; /* long wave 1550nm */
6181		}
6182
6183		/* SFP Type */
6184		memset(sfp, 0, SFP_RTDI_LEN);
6185		rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x0, 1, 0);
6186		if (!rval) {
6187			sfp_flags |= BIT_4; /* optical */
6188			if (sfp[0] == 0x3)
6189				sfp_flags |= BIT_6; /* sfp+ */
6190		}
6191
6192		rsp_payload->sfp_diag_desc.sfp_flags = cpu_to_be16(sfp_flags);
6193
6194		/* SFP Diagnostics */
6195		memset(sfp, 0, SFP_RTDI_LEN);
6196		rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0x60, 10, 0);
6197		if (!rval) {
6198			__be16 *trx = (__force __be16 *)sfp; /* already be16 */
6199			rsp_payload->sfp_diag_desc.temperature = trx[0];
6200			rsp_payload->sfp_diag_desc.vcc = trx[1];
6201			rsp_payload->sfp_diag_desc.tx_bias = trx[2];
6202			rsp_payload->sfp_diag_desc.tx_power = trx[3];
6203			rsp_payload->sfp_diag_desc.rx_power = trx[4];
6204		}
6205	}
6206
6207	/* Port Speed Descriptor */
6208	rsp_payload->port_speed_desc.desc_tag = cpu_to_be32(0x10001);
6209	rsp_payload->port_speed_desc.desc_len =
6210	    cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_speed_desc));
6211	rsp_payload->port_speed_desc.speed_capab = cpu_to_be16(
6212	    qla25xx_fdmi_port_speed_capability(ha));
6213	rsp_payload->port_speed_desc.operating_speed = cpu_to_be16(
6214	    qla25xx_fdmi_port_speed_currently(ha));
6215
6216	/* Link Error Status Descriptor */
6217	rsp_payload->ls_err_desc.desc_tag = cpu_to_be32(0x10002);
6218	rsp_payload->ls_err_desc.desc_len =
6219		cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_err_desc));
6220
6221	if (stat) {
6222		rval = qla24xx_get_isp_stats(vha, stat, stat_dma, 0);
6223		if (!rval) {
6224			rsp_payload->ls_err_desc.link_fail_cnt =
6225			    cpu_to_be32(le32_to_cpu(stat->link_fail_cnt));
6226			rsp_payload->ls_err_desc.loss_sync_cnt =
6227			    cpu_to_be32(le32_to_cpu(stat->loss_sync_cnt));
6228			rsp_payload->ls_err_desc.loss_sig_cnt =
6229			    cpu_to_be32(le32_to_cpu(stat->loss_sig_cnt));
6230			rsp_payload->ls_err_desc.prim_seq_err_cnt =
6231			    cpu_to_be32(le32_to_cpu(stat->prim_seq_err_cnt));
6232			rsp_payload->ls_err_desc.inval_xmit_word_cnt =
6233			    cpu_to_be32(le32_to_cpu(stat->inval_xmit_word_cnt));
6234			rsp_payload->ls_err_desc.inval_crc_cnt =
6235			    cpu_to_be32(le32_to_cpu(stat->inval_crc_cnt));
6236			rsp_payload->ls_err_desc.pn_port_phy_type |= BIT_6;
6237		}
6238	}
6239
6240	/* Portname Descriptor */
6241	rsp_payload->port_name_diag_desc.desc_tag = cpu_to_be32(0x10003);
6242	rsp_payload->port_name_diag_desc.desc_len =
6243	    cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_diag_desc));
6244	memcpy(rsp_payload->port_name_diag_desc.WWNN,
6245	    vha->node_name,
6246	    sizeof(rsp_payload->port_name_diag_desc.WWNN));
6247	memcpy(rsp_payload->port_name_diag_desc.WWPN,
6248	    vha->port_name,
6249	    sizeof(rsp_payload->port_name_diag_desc.WWPN));
6250
6251	/* F-Port Portname Descriptor */
6252	rsp_payload->port_name_direct_desc.desc_tag = cpu_to_be32(0x10003);
6253	rsp_payload->port_name_direct_desc.desc_len =
6254	    cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_direct_desc));
6255	memcpy(rsp_payload->port_name_direct_desc.WWNN,
6256	    vha->fabric_node_name,
6257	    sizeof(rsp_payload->port_name_direct_desc.WWNN));
6258	memcpy(rsp_payload->port_name_direct_desc.WWPN,
6259	    vha->fabric_port_name,
6260	    sizeof(rsp_payload->port_name_direct_desc.WWPN));
6261
6262	/* Bufer Credit Descriptor */
6263	rsp_payload->buffer_credit_desc.desc_tag = cpu_to_be32(0x10006);
6264	rsp_payload->buffer_credit_desc.desc_len =
6265		cpu_to_be32(RDP_DESC_LEN(rsp_payload->buffer_credit_desc));
6266	rsp_payload->buffer_credit_desc.fcport_b2b = 0;
6267	rsp_payload->buffer_credit_desc.attached_fcport_b2b = cpu_to_be32(0);
6268	rsp_payload->buffer_credit_desc.fcport_rtt = cpu_to_be32(0);
6269
6270	if (ha->flags.plogi_template_valid) {
6271		uint32_t tmp =
6272		be16_to_cpu(ha->plogi_els_payld.fl_csp.sp_bb_cred);
6273		rsp_payload->buffer_credit_desc.fcport_b2b = cpu_to_be32(tmp);
6274	}
6275
6276	if (rsp_payload_length < sizeof(*rsp_payload))
6277		goto send;
6278
6279	/* Optical Element Descriptor, Temperature */
6280	rsp_payload->optical_elmt_desc[0].desc_tag = cpu_to_be32(0x10007);
6281	rsp_payload->optical_elmt_desc[0].desc_len =
6282		cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6283	/* Optical Element Descriptor, Voltage */
6284	rsp_payload->optical_elmt_desc[1].desc_tag = cpu_to_be32(0x10007);
6285	rsp_payload->optical_elmt_desc[1].desc_len =
6286		cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6287	/* Optical Element Descriptor, Tx Bias Current */
6288	rsp_payload->optical_elmt_desc[2].desc_tag = cpu_to_be32(0x10007);
6289	rsp_payload->optical_elmt_desc[2].desc_len =
6290		cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6291	/* Optical Element Descriptor, Tx Power */
6292	rsp_payload->optical_elmt_desc[3].desc_tag = cpu_to_be32(0x10007);
6293	rsp_payload->optical_elmt_desc[3].desc_len =
6294		cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6295	/* Optical Element Descriptor, Rx Power */
6296	rsp_payload->optical_elmt_desc[4].desc_tag = cpu_to_be32(0x10007);
6297	rsp_payload->optical_elmt_desc[4].desc_len =
6298		cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6299
6300	if (sfp) {
6301		memset(sfp, 0, SFP_RTDI_LEN);
6302		rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0, 64, 0);
6303		if (!rval) {
6304			__be16 *trx = (__force __be16 *)sfp; /* already be16 */
6305
6306			/* Optical Element Descriptor, Temperature */
6307			rsp_payload->optical_elmt_desc[0].high_alarm = trx[0];
6308			rsp_payload->optical_elmt_desc[0].low_alarm = trx[1];
6309			rsp_payload->optical_elmt_desc[0].high_warn = trx[2];
6310			rsp_payload->optical_elmt_desc[0].low_warn = trx[3];
6311			rsp_payload->optical_elmt_desc[0].element_flags =
6312			    cpu_to_be32(1 << 28);
6313
6314			/* Optical Element Descriptor, Voltage */
6315			rsp_payload->optical_elmt_desc[1].high_alarm = trx[4];
6316			rsp_payload->optical_elmt_desc[1].low_alarm = trx[5];
6317			rsp_payload->optical_elmt_desc[1].high_warn = trx[6];
6318			rsp_payload->optical_elmt_desc[1].low_warn = trx[7];
6319			rsp_payload->optical_elmt_desc[1].element_flags =
6320			    cpu_to_be32(2 << 28);
6321
6322			/* Optical Element Descriptor, Tx Bias Current */
6323			rsp_payload->optical_elmt_desc[2].high_alarm = trx[8];
6324			rsp_payload->optical_elmt_desc[2].low_alarm = trx[9];
6325			rsp_payload->optical_elmt_desc[2].high_warn = trx[10];
6326			rsp_payload->optical_elmt_desc[2].low_warn = trx[11];
6327			rsp_payload->optical_elmt_desc[2].element_flags =
6328			    cpu_to_be32(3 << 28);
6329
6330			/* Optical Element Descriptor, Tx Power */
6331			rsp_payload->optical_elmt_desc[3].high_alarm = trx[12];
6332			rsp_payload->optical_elmt_desc[3].low_alarm = trx[13];
6333			rsp_payload->optical_elmt_desc[3].high_warn = trx[14];
6334			rsp_payload->optical_elmt_desc[3].low_warn = trx[15];
6335			rsp_payload->optical_elmt_desc[3].element_flags =
6336			    cpu_to_be32(4 << 28);
6337
6338			/* Optical Element Descriptor, Rx Power */
6339			rsp_payload->optical_elmt_desc[4].high_alarm = trx[16];
6340			rsp_payload->optical_elmt_desc[4].low_alarm = trx[17];
6341			rsp_payload->optical_elmt_desc[4].high_warn = trx[18];
6342			rsp_payload->optical_elmt_desc[4].low_warn = trx[19];
6343			rsp_payload->optical_elmt_desc[4].element_flags =
6344			    cpu_to_be32(5 << 28);
6345		}
6346
6347		memset(sfp, 0, SFP_RTDI_LEN);
6348		rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 112, 64, 0);
6349		if (!rval) {
6350			/* Temperature high/low alarm/warning */
6351			rsp_payload->optical_elmt_desc[0].element_flags |=
6352			    cpu_to_be32(
6353				(sfp[0] >> 7 & 1) << 3 |
6354				(sfp[0] >> 6 & 1) << 2 |
6355				(sfp[4] >> 7 & 1) << 1 |
6356				(sfp[4] >> 6 & 1) << 0);
6357
6358			/* Voltage high/low alarm/warning */
6359			rsp_payload->optical_elmt_desc[1].element_flags |=
6360			    cpu_to_be32(
6361				(sfp[0] >> 5 & 1) << 3 |
6362				(sfp[0] >> 4 & 1) << 2 |
6363				(sfp[4] >> 5 & 1) << 1 |
6364				(sfp[4] >> 4 & 1) << 0);
6365
6366			/* Tx Bias Current high/low alarm/warning */
6367			rsp_payload->optical_elmt_desc[2].element_flags |=
6368			    cpu_to_be32(
6369				(sfp[0] >> 3 & 1) << 3 |
6370				(sfp[0] >> 2 & 1) << 2 |
6371				(sfp[4] >> 3 & 1) << 1 |
6372				(sfp[4] >> 2 & 1) << 0);
6373
6374			/* Tx Power high/low alarm/warning */
6375			rsp_payload->optical_elmt_desc[3].element_flags |=
6376			    cpu_to_be32(
6377				(sfp[0] >> 1 & 1) << 3 |
6378				(sfp[0] >> 0 & 1) << 2 |
6379				(sfp[4] >> 1 & 1) << 1 |
6380				(sfp[4] >> 0 & 1) << 0);
6381
6382			/* Rx Power high/low alarm/warning */
6383			rsp_payload->optical_elmt_desc[4].element_flags |=
6384			    cpu_to_be32(
6385				(sfp[1] >> 7 & 1) << 3 |
6386				(sfp[1] >> 6 & 1) << 2 |
6387				(sfp[5] >> 7 & 1) << 1 |
6388				(sfp[5] >> 6 & 1) << 0);
6389		}
6390	}
6391
6392	/* Optical Product Data Descriptor */
6393	rsp_payload->optical_prod_desc.desc_tag = cpu_to_be32(0x10008);
6394	rsp_payload->optical_prod_desc.desc_len =
6395		cpu_to_be32(RDP_DESC_LEN(rsp_payload->optical_prod_desc));
6396
6397	if (sfp) {
6398		memset(sfp, 0, SFP_RTDI_LEN);
6399		rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 20, 64, 0);
6400		if (!rval) {
6401			memcpy(rsp_payload->optical_prod_desc.vendor_name,
6402			    sfp + 0,
6403			    sizeof(rsp_payload->optical_prod_desc.vendor_name));
6404			memcpy(rsp_payload->optical_prod_desc.part_number,
6405			    sfp + 20,
6406			    sizeof(rsp_payload->optical_prod_desc.part_number));
6407			memcpy(rsp_payload->optical_prod_desc.revision,
6408			    sfp + 36,
6409			    sizeof(rsp_payload->optical_prod_desc.revision));
6410			memcpy(rsp_payload->optical_prod_desc.serial_number,
6411			    sfp + 48,
6412			    sizeof(rsp_payload->optical_prod_desc.serial_number));
6413		}
6414
6415		memset(sfp, 0, SFP_RTDI_LEN);
6416		rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 84, 8, 0);
6417		if (!rval) {
6418			memcpy(rsp_payload->optical_prod_desc.date,
6419			    sfp + 0,
6420			    sizeof(rsp_payload->optical_prod_desc.date));
6421		}
6422	}
6423
6424send:
6425	ql_dbg(ql_dbg_init, vha, 0x0183,
6426	    "Sending ELS Response to RDP Request...\n");
6427	ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0184,
6428	    "-------- ELS RSP -------\n");
6429	ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0185,
6430	    rsp_els, sizeof(*rsp_els));
6431	ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0186,
6432	    "-------- ELS RSP PAYLOAD -------\n");
6433	ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0187,
6434	    rsp_payload, rsp_payload_length);
6435
6436	rval = qla2x00_issue_iocb(vha, rsp_els, rsp_els_dma, 0);
6437
6438	if (rval) {
6439		ql_log(ql_log_warn, vha, 0x0188,
6440		    "%s: iocb failed to execute -> %x\n", __func__, rval);
6441	} else if (rsp_els->comp_status) {
6442		ql_log(ql_log_warn, vha, 0x0189,
6443		    "%s: iocb failed to complete -> completion=%#x subcode=(%#x,%#x)\n",
6444		    __func__, rsp_els->comp_status,
6445		    rsp_els->error_subcode_1, rsp_els->error_subcode_2);
6446	} else {
6447		ql_dbg(ql_dbg_init, vha, 0x018a, "%s: done.\n", __func__);
6448	}
6449
6450dealloc:
6451	if (stat)
6452		dma_free_coherent(&ha->pdev->dev, sizeof(*stat),
6453		    stat, stat_dma);
6454	if (sfp)
6455		dma_free_coherent(&ha->pdev->dev, SFP_RTDI_LEN,
6456		    sfp, sfp_dma);
6457	if (rsp_payload)
6458		dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_payload),
6459		    rsp_payload, rsp_payload_dma);
6460	if (rsp_els)
6461		dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_els),
6462		    rsp_els, rsp_els_dma);
6463}
6464
6465void
6466qla24xx_free_purex_item(struct purex_item *item)
6467{
6468	if (item == &item->vha->default_item)
6469		memset(&item->vha->default_item, 0, sizeof(struct purex_item));
6470	else
6471		kfree(item);
6472}
6473
6474void qla24xx_process_purex_list(struct purex_list *list)
6475{
6476	struct list_head head = LIST_HEAD_INIT(head);
6477	struct purex_item *item, *next;
6478	ulong flags;
6479
6480	spin_lock_irqsave(&list->lock, flags);
6481	list_splice_init(&list->head, &head);
6482	spin_unlock_irqrestore(&list->lock, flags);
6483
6484	list_for_each_entry_safe(item, next, &head, list) {
6485		list_del(&item->list);
6486		item->process_item(item->vha, item);
6487		qla24xx_free_purex_item(item);
6488	}
6489}
6490
6491/*
6492 * Context: task, can sleep
6493 */
6494void
6495qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
6496{
6497#if 0
6498	uint16_t options = (requester_id << 15) | BIT_7;
6499#endif
6500	uint16_t retry;
6501	uint32_t data;
6502	struct qla_hw_data *ha = base_vha->hw;
6503
6504	might_sleep();
6505
6506	/* IDC-unlock implementation using driver-unlock/lock-id
6507	 * remote registers
6508	 */
6509	retry = 0;
6510retry_unlock:
6511	if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
6512	    == QLA_SUCCESS) {
6513		if (data == ha->portnum) {
6514			qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
6515			/* Clearing lock-id by setting 0xff */
6516			qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
6517		} else if (retry < 10) {
6518			/* SV: XXX: IDC unlock retrying needed here? */
6519
6520			/* Retry for IDC-unlock */
6521			msleep(QLA83XX_WAIT_LOGIC_MS);
6522			retry++;
6523			ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
6524			    "Failed to release IDC lock, retrying=%d\n", retry);
6525			goto retry_unlock;
6526		}
6527	} else if (retry < 10) {
6528		/* Retry for IDC-unlock */
6529		msleep(QLA83XX_WAIT_LOGIC_MS);
6530		retry++;
6531		ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
6532		    "Failed to read drv-lockid, retrying=%d\n", retry);
6533		goto retry_unlock;
6534	}
6535
6536	return;
6537
6538#if 0
6539	/* XXX: IDC-unlock implementation using access-control mbx */
6540	retry = 0;
6541retry_unlock2:
6542	if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
6543		if (retry < 10) {
6544			/* Retry for IDC-unlock */
6545			msleep(QLA83XX_WAIT_LOGIC_MS);
6546			retry++;
6547			ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
6548			    "Failed to release IDC lock, retrying=%d\n", retry);
6549			goto retry_unlock2;
6550		}
6551	}
6552
6553	return;
6554#endif
6555}
6556
6557int
6558__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
6559{
6560	int rval = QLA_SUCCESS;
6561	struct qla_hw_data *ha = vha->hw;
6562	uint32_t drv_presence;
6563
6564	rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6565	if (rval == QLA_SUCCESS) {
6566		drv_presence |= (1 << ha->portnum);
6567		rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6568		    drv_presence);
6569	}
6570
6571	return rval;
6572}
6573
6574int
6575qla83xx_set_drv_presence(scsi_qla_host_t *vha)
6576{
6577	int rval = QLA_SUCCESS;
6578
6579	qla83xx_idc_lock(vha, 0);
6580	rval = __qla83xx_set_drv_presence(vha);
6581	qla83xx_idc_unlock(vha, 0);
6582
6583	return rval;
6584}
6585
6586int
6587__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
6588{
6589	int rval = QLA_SUCCESS;
6590	struct qla_hw_data *ha = vha->hw;
6591	uint32_t drv_presence;
6592
6593	rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6594	if (rval == QLA_SUCCESS) {
6595		drv_presence &= ~(1 << ha->portnum);
6596		rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6597		    drv_presence);
6598	}
6599
6600	return rval;
6601}
6602
6603int
6604qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
6605{
6606	int rval = QLA_SUCCESS;
6607
6608	qla83xx_idc_lock(vha, 0);
6609	rval = __qla83xx_clear_drv_presence(vha);
6610	qla83xx_idc_unlock(vha, 0);
6611
6612	return rval;
6613}
6614
6615static void
6616qla83xx_need_reset_handler(scsi_qla_host_t *vha)
6617{
6618	struct qla_hw_data *ha = vha->hw;
6619	uint32_t drv_ack, drv_presence;
6620	unsigned long ack_timeout;
6621
6622	/* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
6623	ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
6624	while (1) {
6625		qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
6626		qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6627		if ((drv_ack & drv_presence) == drv_presence)
6628			break;
6629
6630		if (time_after_eq(jiffies, ack_timeout)) {
6631			ql_log(ql_log_warn, vha, 0xb067,
6632			    "RESET ACK TIMEOUT! drv_presence=0x%x "
6633			    "drv_ack=0x%x\n", drv_presence, drv_ack);
6634			/*
6635			 * The function(s) which did not ack in time are forced
6636			 * to withdraw any further participation in the IDC
6637			 * reset.
6638			 */
6639			if (drv_ack != drv_presence)
6640				qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6641				    drv_ack);
6642			break;
6643		}
6644
6645		qla83xx_idc_unlock(vha, 0);
6646		msleep(1000);
6647		qla83xx_idc_lock(vha, 0);
6648	}
6649
6650	qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
6651	ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
6652}
6653
6654static int
6655qla83xx_device_bootstrap(scsi_qla_host_t *vha)
6656{
6657	int rval = QLA_SUCCESS;
6658	uint32_t idc_control;
6659
6660	qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
6661	ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
6662
6663	/* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
6664	__qla83xx_get_idc_control(vha, &idc_control);
6665	idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
6666	__qla83xx_set_idc_control(vha, 0);
6667
6668	qla83xx_idc_unlock(vha, 0);
6669	rval = qla83xx_restart_nic_firmware(vha);
6670	qla83xx_idc_lock(vha, 0);
6671
6672	if (rval != QLA_SUCCESS) {
6673		ql_log(ql_log_fatal, vha, 0xb06a,
6674		    "Failed to restart NIC f/w.\n");
6675		qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
6676		ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
6677	} else {
6678		ql_dbg(ql_dbg_p3p, vha, 0xb06c,
6679		    "Success in restarting nic f/w.\n");
6680		qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
6681		ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
6682	}
6683
6684	return rval;
6685}
6686
6687/* Assumes idc_lock always held on entry */
6688int
6689qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
6690{
6691	struct qla_hw_data *ha = base_vha->hw;
6692	int rval = QLA_SUCCESS;
6693	unsigned long dev_init_timeout;
6694	uint32_t dev_state;
6695
6696	/* Wait for MAX-INIT-TIMEOUT for the device to go ready */
6697	dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
6698
6699	while (1) {
6700
6701		if (time_after_eq(jiffies, dev_init_timeout)) {
6702			ql_log(ql_log_warn, base_vha, 0xb06e,
6703			    "Initialization TIMEOUT!\n");
6704			/* Init timeout. Disable further NIC Core
6705			 * communication.
6706			 */
6707			qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
6708				QLA8XXX_DEV_FAILED);
6709			ql_log(ql_log_info, base_vha, 0xb06f,
6710			    "HW State: FAILED.\n");
6711		}
6712
6713		qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
6714		switch (dev_state) {
6715		case QLA8XXX_DEV_READY:
6716			if (ha->flags.nic_core_reset_owner)
6717				qla83xx_idc_audit(base_vha,
6718				    IDC_AUDIT_COMPLETION);
6719			ha->flags.nic_core_reset_owner = 0;
6720			ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
6721			    "Reset_owner reset by 0x%x.\n",
6722			    ha->portnum);
6723			goto exit;
6724		case QLA8XXX_DEV_COLD:
6725			if (ha->flags.nic_core_reset_owner)
6726				rval = qla83xx_device_bootstrap(base_vha);
6727			else {
6728			/* Wait for AEN to change device-state */
6729				qla83xx_idc_unlock(base_vha, 0);
6730				msleep(1000);
6731				qla83xx_idc_lock(base_vha, 0);
6732			}
6733			break;
6734		case QLA8XXX_DEV_INITIALIZING:
6735			/* Wait for AEN to change device-state */
6736			qla83xx_idc_unlock(base_vha, 0);
6737			msleep(1000);
6738			qla83xx_idc_lock(base_vha, 0);
6739			break;
6740		case QLA8XXX_DEV_NEED_RESET:
6741			if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
6742				qla83xx_need_reset_handler(base_vha);
6743			else {
6744				/* Wait for AEN to change device-state */
6745				qla83xx_idc_unlock(base_vha, 0);
6746				msleep(1000);
6747				qla83xx_idc_lock(base_vha, 0);
6748			}
6749			/* reset timeout value after need reset handler */
6750			dev_init_timeout = jiffies +
6751			    (ha->fcoe_dev_init_timeout * HZ);
6752			break;
6753		case QLA8XXX_DEV_NEED_QUIESCENT:
6754			/* XXX: DEBUG for now */
6755			qla83xx_idc_unlock(base_vha, 0);
6756			msleep(1000);
6757			qla83xx_idc_lock(base_vha, 0);
6758			break;
6759		case QLA8XXX_DEV_QUIESCENT:
6760			/* XXX: DEBUG for now */
6761			if (ha->flags.quiesce_owner)
6762				goto exit;
6763
6764			qla83xx_idc_unlock(base_vha, 0);
6765			msleep(1000);
6766			qla83xx_idc_lock(base_vha, 0);
6767			dev_init_timeout = jiffies +
6768			    (ha->fcoe_dev_init_timeout * HZ);
6769			break;
6770		case QLA8XXX_DEV_FAILED:
6771			if (ha->flags.nic_core_reset_owner)
6772				qla83xx_idc_audit(base_vha,
6773				    IDC_AUDIT_COMPLETION);
6774			ha->flags.nic_core_reset_owner = 0;
6775			__qla83xx_clear_drv_presence(base_vha);
6776			qla83xx_idc_unlock(base_vha, 0);
6777			qla8xxx_dev_failed_handler(base_vha);
6778			rval = QLA_FUNCTION_FAILED;
6779			qla83xx_idc_lock(base_vha, 0);
6780			goto exit;
6781		case QLA8XXX_BAD_VALUE:
6782			qla83xx_idc_unlock(base_vha, 0);
6783			msleep(1000);
6784			qla83xx_idc_lock(base_vha, 0);
6785			break;
6786		default:
6787			ql_log(ql_log_warn, base_vha, 0xb071,
6788			    "Unknown Device State: %x.\n", dev_state);
6789			qla83xx_idc_unlock(base_vha, 0);
6790			qla8xxx_dev_failed_handler(base_vha);
6791			rval = QLA_FUNCTION_FAILED;
6792			qla83xx_idc_lock(base_vha, 0);
6793			goto exit;
6794		}
6795	}
6796
6797exit:
6798	return rval;
6799}
6800
6801void
6802qla2x00_disable_board_on_pci_error(struct work_struct *work)
6803{
6804	struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
6805	    board_disable);
6806	struct pci_dev *pdev = ha->pdev;
6807	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
6808
6809	ql_log(ql_log_warn, base_vha, 0x015b,
6810	    "Disabling adapter.\n");
6811
6812	if (!atomic_read(&pdev->enable_cnt)) {
6813		ql_log(ql_log_info, base_vha, 0xfffc,
6814		    "PCI device disabled, no action req for PCI error=%lx\n",
6815		    base_vha->pci_flags);
6816		return;
6817	}
6818
6819	/*
6820	 * if UNLOADING flag is already set, then continue unload,
6821	 * where it was set first.
6822	 */
6823	if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags))
6824		return;
6825
6826	qla2x00_wait_for_sess_deletion(base_vha);
6827
6828	qla2x00_delete_all_vps(ha, base_vha);
6829
6830	qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6831
6832	qla2x00_dfs_remove(base_vha);
6833
6834	qla84xx_put_chip(base_vha);
6835
6836	if (base_vha->timer_active)
6837		qla2x00_stop_timer(base_vha);
6838
6839	base_vha->flags.online = 0;
6840
6841	qla2x00_destroy_deferred_work(ha);
6842
6843	/*
6844	 * Do not try to stop beacon blink as it will issue a mailbox
6845	 * command.
6846	 */
6847	qla2x00_free_sysfs_attr(base_vha, false);
6848
6849	fc_remove_host(base_vha->host);
6850
6851	scsi_remove_host(base_vha->host);
6852
6853	base_vha->flags.init_done = 0;
6854	qla25xx_delete_queues(base_vha);
6855	qla2x00_free_fcports(base_vha);
6856	qla2x00_free_irqs(base_vha);
6857	qla2x00_mem_free(ha);
6858	qla82xx_md_free(base_vha);
6859	qla2x00_free_queues(ha);
6860
6861	qla2x00_unmap_iobases(ha);
6862
6863	pci_release_selected_regions(ha->pdev, ha->bars);
6864	pci_disable_device(pdev);
6865
6866	/*
6867	 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
6868	 */
6869}
6870
6871/**************************************************************************
6872* qla2x00_do_dpc
6873*   This kernel thread is a task that is schedule by the interrupt handler
6874*   to perform the background processing for interrupts.
6875*
6876* Notes:
6877* This task always run in the context of a kernel thread.  It
6878* is kick-off by the driver's detect code and starts up
6879* up one per adapter. It immediately goes to sleep and waits for
6880* some fibre event.  When either the interrupt handler or
6881* the timer routine detects a event it will one of the task
6882* bits then wake us up.
6883**************************************************************************/
6884static int
6885qla2x00_do_dpc(void *data)
6886{
6887	scsi_qla_host_t *base_vha;
6888	struct qla_hw_data *ha;
6889	uint32_t online;
6890	struct qla_qpair *qpair;
6891
6892	ha = (struct qla_hw_data *)data;
6893	base_vha = pci_get_drvdata(ha->pdev);
6894
6895	set_user_nice(current, MIN_NICE);
6896
6897	set_current_state(TASK_INTERRUPTIBLE);
6898	while (1) {
6899		ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
6900		    "DPC handler sleeping.\n");
6901
6902		schedule();
6903
6904		if (kthread_should_stop())
6905			break;
6906
6907		if (test_and_clear_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags))
6908			qla_pci_set_eeh_busy(base_vha);
6909
6910		if (!base_vha->flags.init_done || ha->flags.mbox_busy)
6911			goto end_loop;
6912
6913		if (ha->flags.eeh_busy) {
6914			ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
6915			    "eeh_busy=%d.\n", ha->flags.eeh_busy);
6916			goto end_loop;
6917		}
6918
6919		if (test_bit(UNLOADING, &base_vha->dpc_flags))
6920			/* don't do any work. Wait to be terminated by kthread_stop */
6921			goto end_loop;
6922
6923		ha->dpc_active = 1;
6924
6925		ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
6926		    "DPC handler waking up, dpc_flags=0x%lx.\n",
6927		    base_vha->dpc_flags);
6928
6929		if (IS_P3P_TYPE(ha)) {
6930			if (IS_QLA8044(ha)) {
6931				if (test_and_clear_bit(ISP_UNRECOVERABLE,
6932					&base_vha->dpc_flags)) {
6933					qla8044_idc_lock(ha);
6934					qla8044_wr_direct(base_vha,
6935						QLA8044_CRB_DEV_STATE_INDEX,
6936						QLA8XXX_DEV_FAILED);
6937					qla8044_idc_unlock(ha);
6938					ql_log(ql_log_info, base_vha, 0x4004,
6939						"HW State: FAILED.\n");
6940					qla8044_device_state_handler(base_vha);
6941					continue;
6942				}
6943
6944			} else {
6945				if (test_and_clear_bit(ISP_UNRECOVERABLE,
6946					&base_vha->dpc_flags)) {
6947					qla82xx_idc_lock(ha);
6948					qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
6949						QLA8XXX_DEV_FAILED);
6950					qla82xx_idc_unlock(ha);
6951					ql_log(ql_log_info, base_vha, 0x0151,
6952						"HW State: FAILED.\n");
6953					qla82xx_device_state_handler(base_vha);
6954					continue;
6955				}
6956			}
6957
6958			if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
6959				&base_vha->dpc_flags)) {
6960
6961				ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
6962				    "FCoE context reset scheduled.\n");
6963				if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
6964					&base_vha->dpc_flags))) {
6965					if (qla82xx_fcoe_ctx_reset(base_vha)) {
6966						/* FCoE-ctx reset failed.
6967						 * Escalate to chip-reset
6968						 */
6969						set_bit(ISP_ABORT_NEEDED,
6970							&base_vha->dpc_flags);
6971					}
6972					clear_bit(ABORT_ISP_ACTIVE,
6973						&base_vha->dpc_flags);
6974				}
6975
6976				ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
6977				    "FCoE context reset end.\n");
6978			}
6979		} else if (IS_QLAFX00(ha)) {
6980			if (test_and_clear_bit(ISP_UNRECOVERABLE,
6981				&base_vha->dpc_flags)) {
6982				ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
6983				    "Firmware Reset Recovery\n");
6984				if (qlafx00_reset_initialize(base_vha)) {
6985					/* Failed. Abort isp later. */
6986					if (!test_bit(UNLOADING,
6987					    &base_vha->dpc_flags)) {
6988						set_bit(ISP_UNRECOVERABLE,
6989						    &base_vha->dpc_flags);
6990						ql_dbg(ql_dbg_dpc, base_vha,
6991						    0x4021,
6992						    "Reset Recovery Failed\n");
6993					}
6994				}
6995			}
6996
6997			if (test_and_clear_bit(FX00_TARGET_SCAN,
6998				&base_vha->dpc_flags)) {
6999				ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
7000				    "ISPFx00 Target Scan scheduled\n");
7001				if (qlafx00_rescan_isp(base_vha)) {
7002					if (!test_bit(UNLOADING,
7003					    &base_vha->dpc_flags))
7004						set_bit(ISP_UNRECOVERABLE,
7005						    &base_vha->dpc_flags);
7006					ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
7007					    "ISPFx00 Target Scan Failed\n");
7008				}
7009				ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
7010				    "ISPFx00 Target Scan End\n");
7011			}
7012			if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
7013				&base_vha->dpc_flags)) {
7014				ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
7015				    "ISPFx00 Host Info resend scheduled\n");
7016				qlafx00_fx_disc(base_vha,
7017				    &base_vha->hw->mr.fcport,
7018				    FXDISC_REG_HOST_INFO);
7019			}
7020		}
7021
7022		if (test_and_clear_bit(DETECT_SFP_CHANGE,
7023		    &base_vha->dpc_flags)) {
7024			/* Semantic:
7025			 *  - NO-OP -- await next ISP-ABORT. Preferred method
7026			 *             to minimize disruptions that will occur
7027			 *             when a forced chip-reset occurs.
7028			 *  - Force -- ISP-ABORT scheduled.
7029			 */
7030			/* set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); */
7031		}
7032
7033		if (test_and_clear_bit
7034		    (ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
7035		    !test_bit(UNLOADING, &base_vha->dpc_flags)) {
7036			bool do_reset = true;
7037
7038			switch (base_vha->qlini_mode) {
7039			case QLA2XXX_INI_MODE_ENABLED:
7040				break;
7041			case QLA2XXX_INI_MODE_DISABLED:
7042				if (!qla_tgt_mode_enabled(base_vha) &&
7043				    !ha->flags.fw_started)
7044					do_reset = false;
7045				break;
7046			case QLA2XXX_INI_MODE_DUAL:
7047				if (!qla_dual_mode_enabled(base_vha) &&
7048				    !ha->flags.fw_started)
7049					do_reset = false;
7050				break;
7051			default:
7052				break;
7053			}
7054
7055			if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE,
7056			    &base_vha->dpc_flags))) {
7057				base_vha->flags.online = 1;
7058				ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
7059				    "ISP abort scheduled.\n");
7060				if (ha->isp_ops->abort_isp(base_vha)) {
7061					/* failed. retry later */
7062					set_bit(ISP_ABORT_NEEDED,
7063					    &base_vha->dpc_flags);
7064				}
7065				clear_bit(ABORT_ISP_ACTIVE,
7066						&base_vha->dpc_flags);
7067				ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
7068				    "ISP abort end.\n");
7069			}
7070		}
7071
7072		if (test_bit(PROCESS_PUREX_IOCB, &base_vha->dpc_flags)) {
7073			if (atomic_read(&base_vha->loop_state) == LOOP_READY) {
7074				qla24xx_process_purex_list
7075					(&base_vha->purex_list);
7076				clear_bit(PROCESS_PUREX_IOCB,
7077				    &base_vha->dpc_flags);
7078			}
7079		}
7080
7081		if (IS_QLAFX00(ha))
7082			goto loop_resync_check;
7083
7084		if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7085			ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
7086			    "Quiescence mode scheduled.\n");
7087			if (IS_P3P_TYPE(ha)) {
7088				if (IS_QLA82XX(ha))
7089					qla82xx_device_state_handler(base_vha);
7090				if (IS_QLA8044(ha))
7091					qla8044_device_state_handler(base_vha);
7092				clear_bit(ISP_QUIESCE_NEEDED,
7093				    &base_vha->dpc_flags);
7094				if (!ha->flags.quiesce_owner) {
7095					qla2x00_perform_loop_resync(base_vha);
7096					if (IS_QLA82XX(ha)) {
7097						qla82xx_idc_lock(ha);
7098						qla82xx_clear_qsnt_ready(
7099						    base_vha);
7100						qla82xx_idc_unlock(ha);
7101					} else if (IS_QLA8044(ha)) {
7102						qla8044_idc_lock(ha);
7103						qla8044_clear_qsnt_ready(
7104						    base_vha);
7105						qla8044_idc_unlock(ha);
7106					}
7107				}
7108			} else {
7109				clear_bit(ISP_QUIESCE_NEEDED,
7110				    &base_vha->dpc_flags);
7111				qla2x00_quiesce_io(base_vha);
7112			}
7113			ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
7114			    "Quiescence mode end.\n");
7115		}
7116
7117		if (test_and_clear_bit(RESET_MARKER_NEEDED,
7118				&base_vha->dpc_flags) &&
7119		    (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
7120
7121			ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
7122			    "Reset marker scheduled.\n");
7123			qla2x00_rst_aen(base_vha);
7124			clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7125			ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
7126			    "Reset marker end.\n");
7127		}
7128
7129		/* Retry each device up to login retry count */
7130		if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) &&
7131		    !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
7132		    atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
7133
7134			if (!base_vha->relogin_jif ||
7135			    time_after_eq(jiffies, base_vha->relogin_jif)) {
7136				base_vha->relogin_jif = jiffies + HZ;
7137				clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags);
7138
7139				ql_dbg(ql_dbg_disc, base_vha, 0x400d,
7140				    "Relogin scheduled.\n");
7141				qla24xx_post_relogin_work(base_vha);
7142			}
7143		}
7144loop_resync_check:
7145		if (!qla2x00_reset_active(base_vha) &&
7146		    test_and_clear_bit(LOOP_RESYNC_NEEDED,
7147		    &base_vha->dpc_flags)) {
7148			/*
7149			 * Allow abort_isp to complete before moving on to scanning.
7150			 */
7151			ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
7152			    "Loop resync scheduled.\n");
7153
7154			if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
7155			    &base_vha->dpc_flags))) {
7156
7157				qla2x00_loop_resync(base_vha);
7158
7159				clear_bit(LOOP_RESYNC_ACTIVE,
7160						&base_vha->dpc_flags);
7161			}
7162
7163			ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
7164			    "Loop resync end.\n");
7165		}
7166
7167		if (IS_QLAFX00(ha))
7168			goto intr_on_check;
7169
7170		if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
7171		    atomic_read(&base_vha->loop_state) == LOOP_READY) {
7172			clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
7173			qla2xxx_flash_npiv_conf(base_vha);
7174		}
7175
7176intr_on_check:
7177		if (!ha->interrupts_on)
7178			ha->isp_ops->enable_intrs(ha);
7179
7180		if (test_and_clear_bit(BEACON_BLINK_NEEDED,
7181					&base_vha->dpc_flags)) {
7182			if (ha->beacon_blink_led == 1)
7183				ha->isp_ops->beacon_blink(base_vha);
7184		}
7185
7186		/* qpair online check */
7187		if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
7188		    &base_vha->dpc_flags)) {
7189			if (ha->flags.eeh_busy ||
7190			    ha->flags.pci_channel_io_perm_failure)
7191				online = 0;
7192			else
7193				online = 1;
7194
7195			mutex_lock(&ha->mq_lock);
7196			list_for_each_entry(qpair, &base_vha->qp_list,
7197			    qp_list_elem)
7198			qpair->online = online;
7199			mutex_unlock(&ha->mq_lock);
7200		}
7201
7202		if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED,
7203				       &base_vha->dpc_flags)) {
7204			u16 threshold = ha->nvme_last_rptd_aen + ha->last_zio_threshold;
7205
7206			if (threshold > ha->orig_fw_xcb_count)
7207				threshold = ha->orig_fw_xcb_count;
7208
7209			ql_log(ql_log_info, base_vha, 0xffffff,
7210			       "SET ZIO Activity exchange threshold to %d.\n",
7211			       threshold);
7212			if (qla27xx_set_zio_threshold(base_vha, threshold)) {
7213				ql_log(ql_log_info, base_vha, 0xffffff,
7214				       "Unable to SET ZIO Activity exchange threshold to %d.\n",
7215				       threshold);
7216			}
7217		}
7218
7219		if (!IS_QLAFX00(ha))
7220			qla2x00_do_dpc_all_vps(base_vha);
7221
7222		if (test_and_clear_bit(N2N_LINK_RESET,
7223			&base_vha->dpc_flags)) {
7224			qla2x00_lip_reset(base_vha);
7225		}
7226
7227		ha->dpc_active = 0;
7228end_loop:
7229		set_current_state(TASK_INTERRUPTIBLE);
7230	} /* End of while(1) */
7231	__set_current_state(TASK_RUNNING);
7232
7233	ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
7234	    "DPC handler exiting.\n");
7235
7236	/*
7237	 * Make sure that nobody tries to wake us up again.
7238	 */
7239	ha->dpc_active = 0;
7240
7241	return 0;
7242}
7243
7244void
7245qla2xxx_wake_dpc(struct scsi_qla_host *vha)
7246{
7247	struct qla_hw_data *ha = vha->hw;
7248	struct task_struct *t = ha->dpc_thread;
7249
7250	if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
7251		wake_up_process(t);
7252}
7253EXPORT_SYMBOL(qla2xxx_wake_dpc);
7254
7255/*
7256*  qla2x00_rst_aen
7257*      Processes asynchronous reset.
7258*
7259* Input:
7260*      ha  = adapter block pointer.
7261*/
7262static void
7263qla2x00_rst_aen(scsi_qla_host_t *vha)
7264{
7265	if (vha->flags.online && !vha->flags.reset_active &&
7266	    !atomic_read(&vha->loop_down_timer) &&
7267	    !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
7268		do {
7269			clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
7270
7271			/*
7272			 * Issue marker command only when we are going to start
7273			 * the I/O.
7274			 */
7275			vha->marker_needed = 1;
7276		} while (!atomic_read(&vha->loop_down_timer) &&
7277		    (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
7278	}
7279}
7280
7281static bool qla_do_heartbeat(struct scsi_qla_host *vha)
7282{
7283	struct qla_hw_data *ha = vha->hw;
7284	u32 cmpl_cnt;
7285	u16 i;
7286	bool do_heartbeat = false;
7287
7288	/*
7289	 * Allow do_heartbeat only if we don’t have any active interrupts,
7290	 * but there are still IOs outstanding with firmware.
7291	 */
7292	cmpl_cnt = ha->base_qpair->cmd_completion_cnt;
7293	if (cmpl_cnt == ha->base_qpair->prev_completion_cnt &&
7294	    cmpl_cnt != ha->base_qpair->cmd_cnt) {
7295		do_heartbeat = true;
7296		goto skip;
7297	}
7298	ha->base_qpair->prev_completion_cnt = cmpl_cnt;
7299
7300	for (i = 0; i < ha->max_qpairs; i++) {
7301		if (ha->queue_pair_map[i]) {
7302			cmpl_cnt = ha->queue_pair_map[i]->cmd_completion_cnt;
7303			if (cmpl_cnt == ha->queue_pair_map[i]->prev_completion_cnt &&
7304			    cmpl_cnt != ha->queue_pair_map[i]->cmd_cnt) {
7305				do_heartbeat = true;
7306				break;
7307			}
7308			ha->queue_pair_map[i]->prev_completion_cnt = cmpl_cnt;
7309		}
7310	}
7311
7312skip:
7313	return do_heartbeat;
7314}
7315
7316static void qla_heart_beat(struct scsi_qla_host *vha, u16 dpc_started)
7317{
7318	struct qla_hw_data *ha = vha->hw;
7319
7320	if (vha->vp_idx)
7321		return;
7322
7323	if (vha->hw->flags.eeh_busy || qla2x00_chip_is_down(vha))
7324		return;
7325
7326	/*
7327	 * dpc thread cannot run if heartbeat is running at the same time.
7328	 * We also do not want to starve heartbeat task. Therefore, do
7329	 * heartbeat task at least once every 5 seconds.
7330	 */
7331	if (dpc_started &&
7332	    time_before(jiffies, ha->last_heartbeat_run_jiffies + 5 * HZ))
7333		return;
7334
7335	if (qla_do_heartbeat(vha)) {
7336		ha->last_heartbeat_run_jiffies = jiffies;
7337		queue_work(ha->wq, &ha->heartbeat_work);
7338	}
7339}
7340
7341static void qla_wind_down_chip(scsi_qla_host_t *vha)
7342{
7343	struct qla_hw_data *ha = vha->hw;
7344
7345	if (!ha->flags.eeh_busy)
7346		return;
7347	if (ha->pci_error_state)
7348		/* system is trying to recover */
7349		return;
7350
7351	/*
7352	 * Current system is not handling PCIE error.  At this point, this is
7353	 * best effort to wind down the adapter.
7354	 */
7355	if (time_after_eq(jiffies, ha->eeh_jif + ql2xdelay_before_pci_error_handling * HZ) &&
7356	    !ha->flags.eeh_flush) {
7357		ql_log(ql_log_info, vha, 0x9009,
7358		    "PCI Error detected, attempting to reset hardware.\n");
7359
7360		ha->isp_ops->reset_chip(vha);
7361		ha->isp_ops->disable_intrs(ha);
7362
7363		ha->flags.eeh_flush = EEH_FLUSH_RDY;
7364		ha->eeh_jif = jiffies;
7365
7366	} else if (ha->flags.eeh_flush == EEH_FLUSH_RDY &&
7367	    time_after_eq(jiffies, ha->eeh_jif +  5 * HZ)) {
7368		pci_clear_master(ha->pdev);
7369
7370		/* flush all command */
7371		qla2x00_abort_isp_cleanup(vha);
7372		ha->flags.eeh_flush = EEH_FLUSH_DONE;
7373
7374		ql_log(ql_log_info, vha, 0x900a,
7375		    "PCI Error handling complete, all IOs aborted.\n");
7376	}
7377}
7378
7379/**************************************************************************
7380*   qla2x00_timer
7381*
7382* Description:
7383*   One second timer
7384*
7385* Context: Interrupt
7386***************************************************************************/
7387void
7388qla2x00_timer(struct timer_list *t)
7389{
7390	scsi_qla_host_t *vha = timer_container_of(vha, t, timer);
7391	unsigned long	cpu_flags = 0;
7392	int		start_dpc = 0;
7393	int		index;
7394	srb_t		*sp;
7395	uint16_t        w;
7396	struct qla_hw_data *ha = vha->hw;
7397	struct req_que *req;
7398	unsigned long flags;
7399	fc_port_t *fcport = NULL;
7400
7401	if (ha->flags.eeh_busy) {
7402		qla_wind_down_chip(vha);
7403
7404		ql_dbg(ql_dbg_timer, vha, 0x6000,
7405		    "EEH = %d, restarting timer.\n",
7406		    ha->flags.eeh_busy);
7407		qla2x00_restart_timer(vha, WATCH_INTERVAL);
7408		return;
7409	}
7410
7411	/*
7412	 * Hardware read to raise pending EEH errors during mailbox waits. If
7413	 * the read returns -1 then disable the board.
7414	 */
7415	if (!pci_channel_offline(ha->pdev)) {
7416		pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
7417		qla2x00_check_reg16_for_disconnect(vha, w);
7418	}
7419
7420	/* Make sure qla82xx_watchdog is run only for physical port */
7421	if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
7422		if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
7423			start_dpc++;
7424		if (IS_QLA82XX(ha))
7425			qla82xx_watchdog(vha);
7426		else if (IS_QLA8044(ha))
7427			qla8044_watchdog(vha);
7428	}
7429
7430	if (!vha->vp_idx && IS_QLAFX00(ha))
7431		qlafx00_timer_routine(vha);
7432
7433	if (vha->link_down_time < QLA2XX_MAX_LINK_DOWN_TIME)
7434		vha->link_down_time++;
7435
7436	spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
7437	list_for_each_entry(fcport, &vha->vp_fcports, list) {
7438		if (fcport->tgt_link_down_time < QLA2XX_MAX_LINK_DOWN_TIME)
7439			fcport->tgt_link_down_time++;
7440	}
7441	spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
7442
7443	/* Loop down handler. */
7444	if (atomic_read(&vha->loop_down_timer) > 0 &&
7445	    !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
7446	    !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
7447		&& vha->flags.online) {
7448
7449		if (atomic_read(&vha->loop_down_timer) ==
7450		    vha->loop_down_abort_time) {
7451
7452			ql_log(ql_log_info, vha, 0x6008,
7453			    "Loop down - aborting the queues before time expires.\n");
7454
7455			if (!IS_QLA2100(ha) && vha->link_down_timeout)
7456				atomic_set(&vha->loop_state, LOOP_DEAD);
7457
7458			/*
7459			 * Schedule an ISP abort to return any FCP2-device
7460			 * commands.
7461			 */
7462			/* NPIV - scan physical port only */
7463			if (!vha->vp_idx) {
7464				spin_lock_irqsave(&ha->hardware_lock,
7465				    cpu_flags);
7466				req = ha->req_q_map[0];
7467				for (index = 1;
7468				    index < req->num_outstanding_cmds;
7469				    index++) {
7470					fc_port_t *sfcp;
7471
7472					sp = req->outstanding_cmds[index];
7473					if (!sp)
7474						continue;
7475					if (sp->cmd_type != TYPE_SRB)
7476						continue;
7477					if (sp->type != SRB_SCSI_CMD)
7478						continue;
7479					sfcp = sp->fcport;
7480					if (!(sfcp->flags & FCF_FCP2_DEVICE))
7481						continue;
7482
7483					if (IS_QLA82XX(ha))
7484						set_bit(FCOE_CTX_RESET_NEEDED,
7485							&vha->dpc_flags);
7486					else
7487						set_bit(ISP_ABORT_NEEDED,
7488							&vha->dpc_flags);
7489					break;
7490				}
7491				spin_unlock_irqrestore(&ha->hardware_lock,
7492								cpu_flags);
7493			}
7494			start_dpc++;
7495		}
7496
7497		/* if the loop has been down for 4 minutes, reinit adapter */
7498		if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
7499			if (!(vha->device_flags & DFLG_NO_CABLE) && !vha->vp_idx) {
7500				ql_log(ql_log_warn, vha, 0x6009,
7501				    "Loop down - aborting ISP.\n");
7502
7503				if (IS_QLA82XX(ha))
7504					set_bit(FCOE_CTX_RESET_NEEDED,
7505						&vha->dpc_flags);
7506				else
7507					set_bit(ISP_ABORT_NEEDED,
7508						&vha->dpc_flags);
7509			}
7510		}
7511		ql_dbg(ql_dbg_timer, vha, 0x600a,
7512		    "Loop down - seconds remaining %d.\n",
7513		    atomic_read(&vha->loop_down_timer));
7514	}
7515	/* Check if beacon LED needs to be blinked for physical host only */
7516	if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
7517		/* There is no beacon_blink function for ISP82xx */
7518		if (!IS_P3P_TYPE(ha)) {
7519			set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
7520			start_dpc++;
7521		}
7522	}
7523
7524	/* check if edif running */
7525	if (vha->hw->flags.edif_enabled)
7526		qla_edif_timer(vha);
7527
7528	/* Process any deferred work. */
7529	if (!list_empty(&vha->work_list)) {
7530		unsigned long flags;
7531		bool q = false;
7532
7533		spin_lock_irqsave(&vha->work_lock, flags);
7534		if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
7535			q = true;
7536		spin_unlock_irqrestore(&vha->work_lock, flags);
7537		if (q)
7538			queue_work(vha->hw->wq, &vha->iocb_work);
7539	}
7540
7541	/*
7542	 * FC-NVME
7543	 * see if the active AEN count has changed from what was last reported.
7544	 */
7545	index = atomic_read(&ha->nvme_active_aen_cnt);
7546	if (!vha->vp_idx &&
7547	    (index != ha->nvme_last_rptd_aen) &&
7548	    ha->zio_mode == QLA_ZIO_MODE_6 &&
7549	    !ha->flags.host_shutting_down) {
7550		ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
7551		ql_log(ql_log_info, vha, 0x3002,
7552		    "nvme: Sched: Set ZIO exchange threshold to %d.\n",
7553		    ha->nvme_last_rptd_aen);
7554		set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
7555		start_dpc++;
7556	}
7557
7558	if (!vha->vp_idx &&
7559	    atomic_read(&ha->zio_threshold) != ha->last_zio_threshold &&
7560	    IS_ZIO_THRESHOLD_CAPABLE(ha)) {
7561		ql_log(ql_log_info, vha, 0x3002,
7562		    "Sched: Set ZIO exchange threshold to %d.\n",
7563		    ha->last_zio_threshold);
7564		ha->last_zio_threshold = atomic_read(&ha->zio_threshold);
7565		set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
7566		start_dpc++;
7567	}
7568	qla_adjust_buf(vha);
7569
7570	/* borrowing w to signify dpc will run */
7571	w = 0;
7572	/* Schedule the DPC routine if needed */
7573	if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
7574	    test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
7575	    start_dpc ||
7576	    test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
7577	    test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
7578	    test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
7579	    test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
7580	    test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
7581	    test_bit(RELOGIN_NEEDED, &vha->dpc_flags) ||
7582	    test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags))) {
7583		ql_dbg(ql_dbg_timer, vha, 0x600b,
7584		    "isp_abort_needed=%d loop_resync_needed=%d "
7585		    "start_dpc=%d reset_marker_needed=%d",
7586		    test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
7587		    test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
7588		    start_dpc, test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
7589		ql_dbg(ql_dbg_timer, vha, 0x600c,
7590		    "beacon_blink_needed=%d isp_unrecoverable=%d "
7591		    "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
7592		    "relogin_needed=%d, Process_purex_iocb=%d.\n",
7593		    test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
7594		    test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
7595		    test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
7596		    test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
7597		    test_bit(RELOGIN_NEEDED, &vha->dpc_flags),
7598		    test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags));
7599		qla2xxx_wake_dpc(vha);
7600		w = 1;
7601	}
7602
7603	qla_heart_beat(vha, w);
7604
7605	qla2x00_restart_timer(vha, WATCH_INTERVAL);
7606}
7607
7608/* Firmware interface routines. */
7609
7610#define FW_ISP21XX	0
7611#define FW_ISP22XX	1
7612#define FW_ISP2300	2
7613#define FW_ISP2322	3
7614#define FW_ISP24XX	4
7615#define FW_ISP25XX	5
7616#define FW_ISP81XX	6
7617#define FW_ISP82XX	7
7618#define FW_ISP2031	8
7619#define FW_ISP8031	9
7620#define FW_ISP27XX	10
7621#define FW_ISP28XX	11
7622
7623#define FW_FILE_ISP21XX	"ql2100_fw.bin"
7624#define FW_FILE_ISP22XX	"ql2200_fw.bin"
7625#define FW_FILE_ISP2300	"ql2300_fw.bin"
7626#define FW_FILE_ISP2322	"ql2322_fw.bin"
7627#define FW_FILE_ISP24XX	"ql2400_fw.bin"
7628#define FW_FILE_ISP25XX	"ql2500_fw.bin"
7629#define FW_FILE_ISP81XX	"ql8100_fw.bin"
7630#define FW_FILE_ISP82XX	"ql8200_fw.bin"
7631#define FW_FILE_ISP2031	"ql2600_fw.bin"
7632#define FW_FILE_ISP8031	"ql8300_fw.bin"
7633#define FW_FILE_ISP27XX	"ql2700_fw.bin"
7634#define FW_FILE_ISP28XX	"ql2800_fw.bin"
7635
7636
7637static DEFINE_MUTEX(qla_fw_lock);
7638
7639static struct fw_blob qla_fw_blobs[] = {
7640	{ .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
7641	{ .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
7642	{ .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
7643	{ .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
7644	{ .name = FW_FILE_ISP24XX, },
7645	{ .name = FW_FILE_ISP25XX, },
7646	{ .name = FW_FILE_ISP81XX, },
7647	{ .name = FW_FILE_ISP82XX, },
7648	{ .name = FW_FILE_ISP2031, },
7649	{ .name = FW_FILE_ISP8031, },
7650	{ .name = FW_FILE_ISP27XX, },
7651	{ .name = FW_FILE_ISP28XX, },
7652	{ .name = NULL, },
7653};
7654
7655struct fw_blob *
7656qla2x00_request_firmware(scsi_qla_host_t *vha)
7657{
7658	struct qla_hw_data *ha = vha->hw;
7659	struct fw_blob *blob;
7660
7661	if (IS_QLA2100(ha)) {
7662		blob = &qla_fw_blobs[FW_ISP21XX];
7663	} else if (IS_QLA2200(ha)) {
7664		blob = &qla_fw_blobs[FW_ISP22XX];
7665	} else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
7666		blob = &qla_fw_blobs[FW_ISP2300];
7667	} else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
7668		blob = &qla_fw_blobs[FW_ISP2322];
7669	} else if (IS_QLA24XX_TYPE(ha)) {
7670		blob = &qla_fw_blobs[FW_ISP24XX];
7671	} else if (IS_QLA25XX(ha)) {
7672		blob = &qla_fw_blobs[FW_ISP25XX];
7673	} else if (IS_QLA81XX(ha)) {
7674		blob = &qla_fw_blobs[FW_ISP81XX];
7675	} else if (IS_QLA82XX(ha)) {
7676		blob = &qla_fw_blobs[FW_ISP82XX];
7677	} else if (IS_QLA2031(ha)) {
7678		blob = &qla_fw_blobs[FW_ISP2031];
7679	} else if (IS_QLA8031(ha)) {
7680		blob = &qla_fw_blobs[FW_ISP8031];
7681	} else if (IS_QLA27XX(ha)) {
7682		blob = &qla_fw_blobs[FW_ISP27XX];
7683	} else if (IS_QLA28XX(ha)) {
7684		blob = &qla_fw_blobs[FW_ISP28XX];
7685	} else {
7686		return NULL;
7687	}
7688
7689	if (!blob->name)
7690		return NULL;
7691
7692	mutex_lock(&qla_fw_lock);
7693	if (blob->fw)
7694		goto out;
7695
7696	if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7697		ql_log(ql_log_warn, vha, 0x0063,
7698		    "Failed to load firmware image (%s).\n", blob->name);
7699		blob->fw = NULL;
7700		blob = NULL;
7701	}
7702
7703out:
7704	mutex_unlock(&qla_fw_lock);
7705	return blob;
7706}
7707
7708static void
7709qla2x00_release_firmware(void)
7710{
7711	struct fw_blob *blob;
7712
7713	mutex_lock(&qla_fw_lock);
7714	for (blob = qla_fw_blobs; blob->name; blob++)
7715		release_firmware(blob->fw);
7716	mutex_unlock(&qla_fw_lock);
7717}
7718
7719static void qla_pci_error_cleanup(scsi_qla_host_t *vha)
7720{
7721	struct qla_hw_data *ha = vha->hw;
7722	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
7723	struct qla_qpair *qpair = NULL;
7724	struct scsi_qla_host *vp, *tvp;
7725	fc_port_t *fcport;
7726	int i;
7727	unsigned long flags;
7728
7729	ql_dbg(ql_dbg_aer, vha, 0x9000,
7730	       "%s\n", __func__);
7731	ha->chip_reset++;
7732
7733	ha->base_qpair->chip_reset = ha->chip_reset;
7734	for (i = 0; i < ha->max_qpairs; i++) {
7735		if (ha->queue_pair_map[i])
7736			ha->queue_pair_map[i]->chip_reset =
7737			    ha->base_qpair->chip_reset;
7738	}
7739
7740	/*
7741	 * purge mailbox might take a while. Slot Reset/chip reset
7742	 * will take care of the purge
7743	 */
7744
7745	mutex_lock(&ha->mq_lock);
7746	ha->base_qpair->online = 0;
7747	list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7748		qpair->online = 0;
7749	wmb();
7750	mutex_unlock(&ha->mq_lock);
7751
7752	qla2x00_mark_all_devices_lost(vha);
7753
7754	spin_lock_irqsave(&ha->vport_slock, flags);
7755	list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
7756		atomic_inc(&vp->vref_count);
7757		spin_unlock_irqrestore(&ha->vport_slock, flags);
7758		qla2x00_mark_all_devices_lost(vp);
7759		spin_lock_irqsave(&ha->vport_slock, flags);
7760		atomic_dec(&vp->vref_count);
7761	}
7762	spin_unlock_irqrestore(&ha->vport_slock, flags);
7763
7764	/* Clear all async request states across all VPs. */
7765	list_for_each_entry(fcport, &vha->vp_fcports, list)
7766		fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
7767
7768	spin_lock_irqsave(&ha->vport_slock, flags);
7769	list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
7770		atomic_inc(&vp->vref_count);
7771		spin_unlock_irqrestore(&ha->vport_slock, flags);
7772		list_for_each_entry(fcport, &vp->vp_fcports, list)
7773			fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
7774		spin_lock_irqsave(&ha->vport_slock, flags);
7775		atomic_dec(&vp->vref_count);
7776	}
7777	spin_unlock_irqrestore(&ha->vport_slock, flags);
7778}
7779
7780
7781/**
7782 * qla2xxx_set_affinity_nobalance
7783 * @pdev: pci_dev struct for a qla2xxx device
7784 * @flag: bool
7785 * true: enable "IRQ_NO_BALANCING" bit for msix interrupt
7786 * false: disable "IRQ_NO_BALANCING" bit for msix interrupt
7787 * Description: This function will be called to disable/enable
7788 * "IRQ_NO_BALANCING" to avoid irqbalance daemon
7789 * kicking in during adapter reset.
7790 **/
7791
7792static void qla2xxx_set_affinity_nobalance(struct pci_dev *pdev, bool flag)
7793{
7794	int irq, i;
7795
7796	for (i = 0; i < QLA_BASE_VECTORS; i++) {
7797		irq = pci_irq_vector(pdev, i);
7798
7799		if (flag)
7800			irq_set_status_flags(irq, IRQ_NO_BALANCING);
7801		else
7802			irq_clear_status_flags(irq, IRQ_NO_BALANCING);
7803	}
7804}
7805
7806static pci_ers_result_t
7807qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
7808{
7809	scsi_qla_host_t *vha = pci_get_drvdata(pdev);
7810	struct qla_hw_data *ha = vha->hw;
7811	pci_ers_result_t ret = PCI_ERS_RESULT_NEED_RESET;
7812
7813	ql_log(ql_log_warn, vha, 0x9000,
7814	       "PCI error detected, state %x.\n", state);
7815	ha->pci_error_state = QLA_PCI_ERR_DETECTED;
7816
7817	if (!atomic_read(&pdev->enable_cnt)) {
7818		ql_log(ql_log_info, vha, 0xffff,
7819			"PCI device is disabled,state %x\n", state);
7820		ret = PCI_ERS_RESULT_NEED_RESET;
7821		goto out;
7822	}
7823
7824	qla2xxx_set_affinity_nobalance(pdev, false);
7825
7826	switch (state) {
7827	case pci_channel_io_normal:
7828		qla_pci_set_eeh_busy(vha);
7829		if (ql2xmqsupport || ql2xnvmeenable) {
7830			set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
7831			qla2xxx_wake_dpc(vha);
7832		}
7833		ret = PCI_ERS_RESULT_CAN_RECOVER;
7834		break;
7835	case pci_channel_io_frozen:
7836		qla_pci_set_eeh_busy(vha);
7837		ret = PCI_ERS_RESULT_NEED_RESET;
7838		break;
7839	case pci_channel_io_perm_failure:
7840		ha->flags.pci_channel_io_perm_failure = 1;
7841		qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
7842		if (ql2xmqsupport || ql2xnvmeenable) {
7843			set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
7844			qla2xxx_wake_dpc(vha);
7845		}
7846		ret = PCI_ERS_RESULT_DISCONNECT;
7847	}
7848out:
7849	ql_dbg(ql_dbg_aer, vha, 0x600d,
7850	       "PCI error detected returning [%x].\n", ret);
7851	return ret;
7852}
7853
7854static pci_ers_result_t
7855qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
7856{
7857	int risc_paused = 0;
7858	uint32_t stat;
7859	unsigned long flags;
7860	scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7861	struct qla_hw_data *ha = base_vha->hw;
7862	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
7863	struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
7864
7865	ql_log(ql_log_warn, base_vha, 0x9000,
7866	       "mmio enabled\n");
7867
7868	ha->pci_error_state = QLA_PCI_MMIO_ENABLED;
7869
7870	if (IS_QLA82XX(ha))
7871		return PCI_ERS_RESULT_RECOVERED;
7872
7873	if (qla2x00_isp_reg_stat(ha)) {
7874		ql_log(ql_log_info, base_vha, 0x803f,
7875		    "During mmio enabled, PCI/Register disconnect still detected.\n");
7876		goto out;
7877	}
7878
7879	spin_lock_irqsave(&ha->hardware_lock, flags);
7880	if (IS_QLA2100(ha) || IS_QLA2200(ha)){
7881		stat = rd_reg_word(&reg->hccr);
7882		if (stat & HCCR_RISC_PAUSE)
7883			risc_paused = 1;
7884	} else if (IS_QLA23XX(ha)) {
7885		stat = rd_reg_dword(&reg->u.isp2300.host_status);
7886		if (stat & HSR_RISC_PAUSED)
7887			risc_paused = 1;
7888	} else if (IS_FWI2_CAPABLE(ha)) {
7889		stat = rd_reg_dword(&reg24->host_status);
7890		if (stat & HSRX_RISC_PAUSED)
7891			risc_paused = 1;
7892	}
7893	spin_unlock_irqrestore(&ha->hardware_lock, flags);
7894
7895	if (risc_paused) {
7896		ql_log(ql_log_info, base_vha, 0x9003,
7897		    "RISC paused -- mmio_enabled, Dumping firmware.\n");
7898		qla2xxx_dump_fw(base_vha);
7899	}
7900out:
7901	/* set PCI_ERS_RESULT_NEED_RESET to trigger call to qla2xxx_pci_slot_reset */
7902	ql_dbg(ql_dbg_aer, base_vha, 0x600d,
7903	       "mmio enabled returning.\n");
7904	return PCI_ERS_RESULT_NEED_RESET;
7905}
7906
7907static pci_ers_result_t
7908qla2xxx_pci_slot_reset(struct pci_dev *pdev)
7909{
7910	pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
7911	scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7912	struct qla_hw_data *ha = base_vha->hw;
7913	int rc;
7914	struct qla_qpair *qpair = NULL;
7915
7916	ql_log(ql_log_warn, base_vha, 0x9004,
7917	       "Slot Reset.\n");
7918
7919	ha->pci_error_state = QLA_PCI_SLOT_RESET;
7920
7921	pci_restore_state(pdev);
7922
7923	if (ha->mem_only)
7924		rc = pci_enable_device_mem(pdev);
7925	else
7926		rc = pci_enable_device(pdev);
7927
7928	if (rc) {
7929		ql_log(ql_log_warn, base_vha, 0x9005,
7930		    "Can't re-enable PCI device after reset.\n");
7931		goto exit_slot_reset;
7932	}
7933
7934
7935	if (ha->isp_ops->pci_config(base_vha))
7936		goto exit_slot_reset;
7937
7938	mutex_lock(&ha->mq_lock);
7939	list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7940		qpair->online = 1;
7941	mutex_unlock(&ha->mq_lock);
7942
7943	ha->flags.eeh_busy = 0;
7944	base_vha->flags.online = 1;
7945	set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7946	ha->isp_ops->abort_isp(base_vha);
7947	clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7948
7949	if (qla2x00_isp_reg_stat(ha)) {
7950		ha->flags.eeh_busy = 1;
7951		qla_pci_error_cleanup(base_vha);
7952		ql_log(ql_log_warn, base_vha, 0x9005,
7953		       "Device unable to recover from PCI error.\n");
7954	} else {
7955		ret =  PCI_ERS_RESULT_RECOVERED;
7956	}
7957
7958exit_slot_reset:
7959	ql_dbg(ql_dbg_aer, base_vha, 0x900e,
7960	    "Slot Reset returning %x.\n", ret);
7961
7962	qla2xxx_set_affinity_nobalance(pdev, true);
7963
7964	return ret;
7965}
7966
7967static void
7968qla2xxx_pci_resume(struct pci_dev *pdev)
7969{
7970	scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7971	struct qla_hw_data *ha = base_vha->hw;
7972	int ret;
7973
7974	ql_log(ql_log_warn, base_vha, 0x900f,
7975	       "Pci Resume.\n");
7976
7977
7978	ret = qla2x00_wait_for_hba_online(base_vha);
7979	if (ret != QLA_SUCCESS) {
7980		ql_log(ql_log_fatal, base_vha, 0x9002,
7981		    "The device failed to resume I/O from slot/link_reset.\n");
7982	}
7983	ha->pci_error_state = QLA_PCI_RESUME;
7984	ql_dbg(ql_dbg_aer, base_vha, 0x600d,
7985	       "Pci Resume returning.\n");
7986}
7987
7988void qla_pci_set_eeh_busy(struct scsi_qla_host *vha)
7989{
7990	struct qla_hw_data *ha = vha->hw;
7991	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
7992	bool do_cleanup = false;
7993	unsigned long flags;
7994
7995	if (ha->flags.eeh_busy)
7996		return;
7997
7998	spin_lock_irqsave(&base_vha->work_lock, flags);
7999	if (!ha->flags.eeh_busy) {
8000		ha->eeh_jif = jiffies;
8001		ha->flags.eeh_flush = 0;
8002
8003		ha->flags.eeh_busy = 1;
8004		do_cleanup = true;
8005	}
8006	spin_unlock_irqrestore(&base_vha->work_lock, flags);
8007
8008	if (do_cleanup)
8009		qla_pci_error_cleanup(base_vha);
8010}
8011
8012/*
8013 * this routine will schedule a task to pause IO from interrupt context
8014 * if caller sees a PCIE error event (register read = 0xf's)
8015 */
8016void qla_schedule_eeh_work(struct scsi_qla_host *vha)
8017{
8018	struct qla_hw_data *ha = vha->hw;
8019	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
8020
8021	if (ha->flags.eeh_busy)
8022		return;
8023
8024	set_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags);
8025	qla2xxx_wake_dpc(base_vha);
8026}
8027
8028static void
8029qla_pci_reset_prepare(struct pci_dev *pdev)
8030{
8031	scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
8032	struct qla_hw_data *ha = base_vha->hw;
8033	struct qla_qpair *qpair;
8034
8035	ql_log(ql_log_warn, base_vha, 0xffff,
8036	    "%s.\n", __func__);
8037
8038	/*
8039	 * PCI FLR/function reset is about to reset the
8040	 * slot. Stop the chip to stop all DMA access.
8041	 * It is assumed that pci_reset_done will be called
8042	 * after FLR to resume Chip operation.
8043	 */
8044	ha->flags.eeh_busy = 1;
8045	mutex_lock(&ha->mq_lock);
8046	list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
8047		qpair->online = 0;
8048	mutex_unlock(&ha->mq_lock);
8049
8050	set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
8051	qla2x00_abort_isp_cleanup(base_vha);
8052	qla2x00_abort_all_cmds(base_vha, DID_RESET << 16);
8053}
8054
8055static void
8056qla_pci_reset_done(struct pci_dev *pdev)
8057{
8058	scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
8059	struct qla_hw_data *ha = base_vha->hw;
8060	struct qla_qpair *qpair;
8061
8062	ql_log(ql_log_warn, base_vha, 0xffff,
8063	    "%s.\n", __func__);
8064
8065	/*
8066	 * FLR just completed by PCI layer. Resume adapter
8067	 */
8068	ha->flags.eeh_busy = 0;
8069	mutex_lock(&ha->mq_lock);
8070	list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
8071		qpair->online = 1;
8072	mutex_unlock(&ha->mq_lock);
8073
8074	base_vha->flags.online = 1;
8075	ha->isp_ops->abort_isp(base_vha);
8076	clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
8077}
8078
8079static void qla2xxx_map_queues(struct Scsi_Host *shost)
8080{
8081	scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
8082	struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
8083
8084	if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase)
8085		blk_mq_map_queues(qmap);
8086	else
8087		blk_mq_map_hw_queues(qmap, &vha->hw->pdev->dev,
8088				       vha->irq_offset);
8089}
8090
8091struct scsi_host_template qla2xxx_driver_template = {
8092	.module			= THIS_MODULE,
8093	.name			= QLA2XXX_DRIVER_NAME,
8094	.queuecommand		= qla2xxx_queuecommand,
8095
8096	.eh_timed_out		= fc_eh_timed_out,
8097	.eh_abort_handler	= qla2xxx_eh_abort,
8098	.eh_should_retry_cmd	= fc_eh_should_retry_cmd,
8099	.eh_device_reset_handler = qla2xxx_eh_device_reset,
8100	.eh_target_reset_handler = qla2xxx_eh_target_reset,
8101	.eh_bus_reset_handler	= qla2xxx_eh_bus_reset,
8102	.eh_host_reset_handler	= qla2xxx_eh_host_reset,
8103
8104	.sdev_configure		= qla2xxx_sdev_configure,
8105
8106	.sdev_init		= qla2xxx_sdev_init,
8107	.sdev_destroy		= qla2xxx_sdev_destroy,
8108	.scan_finished		= qla2xxx_scan_finished,
8109	.scan_start		= qla2xxx_scan_start,
8110	.change_queue_depth	= scsi_change_queue_depth,
8111	.map_queues             = qla2xxx_map_queues,
8112	.this_id		= -1,
8113	.cmd_per_lun		= 3,
8114	.sg_tablesize		= SG_ALL,
8115
8116	.max_sectors		= 0xFFFF,
8117	.shost_groups		= qla2x00_host_groups,
8118
8119	.supported_mode		= MODE_INITIATOR,
8120	.track_queue_depth	= 1,
8121	.cmd_size		= sizeof(srb_t),
8122};
8123
8124static const struct pci_error_handlers qla2xxx_err_handler = {
8125	.error_detected = qla2xxx_pci_error_detected,
8126	.mmio_enabled = qla2xxx_pci_mmio_enabled,
8127	.slot_reset = qla2xxx_pci_slot_reset,
8128	.resume = qla2xxx_pci_resume,
8129	.reset_prepare = qla_pci_reset_prepare,
8130	.reset_done = qla_pci_reset_done,
8131};
8132
8133static const struct pci_device_id qla2xxx_pci_tbl[] = {
8134	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
8135	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
8136	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
8137	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
8138	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
8139	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
8140	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
8141	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
8142	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
8143	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
8144	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
8145	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
8146	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
8147	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
8148	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
8149	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
8150	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8151	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
8152	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
8153	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
8154	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
8155	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
8156	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) },
8157	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) },
8158	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) },
8159	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) },
8160	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) },
8161	{ 0 },
8162};
8163MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
8164
8165static struct pci_driver qla2xxx_pci_driver = {
8166	.name		= QLA2XXX_DRIVER_NAME,
8167	.id_table	= qla2xxx_pci_tbl,
8168	.probe		= qla2x00_probe_one,
8169	.remove		= qla2x00_remove_one,
8170	.shutdown	= qla2x00_shutdown,
8171	.err_handler	= &qla2xxx_err_handler,
8172};
8173
8174static const struct file_operations apidev_fops = {
8175	.owner = THIS_MODULE,
8176	.llseek = noop_llseek,
8177};
8178
8179/**
8180 * qla2x00_module_init - Module initialization.
8181 **/
8182static int __init
8183qla2x00_module_init(void)
8184{
8185	int ret = 0;
8186
8187	BUILD_BUG_ON(sizeof(cmd_a64_entry_t) != 64);
8188	BUILD_BUG_ON(sizeof(cmd_entry_t) != 64);
8189	BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64);
8190	BUILD_BUG_ON(sizeof(cont_entry_t) != 64);
8191	BUILD_BUG_ON(sizeof(init_cb_t) != 96);
8192	BUILD_BUG_ON(sizeof(mrk_entry_t) != 64);
8193	BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64);
8194	BUILD_BUG_ON(sizeof(request_t) != 64);
8195	BUILD_BUG_ON(sizeof(struct abort_entry_24xx) != 64);
8196	BUILD_BUG_ON(sizeof(struct abort_iocb_entry_fx00) != 64);
8197	BUILD_BUG_ON(sizeof(struct abts_entry_24xx) != 64);
8198	BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64);
8199	BUILD_BUG_ON(sizeof(struct access_chip_rsp_84xx) != 64);
8200	BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64);
8201	BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64);
8202	BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64);
8203	BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64);
8204	BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64);
8205	BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64);
8206	BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64);
8207	BUILD_BUG_ON(sizeof(struct ct_fdmi1_hba_attributes) != 2604);
8208	BUILD_BUG_ON(sizeof(struct ct_fdmi2_hba_attributes) != 4424);
8209	BUILD_BUG_ON(sizeof(struct ct_fdmi2_port_attributes) != 4164);
8210	BUILD_BUG_ON(sizeof(struct ct_fdmi_hba_attr) != 260);
8211	BUILD_BUG_ON(sizeof(struct ct_fdmi_port_attr) != 260);
8212	BUILD_BUG_ON(sizeof(struct ct_rsp_hdr) != 16);
8213	BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64);
8214	BUILD_BUG_ON(sizeof(struct device_reg_24xx) != 256);
8215	BUILD_BUG_ON(sizeof(struct device_reg_25xxmq) != 24);
8216	BUILD_BUG_ON(sizeof(struct device_reg_2xxx) != 256);
8217	BUILD_BUG_ON(sizeof(struct device_reg_82xx) != 1288);
8218	BUILD_BUG_ON(sizeof(struct device_reg_fx00) != 216);
8219	BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64);
8220	BUILD_BUG_ON(sizeof(struct els_sts_entry_24xx) != 64);
8221	BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64);
8222	BUILD_BUG_ON(sizeof(struct imm_ntfy_from_isp) != 64);
8223	BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128);
8224	BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128);
8225	BUILD_BUG_ON(sizeof(struct logio_entry_24xx) != 64);
8226	BUILD_BUG_ON(sizeof(struct mbx_entry) != 64);
8227	BUILD_BUG_ON(sizeof(struct mid_init_cb_24xx) != 5252);
8228	BUILD_BUG_ON(sizeof(struct mrk_entry_24xx) != 64);
8229	BUILD_BUG_ON(sizeof(struct nvram_24xx) != 512);
8230	BUILD_BUG_ON(sizeof(struct nvram_81xx) != 512);
8231	BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64);
8232	BUILD_BUG_ON(sizeof(struct pt_ls4_rx_unsol) != 64);
8233	BUILD_BUG_ON(sizeof(struct purex_entry_24xx) != 64);
8234	BUILD_BUG_ON(sizeof(struct qla2100_fw_dump) != 123634);
8235	BUILD_BUG_ON(sizeof(struct qla2300_fw_dump) != 136100);
8236	BUILD_BUG_ON(sizeof(struct qla24xx_fw_dump) != 37976);
8237	BUILD_BUG_ON(sizeof(struct qla25xx_fw_dump) != 39228);
8238	BUILD_BUG_ON(sizeof(struct qla2xxx_fce_chain) != 52);
8239	BUILD_BUG_ON(sizeof(struct qla2xxx_fw_dump) != 136172);
8240	BUILD_BUG_ON(sizeof(struct qla2xxx_mq_chain) != 524);
8241	BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_chain) != 8);
8242	BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_header) != 12);
8243	BUILD_BUG_ON(sizeof(struct qla2xxx_offld_chain) != 24);
8244	BUILD_BUG_ON(sizeof(struct qla81xx_fw_dump) != 39420);
8245	BUILD_BUG_ON(sizeof(struct qla82xx_uri_data_desc) != 28);
8246	BUILD_BUG_ON(sizeof(struct qla82xx_uri_table_desc) != 32);
8247	BUILD_BUG_ON(sizeof(struct qla83xx_fw_dump) != 51196);
8248	BUILD_BUG_ON(sizeof(struct qla_fcp_prio_cfg) != FCP_PRIO_CFG_SIZE);
8249	BUILD_BUG_ON(sizeof(struct qla_fdt_layout) != 128);
8250	BUILD_BUG_ON(sizeof(struct qla_flt_header) != 8);
8251	BUILD_BUG_ON(sizeof(struct qla_flt_region) != 16);
8252	BUILD_BUG_ON(sizeof(struct qla_npiv_entry) != 24);
8253	BUILD_BUG_ON(sizeof(struct qla_npiv_header) != 16);
8254	BUILD_BUG_ON(sizeof(struct rdp_rsp_payload) != 336);
8255	BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064);
8256	BUILD_BUG_ON(sizeof(struct sts_entry_24xx) != 64);
8257	BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry) != 64);
8258	BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry_fx00) != 64);
8259	BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64);
8260	BUILD_BUG_ON(sizeof(struct verify_chip_rsp_84xx) != 52);
8261	BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56);
8262	BUILD_BUG_ON(sizeof(struct vp_config_entry_24xx) != 64);
8263	BUILD_BUG_ON(sizeof(struct vp_ctrl_entry_24xx) != 64);
8264	BUILD_BUG_ON(sizeof(struct vp_rpt_id_entry_24xx) != 64);
8265	BUILD_BUG_ON(sizeof(sts21_entry_t) != 64);
8266	BUILD_BUG_ON(sizeof(sts22_entry_t) != 64);
8267	BUILD_BUG_ON(sizeof(sts_cont_entry_t) != 64);
8268	BUILD_BUG_ON(sizeof(sts_entry_t) != 64);
8269	BUILD_BUG_ON(sizeof(sw_info_t) != 32);
8270	BUILD_BUG_ON(sizeof(target_id_t) != 2);
8271
8272	qla_trace_init();
8273
8274	/* Allocate cache for SRBs. */
8275	srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
8276	    SLAB_HWCACHE_ALIGN, NULL);
8277	if (srb_cachep == NULL) {
8278		ql_log(ql_log_fatal, NULL, 0x0001,
8279		    "Unable to allocate SRB cache...Failing load!.\n");
8280		return -ENOMEM;
8281	}
8282
8283	/* Initialize target kmem_cache and mem_pools */
8284	ret = qlt_init();
8285	if (ret < 0) {
8286		goto destroy_cache;
8287	} else if (ret > 0) {
8288		/*
8289		 * If initiator mode is explictly disabled by qlt_init(),
8290		 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
8291		 * performing scsi_scan_target() during LOOP UP event.
8292		 */
8293		qla2xxx_transport_functions.disable_target_scan = 1;
8294		qla2xxx_transport_vport_functions.disable_target_scan = 1;
8295	}
8296
8297	/* Derive version string. */
8298	strcpy(qla2x00_version_str, QLA2XXX_VERSION);
8299	if (ql2xextended_error_logging)
8300		strcat(qla2x00_version_str, "-debug");
8301	if (ql2xextended_error_logging == 1)
8302		ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
8303
8304	qla2xxx_transport_template =
8305	    fc_attach_transport(&qla2xxx_transport_functions);
8306	if (!qla2xxx_transport_template) {
8307		ql_log(ql_log_fatal, NULL, 0x0002,
8308		    "fc_attach_transport failed...Failing load!.\n");
8309		ret = -ENODEV;
8310		goto qlt_exit;
8311	}
8312
8313	apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
8314	if (apidev_major < 0) {
8315		ql_log(ql_log_fatal, NULL, 0x0003,
8316		    "Unable to register char device %s.\n", QLA2XXX_APIDEV);
8317	}
8318
8319	qla2xxx_transport_vport_template =
8320	    fc_attach_transport(&qla2xxx_transport_vport_functions);
8321	if (!qla2xxx_transport_vport_template) {
8322		ql_log(ql_log_fatal, NULL, 0x0004,
8323		    "fc_attach_transport vport failed...Failing load!.\n");
8324		ret = -ENODEV;
8325		goto unreg_chrdev;
8326	}
8327	ql_log(ql_log_info, NULL, 0x0005,
8328	    "QLogic Fibre Channel HBA Driver: %s.\n",
8329	    qla2x00_version_str);
8330	ret = pci_register_driver(&qla2xxx_pci_driver);
8331	if (ret) {
8332		ql_log(ql_log_fatal, NULL, 0x0006,
8333		    "pci_register_driver failed...ret=%d Failing load!.\n",
8334		    ret);
8335		goto release_vport_transport;
8336	}
8337	return ret;
8338
8339release_vport_transport:
8340	fc_release_transport(qla2xxx_transport_vport_template);
8341
8342unreg_chrdev:
8343	if (apidev_major >= 0)
8344		unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
8345	fc_release_transport(qla2xxx_transport_template);
8346
8347qlt_exit:
8348	qlt_exit();
8349
8350destroy_cache:
8351	kmem_cache_destroy(srb_cachep);
8352
8353	qla_trace_uninit();
8354	return ret;
8355}
8356
8357/**
8358 * qla2x00_module_exit - Module cleanup.
8359 **/
8360static void __exit
8361qla2x00_module_exit(void)
8362{
8363	pci_unregister_driver(&qla2xxx_pci_driver);
8364	qla2x00_release_firmware();
8365	kmem_cache_destroy(ctx_cachep);
8366	fc_release_transport(qla2xxx_transport_vport_template);
8367	if (apidev_major >= 0)
8368		unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
8369	fc_release_transport(qla2xxx_transport_template);
8370	qlt_exit();
8371	kmem_cache_destroy(srb_cachep);
8372	qla_trace_uninit();
8373}
8374
8375module_init(qla2x00_module_init);
8376module_exit(qla2x00_module_exit);
8377
8378MODULE_AUTHOR("QLogic Corporation");
8379MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
8380MODULE_LICENSE("GPL");
8381MODULE_FIRMWARE(FW_FILE_ISP21XX);
8382MODULE_FIRMWARE(FW_FILE_ISP22XX);
8383MODULE_FIRMWARE(FW_FILE_ISP2300);
8384MODULE_FIRMWARE(FW_FILE_ISP2322);
8385MODULE_FIRMWARE(FW_FILE_ISP24XX);
8386MODULE_FIRMWARE(FW_FILE_ISP25XX);