qla_edif.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Marvell Fibre Channel HBA Driver
  4 * Copyright (c)  2021    Marvell
  5 */
  6#ifndef __QLA_EDIF_H
  7#define __QLA_EDIF_H
  8
  9struct qla_scsi_host;
 10#define EDIF_APP_ID 0x73730001
 11
 12#define EDIF_MAX_INDEX	2048
 13struct edif_sa_ctl {
 14	struct list_head next;
 15	uint16_t	del_index;
 16	uint16_t	index;
 17	uint16_t	slot;
 18	uint16_t	flags;
 19#define	EDIF_SA_CTL_FLG_REPL		BIT_0
 20#define	EDIF_SA_CTL_FLG_DEL		BIT_1
 21#define EDIF_SA_CTL_FLG_CLEANUP_DEL BIT_4
 22	// Invalidate Index bit and mirrors QLA_SA_UPDATE_FLAGS_DELETE
 23	unsigned long   state;
 24#define EDIF_SA_CTL_USED	1	/* Active Sa update  */
 25#define EDIF_SA_CTL_PEND	2	/* Waiting for slot */
 26#define EDIF_SA_CTL_REPL	3	/* Active Replace and Delete */
 27#define EDIF_SA_CTL_DEL		4	/* Delete Pending */
 28	struct fc_port	*fcport;
 29	struct bsg_job *bsg_job;
 30	struct qla_sa_update_frame sa_frame;
 31};
 32
 33enum enode_flags_t {
 34	ENODE_ACTIVE = 0x1,
 35};
 36
 37struct pur_core {
 38	enum enode_flags_t	enode_flags;
 39	spinlock_t		pur_lock;
 40	struct  list_head	head;
 41};
 42
 43enum db_flags_t {
 44	EDB_ACTIVE = BIT_0,
 45};
 46
 47#define DBELL_ACTIVE(_v) (_v->e_dbell.db_flags & EDB_ACTIVE)
 48#define DBELL_INACTIVE(_v) (!(_v->e_dbell.db_flags & EDB_ACTIVE))
 49
 50struct edif_dbell {
 51	enum db_flags_t		db_flags;
 52	spinlock_t		db_lock;
 53	struct  list_head	head;
 54	struct bsg_job *dbell_bsg_job;
 55	unsigned long bsg_expire;
 56};
 57
 58#define SA_UPDATE_IOCB_TYPE            0x71    /* Security Association Update IOCB entry */
 59struct sa_update_28xx {
 60	uint8_t entry_type;             /* Entry type. */
 61	uint8_t entry_count;            /* Entry count. */
 62	uint8_t sys_define;             /* System Defined. */
 63	uint8_t entry_status;           /* Entry Status. */
 64
 65	uint32_t handle;                /* IOCB System handle. */
 66
 67	union {
 68		__le16 nport_handle;  /* in: N_PORT handle. */
 69		__le16 comp_sts;              /* out: completion status */
 70#define CS_PORT_EDIF_UNAVAIL	0x28
 71#define CS_PORT_EDIF_LOGOUT	0x29
 72#define CS_PORT_EDIF_SUPP_NOT_RDY 0x64
 73#define CS_PORT_EDIF_INV_REQ      0x66
 74	} u;
 75	uint8_t vp_index;
 76	uint8_t reserved_1;
 77	uint8_t port_id[3];
 78	uint8_t flags;
 79#define SA_FLAG_INVALIDATE BIT_0
 80#define SA_FLAG_TX	   BIT_1 // 1=tx, 0=rx
 81
 82	uint8_t sa_key[32];     /* 256 bit key */
 83	__le32 salt;
 84	__le32 spi;
 85	uint8_t sa_control;
 86#define SA_CNTL_ENC_FCSP        (1 << 3)
 87#define SA_CNTL_ENC_OPD         (2 << 3)
 88#define SA_CNTL_ENC_MSK         (3 << 3)  // mask bits 4,3
 89#define SA_CNTL_AES_GMAC	(1 << 2)
 90#define SA_CNTL_KEY256          (2 << 0)
 91#define SA_CNTL_KEY128          0
 92
 93	uint8_t reserved_2;
 94	__le16 sa_index;   // reserve: bit 11-15
 95	__le16 old_sa_info;
 96	__le16 new_sa_info;
 97};
 98
 99#define        NUM_ENTRIES     256
100#define        PUR_GET         1
101
102struct dinfo {
103	int		nodecnt;
104	int		lstate;
105};
106
107struct pur_ninfo {
108	port_id_t       pur_sid;
109	port_id_t	pur_did;
110	uint8_t		vp_idx;
111	short           pur_bytes_rcvd;
112	unsigned short  pur_nphdl;
113	unsigned int    pur_rx_xchg_address;
114};
115
116struct purexevent {
117	struct  pur_ninfo	pur_info;
118	unsigned char		*msgp;
119	u32			msgp_len;
120};
121
122#define	N_UNDEF		0
123#define	N_PUREX		1
124struct enode {
125	struct list_head	list;
126	struct dinfo		dinfo;
127	uint32_t		ntype;
128	union {
129		struct purexevent	purexinfo;
130	} u;
131};
132
133#define RX_ELS_SIZE (roundup(sizeof(struct enode) + ELS_MAX_PAYLOAD, SMP_CACHE_BYTES))
134
135#define EDIF_SESSION_DOWN(_s) \
136	(qla_ini_mode_enabled(_s->vha) && (_s->disc_state == DSC_DELETE_PEND || \
137	 _s->disc_state == DSC_DELETED || \
138	 !_s->edif.app_sess_online))
139
140#define EDIF_NEGOTIATION_PENDING(_fcport) \
141	(DBELL_ACTIVE(_fcport->vha) && \
142	 (_fcport->disc_state == DSC_LOGIN_AUTH_PEND))
143
144#define EDIF_SESS_DELETE(_s) \
145	(qla_ini_mode_enabled(_s->vha) && (_s->disc_state == DSC_DELETE_PEND || \
146	 _s->disc_state == DSC_DELETED))
147
148#define EDIF_CAP(_ha) (ql2xsecenable && IS_QLA28XX(_ha))
149
150#endif	/* __QLA_EDIF_H */