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pm8001_hwi.c
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linux-6.19.14/drivers/scsi/pm8001/pm8001_hwi.c
1/* 2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver 3 * 4 * Copyright (c) 2008-2009 USI Co., Ltd. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon 16 * including a substantially similar Disclaimer requirement for further 17 * binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * NO WARRANTY 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGES. 38 * 39 */ 40 #include <linux/slab.h> 41 #include "pm8001_sas.h" 42 #include "pm8001_hwi.h" 43 #include "pm8001_chips.h" 44 #include "pm8001_ctl.h" 45 #include "pm80xx_tracepoints.h" 46 47/** 48 * read_main_config_table - read the configure table and save it. 49 * @pm8001_ha: our hba card information 50 */ 51static void read_main_config_table(struct pm8001_hba_info *pm8001_ha) 52{ 53 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 54 pm8001_ha->main_cfg_tbl.pm8001_tbl.signature = 55 pm8001_mr32(address, 0x00); 56 pm8001_ha->main_cfg_tbl.pm8001_tbl.interface_rev = 57 pm8001_mr32(address, 0x04); 58 pm8001_ha->main_cfg_tbl.pm8001_tbl.firmware_rev = 59 pm8001_mr32(address, 0x08); 60 pm8001_ha->main_cfg_tbl.pm8001_tbl.max_out_io = 61 pm8001_mr32(address, 0x0C); 62 pm8001_ha->main_cfg_tbl.pm8001_tbl.max_sgl = 63 pm8001_mr32(address, 0x10); 64 pm8001_ha->main_cfg_tbl.pm8001_tbl.ctrl_cap_flag = 65 pm8001_mr32(address, 0x14); 66 pm8001_ha->main_cfg_tbl.pm8001_tbl.gst_offset = 67 pm8001_mr32(address, 0x18); 68 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_queue_offset = 69 pm8001_mr32(address, MAIN_IBQ_OFFSET); 70 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_queue_offset = 71 pm8001_mr32(address, MAIN_OBQ_OFFSET); 72 pm8001_ha->main_cfg_tbl.pm8001_tbl.hda_mode_flag = 73 pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET); 74 75 /* read analog Setting offset from the configuration table */ 76 pm8001_ha->main_cfg_tbl.pm8001_tbl.anolog_setup_table_offset = 77 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET); 78 79 /* read Error Dump Offset and Length */ 80 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset0 = 81 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET); 82 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length0 = 83 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH); 84 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset1 = 85 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET); 86 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length1 = 87 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH); 88} 89 90/** 91 * read_general_status_table - read the general status table and save it. 92 * @pm8001_ha: our hba card information 93 */ 94static void read_general_status_table(struct pm8001_hba_info *pm8001_ha) 95{ 96 void __iomem *address = pm8001_ha->general_stat_tbl_addr; 97 pm8001_ha->gs_tbl.pm8001_tbl.gst_len_mpistate = 98 pm8001_mr32(address, 0x00); 99 pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state0 = 100 pm8001_mr32(address, 0x04); 101 pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state1 = 102 pm8001_mr32(address, 0x08); 103 pm8001_ha->gs_tbl.pm8001_tbl.msgu_tcnt = 104 pm8001_mr32(address, 0x0C); 105 pm8001_ha->gs_tbl.pm8001_tbl.iop_tcnt = 106 pm8001_mr32(address, 0x10); 107 pm8001_ha->gs_tbl.pm8001_tbl.rsvd = 108 pm8001_mr32(address, 0x14); 109 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[0] = 110 pm8001_mr32(address, 0x18); 111 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[1] = 112 pm8001_mr32(address, 0x1C); 113 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[2] = 114 pm8001_mr32(address, 0x20); 115 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[3] = 116 pm8001_mr32(address, 0x24); 117 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[4] = 118 pm8001_mr32(address, 0x28); 119 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[5] = 120 pm8001_mr32(address, 0x2C); 121 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[6] = 122 pm8001_mr32(address, 0x30); 123 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[7] = 124 pm8001_mr32(address, 0x34); 125 pm8001_ha->gs_tbl.pm8001_tbl.gpio_input_val = 126 pm8001_mr32(address, 0x38); 127 pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[0] = 128 pm8001_mr32(address, 0x3C); 129 pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[1] = 130 pm8001_mr32(address, 0x40); 131 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[0] = 132 pm8001_mr32(address, 0x44); 133 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[1] = 134 pm8001_mr32(address, 0x48); 135 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[2] = 136 pm8001_mr32(address, 0x4C); 137 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[3] = 138 pm8001_mr32(address, 0x50); 139 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[4] = 140 pm8001_mr32(address, 0x54); 141 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[5] = 142 pm8001_mr32(address, 0x58); 143 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[6] = 144 pm8001_mr32(address, 0x5C); 145 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[7] = 146 pm8001_mr32(address, 0x60); 147} 148 149/** 150 * read_inbnd_queue_table - read the inbound queue table and save it. 151 * @pm8001_ha: our hba card information 152 */ 153static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 154{ 155 int i; 156 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 157 for (i = 0; i < PM8001_MAX_INB_NUM; i++) { 158 u32 offset = i * 0x20; 159 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 160 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14))); 161 pm8001_ha->inbnd_q_tbl[i].pi_offset = 162 pm8001_mr32(address, (offset + 0x18)); 163 } 164} 165 166/** 167 * read_outbnd_queue_table - read the outbound queue table and save it. 168 * @pm8001_ha: our hba card information 169 */ 170static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 171{ 172 int i; 173 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 174 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) { 175 u32 offset = i * 0x24; 176 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 177 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14))); 178 pm8001_ha->outbnd_q_tbl[i].ci_offset = 179 pm8001_mr32(address, (offset + 0x18)); 180 } 181} 182 183/** 184 * init_default_table_values - init the default table. 185 * @pm8001_ha: our hba card information 186 */ 187static void init_default_table_values(struct pm8001_hba_info *pm8001_ha) 188{ 189 int i; 190 u32 offsetib, offsetob; 191 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr; 192 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr; 193 u32 ib_offset = pm8001_ha->ib_offset; 194 u32 ob_offset = pm8001_ha->ob_offset; 195 u32 ci_offset = pm8001_ha->ci_offset; 196 u32 pi_offset = pm8001_ha->pi_offset; 197 198 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd = 0; 199 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3 = 0; 200 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7 = 0; 201 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3 = 0; 202 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7 = 0; 203 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid0_3 = 204 0; 205 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid4_7 = 206 0; 207 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid0_3 = 0; 208 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid4_7 = 0; 209 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid0_3 = 0; 210 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid4_7 = 0; 211 212 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr = 213 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi; 214 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr = 215 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo; 216 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size = 217 PM8001_EVENT_LOG_SIZE; 218 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option = 0x01; 219 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr = 220 pm8001_ha->memoryMap.region[IOP].phys_addr_hi; 221 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr = 222 pm8001_ha->memoryMap.region[IOP].phys_addr_lo; 223 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size = 224 PM8001_EVENT_LOG_SIZE; 225 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option = 0x01; 226 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt = 0x01; 227 for (i = 0; i < pm8001_ha->max_q_num; i++) { 228 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt = 229 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30); 230 pm8001_ha->inbnd_q_tbl[i].upper_base_addr = 231 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_hi; 232 pm8001_ha->inbnd_q_tbl[i].lower_base_addr = 233 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_lo; 234 pm8001_ha->inbnd_q_tbl[i].base_virt = 235 (u8 *)pm8001_ha->memoryMap.region[ib_offset + i].virt_ptr; 236 pm8001_ha->inbnd_q_tbl[i].total_length = 237 pm8001_ha->memoryMap.region[ib_offset + i].total_len; 238 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr = 239 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_hi; 240 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr = 241 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_lo; 242 pm8001_ha->inbnd_q_tbl[i].ci_virt = 243 pm8001_ha->memoryMap.region[ci_offset + i].virt_ptr; 244 pm8001_write_32(pm8001_ha->inbnd_q_tbl[i].ci_virt, 0, 0); 245 offsetib = i * 0x20; 246 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 247 get_pci_bar_index(pm8001_mr32(addressib, 248 (offsetib + 0x14))); 249 pm8001_ha->inbnd_q_tbl[i].pi_offset = 250 pm8001_mr32(addressib, (offsetib + 0x18)); 251 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0; 252 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0; 253 } 254 for (i = 0; i < pm8001_ha->max_q_num; i++) { 255 pm8001_ha->outbnd_q_tbl[i].element_size_cnt = 256 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30); 257 pm8001_ha->outbnd_q_tbl[i].upper_base_addr = 258 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_hi; 259 pm8001_ha->outbnd_q_tbl[i].lower_base_addr = 260 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_lo; 261 pm8001_ha->outbnd_q_tbl[i].base_virt = 262 (u8 *)pm8001_ha->memoryMap.region[ob_offset + i].virt_ptr; 263 pm8001_ha->outbnd_q_tbl[i].total_length = 264 pm8001_ha->memoryMap.region[ob_offset + i].total_len; 265 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr = 266 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_hi; 267 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr = 268 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_lo; 269 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = 270 0 | (10 << 16) | (i << 24); 271 pm8001_ha->outbnd_q_tbl[i].pi_virt = 272 pm8001_ha->memoryMap.region[pi_offset + i].virt_ptr; 273 pm8001_write_32(pm8001_ha->outbnd_q_tbl[i].pi_virt, 0, 0); 274 offsetob = i * 0x24; 275 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 276 get_pci_bar_index(pm8001_mr32(addressob, 277 offsetob + 0x14)); 278 pm8001_ha->outbnd_q_tbl[i].ci_offset = 279 pm8001_mr32(addressob, (offsetob + 0x18)); 280 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0; 281 pm8001_ha->outbnd_q_tbl[i].producer_index = 0; 282 } 283} 284 285/** 286 * update_main_config_table - update the main default table to the HBA. 287 * @pm8001_ha: our hba card information 288 */ 289static void update_main_config_table(struct pm8001_hba_info *pm8001_ha) 290{ 291 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 292 pm8001_mw32(address, 0x24, 293 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd); 294 pm8001_mw32(address, 0x28, 295 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3); 296 pm8001_mw32(address, 0x2C, 297 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7); 298 pm8001_mw32(address, 0x30, 299 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3); 300 pm8001_mw32(address, 0x34, 301 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7); 302 pm8001_mw32(address, 0x38, 303 pm8001_ha->main_cfg_tbl.pm8001_tbl. 304 outbound_tgt_ITNexus_event_pid0_3); 305 pm8001_mw32(address, 0x3C, 306 pm8001_ha->main_cfg_tbl.pm8001_tbl. 307 outbound_tgt_ITNexus_event_pid4_7); 308 pm8001_mw32(address, 0x40, 309 pm8001_ha->main_cfg_tbl.pm8001_tbl. 310 outbound_tgt_ssp_event_pid0_3); 311 pm8001_mw32(address, 0x44, 312 pm8001_ha->main_cfg_tbl.pm8001_tbl. 313 outbound_tgt_ssp_event_pid4_7); 314 pm8001_mw32(address, 0x48, 315 pm8001_ha->main_cfg_tbl.pm8001_tbl. 316 outbound_tgt_smp_event_pid0_3); 317 pm8001_mw32(address, 0x4C, 318 pm8001_ha->main_cfg_tbl.pm8001_tbl. 319 outbound_tgt_smp_event_pid4_7); 320 pm8001_mw32(address, 0x50, 321 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr); 322 pm8001_mw32(address, 0x54, 323 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr); 324 pm8001_mw32(address, 0x58, 325 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size); 326 pm8001_mw32(address, 0x5C, 327 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option); 328 pm8001_mw32(address, 0x60, 329 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr); 330 pm8001_mw32(address, 0x64, 331 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr); 332 pm8001_mw32(address, 0x68, 333 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size); 334 pm8001_mw32(address, 0x6C, 335 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option); 336 pm8001_mw32(address, 0x70, 337 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt); 338} 339 340/** 341 * update_inbnd_queue_table - update the inbound queue table to the HBA. 342 * @pm8001_ha: our hba card information 343 * @number: entry in the queue 344 */ 345static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha, 346 int number) 347{ 348 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 349 u16 offset = number * 0x20; 350 pm8001_mw32(address, offset + 0x00, 351 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt); 352 pm8001_mw32(address, offset + 0x04, 353 pm8001_ha->inbnd_q_tbl[number].upper_base_addr); 354 pm8001_mw32(address, offset + 0x08, 355 pm8001_ha->inbnd_q_tbl[number].lower_base_addr); 356 pm8001_mw32(address, offset + 0x0C, 357 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr); 358 pm8001_mw32(address, offset + 0x10, 359 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr); 360} 361 362/** 363 * update_outbnd_queue_table - update the outbound queue table to the HBA. 364 * @pm8001_ha: our hba card information 365 * @number: entry in the queue 366 */ 367static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha, 368 int number) 369{ 370 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 371 u16 offset = number * 0x24; 372 pm8001_mw32(address, offset + 0x00, 373 pm8001_ha->outbnd_q_tbl[number].element_size_cnt); 374 pm8001_mw32(address, offset + 0x04, 375 pm8001_ha->outbnd_q_tbl[number].upper_base_addr); 376 pm8001_mw32(address, offset + 0x08, 377 pm8001_ha->outbnd_q_tbl[number].lower_base_addr); 378 pm8001_mw32(address, offset + 0x0C, 379 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr); 380 pm8001_mw32(address, offset + 0x10, 381 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr); 382 pm8001_mw32(address, offset + 0x1C, 383 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay); 384} 385 386/** 387 * pm8001_bar4_shift - function is called to shift BAR base address 388 * @pm8001_ha : our hba card information 389 * @shiftValue : shifting value in memory bar. 390 */ 391int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue) 392{ 393 u32 regVal; 394 unsigned long start; 395 396 /* program the inbound AXI translation Lower Address */ 397 pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue); 398 399 /* confirm the setting is written */ 400 start = jiffies + HZ; /* 1 sec */ 401 do { 402 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW); 403 } while ((regVal != shiftValue) && time_before(jiffies, start)); 404 405 if (regVal != shiftValue) { 406 pm8001_dbg(pm8001_ha, INIT, 407 "TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW = 0x%x\n", 408 regVal); 409 return -1; 410 } 411 return 0; 412} 413 414/** 415 * mpi_set_phys_g3_with_ssc 416 * @pm8001_ha: our hba card information 417 * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc. 418 */ 419static void mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha, 420 u32 SSCbit) 421{ 422 u32 offset, i; 423 unsigned long flags; 424 425#define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000 426#define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000 427#define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074 428#define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074 429#define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12 430#define PHY_G3_WITH_SSC_BIT_SHIFT 13 431#define SNW3_PHY_CAPABILITIES_PARITY 31 432 433 /* 434 * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3) 435 * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7) 436 */ 437 spin_lock_irqsave(&pm8001_ha->lock, flags); 438 if (-1 == pm8001_bar4_shift(pm8001_ha, 439 SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR)) { 440 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 441 return; 442 } 443 444 for (i = 0; i < 4; i++) { 445 offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i; 446 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501); 447 } 448 /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */ 449 if (-1 == pm8001_bar4_shift(pm8001_ha, 450 SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR)) { 451 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 452 return; 453 } 454 for (i = 4; i < 8; i++) { 455 offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4); 456 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501); 457 } 458 /************************************************************* 459 Change the SSC upspreading value to 0x0 so that upspreading is disabled. 460 Device MABC SMOD0 Controls 461 Address: (via MEMBASE-III): 462 Using shifted destination address 0x0_0000: with Offset 0xD8 463 464 31:28 R/W Reserved Do not change 465 27:24 R/W SAS_SMOD_SPRDUP 0000 466 23:20 R/W SAS_SMOD_SPRDDN 0000 467 19:0 R/W Reserved Do not change 468 Upon power-up this register will read as 0x8990c016, 469 and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000 470 so that the written value will be 0x8090c016. 471 This will ensure only down-spreading SSC is enabled on the SPC. 472 *************************************************************/ 473 pm8001_cr32(pm8001_ha, 2, 0xd8); 474 pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016); 475 476 /*set the shifted destination address to 0x0 to avoid error operation */ 477 pm8001_bar4_shift(pm8001_ha, 0x0); 478 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 479 return; 480} 481 482/** 483 * mpi_set_open_retry_interval_reg 484 * @pm8001_ha: our hba card information 485 * @interval: interval time for each OPEN_REJECT (RETRY). The units are in 1us. 486 */ 487static void mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha, 488 u32 interval) 489{ 490 u32 offset; 491 u32 value; 492 u32 i; 493 unsigned long flags; 494 495#define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000 496#define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000 497#define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4 498#define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4 499#define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF 500 501 value = interval & OPEN_RETRY_INTERVAL_REG_MASK; 502 spin_lock_irqsave(&pm8001_ha->lock, flags); 503 /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/ 504 if (-1 == pm8001_bar4_shift(pm8001_ha, 505 OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR)) { 506 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 507 return; 508 } 509 for (i = 0; i < 4; i++) { 510 offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i; 511 pm8001_cw32(pm8001_ha, 2, offset, value); 512 } 513 514 if (-1 == pm8001_bar4_shift(pm8001_ha, 515 OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR)) { 516 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 517 return; 518 } 519 for (i = 4; i < 8; i++) { 520 offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4); 521 pm8001_cw32(pm8001_ha, 2, offset, value); 522 } 523 /*set the shifted destination address to 0x0 to avoid error operation */ 524 pm8001_bar4_shift(pm8001_ha, 0x0); 525 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 526 return; 527} 528 529/** 530 * mpi_init_check - check firmware initialization status. 531 * @pm8001_ha: our hba card information 532 */ 533static int mpi_init_check(struct pm8001_hba_info *pm8001_ha) 534{ 535 u32 max_wait_count; 536 u32 value; 537 u32 gst_len_mpistate; 538 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the 539 table is updated */ 540 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE); 541 /* wait until Inbound DoorBell Clear Register toggled */ 542 max_wait_count = 1 * 1000 * 1000;/* 1 sec */ 543 do { 544 udelay(1); 545 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 546 value &= SPC_MSGU_CFG_TABLE_UPDATE; 547 } while ((value != 0) && (--max_wait_count)); 548 549 if (!max_wait_count) 550 return -1; 551 /* check the MPI-State for initialization */ 552 gst_len_mpistate = 553 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 554 GST_GSTLEN_MPIS_OFFSET); 555 if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK)) 556 return -1; 557 /* check MPI Initialization error */ 558 gst_len_mpistate = gst_len_mpistate >> 16; 559 if (0x0000 != gst_len_mpistate) 560 return -1; 561 return 0; 562} 563 564/** 565 * check_fw_ready - The LLDD check if the FW is ready, if not, return error. 566 * @pm8001_ha: our hba card information 567 */ 568static int check_fw_ready(struct pm8001_hba_info *pm8001_ha) 569{ 570 u32 value, value1; 571 u32 max_wait_count; 572 /* check error state */ 573 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 574 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 575 /* check AAP error */ 576 if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) { 577 /* error state */ 578 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); 579 return -1; 580 } 581 582 /* check IOP error */ 583 if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) { 584 /* error state */ 585 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); 586 return -1; 587 } 588 589 /* bit 4-31 of scratch pad1 should be zeros if it is not 590 in error state*/ 591 if (value & SCRATCH_PAD1_STATE_MASK) { 592 /* error case */ 593 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); 594 return -1; 595 } 596 597 /* bit 2, 4-31 of scratch pad2 should be zeros if it is not 598 in error state */ 599 if (value1 & SCRATCH_PAD2_STATE_MASK) { 600 /* error case */ 601 return -1; 602 } 603 604 max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */ 605 606 /* wait until scratch pad 1 and 2 registers in ready state */ 607 do { 608 udelay(1); 609 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) 610 & SCRATCH_PAD1_RDY; 611 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) 612 & SCRATCH_PAD2_RDY; 613 if ((--max_wait_count) == 0) 614 return -1; 615 } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY)); 616 return 0; 617} 618 619static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha) 620{ 621 void __iomem *base_addr; 622 u32 value; 623 u32 offset; 624 u32 pcibar; 625 u32 pcilogic; 626 627 value = pm8001_cr32(pm8001_ha, 0, 0x44); 628 offset = value & 0x03FFFFFF; 629 pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 Offset: %x\n", offset); 630 pcilogic = (value & 0xFC000000) >> 26; 631 pcibar = get_pci_bar_index(pcilogic); 632 pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 PCI BAR: %d\n", pcibar); 633 pm8001_ha->main_cfg_tbl_addr = base_addr = 634 pm8001_ha->io_mem[pcibar].memvirtaddr + offset; 635 pm8001_ha->general_stat_tbl_addr = 636 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18); 637 pm8001_ha->inbnd_q_tbl_addr = 638 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C); 639 pm8001_ha->outbnd_q_tbl_addr = 640 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20); 641} 642 643/** 644 * pm8001_chip_init - the main init function that initialize whole PM8001 chip. 645 * @pm8001_ha: our hba card information 646 */ 647static int pm8001_chip_init(struct pm8001_hba_info *pm8001_ha) 648{ 649 u32 i = 0; 650 u16 deviceid; 651 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid); 652 /* 8081 controllers need BAR shift to access MPI space 653 * as this is shared with BIOS data */ 654 if (deviceid == 0x8081 || deviceid == 0x0042) { 655 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) { 656 pm8001_dbg(pm8001_ha, FAIL, 657 "Shift Bar4 to 0x%x failed\n", 658 GSM_SM_BASE); 659 return -1; 660 } 661 } 662 /* check the firmware status */ 663 if (-1 == check_fw_ready(pm8001_ha)) { 664 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n"); 665 return -EBUSY; 666 } 667 668 /* Initialize pci space address eg: mpi offset */ 669 init_pci_device_addresses(pm8001_ha); 670 init_default_table_values(pm8001_ha); 671 read_main_config_table(pm8001_ha); 672 read_general_status_table(pm8001_ha); 673 read_inbnd_queue_table(pm8001_ha); 674 read_outbnd_queue_table(pm8001_ha); 675 /* update main config table ,inbound table and outbound table */ 676 update_main_config_table(pm8001_ha); 677 for (i = 0; i < pm8001_ha->max_q_num; i++) 678 update_inbnd_queue_table(pm8001_ha, i); 679 for (i = 0; i < pm8001_ha->max_q_num; i++) 680 update_outbnd_queue_table(pm8001_ha, i); 681 /* 8081 controller donot require these operations */ 682 if (deviceid != 0x8081 && deviceid != 0x0042) { 683 mpi_set_phys_g3_with_ssc(pm8001_ha, 0); 684 /* 7->130ms, 34->500ms, 119->1.5s */ 685 mpi_set_open_retry_interval_reg(pm8001_ha, 119); 686 } 687 /* notify firmware update finished and check initialization status */ 688 if (0 == mpi_init_check(pm8001_ha)) { 689 pm8001_dbg(pm8001_ha, INIT, "MPI initialize successful!\n"); 690 } else 691 return -EBUSY; 692 /*This register is a 16-bit timer with a resolution of 1us. This is the 693 timer used for interrupt delay/coalescing in the PCIe Application Layer. 694 Zero is not a valid value. A value of 1 in the register will cause the 695 interrupts to be normal. A value greater than 1 will cause coalescing 696 delays.*/ 697 pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1); 698 pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0); 699 return 0; 700} 701 702static void pm8001_chip_post_init(struct pm8001_hba_info *pm8001_ha) 703{ 704} 705 706static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha) 707{ 708 u32 max_wait_count; 709 u32 value; 710 u32 gst_len_mpistate; 711 u16 deviceid; 712 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid); 713 if (deviceid == 0x8081 || deviceid == 0x0042) { 714 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) { 715 pm8001_dbg(pm8001_ha, FAIL, 716 "Shift Bar4 to 0x%x failed\n", 717 GSM_SM_BASE); 718 return -1; 719 } 720 } 721 init_pci_device_addresses(pm8001_ha); 722 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the 723 table is stop */ 724 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET); 725 726 /* wait until Inbound DoorBell Clear Register toggled */ 727 max_wait_count = 1 * 1000 * 1000;/* 1 sec */ 728 do { 729 udelay(1); 730 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 731 value &= SPC_MSGU_CFG_TABLE_RESET; 732 } while ((value != 0) && (--max_wait_count)); 733 734 if (!max_wait_count) { 735 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:IBDB value/=0x%x\n", 736 value); 737 return -1; 738 } 739 740 /* check the MPI-State for termination in progress */ 741 /* wait until Inbound DoorBell Clear Register toggled */ 742 max_wait_count = 1 * 1000 * 1000; /* 1 sec */ 743 do { 744 udelay(1); 745 gst_len_mpistate = 746 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 747 GST_GSTLEN_MPIS_OFFSET); 748 if (GST_MPI_STATE_UNINIT == 749 (gst_len_mpistate & GST_MPI_STATE_MASK)) 750 break; 751 } while (--max_wait_count); 752 if (!max_wait_count) { 753 pm8001_dbg(pm8001_ha, FAIL, " TIME OUT MPI State = 0x%x\n", 754 gst_len_mpistate & GST_MPI_STATE_MASK); 755 return -1; 756 } 757 return 0; 758} 759 760/** 761 * soft_reset_ready_check - Function to check FW is ready for soft reset. 762 * @pm8001_ha: our hba card information 763 */ 764static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha) 765{ 766 u32 regVal, regVal1, regVal2; 767 if (mpi_uninit_check(pm8001_ha) != 0) { 768 pm8001_dbg(pm8001_ha, FAIL, "MPI state is not ready\n"); 769 return -1; 770 } 771 /* read the scratch pad 2 register bit 2 */ 772 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) 773 & SCRATCH_PAD2_FWRDY_RST; 774 if (regVal == SCRATCH_PAD2_FWRDY_RST) { 775 pm8001_dbg(pm8001_ha, INIT, "Firmware is ready for reset.\n"); 776 } else { 777 unsigned long flags; 778 /* Trigger NMI twice via RB6 */ 779 spin_lock_irqsave(&pm8001_ha->lock, flags); 780 if (-1 == pm8001_bar4_shift(pm8001_ha, RB6_ACCESS_REG)) { 781 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 782 pm8001_dbg(pm8001_ha, FAIL, 783 "Shift Bar4 to 0x%x failed\n", 784 RB6_ACCESS_REG); 785 return -1; 786 } 787 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, 788 RB6_MAGIC_NUMBER_RST); 789 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST); 790 /* wait for 100 ms */ 791 mdelay(100); 792 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) & 793 SCRATCH_PAD2_FWRDY_RST; 794 if (regVal != SCRATCH_PAD2_FWRDY_RST) { 795 regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 796 regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 797 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:MSGU_SCRATCH_PAD1=0x%x, MSGU_SCRATCH_PAD2=0x%x\n", 798 regVal1, regVal2); 799 pm8001_dbg(pm8001_ha, FAIL, 800 "SCRATCH_PAD0 value = 0x%x\n", 801 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)); 802 pm8001_dbg(pm8001_ha, FAIL, 803 "SCRATCH_PAD3 value = 0x%x\n", 804 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)); 805 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 806 return -1; 807 } 808 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 809 } 810 return 0; 811} 812 813/** 814 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all 815 * the FW register status to the originated status. 816 * @pm8001_ha: our hba card information 817 */ 818static int 819pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha) 820{ 821 u32 regVal, toggleVal; 822 u32 max_wait_count; 823 u32 regVal1, regVal2, regVal3; 824 u32 signature = 0x252acbcd; /* for host scratch pad0 */ 825 unsigned long flags; 826 827 /* step1: Check FW is ready for soft reset */ 828 if (soft_reset_ready_check(pm8001_ha) != 0) { 829 pm8001_dbg(pm8001_ha, FAIL, "FW is not ready\n"); 830 return -1; 831 } 832 833 /* step 2: clear NMI status register on AAP1 and IOP, write the same 834 value to clear */ 835 /* map 0x60000 to BAR4(0x20), BAR2(win) */ 836 spin_lock_irqsave(&pm8001_ha->lock, flags); 837 if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) { 838 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 839 pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n", 840 MBIC_AAP1_ADDR_BASE); 841 return -1; 842 } 843 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP); 844 pm8001_dbg(pm8001_ha, INIT, "MBIC - NMI Enable VPE0 (IOP)= 0x%x\n", 845 regVal); 846 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0); 847 /* map 0x70000 to BAR4(0x20), BAR2(win) */ 848 if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) { 849 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 850 pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n", 851 MBIC_IOP_ADDR_BASE); 852 return -1; 853 } 854 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1); 855 pm8001_dbg(pm8001_ha, INIT, "MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n", 856 regVal); 857 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0); 858 859 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE); 860 pm8001_dbg(pm8001_ha, INIT, "PCIE -Event Interrupt Enable = 0x%x\n", 861 regVal); 862 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0); 863 864 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT); 865 pm8001_dbg(pm8001_ha, INIT, "PCIE - Event Interrupt = 0x%x\n", 866 regVal); 867 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal); 868 869 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE); 870 pm8001_dbg(pm8001_ha, INIT, "PCIE -Error Interrupt Enable = 0x%x\n", 871 regVal); 872 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0); 873 874 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT); 875 pm8001_dbg(pm8001_ha, INIT, "PCIE - Error Interrupt = 0x%x\n", regVal); 876 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal); 877 878 /* read the scratch pad 1 register bit 2 */ 879 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) 880 & SCRATCH_PAD1_RST; 881 toggleVal = regVal ^ SCRATCH_PAD1_RST; 882 883 /* set signature in host scratch pad0 register to tell SPC that the 884 host performs the soft reset */ 885 pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature); 886 887 /* read required registers for confirmming */ 888 /* map 0x0700000 to BAR4(0x20), BAR2(win) */ 889 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) { 890 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 891 pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n", 892 GSM_ADDR_BASE); 893 return -1; 894 } 895 pm8001_dbg(pm8001_ha, INIT, 896 "GSM 0x0(0x00007b88)-GSM Configuration and Reset = 0x%x\n", 897 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)); 898 899 /* step 3: host read GSM Configuration and Reset register */ 900 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET); 901 /* Put those bits to low */ 902 /* GSM XCBI offset = 0x70 0000 903 0x00 Bit 13 COM_SLV_SW_RSTB 1 904 0x00 Bit 12 QSSP_SW_RSTB 1 905 0x00 Bit 11 RAAE_SW_RSTB 1 906 0x00 Bit 9 RB_1_SW_RSTB 1 907 0x00 Bit 8 SM_SW_RSTB 1 908 */ 909 regVal &= ~(0x00003b00); 910 /* host write GSM Configuration and Reset register */ 911 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal); 912 pm8001_dbg(pm8001_ha, INIT, 913 "GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM Configuration and Reset is set to = 0x%x\n", 914 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)); 915 916 /* step 4: */ 917 /* disable GSM - Read Address Parity Check */ 918 regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK); 919 pm8001_dbg(pm8001_ha, INIT, 920 "GSM 0x700038 - Read Address Parity Check Enable = 0x%x\n", 921 regVal1); 922 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0); 923 pm8001_dbg(pm8001_ha, INIT, 924 "GSM 0x700038 - Read Address Parity Check Enable is set to = 0x%x\n", 925 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)); 926 927 /* disable GSM - Write Address Parity Check */ 928 regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK); 929 pm8001_dbg(pm8001_ha, INIT, 930 "GSM 0x700040 - Write Address Parity Check Enable = 0x%x\n", 931 regVal2); 932 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0); 933 pm8001_dbg(pm8001_ha, INIT, 934 "GSM 0x700040 - Write Address Parity Check Enable is set to = 0x%x\n", 935 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)); 936 937 /* disable GSM - Write Data Parity Check */ 938 regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK); 939 pm8001_dbg(pm8001_ha, INIT, "GSM 0x300048 - Write Data Parity Check Enable = 0x%x\n", 940 regVal3); 941 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0); 942 pm8001_dbg(pm8001_ha, INIT, 943 "GSM 0x300048 - Write Data Parity Check Enable is set to = 0x%x\n", 944 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)); 945 946 /* step 5: delay 10 usec */ 947 udelay(10); 948 /* step 5-b: set GPIO-0 output control to tristate anyway */ 949 if (-1 == pm8001_bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) { 950 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 951 pm8001_dbg(pm8001_ha, INIT, "Shift Bar4 to 0x%x failed\n", 952 GPIO_ADDR_BASE); 953 return -1; 954 } 955 regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET); 956 pm8001_dbg(pm8001_ha, INIT, "GPIO Output Control Register: = 0x%x\n", 957 regVal); 958 /* set GPIO-0 output control to tri-state */ 959 regVal &= 0xFFFFFFFC; 960 pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal); 961 962 /* Step 6: Reset the IOP and AAP1 */ 963 /* map 0x00000 to BAR4(0x20), BAR2(win) */ 964 if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) { 965 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 966 pm8001_dbg(pm8001_ha, FAIL, "SPC Shift Bar4 to 0x%x failed\n", 967 SPC_TOP_LEVEL_ADDR_BASE); 968 return -1; 969 } 970 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); 971 pm8001_dbg(pm8001_ha, INIT, "Top Register before resetting IOP/AAP1:= 0x%x\n", 972 regVal); 973 regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS); 974 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); 975 976 /* step 7: Reset the BDMA/OSSP */ 977 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); 978 pm8001_dbg(pm8001_ha, INIT, "Top Register before resetting BDMA/OSSP: = 0x%x\n", 979 regVal); 980 regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP); 981 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); 982 983 /* step 8: delay 10 usec */ 984 udelay(10); 985 986 /* step 9: bring the BDMA and OSSP out of reset */ 987 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); 988 pm8001_dbg(pm8001_ha, INIT, 989 "Top Register before bringing up BDMA/OSSP:= 0x%x\n", 990 regVal); 991 regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP); 992 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); 993 994 /* step 10: delay 10 usec */ 995 udelay(10); 996 997 /* step 11: reads and sets the GSM Configuration and Reset Register */ 998 /* map 0x0700000 to BAR4(0x20), BAR2(win) */ 999 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) { 1000 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1001 pm8001_dbg(pm8001_ha, FAIL, "SPC Shift Bar4 to 0x%x failed\n", 1002 GSM_ADDR_BASE); 1003 return -1; 1004 } 1005 pm8001_dbg(pm8001_ha, INIT, 1006 "GSM 0x0 (0x00007b88)-GSM Configuration and Reset = 0x%x\n", 1007 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)); 1008 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET); 1009 /* Put those bits to high */ 1010 /* GSM XCBI offset = 0x70 0000 1011 0x00 Bit 13 COM_SLV_SW_RSTB 1 1012 0x00 Bit 12 QSSP_SW_RSTB 1 1013 0x00 Bit 11 RAAE_SW_RSTB 1 1014 0x00 Bit 9 RB_1_SW_RSTB 1 1015 0x00 Bit 8 SM_SW_RSTB 1 1016 */ 1017 regVal |= (GSM_CONFIG_RESET_VALUE); 1018 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal); 1019 pm8001_dbg(pm8001_ha, INIT, "GSM (0x00004088 ==> 0x00007b88) - GSM Configuration and Reset is set to = 0x%x\n", 1020 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)); 1021 1022 /* step 12: Restore GSM - Read Address Parity Check */ 1023 regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK); 1024 /* just for debugging */ 1025 pm8001_dbg(pm8001_ha, INIT, 1026 "GSM 0x700038 - Read Address Parity Check Enable = 0x%x\n", 1027 regVal); 1028 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1); 1029 pm8001_dbg(pm8001_ha, INIT, "GSM 0x700038 - Read Address Parity Check Enable is set to = 0x%x\n", 1030 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)); 1031 /* Restore GSM - Write Address Parity Check */ 1032 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK); 1033 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2); 1034 pm8001_dbg(pm8001_ha, INIT, 1035 "GSM 0x700040 - Write Address Parity Check Enable is set to = 0x%x\n", 1036 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)); 1037 /* Restore GSM - Write Data Parity Check */ 1038 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK); 1039 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3); 1040 pm8001_dbg(pm8001_ha, INIT, 1041 "GSM 0x700048 - Write Data Parity Check Enable is set to = 0x%x\n", 1042 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)); 1043 1044 /* step 13: bring the IOP and AAP1 out of reset */ 1045 /* map 0x00000 to BAR4(0x20), BAR2(win) */ 1046 if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) { 1047 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1048 pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n", 1049 SPC_TOP_LEVEL_ADDR_BASE); 1050 return -1; 1051 } 1052 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); 1053 regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS); 1054 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); 1055 1056 /* step 14: delay 10 usec - Normal Mode */ 1057 udelay(10); 1058 /* check Soft Reset Normal mode or Soft Reset HDA mode */ 1059 if (signature == SPC_SOFT_RESET_SIGNATURE) { 1060 /* step 15 (Normal Mode): wait until scratch pad1 register 1061 bit 2 toggled */ 1062 max_wait_count = 2 * 1000 * 1000;/* 2 sec */ 1063 do { 1064 udelay(1); 1065 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) & 1066 SCRATCH_PAD1_RST; 1067 } while ((regVal != toggleVal) && (--max_wait_count)); 1068 1069 if (!max_wait_count) { 1070 regVal = pm8001_cr32(pm8001_ha, 0, 1071 MSGU_SCRATCH_PAD_1); 1072 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT : ToggleVal 0x%x,MSGU_SCRATCH_PAD1 = 0x%x\n", 1073 toggleVal, regVal); 1074 pm8001_dbg(pm8001_ha, FAIL, 1075 "SCRATCH_PAD0 value = 0x%x\n", 1076 pm8001_cr32(pm8001_ha, 0, 1077 MSGU_SCRATCH_PAD_0)); 1078 pm8001_dbg(pm8001_ha, FAIL, 1079 "SCRATCH_PAD2 value = 0x%x\n", 1080 pm8001_cr32(pm8001_ha, 0, 1081 MSGU_SCRATCH_PAD_2)); 1082 pm8001_dbg(pm8001_ha, FAIL, 1083 "SCRATCH_PAD3 value = 0x%x\n", 1084 pm8001_cr32(pm8001_ha, 0, 1085 MSGU_SCRATCH_PAD_3)); 1086 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1087 return -1; 1088 } 1089 1090 /* step 16 (Normal) - Clear ODMR and ODCR */ 1091 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); 1092 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); 1093 1094 /* step 17 (Normal Mode): wait for the FW and IOP to get 1095 ready - 1 sec timeout */ 1096 /* Wait for the SPC Configuration Table to be ready */ 1097 if (check_fw_ready(pm8001_ha) == -1) { 1098 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1099 /* return error if MPI Configuration Table not ready */ 1100 pm8001_dbg(pm8001_ha, INIT, 1101 "FW not ready SCRATCH_PAD1 = 0x%x\n", 1102 regVal); 1103 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 1104 /* return error if MPI Configuration Table not ready */ 1105 pm8001_dbg(pm8001_ha, INIT, 1106 "FW not ready SCRATCH_PAD2 = 0x%x\n", 1107 regVal); 1108 pm8001_dbg(pm8001_ha, INIT, 1109 "SCRATCH_PAD0 value = 0x%x\n", 1110 pm8001_cr32(pm8001_ha, 0, 1111 MSGU_SCRATCH_PAD_0)); 1112 pm8001_dbg(pm8001_ha, INIT, 1113 "SCRATCH_PAD3 value = 0x%x\n", 1114 pm8001_cr32(pm8001_ha, 0, 1115 MSGU_SCRATCH_PAD_3)); 1116 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1117 return -1; 1118 } 1119 } 1120 pm8001_bar4_shift(pm8001_ha, 0); 1121 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1122 1123 pm8001_dbg(pm8001_ha, INIT, "SPC soft reset Complete\n"); 1124 return 0; 1125} 1126 1127static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha) 1128{ 1129 u32 i; 1130 u32 regVal; 1131 pm8001_dbg(pm8001_ha, INIT, "chip reset start\n"); 1132 1133 /* do SPC chip reset. */ 1134 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET); 1135 regVal &= ~(SPC_REG_RESET_DEVICE); 1136 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal); 1137 1138 /* delay 10 usec */ 1139 udelay(10); 1140 1141 /* bring chip reset out of reset */ 1142 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET); 1143 regVal |= SPC_REG_RESET_DEVICE; 1144 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal); 1145 1146 /* delay 10 usec */ 1147 udelay(10); 1148 1149 /* wait for 20 msec until the firmware gets reloaded */ 1150 i = 20; 1151 do { 1152 mdelay(1); 1153 } while ((--i) != 0); 1154 1155 pm8001_dbg(pm8001_ha, INIT, "chip reset finished\n"); 1156} 1157 1158/** 1159 * pm8001_chip_iounmap - which mapped when initialized. 1160 * @pm8001_ha: our hba card information 1161 */ 1162void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha) 1163{ 1164 s8 bar, logical = 0; 1165 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) { 1166 /* 1167 ** logical BARs for SPC: 1168 ** bar 0 and 1 - logical BAR0 1169 ** bar 2 and 3 - logical BAR1 1170 ** bar4 - logical BAR2 1171 ** bar5 - logical BAR3 1172 ** Skip the appropriate assignments: 1173 */ 1174 if ((bar == 1) || (bar == 3)) 1175 continue; 1176 if (pm8001_ha->io_mem[logical].memvirtaddr) { 1177 iounmap(pm8001_ha->io_mem[logical].memvirtaddr); 1178 logical++; 1179 } 1180 } 1181} 1182 1183/** 1184 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt 1185 * @pm8001_ha: our hba card information 1186 * @vec: unused 1187 */ 1188static void 1189pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec) 1190{ 1191 if (pm8001_ha->use_msix) { 1192 pm8001_cw32(pm8001_ha, 0, MSIX_TABLE_BASE, 1193 MSIX_INTERRUPT_ENABLE); 1194 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, 1); 1195 } else { 1196 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); 1197 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); 1198 } 1199} 1200 1201/** 1202 * pm8001_chip_interrupt_disable - disable PM8001 chip interrupt 1203 * @pm8001_ha: our hba card information 1204 * @vec: unused 1205 */ 1206static void 1207pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec) 1208{ 1209 if (pm8001_ha->use_msix) 1210 pm8001_cw32(pm8001_ha, 0, MSIX_TABLE_BASE, 1211 MSIX_INTERRUPT_DISABLE); 1212 else 1213 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL); 1214} 1215 1216/** 1217 * pm8001_mpi_msg_free_get - get the free message buffer for transfer 1218 * inbound queue. 1219 * @circularQ: the inbound queue we want to transfer to HBA. 1220 * @messageSize: the message size of this transfer, normally it is 64 bytes 1221 * @messagePtr: the pointer to message. 1222 */ 1223int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ, 1224 u16 messageSize, void **messagePtr) 1225{ 1226 u32 offset, consumer_index; 1227 struct mpi_msg_hdr *msgHeader; 1228 u8 bcCount = 1; /* only support single buffer */ 1229 1230 /* Checks is the requested message size can be allocated in this queue*/ 1231 if (messageSize > IOMB_SIZE_SPCV) { 1232 *messagePtr = NULL; 1233 return -1; 1234 } 1235 1236 /* Stores the new consumer index */ 1237 consumer_index = pm8001_read_32(circularQ->ci_virt); 1238 circularQ->consumer_index = cpu_to_le32(consumer_index); 1239 if (((circularQ->producer_idx + bcCount) % PM8001_MPI_QUEUE) == 1240 le32_to_cpu(circularQ->consumer_index)) { 1241 *messagePtr = NULL; 1242 return -1; 1243 } 1244 /* get memory IOMB buffer address */ 1245 offset = circularQ->producer_idx * messageSize; 1246 /* increment to next bcCount element */ 1247 circularQ->producer_idx = (circularQ->producer_idx + bcCount) 1248 % PM8001_MPI_QUEUE; 1249 /* Adds that distance to the base of the region virtual address plus 1250 the message header size*/ 1251 msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset); 1252 *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr); 1253 return 0; 1254} 1255 1256/** 1257 * pm8001_mpi_build_cmd- build the message queue for transfer, update the PI to 1258 * FW to tell the fw to get this message from IOMB. 1259 * @pm8001_ha: our hba card information 1260 * @q_index: the index in the inbound queue we want to transfer to HBA. 1261 * @opCode: the operation code represents commands which LLDD and fw recognized. 1262 * @payload: the command payload of each operation command. 1263 * @nb: size in bytes of the command payload 1264 * @responseQueue: queue to interrupt on w/ command response (if any) 1265 */ 1266int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha, 1267 u32 q_index, u32 opCode, void *payload, size_t nb, 1268 u32 responseQueue) 1269{ 1270 u32 Header = 0, hpriority = 0, bc = 1, category = 0x02; 1271 void *pMessage; 1272 unsigned long flags; 1273 struct inbound_queue_table *circularQ = &pm8001_ha->inbnd_q_tbl[q_index]; 1274 int rv; 1275 u32 htag = le32_to_cpu(*(__le32 *)payload); 1276 1277 trace_pm80xx_mpi_build_cmd(pm8001_ha->id, opCode, htag, q_index, 1278 circularQ->producer_idx, le32_to_cpu(circularQ->consumer_index)); 1279 1280 if (WARN_ON(q_index >= pm8001_ha->max_q_num)) 1281 return -EINVAL; 1282 1283 spin_lock_irqsave(&circularQ->iq_lock, flags); 1284 rv = pm8001_mpi_msg_free_get(circularQ, pm8001_ha->iomb_size, 1285 &pMessage); 1286 if (rv < 0) { 1287 pm8001_dbg(pm8001_ha, IO, "No free mpi buffer\n"); 1288 rv = -ENOMEM; 1289 goto done; 1290 } 1291 1292 if (nb > (pm8001_ha->iomb_size - sizeof(struct mpi_msg_hdr))) 1293 nb = pm8001_ha->iomb_size - sizeof(struct mpi_msg_hdr); 1294 memcpy(pMessage, payload, nb); 1295 if (nb + sizeof(struct mpi_msg_hdr) < pm8001_ha->iomb_size) 1296 memset(pMessage + nb, 0, pm8001_ha->iomb_size - 1297 (nb + sizeof(struct mpi_msg_hdr))); 1298 1299 /*Build the header*/ 1300 Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24) 1301 | ((responseQueue & 0x3F) << 16) 1302 | ((category & 0xF) << 12) | (opCode & 0xFFF)); 1303 1304 pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header)); 1305 /*Update the PI to the firmware*/ 1306 pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar, 1307 circularQ->pi_offset, circularQ->producer_idx); 1308 pm8001_dbg(pm8001_ha, DEVIO, 1309 "INB Q %x OPCODE:%x , UPDATED PI=%d CI=%d\n", 1310 responseQueue, opCode, circularQ->producer_idx, 1311 circularQ->consumer_index); 1312done: 1313 spin_unlock_irqrestore(&circularQ->iq_lock, flags); 1314 return rv; 1315} 1316 1317u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg, 1318 struct outbound_queue_table *circularQ, u8 bc) 1319{ 1320 u32 producer_index; 1321 struct mpi_msg_hdr *msgHeader; 1322 struct mpi_msg_hdr *pOutBoundMsgHeader; 1323 1324 msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr)); 1325 pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + 1326 circularQ->consumer_idx * pm8001_ha->iomb_size); 1327 if (pOutBoundMsgHeader != msgHeader) { 1328 pm8001_dbg(pm8001_ha, FAIL, 1329 "consumer_idx = %d msgHeader = %p\n", 1330 circularQ->consumer_idx, msgHeader); 1331 1332 /* Update the producer index from SPC */ 1333 producer_index = pm8001_read_32(circularQ->pi_virt); 1334 circularQ->producer_index = cpu_to_le32(producer_index); 1335 pm8001_dbg(pm8001_ha, FAIL, 1336 "consumer_idx = %d producer_index = %dmsgHeader = %p\n", 1337 circularQ->consumer_idx, 1338 circularQ->producer_index, msgHeader); 1339 return 0; 1340 } 1341 /* free the circular queue buffer elements associated with the message*/ 1342 circularQ->consumer_idx = (circularQ->consumer_idx + bc) 1343 % PM8001_MPI_QUEUE; 1344 /* update the CI of outbound queue */ 1345 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset, 1346 circularQ->consumer_idx); 1347 /* Update the producer index from SPC*/ 1348 producer_index = pm8001_read_32(circularQ->pi_virt); 1349 circularQ->producer_index = cpu_to_le32(producer_index); 1350 pm8001_dbg(pm8001_ha, IO, " CI=%d PI=%d\n", 1351 circularQ->consumer_idx, circularQ->producer_index); 1352 return 0; 1353} 1354 1355/** 1356 * pm8001_mpi_msg_consume- get the MPI message from outbound queue 1357 * message table. 1358 * @pm8001_ha: our hba card information 1359 * @circularQ: the outbound queue table. 1360 * @messagePtr1: the message contents of this outbound message. 1361 * @pBC: the message size. 1362 */ 1363u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha, 1364 struct outbound_queue_table *circularQ, 1365 void **messagePtr1, u8 *pBC) 1366{ 1367 struct mpi_msg_hdr *msgHeader; 1368 __le32 msgHeader_tmp; 1369 u32 header_tmp; 1370 do { 1371 /* If there are not-yet-delivered messages ... */ 1372 if (le32_to_cpu(circularQ->producer_index) 1373 != circularQ->consumer_idx) { 1374 /*Get the pointer to the circular queue buffer element*/ 1375 msgHeader = (struct mpi_msg_hdr *) 1376 (circularQ->base_virt + 1377 circularQ->consumer_idx * pm8001_ha->iomb_size); 1378 /* read header */ 1379 header_tmp = pm8001_read_32(msgHeader); 1380 msgHeader_tmp = cpu_to_le32(header_tmp); 1381 pm8001_dbg(pm8001_ha, DEVIO, 1382 "outbound opcode msgheader:%x ci=%d pi=%d\n", 1383 msgHeader_tmp, circularQ->consumer_idx, 1384 circularQ->producer_index); 1385 if (0 != (le32_to_cpu(msgHeader_tmp) & 0x80000000)) { 1386 if (OPC_OUB_SKIP_ENTRY != 1387 (le32_to_cpu(msgHeader_tmp) & 0xfff)) { 1388 *messagePtr1 = 1389 ((u8 *)msgHeader) + 1390 sizeof(struct mpi_msg_hdr); 1391 *pBC = (u8)((le32_to_cpu(msgHeader_tmp) 1392 >> 24) & 0x1f); 1393 pm8001_dbg(pm8001_ha, IO, 1394 ": CI=%d PI=%d msgHeader=%x\n", 1395 circularQ->consumer_idx, 1396 circularQ->producer_index, 1397 msgHeader_tmp); 1398 return MPI_IO_STATUS_SUCCESS; 1399 } else { 1400 circularQ->consumer_idx = 1401 (circularQ->consumer_idx + 1402 ((le32_to_cpu(msgHeader_tmp) 1403 >> 24) & 0x1f)) 1404 % PM8001_MPI_QUEUE; 1405 msgHeader_tmp = 0; 1406 pm8001_write_32(msgHeader, 0, 0); 1407 /* update the CI of outbound queue */ 1408 pm8001_cw32(pm8001_ha, 1409 circularQ->ci_pci_bar, 1410 circularQ->ci_offset, 1411 circularQ->consumer_idx); 1412 } 1413 } else { 1414 circularQ->consumer_idx = 1415 (circularQ->consumer_idx + 1416 ((le32_to_cpu(msgHeader_tmp) >> 24) & 1417 0x1f)) % PM8001_MPI_QUEUE; 1418 msgHeader_tmp = 0; 1419 pm8001_write_32(msgHeader, 0, 0); 1420 /* update the CI of outbound queue */ 1421 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, 1422 circularQ->ci_offset, 1423 circularQ->consumer_idx); 1424 return MPI_IO_STATUS_FAIL; 1425 } 1426 } else { 1427 u32 producer_index; 1428 void *pi_virt = circularQ->pi_virt; 1429 /* spurious interrupt during setup if 1430 * kexec-ing and driver doing a doorbell access 1431 * with the pre-kexec oq interrupt setup 1432 */ 1433 if (!pi_virt) 1434 break; 1435 /* Update the producer index from SPC */ 1436 producer_index = pm8001_read_32(pi_virt); 1437 circularQ->producer_index = cpu_to_le32(producer_index); 1438 } 1439 } while (le32_to_cpu(circularQ->producer_index) != 1440 circularQ->consumer_idx); 1441 /* while we don't have any more not-yet-delivered message */ 1442 /* report empty */ 1443 return MPI_IO_STATUS_BUSY; 1444} 1445 1446void pm8001_work_fn(struct work_struct *work) 1447{ 1448 struct pm8001_work *pw = container_of(work, struct pm8001_work, work); 1449 struct pm8001_device *pm8001_dev; 1450 struct domain_device *dev; 1451 1452 /* 1453 * So far, all users of this stash an associated structure here. 1454 * If we get here, and this pointer is null, then the action 1455 * was cancelled. This nullification happens when the device 1456 * goes away. 1457 */ 1458 if (pw->handler != IO_FATAL_ERROR) { 1459 pm8001_dev = pw->data; /* Most stash device structure */ 1460 if ((pm8001_dev == NULL) 1461 || ((pw->handler != IO_XFER_ERROR_BREAK) 1462 && (pm8001_dev->dev_type == SAS_PHY_UNUSED))) { 1463 kfree(pw); 1464 return; 1465 } 1466 } 1467 1468 switch (pw->handler) { 1469 case IO_XFER_ERROR_BREAK: 1470 { /* This one stashes the sas_task instead */ 1471 struct sas_task *t = (struct sas_task *)pm8001_dev; 1472 struct pm8001_ccb_info *ccb; 1473 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha; 1474 unsigned long flags, flags1; 1475 struct task_status_struct *ts; 1476 int i; 1477 1478 if (pm8001_query_task(t) == TMF_RESP_FUNC_SUCC) 1479 break; /* Task still on lu */ 1480 spin_lock_irqsave(&pm8001_ha->lock, flags); 1481 1482 spin_lock_irqsave(&t->task_state_lock, flags1); 1483 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) { 1484 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1485 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1486 break; /* Task got completed by another */ 1487 } 1488 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1489 1490 /* Search for a possible ccb that matches the task */ 1491 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) { 1492 ccb = &pm8001_ha->ccb_info[i]; 1493 if ((ccb->ccb_tag != PM8001_INVALID_TAG) && 1494 (ccb->task == t)) 1495 break; 1496 } 1497 if (!ccb) { 1498 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1499 break; /* Task got freed by another */ 1500 } 1501 ts = &t->task_status; 1502 ts->resp = SAS_TASK_COMPLETE; 1503 /* Force the midlayer to retry */ 1504 ts->stat = SAS_QUEUE_FULL; 1505 pm8001_dev = ccb->device; 1506 if (pm8001_dev) 1507 atomic_dec(&pm8001_dev->running_req); 1508 spin_lock_irqsave(&t->task_state_lock, flags1); 1509 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 1510 t->task_state_flags |= SAS_TASK_STATE_DONE; 1511 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 1512 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1513 pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 1514 t, pw->handler, ts->resp, ts->stat); 1515 pm8001_ccb_task_free(pm8001_ha, ccb); 1516 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1517 } else { 1518 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1519 pm8001_ccb_task_free(pm8001_ha, ccb); 1520 mb();/* in order to force CPU ordering */ 1521 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1522 t->task_done(t); 1523 } 1524 } break; 1525 case IO_XFER_OPEN_RETRY_TIMEOUT: 1526 { /* This one stashes the sas_task instead */ 1527 struct sas_task *t = (struct sas_task *)pm8001_dev; 1528 struct pm8001_ccb_info *ccb; 1529 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha; 1530 unsigned long flags, flags1; 1531 int i, ret = 0; 1532 1533 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 1534 1535 ret = pm8001_query_task(t); 1536 1537 if (ret == TMF_RESP_FUNC_SUCC) 1538 pm8001_dbg(pm8001_ha, IO, "...Task on lu\n"); 1539 else if (ret == TMF_RESP_FUNC_COMPLETE) 1540 pm8001_dbg(pm8001_ha, IO, "...Task NOT on lu\n"); 1541 else 1542 pm8001_dbg(pm8001_ha, DEVIO, "...query task failed!!!\n"); 1543 1544 spin_lock_irqsave(&pm8001_ha->lock, flags); 1545 1546 spin_lock_irqsave(&t->task_state_lock, flags1); 1547 1548 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) { 1549 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1550 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1551 if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */ 1552 (void)pm8001_abort_task(t); 1553 break; /* Task got completed by another */ 1554 } 1555 1556 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1557 1558 /* Search for a possible ccb that matches the task */ 1559 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) { 1560 ccb = &pm8001_ha->ccb_info[i]; 1561 if ((ccb->ccb_tag != PM8001_INVALID_TAG) && 1562 (ccb->task == t)) 1563 break; 1564 } 1565 if (!ccb) { 1566 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1567 if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */ 1568 (void)pm8001_abort_task(t); 1569 break; /* Task got freed by another */ 1570 } 1571 1572 pm8001_dev = ccb->device; 1573 dev = pm8001_dev->sas_device; 1574 1575 switch (ret) { 1576 case TMF_RESP_FUNC_SUCC: /* task on lu */ 1577 ccb->open_retry = 1; /* Snub completion */ 1578 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1579 ret = pm8001_abort_task(t); 1580 ccb->open_retry = 0; 1581 switch (ret) { 1582 case TMF_RESP_FUNC_SUCC: 1583 case TMF_RESP_FUNC_COMPLETE: 1584 break; 1585 default: /* device misbehavior */ 1586 ret = TMF_RESP_FUNC_FAILED; 1587 pm8001_dbg(pm8001_ha, IO, "...Reset phy\n"); 1588 pm8001_I_T_nexus_reset(dev); 1589 break; 1590 } 1591 break; 1592 1593 case TMF_RESP_FUNC_COMPLETE: /* task not on lu */ 1594 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1595 /* Do we need to abort the task locally? */ 1596 break; 1597 1598 default: /* device misbehavior */ 1599 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1600 ret = TMF_RESP_FUNC_FAILED; 1601 pm8001_dbg(pm8001_ha, IO, "...Reset phy\n"); 1602 pm8001_I_T_nexus_reset(dev); 1603 } 1604 1605 if (ret == TMF_RESP_FUNC_FAILED) 1606 t = NULL; 1607 pm8001_open_reject_retry(pm8001_ha, t, pm8001_dev); 1608 pm8001_dbg(pm8001_ha, IO, "...Complete\n"); 1609 } break; 1610 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 1611 dev = pm8001_dev->sas_device; 1612 pm8001_I_T_nexus_event_handler(dev); 1613 break; 1614 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: 1615 dev = pm8001_dev->sas_device; 1616 pm8001_I_T_nexus_reset(dev); 1617 break; 1618 case IO_DS_IN_ERROR: 1619 dev = pm8001_dev->sas_device; 1620 pm8001_I_T_nexus_reset(dev); 1621 break; 1622 case IO_DS_NON_OPERATIONAL: 1623 dev = pm8001_dev->sas_device; 1624 pm8001_I_T_nexus_reset(dev); 1625 break; 1626 case IO_FATAL_ERROR: 1627 { 1628 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha; 1629 struct pm8001_ccb_info *ccb; 1630 struct task_status_struct *ts; 1631 struct sas_task *task; 1632 int i; 1633 u32 device_id; 1634 1635 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) { 1636 ccb = &pm8001_ha->ccb_info[i]; 1637 task = ccb->task; 1638 ts = &task->task_status; 1639 1640 if (task != NULL) { 1641 dev = task->dev; 1642 if (!dev) { 1643 pm8001_dbg(pm8001_ha, FAIL, 1644 "dev is NULL\n"); 1645 continue; 1646 } 1647 /*complete sas task and update to top layer */ 1648 pm8001_ccb_task_free(pm8001_ha, ccb); 1649 ts->resp = SAS_TASK_COMPLETE; 1650 task->task_done(task); 1651 } else if (ccb->ccb_tag != PM8001_INVALID_TAG) { 1652 /* complete the internal commands/non-sas task */ 1653 pm8001_dev = ccb->device; 1654 if (pm8001_dev->dcompletion) { 1655 complete(pm8001_dev->dcompletion); 1656 pm8001_dev->dcompletion = NULL; 1657 } 1658 complete(pm8001_ha->nvmd_completion); 1659 pm8001_ccb_free(pm8001_ha, ccb); 1660 } 1661 } 1662 /* Deregister all the device ids */ 1663 for (i = 0; i < PM8001_MAX_DEVICES; i++) { 1664 pm8001_dev = &pm8001_ha->devices[i]; 1665 device_id = pm8001_dev->device_id; 1666 if (device_id) { 1667 PM8001_CHIP_DISP->dereg_dev_req(pm8001_ha, device_id); 1668 pm8001_free_dev(pm8001_dev); 1669 } 1670 } 1671 } 1672 break; 1673 case IO_XFER_ERROR_ABORTED_NCQ_MODE: 1674 { 1675 dev = pm8001_dev->sas_device; 1676 sas_ata_device_link_abort(dev, false); 1677 } 1678 break; 1679 } 1680 kfree(pw); 1681} 1682 1683int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data, 1684 int handler) 1685{ 1686 struct pm8001_work *pw; 1687 int ret = 0; 1688 1689 pw = kmalloc(sizeof(struct pm8001_work), GFP_ATOMIC); 1690 if (pw) { 1691 pw->pm8001_ha = pm8001_ha; 1692 pw->data = data; 1693 pw->handler = handler; 1694 INIT_WORK(&pw->work, pm8001_work_fn); 1695 queue_work(pm8001_wq, &pw->work); 1696 } else 1697 ret = -ENOMEM; 1698 1699 return ret; 1700} 1701 1702/** 1703 * mpi_ssp_completion- process the event that FW response to the SSP request. 1704 * @pm8001_ha: our hba card information 1705 * @piomb: the message contents of this outbound message. 1706 * 1707 * When FW has completed a ssp request for example a IO request, after it has 1708 * filled the SG data with the data, it will trigger this event representing 1709 * that he has finished the job; please check the corresponding buffer. 1710 * So we will tell the caller who maybe waiting the result to tell upper layer 1711 * that the task has been finished. 1712 */ 1713static void 1714mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 1715{ 1716 struct sas_task *t; 1717 struct pm8001_ccb_info *ccb; 1718 unsigned long flags; 1719 u32 status; 1720 u32 param; 1721 u32 tag; 1722 struct ssp_completion_resp *psspPayload; 1723 struct task_status_struct *ts; 1724 struct ssp_response_iu *iu; 1725 struct pm8001_device *pm8001_dev; 1726 psspPayload = (struct ssp_completion_resp *)(piomb + 4); 1727 status = le32_to_cpu(psspPayload->status); 1728 tag = le32_to_cpu(psspPayload->tag); 1729 ccb = &pm8001_ha->ccb_info[tag]; 1730 if ((status == IO_ABORTED) && ccb->open_retry) { 1731 /* Being completed by another */ 1732 ccb->open_retry = 0; 1733 return; 1734 } 1735 pm8001_dev = ccb->device; 1736 param = le32_to_cpu(psspPayload->param); 1737 1738 t = ccb->task; 1739 1740 if (status && status != IO_UNDERFLOW) 1741 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", status); 1742 if (unlikely(!t || !t->lldd_task || !t->dev)) 1743 return; 1744 ts = &t->task_status; 1745 /* Print sas address of IO failed device */ 1746 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && 1747 (status != IO_UNDERFLOW)) 1748 pm8001_dbg(pm8001_ha, FAIL, "SAS Address of IO Failure Drive:%016llx\n", 1749 SAS_ADDR(t->dev->sas_addr)); 1750 1751 if (status) 1752 pm8001_dbg(pm8001_ha, IOERR, 1753 "status:0x%x, tag:0x%x, task:0x%p\n", 1754 status, tag, t); 1755 1756 switch (status) { 1757 case IO_SUCCESS: 1758 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS,param = %d\n", 1759 param); 1760 if (param == 0) { 1761 ts->resp = SAS_TASK_COMPLETE; 1762 ts->stat = SAS_SAM_STAT_GOOD; 1763 } else { 1764 ts->resp = SAS_TASK_COMPLETE; 1765 ts->stat = SAS_PROTO_RESPONSE; 1766 ts->residual = param; 1767 iu = &psspPayload->ssp_resp_iu; 1768 sas_ssp_task_response(pm8001_ha->dev, t, iu); 1769 } 1770 if (pm8001_dev) 1771 atomic_dec(&pm8001_dev->running_req); 1772 break; 1773 case IO_ABORTED: 1774 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n"); 1775 ts->resp = SAS_TASK_COMPLETE; 1776 ts->stat = SAS_ABORTED_TASK; 1777 break; 1778 case IO_UNDERFLOW: 1779 /* SSP Completion with error */ 1780 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW,param = %d\n", 1781 param); 1782 ts->resp = SAS_TASK_COMPLETE; 1783 ts->stat = SAS_DATA_UNDERRUN; 1784 ts->residual = param; 1785 if (pm8001_dev) 1786 atomic_dec(&pm8001_dev->running_req); 1787 break; 1788 case IO_NO_DEVICE: 1789 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n"); 1790 ts->resp = SAS_TASK_UNDELIVERED; 1791 ts->stat = SAS_PHY_DOWN; 1792 break; 1793 case IO_XFER_ERROR_BREAK: 1794 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 1795 ts->resp = SAS_TASK_COMPLETE; 1796 ts->stat = SAS_OPEN_REJECT; 1797 /* Force the midlayer to retry */ 1798 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1799 break; 1800 case IO_XFER_ERROR_PHY_NOT_READY: 1801 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 1802 ts->resp = SAS_TASK_COMPLETE; 1803 ts->stat = SAS_OPEN_REJECT; 1804 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1805 break; 1806 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 1807 pm8001_dbg(pm8001_ha, IO, 1808 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 1809 ts->resp = SAS_TASK_COMPLETE; 1810 ts->stat = SAS_OPEN_REJECT; 1811 ts->open_rej_reason = SAS_OREJ_EPROTO; 1812 break; 1813 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 1814 pm8001_dbg(pm8001_ha, IO, 1815 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 1816 ts->resp = SAS_TASK_COMPLETE; 1817 ts->stat = SAS_OPEN_REJECT; 1818 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1819 break; 1820 case IO_OPEN_CNX_ERROR_BREAK: 1821 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 1822 ts->resp = SAS_TASK_COMPLETE; 1823 ts->stat = SAS_OPEN_REJECT; 1824 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1825 break; 1826 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 1827 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 1828 ts->resp = SAS_TASK_COMPLETE; 1829 ts->stat = SAS_OPEN_REJECT; 1830 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1831 if (!t->uldd_task) 1832 pm8001_handle_event(pm8001_ha, 1833 pm8001_dev, 1834 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 1835 break; 1836 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 1837 pm8001_dbg(pm8001_ha, IO, 1838 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 1839 ts->resp = SAS_TASK_COMPLETE; 1840 ts->stat = SAS_OPEN_REJECT; 1841 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 1842 break; 1843 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 1844 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 1845 ts->resp = SAS_TASK_COMPLETE; 1846 ts->stat = SAS_OPEN_REJECT; 1847 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 1848 break; 1849 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 1850 pm8001_dbg(pm8001_ha, IO, 1851 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 1852 ts->resp = SAS_TASK_UNDELIVERED; 1853 ts->stat = SAS_OPEN_REJECT; 1854 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 1855 break; 1856 case IO_XFER_ERROR_NAK_RECEIVED: 1857 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 1858 ts->resp = SAS_TASK_COMPLETE; 1859 ts->stat = SAS_OPEN_REJECT; 1860 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1861 break; 1862 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 1863 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"); 1864 ts->resp = SAS_TASK_COMPLETE; 1865 ts->stat = SAS_NAK_R_ERR; 1866 break; 1867 case IO_XFER_ERROR_DMA: 1868 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n"); 1869 ts->resp = SAS_TASK_COMPLETE; 1870 ts->stat = SAS_OPEN_REJECT; 1871 break; 1872 case IO_XFER_OPEN_RETRY_TIMEOUT: 1873 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 1874 ts->resp = SAS_TASK_COMPLETE; 1875 ts->stat = SAS_OPEN_REJECT; 1876 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1877 break; 1878 case IO_XFER_ERROR_OFFSET_MISMATCH: 1879 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n"); 1880 ts->resp = SAS_TASK_COMPLETE; 1881 ts->stat = SAS_OPEN_REJECT; 1882 break; 1883 case IO_PORT_IN_RESET: 1884 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n"); 1885 ts->resp = SAS_TASK_COMPLETE; 1886 ts->stat = SAS_OPEN_REJECT; 1887 break; 1888 case IO_DS_NON_OPERATIONAL: 1889 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n"); 1890 ts->resp = SAS_TASK_COMPLETE; 1891 ts->stat = SAS_OPEN_REJECT; 1892 if (!t->uldd_task) 1893 pm8001_handle_event(pm8001_ha, 1894 pm8001_dev, 1895 IO_DS_NON_OPERATIONAL); 1896 break; 1897 case IO_DS_IN_RECOVERY: 1898 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n"); 1899 ts->resp = SAS_TASK_COMPLETE; 1900 ts->stat = SAS_OPEN_REJECT; 1901 break; 1902 case IO_TM_TAG_NOT_FOUND: 1903 pm8001_dbg(pm8001_ha, IO, "IO_TM_TAG_NOT_FOUND\n"); 1904 ts->resp = SAS_TASK_COMPLETE; 1905 ts->stat = SAS_OPEN_REJECT; 1906 break; 1907 case IO_SSP_EXT_IU_ZERO_LEN_ERROR: 1908 pm8001_dbg(pm8001_ha, IO, "IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"); 1909 ts->resp = SAS_TASK_COMPLETE; 1910 ts->stat = SAS_OPEN_REJECT; 1911 break; 1912 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 1913 pm8001_dbg(pm8001_ha, IO, 1914 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"); 1915 ts->resp = SAS_TASK_COMPLETE; 1916 ts->stat = SAS_OPEN_REJECT; 1917 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1918 break; 1919 default: 1920 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status); 1921 /* not allowed case. Therefore, return failed status */ 1922 ts->resp = SAS_TASK_COMPLETE; 1923 ts->stat = SAS_OPEN_REJECT; 1924 break; 1925 } 1926 pm8001_dbg(pm8001_ha, IO, "scsi_status = %x\n", 1927 psspPayload->ssp_resp_iu.status); 1928 spin_lock_irqsave(&t->task_state_lock, flags); 1929 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 1930 t->task_state_flags |= SAS_TASK_STATE_DONE; 1931 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 1932 spin_unlock_irqrestore(&t->task_state_lock, flags); 1933 pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 1934 t, status, ts->resp, ts->stat); 1935 pm8001_ccb_task_free(pm8001_ha, ccb); 1936 } else { 1937 spin_unlock_irqrestore(&t->task_state_lock, flags); 1938 pm8001_ccb_task_free(pm8001_ha, ccb); 1939 mb();/* in order to force CPU ordering */ 1940 t->task_done(t); 1941 } 1942} 1943 1944/*See the comments for mpi_ssp_completion */ 1945static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha, void *piomb) 1946{ 1947 struct sas_task *t; 1948 unsigned long flags; 1949 struct task_status_struct *ts; 1950 struct pm8001_ccb_info *ccb; 1951 struct pm8001_device *pm8001_dev; 1952 struct ssp_event_resp *psspPayload = 1953 (struct ssp_event_resp *)(piomb + 4); 1954 u32 event = le32_to_cpu(psspPayload->event); 1955 u32 tag = le32_to_cpu(psspPayload->tag); 1956 u32 port_id = le32_to_cpu(psspPayload->port_id); 1957 u32 dev_id = le32_to_cpu(psspPayload->device_id); 1958 1959 ccb = &pm8001_ha->ccb_info[tag]; 1960 t = ccb->task; 1961 pm8001_dev = ccb->device; 1962 if (event) 1963 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", event); 1964 if (unlikely(!t || !t->lldd_task || !t->dev)) 1965 return; 1966 ts = &t->task_status; 1967 pm8001_dbg(pm8001_ha, DEVIO, "port_id = %x,device_id = %x\n", 1968 port_id, dev_id); 1969 switch (event) { 1970 case IO_OVERFLOW: 1971 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n"); 1972 ts->resp = SAS_TASK_COMPLETE; 1973 ts->stat = SAS_DATA_OVERRUN; 1974 ts->residual = 0; 1975 if (pm8001_dev) 1976 atomic_dec(&pm8001_dev->running_req); 1977 break; 1978 case IO_XFER_ERROR_BREAK: 1979 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 1980 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK); 1981 return; 1982 case IO_XFER_ERROR_PHY_NOT_READY: 1983 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 1984 ts->resp = SAS_TASK_COMPLETE; 1985 ts->stat = SAS_OPEN_REJECT; 1986 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1987 break; 1988 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 1989 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 1990 ts->resp = SAS_TASK_COMPLETE; 1991 ts->stat = SAS_OPEN_REJECT; 1992 ts->open_rej_reason = SAS_OREJ_EPROTO; 1993 break; 1994 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 1995 pm8001_dbg(pm8001_ha, IO, 1996 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 1997 ts->resp = SAS_TASK_COMPLETE; 1998 ts->stat = SAS_OPEN_REJECT; 1999 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2000 break; 2001 case IO_OPEN_CNX_ERROR_BREAK: 2002 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2003 ts->resp = SAS_TASK_COMPLETE; 2004 ts->stat = SAS_OPEN_REJECT; 2005 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2006 break; 2007 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2008 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2009 ts->resp = SAS_TASK_COMPLETE; 2010 ts->stat = SAS_OPEN_REJECT; 2011 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2012 if (!t->uldd_task) 2013 pm8001_handle_event(pm8001_ha, 2014 pm8001_dev, 2015 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2016 break; 2017 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2018 pm8001_dbg(pm8001_ha, IO, 2019 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2020 ts->resp = SAS_TASK_COMPLETE; 2021 ts->stat = SAS_OPEN_REJECT; 2022 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2023 break; 2024 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2025 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2026 ts->resp = SAS_TASK_COMPLETE; 2027 ts->stat = SAS_OPEN_REJECT; 2028 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2029 break; 2030 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2031 pm8001_dbg(pm8001_ha, IO, 2032 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2033 ts->resp = SAS_TASK_COMPLETE; 2034 ts->stat = SAS_OPEN_REJECT; 2035 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2036 break; 2037 case IO_XFER_ERROR_NAK_RECEIVED: 2038 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 2039 ts->resp = SAS_TASK_COMPLETE; 2040 ts->stat = SAS_OPEN_REJECT; 2041 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2042 break; 2043 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2044 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"); 2045 ts->resp = SAS_TASK_COMPLETE; 2046 ts->stat = SAS_NAK_R_ERR; 2047 break; 2048 case IO_XFER_OPEN_RETRY_TIMEOUT: 2049 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2050 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT); 2051 return; 2052 case IO_XFER_ERROR_UNEXPECTED_PHASE: 2053 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n"); 2054 ts->resp = SAS_TASK_COMPLETE; 2055 ts->stat = SAS_DATA_OVERRUN; 2056 break; 2057 case IO_XFER_ERROR_XFER_RDY_OVERRUN: 2058 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n"); 2059 ts->resp = SAS_TASK_COMPLETE; 2060 ts->stat = SAS_DATA_OVERRUN; 2061 break; 2062 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 2063 pm8001_dbg(pm8001_ha, IO, 2064 "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"); 2065 ts->resp = SAS_TASK_COMPLETE; 2066 ts->stat = SAS_DATA_OVERRUN; 2067 break; 2068 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT: 2069 pm8001_dbg(pm8001_ha, IO, 2070 "IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"); 2071 ts->resp = SAS_TASK_COMPLETE; 2072 ts->stat = SAS_DATA_OVERRUN; 2073 break; 2074 case IO_XFER_ERROR_OFFSET_MISMATCH: 2075 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n"); 2076 ts->resp = SAS_TASK_COMPLETE; 2077 ts->stat = SAS_DATA_OVERRUN; 2078 break; 2079 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 2080 pm8001_dbg(pm8001_ha, IO, 2081 "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"); 2082 ts->resp = SAS_TASK_COMPLETE; 2083 ts->stat = SAS_DATA_OVERRUN; 2084 break; 2085 case IO_XFER_CMD_FRAME_ISSUED: 2086 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n"); 2087 return; 2088 default: 2089 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event); 2090 /* not allowed case. Therefore, return failed status */ 2091 ts->resp = SAS_TASK_COMPLETE; 2092 ts->stat = SAS_DATA_OVERRUN; 2093 break; 2094 } 2095 spin_lock_irqsave(&t->task_state_lock, flags); 2096 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2097 t->task_state_flags |= SAS_TASK_STATE_DONE; 2098 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2099 spin_unlock_irqrestore(&t->task_state_lock, flags); 2100 pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 2101 t, event, ts->resp, ts->stat); 2102 pm8001_ccb_task_free(pm8001_ha, ccb); 2103 } else { 2104 spin_unlock_irqrestore(&t->task_state_lock, flags); 2105 pm8001_ccb_task_free(pm8001_ha, ccb); 2106 mb();/* in order to force CPU ordering */ 2107 t->task_done(t); 2108 } 2109} 2110 2111/*See the comments for mpi_ssp_completion */ 2112static void 2113mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 2114{ 2115 struct sas_task *t; 2116 struct pm8001_ccb_info *ccb; 2117 u32 param; 2118 u32 status; 2119 u32 tag; 2120 int i, j; 2121 u8 sata_addr_low[4]; 2122 u32 temp_sata_addr_low; 2123 u8 sata_addr_hi[4]; 2124 u32 temp_sata_addr_hi; 2125 struct sata_completion_resp *psataPayload; 2126 struct task_status_struct *ts; 2127 struct ata_task_resp *resp ; 2128 u32 *sata_resp; 2129 struct pm8001_device *pm8001_dev; 2130 unsigned long flags; 2131 2132 psataPayload = (struct sata_completion_resp *)(piomb + 4); 2133 status = le32_to_cpu(psataPayload->status); 2134 param = le32_to_cpu(psataPayload->param); 2135 tag = le32_to_cpu(psataPayload->tag); 2136 2137 ccb = &pm8001_ha->ccb_info[tag]; 2138 t = ccb->task; 2139 pm8001_dev = ccb->device; 2140 2141 if (t) { 2142 if (t->dev && (t->dev->lldd_dev)) 2143 pm8001_dev = t->dev->lldd_dev; 2144 } else { 2145 pm8001_dbg(pm8001_ha, FAIL, "task null, freeing CCB tag %d\n", 2146 ccb->ccb_tag); 2147 pm8001_ccb_free(pm8001_ha, ccb); 2148 return; 2149 } 2150 2151 if (pm8001_dev && unlikely(!t || !t->lldd_task || !t->dev)) { 2152 pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n"); 2153 return; 2154 } 2155 2156 ts = &t->task_status; 2157 2158 if (status) 2159 pm8001_dbg(pm8001_ha, IOERR, 2160 "status:0x%x, tag:0x%x, task::0x%p\n", 2161 status, tag, t); 2162 2163 /* Print sas address of IO failed device */ 2164 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && 2165 (status != IO_UNDERFLOW)) { 2166 if (!dev_parent_is_expander(t->dev)) { 2167 for (i = 0, j = 4; j <= 7 && i <= 3; i++, j++) 2168 sata_addr_low[i] = pm8001_ha->sas_addr[j]; 2169 for (i = 0, j = 0; j <= 3 && i <= 3; i++, j++) 2170 sata_addr_hi[i] = pm8001_ha->sas_addr[j]; 2171 memcpy(&temp_sata_addr_low, sata_addr_low, 2172 sizeof(sata_addr_low)); 2173 memcpy(&temp_sata_addr_hi, sata_addr_hi, 2174 sizeof(sata_addr_hi)); 2175 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff) 2176 |((temp_sata_addr_hi << 8) & 2177 0xff0000) | 2178 ((temp_sata_addr_hi >> 8) 2179 & 0xff00) | 2180 ((temp_sata_addr_hi << 24) & 2181 0xff000000)); 2182 temp_sata_addr_low = ((((temp_sata_addr_low >> 24) 2183 & 0xff) | 2184 ((temp_sata_addr_low << 8) 2185 & 0xff0000) | 2186 ((temp_sata_addr_low >> 8) 2187 & 0xff00) | 2188 ((temp_sata_addr_low << 24) 2189 & 0xff000000)) + 2190 pm8001_dev->attached_phy + 2191 0x10); 2192 pm8001_dbg(pm8001_ha, FAIL, 2193 "SAS Address of IO Failure Drive:%08x%08x\n", 2194 temp_sata_addr_hi, 2195 temp_sata_addr_low); 2196 } else { 2197 pm8001_dbg(pm8001_ha, FAIL, 2198 "SAS Address of IO Failure Drive:%016llx\n", 2199 SAS_ADDR(t->dev->sas_addr)); 2200 } 2201 } 2202 switch (status) { 2203 case IO_SUCCESS: 2204 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n"); 2205 if (param == 0) { 2206 ts->resp = SAS_TASK_COMPLETE; 2207 ts->stat = SAS_SAM_STAT_GOOD; 2208 } else { 2209 u8 len; 2210 ts->resp = SAS_TASK_COMPLETE; 2211 ts->stat = SAS_PROTO_RESPONSE; 2212 ts->residual = param; 2213 pm8001_dbg(pm8001_ha, IO, 2214 "SAS_PROTO_RESPONSE len = %d\n", 2215 param); 2216 sata_resp = &psataPayload->sata_resp[0]; 2217 resp = (struct ata_task_resp *)ts->buf; 2218 if (t->ata_task.dma_xfer == 0 && 2219 t->data_dir == DMA_FROM_DEVICE) { 2220 len = sizeof(struct pio_setup_fis); 2221 pm8001_dbg(pm8001_ha, IO, 2222 "PIO read len = %d\n", len); 2223 } else if (t->ata_task.use_ncq && 2224 t->data_dir != DMA_NONE) { 2225 len = sizeof(struct set_dev_bits_fis); 2226 pm8001_dbg(pm8001_ha, IO, "FPDMA len = %d\n", 2227 len); 2228 } else { 2229 len = sizeof(struct dev_to_host_fis); 2230 pm8001_dbg(pm8001_ha, IO, "other len = %d\n", 2231 len); 2232 } 2233 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) { 2234 resp->frame_len = len; 2235 memcpy(&resp->ending_fis[0], sata_resp, len); 2236 ts->buf_valid_size = sizeof(*resp); 2237 } else 2238 pm8001_dbg(pm8001_ha, IO, 2239 "response too large\n"); 2240 } 2241 if (pm8001_dev) 2242 atomic_dec(&pm8001_dev->running_req); 2243 break; 2244 case IO_ABORTED: 2245 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n"); 2246 ts->resp = SAS_TASK_COMPLETE; 2247 ts->stat = SAS_ABORTED_TASK; 2248 if (pm8001_dev) 2249 atomic_dec(&pm8001_dev->running_req); 2250 break; 2251 /* following cases are to do cases */ 2252 case IO_UNDERFLOW: 2253 /* SATA Completion with error */ 2254 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW param = %d\n", param); 2255 ts->resp = SAS_TASK_COMPLETE; 2256 ts->stat = SAS_DATA_UNDERRUN; 2257 ts->residual = param; 2258 if (pm8001_dev) 2259 atomic_dec(&pm8001_dev->running_req); 2260 break; 2261 case IO_NO_DEVICE: 2262 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n"); 2263 ts->resp = SAS_TASK_UNDELIVERED; 2264 ts->stat = SAS_PHY_DOWN; 2265 if (pm8001_dev) 2266 atomic_dec(&pm8001_dev->running_req); 2267 break; 2268 case IO_XFER_ERROR_BREAK: 2269 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 2270 ts->resp = SAS_TASK_COMPLETE; 2271 ts->stat = SAS_INTERRUPTED; 2272 if (pm8001_dev) 2273 atomic_dec(&pm8001_dev->running_req); 2274 break; 2275 case IO_XFER_ERROR_PHY_NOT_READY: 2276 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 2277 ts->resp = SAS_TASK_COMPLETE; 2278 ts->stat = SAS_OPEN_REJECT; 2279 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2280 if (pm8001_dev) 2281 atomic_dec(&pm8001_dev->running_req); 2282 break; 2283 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2284 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2285 ts->resp = SAS_TASK_COMPLETE; 2286 ts->stat = SAS_OPEN_REJECT; 2287 ts->open_rej_reason = SAS_OREJ_EPROTO; 2288 if (pm8001_dev) 2289 atomic_dec(&pm8001_dev->running_req); 2290 break; 2291 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2292 pm8001_dbg(pm8001_ha, IO, 2293 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2294 ts->resp = SAS_TASK_COMPLETE; 2295 ts->stat = SAS_OPEN_REJECT; 2296 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2297 if (pm8001_dev) 2298 atomic_dec(&pm8001_dev->running_req); 2299 break; 2300 case IO_OPEN_CNX_ERROR_BREAK: 2301 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2302 ts->resp = SAS_TASK_COMPLETE; 2303 ts->stat = SAS_OPEN_REJECT; 2304 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2305 if (pm8001_dev) 2306 atomic_dec(&pm8001_dev->running_req); 2307 break; 2308 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2309 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2310 ts->resp = SAS_TASK_COMPLETE; 2311 ts->stat = SAS_DEV_NO_RESPONSE; 2312 if (!t->uldd_task) { 2313 pm8001_handle_event(pm8001_ha, 2314 pm8001_dev, 2315 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2316 ts->resp = SAS_TASK_UNDELIVERED; 2317 ts->stat = SAS_QUEUE_FULL; 2318 pm8001_ccb_task_free_done(pm8001_ha, ccb); 2319 return; 2320 } 2321 break; 2322 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2323 pm8001_dbg(pm8001_ha, IO, 2324 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2325 ts->resp = SAS_TASK_UNDELIVERED; 2326 ts->stat = SAS_OPEN_REJECT; 2327 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2328 if (!t->uldd_task) { 2329 pm8001_handle_event(pm8001_ha, 2330 pm8001_dev, 2331 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2332 ts->resp = SAS_TASK_UNDELIVERED; 2333 ts->stat = SAS_QUEUE_FULL; 2334 pm8001_ccb_task_free_done(pm8001_ha, ccb); 2335 return; 2336 } 2337 break; 2338 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2339 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2340 ts->resp = SAS_TASK_COMPLETE; 2341 ts->stat = SAS_OPEN_REJECT; 2342 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2343 if (pm8001_dev) 2344 atomic_dec(&pm8001_dev->running_req); 2345 break; 2346 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: 2347 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n"); 2348 ts->resp = SAS_TASK_COMPLETE; 2349 ts->stat = SAS_DEV_NO_RESPONSE; 2350 if (!t->uldd_task) { 2351 pm8001_handle_event(pm8001_ha, 2352 pm8001_dev, 2353 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY); 2354 ts->resp = SAS_TASK_UNDELIVERED; 2355 ts->stat = SAS_QUEUE_FULL; 2356 pm8001_ccb_task_free_done(pm8001_ha, ccb); 2357 return; 2358 } 2359 break; 2360 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2361 pm8001_dbg(pm8001_ha, IO, 2362 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2363 ts->resp = SAS_TASK_COMPLETE; 2364 ts->stat = SAS_OPEN_REJECT; 2365 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2366 if (pm8001_dev) 2367 atomic_dec(&pm8001_dev->running_req); 2368 break; 2369 case IO_XFER_ERROR_NAK_RECEIVED: 2370 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 2371 ts->resp = SAS_TASK_COMPLETE; 2372 ts->stat = SAS_NAK_R_ERR; 2373 if (pm8001_dev) 2374 atomic_dec(&pm8001_dev->running_req); 2375 break; 2376 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2377 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"); 2378 ts->resp = SAS_TASK_COMPLETE; 2379 ts->stat = SAS_NAK_R_ERR; 2380 if (pm8001_dev) 2381 atomic_dec(&pm8001_dev->running_req); 2382 break; 2383 case IO_XFER_ERROR_DMA: 2384 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n"); 2385 ts->resp = SAS_TASK_COMPLETE; 2386 ts->stat = SAS_ABORTED_TASK; 2387 if (pm8001_dev) 2388 atomic_dec(&pm8001_dev->running_req); 2389 break; 2390 case IO_XFER_ERROR_SATA_LINK_TIMEOUT: 2391 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"); 2392 ts->resp = SAS_TASK_UNDELIVERED; 2393 ts->stat = SAS_DEV_NO_RESPONSE; 2394 if (pm8001_dev) 2395 atomic_dec(&pm8001_dev->running_req); 2396 break; 2397 case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2398 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n"); 2399 ts->resp = SAS_TASK_COMPLETE; 2400 ts->stat = SAS_DATA_UNDERRUN; 2401 if (pm8001_dev) 2402 atomic_dec(&pm8001_dev->running_req); 2403 break; 2404 case IO_XFER_OPEN_RETRY_TIMEOUT: 2405 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2406 ts->resp = SAS_TASK_COMPLETE; 2407 ts->stat = SAS_OPEN_TO; 2408 if (pm8001_dev) 2409 atomic_dec(&pm8001_dev->running_req); 2410 break; 2411 case IO_PORT_IN_RESET: 2412 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n"); 2413 ts->resp = SAS_TASK_COMPLETE; 2414 ts->stat = SAS_DEV_NO_RESPONSE; 2415 if (pm8001_dev) 2416 atomic_dec(&pm8001_dev->running_req); 2417 break; 2418 case IO_DS_NON_OPERATIONAL: 2419 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n"); 2420 ts->resp = SAS_TASK_COMPLETE; 2421 ts->stat = SAS_DEV_NO_RESPONSE; 2422 if (!t->uldd_task) { 2423 pm8001_handle_event(pm8001_ha, pm8001_dev, 2424 IO_DS_NON_OPERATIONAL); 2425 ts->resp = SAS_TASK_UNDELIVERED; 2426 ts->stat = SAS_QUEUE_FULL; 2427 pm8001_ccb_task_free_done(pm8001_ha, ccb); 2428 return; 2429 } 2430 break; 2431 case IO_DS_IN_RECOVERY: 2432 pm8001_dbg(pm8001_ha, IO, " IO_DS_IN_RECOVERY\n"); 2433 ts->resp = SAS_TASK_COMPLETE; 2434 ts->stat = SAS_DEV_NO_RESPONSE; 2435 if (pm8001_dev) 2436 atomic_dec(&pm8001_dev->running_req); 2437 break; 2438 case IO_DS_IN_ERROR: 2439 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_ERROR\n"); 2440 ts->resp = SAS_TASK_COMPLETE; 2441 ts->stat = SAS_DEV_NO_RESPONSE; 2442 if (!t->uldd_task) { 2443 pm8001_handle_event(pm8001_ha, pm8001_dev, 2444 IO_DS_IN_ERROR); 2445 ts->resp = SAS_TASK_UNDELIVERED; 2446 ts->stat = SAS_QUEUE_FULL; 2447 pm8001_ccb_task_free_done(pm8001_ha, ccb); 2448 return; 2449 } 2450 break; 2451 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2452 pm8001_dbg(pm8001_ha, IO, 2453 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"); 2454 ts->resp = SAS_TASK_COMPLETE; 2455 ts->stat = SAS_OPEN_REJECT; 2456 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2457 if (pm8001_dev) 2458 atomic_dec(&pm8001_dev->running_req); 2459 break; 2460 default: 2461 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status); 2462 /* not allowed case. Therefore, return failed status */ 2463 ts->resp = SAS_TASK_COMPLETE; 2464 ts->stat = SAS_DEV_NO_RESPONSE; 2465 if (pm8001_dev) 2466 atomic_dec(&pm8001_dev->running_req); 2467 break; 2468 } 2469 spin_lock_irqsave(&t->task_state_lock, flags); 2470 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2471 t->task_state_flags |= SAS_TASK_STATE_DONE; 2472 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2473 spin_unlock_irqrestore(&t->task_state_lock, flags); 2474 pm8001_dbg(pm8001_ha, FAIL, 2475 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 2476 t, status, ts->resp, ts->stat); 2477 pm8001_ccb_task_free(pm8001_ha, ccb); 2478 } else { 2479 spin_unlock_irqrestore(&t->task_state_lock, flags); 2480 pm8001_ccb_task_free_done(pm8001_ha, ccb); 2481 } 2482} 2483 2484/*See the comments for mpi_ssp_completion */ 2485static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha, void *piomb) 2486{ 2487 struct sas_task *t; 2488 struct task_status_struct *ts; 2489 struct pm8001_ccb_info *ccb; 2490 struct pm8001_device *pm8001_dev; 2491 struct sata_event_resp *psataPayload = 2492 (struct sata_event_resp *)(piomb + 4); 2493 u32 event = le32_to_cpu(psataPayload->event); 2494 u32 tag = le32_to_cpu(psataPayload->tag); 2495 u32 port_id = le32_to_cpu(psataPayload->port_id); 2496 u32 dev_id = le32_to_cpu(psataPayload->device_id); 2497 2498 if (event) 2499 pm8001_dbg(pm8001_ha, FAIL, "SATA EVENT 0x%x\n", event); 2500 2501 /* Check if this is NCQ error */ 2502 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) { 2503 /* find device using device id */ 2504 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id); 2505 if (pm8001_dev) 2506 pm8001_handle_event(pm8001_ha, 2507 pm8001_dev, 2508 IO_XFER_ERROR_ABORTED_NCQ_MODE); 2509 return; 2510 } 2511 2512 ccb = &pm8001_ha->ccb_info[tag]; 2513 t = ccb->task; 2514 pm8001_dev = ccb->device; 2515 if (event) 2516 pm8001_dbg(pm8001_ha, FAIL, "sata IO status 0x%x\n", event); 2517 2518 if (unlikely(!t)) { 2519 pm8001_dbg(pm8001_ha, FAIL, "task null, freeing CCB tag %d\n", 2520 ccb->ccb_tag); 2521 pm8001_ccb_free(pm8001_ha, ccb); 2522 return; 2523 } 2524 2525 if (unlikely(!t->lldd_task || !t->dev)) 2526 return; 2527 2528 ts = &t->task_status; 2529 pm8001_dbg(pm8001_ha, DEVIO, 2530 "port_id:0x%x, device_id:0x%x, tag:0x%x, event:0x%x\n", 2531 port_id, dev_id, tag, event); 2532 switch (event) { 2533 case IO_OVERFLOW: 2534 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n"); 2535 ts->resp = SAS_TASK_COMPLETE; 2536 ts->stat = SAS_DATA_OVERRUN; 2537 ts->residual = 0; 2538 break; 2539 case IO_XFER_ERROR_BREAK: 2540 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 2541 ts->resp = SAS_TASK_COMPLETE; 2542 ts->stat = SAS_INTERRUPTED; 2543 break; 2544 case IO_XFER_ERROR_PHY_NOT_READY: 2545 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 2546 ts->resp = SAS_TASK_COMPLETE; 2547 ts->stat = SAS_OPEN_REJECT; 2548 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2549 break; 2550 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2551 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2552 ts->resp = SAS_TASK_COMPLETE; 2553 ts->stat = SAS_OPEN_REJECT; 2554 ts->open_rej_reason = SAS_OREJ_EPROTO; 2555 break; 2556 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2557 pm8001_dbg(pm8001_ha, IO, 2558 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2559 ts->resp = SAS_TASK_COMPLETE; 2560 ts->stat = SAS_OPEN_REJECT; 2561 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2562 break; 2563 case IO_OPEN_CNX_ERROR_BREAK: 2564 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2565 ts->resp = SAS_TASK_COMPLETE; 2566 ts->stat = SAS_OPEN_REJECT; 2567 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2568 break; 2569 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2570 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2571 ts->resp = SAS_TASK_UNDELIVERED; 2572 ts->stat = SAS_DEV_NO_RESPONSE; 2573 if (!t->uldd_task) { 2574 pm8001_handle_event(pm8001_ha, 2575 pm8001_dev, 2576 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2577 ts->resp = SAS_TASK_COMPLETE; 2578 ts->stat = SAS_QUEUE_FULL; 2579 return; 2580 } 2581 break; 2582 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2583 pm8001_dbg(pm8001_ha, IO, 2584 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2585 ts->resp = SAS_TASK_UNDELIVERED; 2586 ts->stat = SAS_OPEN_REJECT; 2587 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2588 break; 2589 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2590 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2591 ts->resp = SAS_TASK_COMPLETE; 2592 ts->stat = SAS_OPEN_REJECT; 2593 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2594 break; 2595 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2596 pm8001_dbg(pm8001_ha, IO, 2597 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2598 ts->resp = SAS_TASK_COMPLETE; 2599 ts->stat = SAS_OPEN_REJECT; 2600 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2601 break; 2602 case IO_XFER_ERROR_NAK_RECEIVED: 2603 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 2604 ts->resp = SAS_TASK_COMPLETE; 2605 ts->stat = SAS_NAK_R_ERR; 2606 break; 2607 case IO_XFER_ERROR_PEER_ABORTED: 2608 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PEER_ABORTED\n"); 2609 ts->resp = SAS_TASK_COMPLETE; 2610 ts->stat = SAS_NAK_R_ERR; 2611 break; 2612 case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2613 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n"); 2614 ts->resp = SAS_TASK_COMPLETE; 2615 ts->stat = SAS_DATA_UNDERRUN; 2616 break; 2617 case IO_XFER_OPEN_RETRY_TIMEOUT: 2618 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2619 ts->resp = SAS_TASK_COMPLETE; 2620 ts->stat = SAS_OPEN_TO; 2621 break; 2622 case IO_XFER_ERROR_UNEXPECTED_PHASE: 2623 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n"); 2624 ts->resp = SAS_TASK_COMPLETE; 2625 ts->stat = SAS_OPEN_TO; 2626 break; 2627 case IO_XFER_ERROR_XFER_RDY_OVERRUN: 2628 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n"); 2629 ts->resp = SAS_TASK_COMPLETE; 2630 ts->stat = SAS_OPEN_TO; 2631 break; 2632 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 2633 pm8001_dbg(pm8001_ha, IO, 2634 "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"); 2635 ts->resp = SAS_TASK_COMPLETE; 2636 ts->stat = SAS_OPEN_TO; 2637 break; 2638 case IO_XFER_ERROR_OFFSET_MISMATCH: 2639 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n"); 2640 ts->resp = SAS_TASK_COMPLETE; 2641 ts->stat = SAS_OPEN_TO; 2642 break; 2643 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 2644 pm8001_dbg(pm8001_ha, IO, 2645 "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"); 2646 ts->resp = SAS_TASK_COMPLETE; 2647 ts->stat = SAS_OPEN_TO; 2648 break; 2649 case IO_XFER_CMD_FRAME_ISSUED: 2650 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n"); 2651 break; 2652 case IO_XFER_PIO_SETUP_ERROR: 2653 pm8001_dbg(pm8001_ha, IO, "IO_XFER_PIO_SETUP_ERROR\n"); 2654 ts->resp = SAS_TASK_COMPLETE; 2655 ts->stat = SAS_OPEN_TO; 2656 break; 2657 default: 2658 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event); 2659 /* not allowed case. Therefore, return failed status */ 2660 ts->resp = SAS_TASK_COMPLETE; 2661 ts->stat = SAS_OPEN_TO; 2662 break; 2663 } 2664} 2665 2666/*See the comments for mpi_ssp_completion */ 2667static void 2668mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 2669{ 2670 struct sas_task *t; 2671 struct pm8001_ccb_info *ccb; 2672 unsigned long flags; 2673 u32 status; 2674 u32 tag; 2675 struct smp_completion_resp *psmpPayload; 2676 struct task_status_struct *ts; 2677 struct pm8001_device *pm8001_dev; 2678 2679 psmpPayload = (struct smp_completion_resp *)(piomb + 4); 2680 status = le32_to_cpu(psmpPayload->status); 2681 tag = le32_to_cpu(psmpPayload->tag); 2682 2683 ccb = &pm8001_ha->ccb_info[tag]; 2684 t = ccb->task; 2685 ts = &t->task_status; 2686 pm8001_dev = ccb->device; 2687 if (status) { 2688 pm8001_dbg(pm8001_ha, FAIL, "smp IO status 0x%x\n", status); 2689 pm8001_dbg(pm8001_ha, IOERR, 2690 "status:0x%x, tag:0x%x, task:0x%p\n", 2691 status, tag, t); 2692 } 2693 if (unlikely(!t || !t->lldd_task || !t->dev)) 2694 return; 2695 2696 switch (status) { 2697 case IO_SUCCESS: 2698 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n"); 2699 ts->resp = SAS_TASK_COMPLETE; 2700 ts->stat = SAS_SAM_STAT_GOOD; 2701 if (pm8001_dev) 2702 atomic_dec(&pm8001_dev->running_req); 2703 break; 2704 case IO_ABORTED: 2705 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB\n"); 2706 ts->resp = SAS_TASK_COMPLETE; 2707 ts->stat = SAS_ABORTED_TASK; 2708 if (pm8001_dev) 2709 atomic_dec(&pm8001_dev->running_req); 2710 break; 2711 case IO_OVERFLOW: 2712 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n"); 2713 ts->resp = SAS_TASK_COMPLETE; 2714 ts->stat = SAS_DATA_OVERRUN; 2715 ts->residual = 0; 2716 if (pm8001_dev) 2717 atomic_dec(&pm8001_dev->running_req); 2718 break; 2719 case IO_NO_DEVICE: 2720 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n"); 2721 ts->resp = SAS_TASK_COMPLETE; 2722 ts->stat = SAS_PHY_DOWN; 2723 break; 2724 case IO_ERROR_HW_TIMEOUT: 2725 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_HW_TIMEOUT\n"); 2726 ts->resp = SAS_TASK_COMPLETE; 2727 ts->stat = SAS_SAM_STAT_BUSY; 2728 break; 2729 case IO_XFER_ERROR_BREAK: 2730 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 2731 ts->resp = SAS_TASK_COMPLETE; 2732 ts->stat = SAS_SAM_STAT_BUSY; 2733 break; 2734 case IO_XFER_ERROR_PHY_NOT_READY: 2735 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 2736 ts->resp = SAS_TASK_COMPLETE; 2737 ts->stat = SAS_SAM_STAT_BUSY; 2738 break; 2739 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2740 pm8001_dbg(pm8001_ha, IO, 2741 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2742 ts->resp = SAS_TASK_COMPLETE; 2743 ts->stat = SAS_OPEN_REJECT; 2744 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2745 break; 2746 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2747 pm8001_dbg(pm8001_ha, IO, 2748 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2749 ts->resp = SAS_TASK_COMPLETE; 2750 ts->stat = SAS_OPEN_REJECT; 2751 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2752 break; 2753 case IO_OPEN_CNX_ERROR_BREAK: 2754 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2755 ts->resp = SAS_TASK_COMPLETE; 2756 ts->stat = SAS_OPEN_REJECT; 2757 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2758 break; 2759 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2760 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2761 ts->resp = SAS_TASK_COMPLETE; 2762 ts->stat = SAS_OPEN_REJECT; 2763 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2764 pm8001_handle_event(pm8001_ha, 2765 pm8001_dev, 2766 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2767 break; 2768 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2769 pm8001_dbg(pm8001_ha, IO, 2770 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2771 ts->resp = SAS_TASK_COMPLETE; 2772 ts->stat = SAS_OPEN_REJECT; 2773 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2774 break; 2775 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2776 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2777 ts->resp = SAS_TASK_COMPLETE; 2778 ts->stat = SAS_OPEN_REJECT; 2779 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2780 break; 2781 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2782 pm8001_dbg(pm8001_ha, IO, 2783 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2784 ts->resp = SAS_TASK_COMPLETE; 2785 ts->stat = SAS_OPEN_REJECT; 2786 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2787 break; 2788 case IO_XFER_ERROR_RX_FRAME: 2789 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_RX_FRAME\n"); 2790 ts->resp = SAS_TASK_COMPLETE; 2791 ts->stat = SAS_DEV_NO_RESPONSE; 2792 break; 2793 case IO_XFER_OPEN_RETRY_TIMEOUT: 2794 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2795 ts->resp = SAS_TASK_COMPLETE; 2796 ts->stat = SAS_OPEN_REJECT; 2797 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2798 break; 2799 case IO_ERROR_INTERNAL_SMP_RESOURCE: 2800 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_INTERNAL_SMP_RESOURCE\n"); 2801 ts->resp = SAS_TASK_COMPLETE; 2802 ts->stat = SAS_QUEUE_FULL; 2803 break; 2804 case IO_PORT_IN_RESET: 2805 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n"); 2806 ts->resp = SAS_TASK_COMPLETE; 2807 ts->stat = SAS_OPEN_REJECT; 2808 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2809 break; 2810 case IO_DS_NON_OPERATIONAL: 2811 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n"); 2812 ts->resp = SAS_TASK_COMPLETE; 2813 ts->stat = SAS_DEV_NO_RESPONSE; 2814 break; 2815 case IO_DS_IN_RECOVERY: 2816 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n"); 2817 ts->resp = SAS_TASK_COMPLETE; 2818 ts->stat = SAS_OPEN_REJECT; 2819 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2820 break; 2821 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2822 pm8001_dbg(pm8001_ha, IO, 2823 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"); 2824 ts->resp = SAS_TASK_COMPLETE; 2825 ts->stat = SAS_OPEN_REJECT; 2826 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2827 break; 2828 default: 2829 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status); 2830 ts->resp = SAS_TASK_COMPLETE; 2831 ts->stat = SAS_DEV_NO_RESPONSE; 2832 /* not allowed case. Therefore, return failed status */ 2833 break; 2834 } 2835 spin_lock_irqsave(&t->task_state_lock, flags); 2836 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2837 t->task_state_flags |= SAS_TASK_STATE_DONE; 2838 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2839 spin_unlock_irqrestore(&t->task_state_lock, flags); 2840 pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 2841 t, status, ts->resp, ts->stat); 2842 pm8001_ccb_task_free(pm8001_ha, ccb); 2843 } else { 2844 spin_unlock_irqrestore(&t->task_state_lock, flags); 2845 pm8001_ccb_task_free_done(pm8001_ha, ccb); 2846 } 2847} 2848 2849void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha, 2850 void *piomb) 2851{ 2852 struct set_dev_state_resp *pPayload = 2853 (struct set_dev_state_resp *)(piomb + 4); 2854 u32 tag = le32_to_cpu(pPayload->tag); 2855 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; 2856 struct pm8001_device *pm8001_dev = ccb->device; 2857 u32 status = le32_to_cpu(pPayload->status); 2858 u32 device_id = le32_to_cpu(pPayload->device_id); 2859 u8 pds = le32_to_cpu(pPayload->pds_nds) & PDS_BITS; 2860 u8 nds = le32_to_cpu(pPayload->pds_nds) & NDS_BITS; 2861 2862 pm8001_dbg(pm8001_ha, MSG, 2863 "Set device id = 0x%x state from 0x%x to 0x%x status = 0x%x!\n", 2864 device_id, pds, nds, status); 2865 complete(pm8001_dev->setds_completion); 2866 pm8001_ccb_free(pm8001_ha, ccb); 2867} 2868 2869void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 2870{ 2871 struct get_nvm_data_resp *pPayload = 2872 (struct get_nvm_data_resp *)(piomb + 4); 2873 u32 tag = le32_to_cpu(pPayload->tag); 2874 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; 2875 u32 dlen_status = le32_to_cpu(pPayload->dlen_status); 2876 2877 complete(pm8001_ha->nvmd_completion); 2878 pm8001_dbg(pm8001_ha, MSG, "Set nvm data complete!\n"); 2879 if ((dlen_status & NVMD_STAT) != 0) { 2880 pm8001_dbg(pm8001_ha, FAIL, "Set nvm data error %x\n", 2881 dlen_status); 2882 } 2883 pm8001_ccb_free(pm8001_ha, ccb); 2884} 2885 2886void 2887pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 2888{ 2889 struct fw_control_ex *fw_control_context; 2890 struct get_nvm_data_resp *pPayload = 2891 (struct get_nvm_data_resp *)(piomb + 4); 2892 u32 tag = le32_to_cpu(pPayload->tag); 2893 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; 2894 u32 dlen_status = le32_to_cpu(pPayload->dlen_status); 2895 u32 ir_tds_bn_dps_das_nvm = 2896 le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm); 2897 void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr; 2898 fw_control_context = ccb->fw_control_context; 2899 2900 pm8001_dbg(pm8001_ha, MSG, "Get nvm data complete!\n"); 2901 if ((dlen_status & NVMD_STAT) != 0) { 2902 pm8001_dbg(pm8001_ha, FAIL, "Get nvm data error %x\n", 2903 dlen_status); 2904 complete(pm8001_ha->nvmd_completion); 2905 /* We should free tag during failure also, the tag is not being 2906 * freed by requesting path anywhere. 2907 */ 2908 pm8001_ccb_free(pm8001_ha, ccb); 2909 return; 2910 } 2911 if (ir_tds_bn_dps_das_nvm & IPMode) { 2912 /* indirect mode - IR bit set */ 2913 pm8001_dbg(pm8001_ha, MSG, "Get NVMD success, IR=1\n"); 2914 if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) { 2915 if (ir_tds_bn_dps_das_nvm == 0x80a80200) { 2916 memcpy(pm8001_ha->sas_addr, 2917 ((u8 *)virt_addr + 4), 2918 SAS_ADDR_SIZE); 2919 pm8001_dbg(pm8001_ha, MSG, "Get SAS address from VPD successfully!\n"); 2920 } 2921 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM) 2922 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) || 2923 ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) { 2924 ; 2925 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP) 2926 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) { 2927 ; 2928 } else { 2929 /* Should not be happened*/ 2930 pm8001_dbg(pm8001_ha, MSG, 2931 "(IR=1)Wrong Device type 0x%x\n", 2932 ir_tds_bn_dps_das_nvm); 2933 } 2934 } else /* direct mode */{ 2935 pm8001_dbg(pm8001_ha, MSG, 2936 "Get NVMD success, IR=0, dataLen=%d\n", 2937 (dlen_status & NVMD_LEN) >> 24); 2938 } 2939 /* Though fw_control_context is freed below, usrAddr still needs 2940 * to be updated as this holds the response to the request function 2941 */ 2942 memcpy(fw_control_context->usrAddr, 2943 pm8001_ha->memoryMap.region[NVMD].virt_ptr, 2944 fw_control_context->len); 2945 kfree(ccb->fw_control_context); 2946 /* To avoid race condition, complete should be 2947 * called after the message is copied to 2948 * fw_control_context->usrAddr 2949 */ 2950 complete(pm8001_ha->nvmd_completion); 2951 pm8001_dbg(pm8001_ha, MSG, "Get nvmd data complete!\n"); 2952 pm8001_ccb_free(pm8001_ha, ccb); 2953} 2954 2955int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb) 2956{ 2957 u32 tag; 2958 struct local_phy_ctl_resp *pPayload = 2959 (struct local_phy_ctl_resp *)(piomb + 4); 2960 u32 status = le32_to_cpu(pPayload->status); 2961 u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS; 2962 u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS; 2963 tag = le32_to_cpu(pPayload->tag); 2964 if (status != 0) { 2965 pm8001_dbg(pm8001_ha, MSG, 2966 "%x phy execute %x phy op failed!\n", 2967 phy_id, phy_op); 2968 } else { 2969 pm8001_dbg(pm8001_ha, MSG, 2970 "%x phy execute %x phy op success!\n", 2971 phy_id, phy_op); 2972 pm8001_ha->phy[phy_id].reset_success = true; 2973 } 2974 if (pm8001_ha->phy[phy_id].enable_completion) { 2975 complete(pm8001_ha->phy[phy_id].enable_completion); 2976 pm8001_ha->phy[phy_id].enable_completion = NULL; 2977 } 2978 pm8001_tag_free(pm8001_ha, tag); 2979 return 0; 2980} 2981 2982/** 2983 * pm8001_bytes_dmaed - one of the interface function communication with libsas 2984 * @pm8001_ha: our hba card information 2985 * @i: which phy that received the event. 2986 * 2987 * when HBA driver received the identify done event or initiate FIS received 2988 * event(for SATA), it will invoke this function to notify the sas layer that 2989 * the sas toplogy has formed, please discover the whole sas domain, 2990 * while receive a broadcast(change) primitive just tell the sas 2991 * layer to discover the changed domain rather than the whole domain. 2992 */ 2993void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i) 2994{ 2995 struct pm8001_phy *phy = &pm8001_ha->phy[i]; 2996 struct asd_sas_phy *sas_phy = &phy->sas_phy; 2997 if (!phy->phy_attached) 2998 return; 2999 3000 if (phy->phy_type & PORT_TYPE_SAS) { 3001 struct sas_identify_frame *id; 3002 id = (struct sas_identify_frame *)phy->frame_rcvd; 3003 id->dev_type = phy->identify.device_type; 3004 id->initiator_bits = SAS_PROTOCOL_ALL; 3005 id->target_bits = phy->identify.target_port_protocols; 3006 } else if (phy->phy_type & PORT_TYPE_SATA) { 3007 /*Nothing*/ 3008 } 3009 pm8001_dbg(pm8001_ha, MSG, "phy %d byte dmaded.\n", i); 3010 3011 sas_phy->frame_rcvd_size = phy->frame_rcvd_size; 3012 sas_notify_port_event(sas_phy, PORTE_BYTES_DMAED, GFP_ATOMIC); 3013} 3014 3015/* Get the link rate speed */ 3016void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate) 3017{ 3018 struct sas_phy *sas_phy = phy->sas_phy.phy; 3019 3020 switch (link_rate) { 3021 case PHY_SPEED_120: 3022 phy->sas_phy.linkrate = SAS_LINK_RATE_12_0_GBPS; 3023 break; 3024 case PHY_SPEED_60: 3025 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS; 3026 break; 3027 case PHY_SPEED_30: 3028 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS; 3029 break; 3030 case PHY_SPEED_15: 3031 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS; 3032 break; 3033 } 3034 sas_phy->negotiated_linkrate = phy->sas_phy.linkrate; 3035 sas_phy->maximum_linkrate_hw = phy->maximum_linkrate; 3036 sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS; 3037 sas_phy->maximum_linkrate = phy->maximum_linkrate; 3038 sas_phy->minimum_linkrate = phy->minimum_linkrate; 3039} 3040 3041/** 3042 * pm8001_get_attached_sas_addr - extract/generate attached SAS address 3043 * @phy: pointer to asd_phy 3044 * @sas_addr: pointer to buffer where the SAS address is to be written 3045 * 3046 * This function extracts the SAS address from an IDENTIFY frame 3047 * received. If OOB is SATA, then a SAS address is generated from the 3048 * HA tables. 3049 * 3050 * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame 3051 * buffer. 3052 */ 3053void pm8001_get_attached_sas_addr(struct pm8001_phy *phy, 3054 u8 *sas_addr) 3055{ 3056 if (phy->sas_phy.frame_rcvd[0] == 0x34 3057 && phy->sas_phy.oob_mode == SATA_OOB_MODE) { 3058 struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha; 3059 /* FIS device-to-host */ 3060 u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr); 3061 addr += phy->sas_phy.id; 3062 *(__be64 *)sas_addr = cpu_to_be64(addr); 3063 } else { 3064 struct sas_identify_frame *idframe = 3065 (void *) phy->sas_phy.frame_rcvd; 3066 memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE); 3067 } 3068} 3069 3070/** 3071 * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW. 3072 * @pm8001_ha: our hba card information 3073 * @Qnum: the outbound queue message number. 3074 * @SEA: source of event to ack 3075 * @port_id: port id. 3076 * @phyId: phy id. 3077 * @param0: parameter 0. 3078 * @param1: parameter 1. 3079 */ 3080static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha, 3081 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1) 3082{ 3083 struct hw_event_ack_req payload; 3084 u32 opc = OPC_INB_SAS_HW_EVENT_ACK; 3085 3086 memset((u8 *)&payload, 0, sizeof(payload)); 3087 payload.tag = cpu_to_le32(1); 3088 payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) | 3089 ((phyId & 0x0F) << 4) | (port_id & 0x0F)); 3090 payload.param0 = cpu_to_le32(param0); 3091 payload.param1 = cpu_to_le32(param1); 3092 3093 pm8001_mpi_build_cmd(pm8001_ha, Qnum, opc, &payload, sizeof(payload), 0); 3094} 3095 3096static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 3097 u32 phyId, u32 phy_op); 3098 3099/** 3100 * hw_event_sas_phy_up -FW tells me a SAS phy up event. 3101 * @pm8001_ha: our hba card information 3102 * @piomb: IO message buffer 3103 */ 3104static void 3105hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 3106{ 3107 struct hw_event_resp *pPayload = 3108 (struct hw_event_resp *)(piomb + 4); 3109 u32 lr_evt_status_phyid_portid = 3110 le32_to_cpu(pPayload->lr_evt_status_phyid_portid); 3111 u8 link_rate = 3112 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28); 3113 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); 3114 u8 phy_id = 3115 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); 3116 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate); 3117 u8 portstate = (u8)(npip_portstate & 0x0000000F); 3118 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3119 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3120 unsigned long flags; 3121 u8 deviceType = pPayload->sas_identify.dev_type; 3122 phy->port = port; 3123 port->port_id = port_id; 3124 port->port_state = portstate; 3125 phy->phy_state = PHY_STATE_LINK_UP_SPC; 3126 pm8001_dbg(pm8001_ha, MSG, 3127 "HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n", 3128 port_id, phy_id); 3129 3130 switch (deviceType) { 3131 case SAS_PHY_UNUSED: 3132 pm8001_dbg(pm8001_ha, MSG, "device type no device.\n"); 3133 break; 3134 case SAS_END_DEVICE: 3135 pm8001_dbg(pm8001_ha, MSG, "end device.\n"); 3136 pm8001_chip_phy_ctl_req(pm8001_ha, phy_id, 3137 PHY_NOTIFY_ENABLE_SPINUP); 3138 port->port_attached = 1; 3139 pm8001_get_lrate_mode(phy, link_rate); 3140 break; 3141 case SAS_EDGE_EXPANDER_DEVICE: 3142 pm8001_dbg(pm8001_ha, MSG, "expander device.\n"); 3143 port->port_attached = 1; 3144 pm8001_get_lrate_mode(phy, link_rate); 3145 break; 3146 case SAS_FANOUT_EXPANDER_DEVICE: 3147 pm8001_dbg(pm8001_ha, MSG, "fanout expander device.\n"); 3148 port->port_attached = 1; 3149 pm8001_get_lrate_mode(phy, link_rate); 3150 break; 3151 default: 3152 pm8001_dbg(pm8001_ha, DEVIO, "unknown device type(%x)\n", 3153 deviceType); 3154 break; 3155 } 3156 phy->phy_type |= PORT_TYPE_SAS; 3157 phy->identify.device_type = deviceType; 3158 phy->phy_attached = 1; 3159 if (phy->identify.device_type == SAS_END_DEVICE) 3160 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP; 3161 else if (phy->identify.device_type != SAS_PHY_UNUSED) 3162 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP; 3163 phy->sas_phy.oob_mode = SAS_OOB_MODE; 3164 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC); 3165 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 3166 memcpy(phy->frame_rcvd, &pPayload->sas_identify, 3167 sizeof(struct sas_identify_frame)-4); 3168 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4; 3169 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 3170 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 3171 if (pm8001_ha->flags == PM8001F_RUN_TIME) 3172 mdelay(200);/*delay a moment to wait disk to spinup*/ 3173 pm8001_bytes_dmaed(pm8001_ha, phy_id); 3174} 3175 3176/** 3177 * hw_event_sata_phy_up -FW tells me a SATA phy up event. 3178 * @pm8001_ha: our hba card information 3179 * @piomb: IO message buffer 3180 */ 3181static void 3182hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 3183{ 3184 struct hw_event_resp *pPayload = 3185 (struct hw_event_resp *)(piomb + 4); 3186 u32 lr_evt_status_phyid_portid = 3187 le32_to_cpu(pPayload->lr_evt_status_phyid_portid); 3188 u8 link_rate = 3189 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28); 3190 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); 3191 u8 phy_id = 3192 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); 3193 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate); 3194 u8 portstate = (u8)(npip_portstate & 0x0000000F); 3195 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3196 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3197 unsigned long flags; 3198 pm8001_dbg(pm8001_ha, DEVIO, "HW_EVENT_SATA_PHY_UP port id = %d, phy id = %d\n", 3199 port_id, phy_id); 3200 phy->port = port; 3201 port->port_id = port_id; 3202 port->port_state = portstate; 3203 phy->phy_state = PHY_STATE_LINK_UP_SPC; 3204 port->port_attached = 1; 3205 pm8001_get_lrate_mode(phy, link_rate); 3206 phy->phy_type |= PORT_TYPE_SATA; 3207 phy->phy_attached = 1; 3208 phy->sas_phy.oob_mode = SATA_OOB_MODE; 3209 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC); 3210 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 3211 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4), 3212 sizeof(struct dev_to_host_fis)); 3213 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 3214 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 3215 phy->identify.device_type = SAS_SATA_DEV; 3216 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 3217 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 3218 pm8001_bytes_dmaed(pm8001_ha, phy_id); 3219} 3220 3221/** 3222 * hw_event_phy_down -we should notify the libsas the phy is down. 3223 * @pm8001_ha: our hba card information 3224 * @piomb: IO message buffer 3225 */ 3226static void 3227hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb) 3228{ 3229 struct hw_event_resp *pPayload = 3230 (struct hw_event_resp *)(piomb + 4); 3231 u32 lr_evt_status_phyid_portid = 3232 le32_to_cpu(pPayload->lr_evt_status_phyid_portid); 3233 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); 3234 u8 phy_id = 3235 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); 3236 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate); 3237 u8 portstate = (u8)(npip_portstate & 0x0000000F); 3238 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3239 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3240 port->port_state = portstate; 3241 phy->phy_type = 0; 3242 phy->identify.device_type = 0; 3243 phy->phy_attached = 0; 3244 memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE); 3245 switch (portstate) { 3246 case PORT_VALID: 3247 break; 3248 case PORT_INVALID: 3249 pm8001_dbg(pm8001_ha, MSG, " PortInvalid portID %d\n", 3250 port_id); 3251 pm8001_dbg(pm8001_ha, MSG, 3252 " Last phy Down and port invalid\n"); 3253 port->port_attached = 0; 3254 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3255 port_id, phy_id, 0, 0); 3256 break; 3257 case PORT_IN_RESET: 3258 pm8001_dbg(pm8001_ha, MSG, " Port In Reset portID %d\n", 3259 port_id); 3260 break; 3261 case PORT_NOT_ESTABLISHED: 3262 pm8001_dbg(pm8001_ha, MSG, 3263 " phy Down and PORT_NOT_ESTABLISHED\n"); 3264 port->port_attached = 0; 3265 break; 3266 case PORT_LOSTCOMM: 3267 pm8001_dbg(pm8001_ha, MSG, " phy Down and PORT_LOSTCOMM\n"); 3268 pm8001_dbg(pm8001_ha, MSG, 3269 " Last phy Down and port invalid\n"); 3270 port->port_attached = 0; 3271 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3272 port_id, phy_id, 0, 0); 3273 break; 3274 default: 3275 port->port_attached = 0; 3276 pm8001_dbg(pm8001_ha, DEVIO, " phy Down and(default) = %x\n", 3277 portstate); 3278 break; 3279 3280 } 3281} 3282 3283/** 3284 * pm8001_mpi_reg_resp -process register device ID response. 3285 * @pm8001_ha: our hba card information 3286 * @piomb: IO message buffer 3287 * 3288 * when sas layer find a device it will notify LLDD, then the driver register 3289 * the domain device to FW, this event is the return device ID which the FW 3290 * has assigned, from now, inter-communication with FW is no longer using the 3291 * SAS address, use device ID which FW assigned. 3292 */ 3293int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3294{ 3295 u32 status; 3296 u32 device_id; 3297 u32 htag; 3298 struct pm8001_ccb_info *ccb; 3299 struct pm8001_device *pm8001_dev; 3300 struct dev_reg_resp *registerRespPayload = 3301 (struct dev_reg_resp *)(piomb + 4); 3302 3303 htag = le32_to_cpu(registerRespPayload->tag); 3304 ccb = &pm8001_ha->ccb_info[htag]; 3305 pm8001_dev = ccb->device; 3306 status = le32_to_cpu(registerRespPayload->status); 3307 device_id = le32_to_cpu(registerRespPayload->device_id); 3308 pm8001_dbg(pm8001_ha, INIT, 3309 "register device status %d phy_id 0x%x device_id %d\n", 3310 status, pm8001_dev->attached_phy, device_id); 3311 switch (status) { 3312 case DEVREG_SUCCESS: 3313 pm8001_dbg(pm8001_ha, MSG, "DEVREG_SUCCESS\n"); 3314 pm8001_dev->device_id = device_id; 3315 break; 3316 case DEVREG_FAILURE_OUT_OF_RESOURCE: 3317 pm8001_dbg(pm8001_ha, MSG, "DEVREG_FAILURE_OUT_OF_RESOURCE\n"); 3318 break; 3319 case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED: 3320 pm8001_dbg(pm8001_ha, MSG, 3321 "DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n"); 3322 break; 3323 case DEVREG_FAILURE_INVALID_PHY_ID: 3324 pm8001_dbg(pm8001_ha, MSG, "DEVREG_FAILURE_INVALID_PHY_ID\n"); 3325 break; 3326 case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED: 3327 pm8001_dbg(pm8001_ha, MSG, 3328 "DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n"); 3329 break; 3330 case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE: 3331 pm8001_dbg(pm8001_ha, MSG, 3332 "DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n"); 3333 break; 3334 case DEVREG_FAILURE_PORT_NOT_VALID_STATE: 3335 pm8001_dbg(pm8001_ha, MSG, 3336 "DEVREG_FAILURE_PORT_NOT_VALID_STATE\n"); 3337 break; 3338 case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID: 3339 pm8001_dbg(pm8001_ha, MSG, 3340 "DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n"); 3341 break; 3342 default: 3343 pm8001_dbg(pm8001_ha, MSG, 3344 "DEVREG_FAILURE_DEVICE_TYPE_NOT_SUPPORTED\n"); 3345 break; 3346 } 3347 complete(pm8001_dev->dcompletion); 3348 pm8001_ccb_free(pm8001_ha, ccb); 3349 return 0; 3350} 3351 3352int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3353{ 3354 u32 status; 3355 u32 device_id; 3356 struct dev_reg_resp *registerRespPayload = 3357 (struct dev_reg_resp *)(piomb + 4); 3358 3359 status = le32_to_cpu(registerRespPayload->status); 3360 device_id = le32_to_cpu(registerRespPayload->device_id); 3361 if (status != 0) 3362 pm8001_dbg(pm8001_ha, MSG, 3363 " deregister device failed ,status = %x, device_id = %x\n", 3364 status, device_id); 3365 return 0; 3366} 3367 3368/** 3369 * pm8001_mpi_fw_flash_update_resp - Response from FW for flash update command. 3370 * @pm8001_ha: our hba card information 3371 * @piomb: IO message buffer 3372 */ 3373int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha, 3374 void *piomb) 3375{ 3376 u32 status; 3377 struct fw_flash_Update_resp *ppayload = 3378 (struct fw_flash_Update_resp *)(piomb + 4); 3379 u32 tag = le32_to_cpu(ppayload->tag); 3380 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; 3381 3382 status = le32_to_cpu(ppayload->status); 3383 switch (status) { 3384 case FLASH_UPDATE_COMPLETE_PENDING_REBOOT: 3385 pm8001_dbg(pm8001_ha, MSG, 3386 ": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n"); 3387 break; 3388 case FLASH_UPDATE_IN_PROGRESS: 3389 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_IN_PROGRESS\n"); 3390 break; 3391 case FLASH_UPDATE_HDR_ERR: 3392 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_HDR_ERR\n"); 3393 break; 3394 case FLASH_UPDATE_OFFSET_ERR: 3395 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_OFFSET_ERR\n"); 3396 break; 3397 case FLASH_UPDATE_CRC_ERR: 3398 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_CRC_ERR\n"); 3399 break; 3400 case FLASH_UPDATE_LENGTH_ERR: 3401 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_LENGTH_ERR\n"); 3402 break; 3403 case FLASH_UPDATE_HW_ERR: 3404 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_HW_ERR\n"); 3405 break; 3406 case FLASH_UPDATE_DNLD_NOT_SUPPORTED: 3407 pm8001_dbg(pm8001_ha, MSG, 3408 ": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n"); 3409 break; 3410 case FLASH_UPDATE_DISABLED: 3411 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_DISABLED\n"); 3412 break; 3413 default: 3414 pm8001_dbg(pm8001_ha, DEVIO, "No matched status = %d\n", 3415 status); 3416 break; 3417 } 3418 kfree(ccb->fw_control_context); 3419 pm8001_ccb_free(pm8001_ha, ccb); 3420 complete(pm8001_ha->nvmd_completion); 3421 return 0; 3422} 3423 3424int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha, void *piomb) 3425{ 3426 u32 status; 3427 int i; 3428 struct general_event_resp *pPayload = 3429 (struct general_event_resp *)(piomb + 4); 3430 status = le32_to_cpu(pPayload->status); 3431 pm8001_dbg(pm8001_ha, MSG, " status = 0x%x\n", status); 3432 for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++) 3433 pm8001_dbg(pm8001_ha, MSG, "inb_IOMB_payload[0x%x] 0x%x,\n", 3434 i, 3435 pPayload->inb_IOMB_payload[i]); 3436 return 0; 3437} 3438 3439int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3440{ 3441 struct sas_task *t; 3442 struct pm8001_ccb_info *ccb; 3443 unsigned long flags; 3444 u32 status ; 3445 u32 tag, scp; 3446 struct task_status_struct *ts; 3447 struct pm8001_device *pm8001_dev; 3448 3449 struct task_abort_resp *pPayload = 3450 (struct task_abort_resp *)(piomb + 4); 3451 3452 status = le32_to_cpu(pPayload->status); 3453 tag = le32_to_cpu(pPayload->tag); 3454 3455 scp = le32_to_cpu(pPayload->scp); 3456 ccb = &pm8001_ha->ccb_info[tag]; 3457 t = ccb->task; 3458 pm8001_dev = ccb->device; /* retrieve device */ 3459 3460 if (!t) { 3461 pm8001_dbg(pm8001_ha, FAIL, " TASK NULL. RETURNING !!!\n"); 3462 return -1; 3463 } 3464 3465 if (t->task_proto == SAS_PROTOCOL_INTERNAL_ABORT) 3466 atomic_dec(&pm8001_dev->running_req); 3467 3468 ts = &t->task_status; 3469 if (status != 0) 3470 pm8001_dbg(pm8001_ha, FAIL, "task abort failed status 0x%x ,tag = 0x%x, scp= 0x%x\n", 3471 status, tag, scp); 3472 switch (status) { 3473 case IO_SUCCESS: 3474 pm8001_dbg(pm8001_ha, FAIL, "ABORT IO_SUCCESS for tag %#x\n", 3475 tag); 3476 ts->resp = SAS_TASK_COMPLETE; 3477 ts->stat = SAS_SAM_STAT_GOOD; 3478 break; 3479 case IO_NOT_VALID: 3480 pm8001_dbg(pm8001_ha, FAIL, "IO_NOT_VALID for tag %#x\n", tag); 3481 ts->resp = TMF_RESP_FUNC_FAILED; 3482 break; 3483 } 3484 spin_lock_irqsave(&t->task_state_lock, flags); 3485 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 3486 t->task_state_flags |= SAS_TASK_STATE_DONE; 3487 spin_unlock_irqrestore(&t->task_state_lock, flags); 3488 pm8001_ccb_task_free(pm8001_ha, ccb); 3489 mb(); 3490 3491 t->task_done(t); 3492 3493 return 0; 3494} 3495 3496/** 3497 * mpi_hw_event -The hw event has come. 3498 * @pm8001_ha: our hba card information 3499 * @piomb: IO message buffer 3500 */ 3501static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb) 3502{ 3503 unsigned long flags; 3504 struct hw_event_resp *pPayload = 3505 (struct hw_event_resp *)(piomb + 4); 3506 u32 lr_evt_status_phyid_portid = 3507 le32_to_cpu(pPayload->lr_evt_status_phyid_portid); 3508 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); 3509 u8 phy_id = 3510 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); 3511 u16 eventType = 3512 (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8); 3513 u8 status = 3514 (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24); 3515 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3516 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3517 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id]; 3518 pm8001_dbg(pm8001_ha, DEVIO, 3519 "SPC HW event for portid:%d, phyid:%d, event:%x, status:%x\n", 3520 port_id, phy_id, eventType, status); 3521 switch (eventType) { 3522 case HW_EVENT_PHY_START_STATUS: 3523 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS status = %x\n", 3524 status); 3525 if (status == 0) 3526 phy->phy_state = 1; 3527 3528 if (pm8001_ha->flags == PM8001F_RUN_TIME && 3529 phy->enable_completion != NULL) { 3530 complete(phy->enable_completion); 3531 phy->enable_completion = NULL; 3532 } 3533 break; 3534 case HW_EVENT_SAS_PHY_UP: 3535 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS\n"); 3536 hw_event_sas_phy_up(pm8001_ha, piomb); 3537 break; 3538 case HW_EVENT_SATA_PHY_UP: 3539 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_PHY_UP\n"); 3540 hw_event_sata_phy_up(pm8001_ha, piomb); 3541 break; 3542 case HW_EVENT_PHY_STOP_STATUS: 3543 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_STOP_STATUS status = %x\n", 3544 status); 3545 if (status == 0) 3546 phy->phy_state = 0; 3547 break; 3548 case HW_EVENT_SATA_SPINUP_HOLD: 3549 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_SPINUP_HOLD\n"); 3550 sas_notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD, 3551 GFP_ATOMIC); 3552 break; 3553 case HW_EVENT_PHY_DOWN: 3554 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_DOWN\n"); 3555 sas_notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL, 3556 GFP_ATOMIC); 3557 phy->phy_attached = 0; 3558 phy->phy_state = 0; 3559 hw_event_phy_down(pm8001_ha, piomb); 3560 break; 3561 case HW_EVENT_PORT_INVALID: 3562 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_INVALID\n"); 3563 sas_phy_disconnected(sas_phy); 3564 phy->phy_attached = 0; 3565 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3566 GFP_ATOMIC); 3567 break; 3568 /* the broadcast change primitive received, tell the LIBSAS this event 3569 to revalidate the sas domain*/ 3570 case HW_EVENT_BROADCAST_CHANGE: 3571 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_CHANGE\n"); 3572 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE, 3573 port_id, phy_id, 1, 0); 3574 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3575 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE; 3576 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3577 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD, 3578 GFP_ATOMIC); 3579 break; 3580 case HW_EVENT_PHY_ERROR: 3581 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_ERROR\n"); 3582 sas_phy_disconnected(&phy->sas_phy); 3583 phy->phy_attached = 0; 3584 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR, GFP_ATOMIC); 3585 break; 3586 case HW_EVENT_BROADCAST_EXP: 3587 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_EXP\n"); 3588 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3589 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP; 3590 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3591 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD, 3592 GFP_ATOMIC); 3593 break; 3594 case HW_EVENT_LINK_ERR_INVALID_DWORD: 3595 pm8001_dbg(pm8001_ha, MSG, 3596 "HW_EVENT_LINK_ERR_INVALID_DWORD\n"); 3597 pm8001_hw_event_ack_req(pm8001_ha, 0, 3598 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0); 3599 sas_phy_disconnected(sas_phy); 3600 phy->phy_attached = 0; 3601 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3602 GFP_ATOMIC); 3603 break; 3604 case HW_EVENT_LINK_ERR_DISPARITY_ERROR: 3605 pm8001_dbg(pm8001_ha, MSG, 3606 "HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"); 3607 pm8001_hw_event_ack_req(pm8001_ha, 0, 3608 HW_EVENT_LINK_ERR_DISPARITY_ERROR, 3609 port_id, phy_id, 0, 0); 3610 sas_phy_disconnected(sas_phy); 3611 phy->phy_attached = 0; 3612 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3613 GFP_ATOMIC); 3614 break; 3615 case HW_EVENT_LINK_ERR_CODE_VIOLATION: 3616 pm8001_dbg(pm8001_ha, MSG, 3617 "HW_EVENT_LINK_ERR_CODE_VIOLATION\n"); 3618 pm8001_hw_event_ack_req(pm8001_ha, 0, 3619 HW_EVENT_LINK_ERR_CODE_VIOLATION, 3620 port_id, phy_id, 0, 0); 3621 sas_phy_disconnected(sas_phy); 3622 phy->phy_attached = 0; 3623 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3624 GFP_ATOMIC); 3625 break; 3626 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH: 3627 pm8001_dbg(pm8001_ha, MSG, 3628 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"); 3629 pm8001_hw_event_ack_req(pm8001_ha, 0, 3630 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH, 3631 port_id, phy_id, 0, 0); 3632 sas_phy_disconnected(sas_phy); 3633 phy->phy_attached = 0; 3634 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3635 GFP_ATOMIC); 3636 break; 3637 case HW_EVENT_MALFUNCTION: 3638 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_MALFUNCTION\n"); 3639 break; 3640 case HW_EVENT_BROADCAST_SES: 3641 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_SES\n"); 3642 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3643 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES; 3644 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3645 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD, 3646 GFP_ATOMIC); 3647 break; 3648 case HW_EVENT_INBOUND_CRC_ERROR: 3649 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_INBOUND_CRC_ERROR\n"); 3650 pm8001_hw_event_ack_req(pm8001_ha, 0, 3651 HW_EVENT_INBOUND_CRC_ERROR, 3652 port_id, phy_id, 0, 0); 3653 break; 3654 case HW_EVENT_HARD_RESET_RECEIVED: 3655 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_HARD_RESET_RECEIVED\n"); 3656 sas_notify_port_event(sas_phy, PORTE_HARD_RESET, GFP_ATOMIC); 3657 break; 3658 case HW_EVENT_ID_FRAME_TIMEOUT: 3659 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_ID_FRAME_TIMEOUT\n"); 3660 sas_phy_disconnected(sas_phy); 3661 phy->phy_attached = 0; 3662 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3663 GFP_ATOMIC); 3664 break; 3665 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED: 3666 pm8001_dbg(pm8001_ha, MSG, 3667 "HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"); 3668 pm8001_hw_event_ack_req(pm8001_ha, 0, 3669 HW_EVENT_LINK_ERR_PHY_RESET_FAILED, 3670 port_id, phy_id, 0, 0); 3671 sas_phy_disconnected(sas_phy); 3672 phy->phy_attached = 0; 3673 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3674 GFP_ATOMIC); 3675 break; 3676 case HW_EVENT_PORT_RESET_TIMER_TMO: 3677 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_TIMER_TMO\n"); 3678 sas_phy_disconnected(sas_phy); 3679 phy->phy_attached = 0; 3680 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3681 GFP_ATOMIC); 3682 break; 3683 case HW_EVENT_PORT_RECOVERY_TIMER_TMO: 3684 pm8001_dbg(pm8001_ha, MSG, 3685 "HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"); 3686 sas_phy_disconnected(sas_phy); 3687 phy->phy_attached = 0; 3688 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3689 GFP_ATOMIC); 3690 break; 3691 case HW_EVENT_PORT_RECOVER: 3692 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RECOVER\n"); 3693 break; 3694 case HW_EVENT_PORT_RESET_COMPLETE: 3695 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_COMPLETE\n"); 3696 break; 3697 case EVENT_BROADCAST_ASYNCH_EVENT: 3698 pm8001_dbg(pm8001_ha, MSG, "EVENT_BROADCAST_ASYNCH_EVENT\n"); 3699 break; 3700 default: 3701 pm8001_dbg(pm8001_ha, DEVIO, "Unknown event type = %x\n", 3702 eventType); 3703 break; 3704 } 3705 return 0; 3706} 3707 3708/** 3709 * process_one_iomb - process one outbound Queue memory block 3710 * @pm8001_ha: our hba card information 3711 * @piomb: IO message buffer 3712 */ 3713static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb) 3714{ 3715 __le32 pHeader = *(__le32 *)piomb; 3716 u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF); 3717 3718 pm8001_dbg(pm8001_ha, MSG, "process_one_iomb:\n"); 3719 3720 switch (opc) { 3721 case OPC_OUB_ECHO: 3722 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_ECHO\n"); 3723 break; 3724 case OPC_OUB_HW_EVENT: 3725 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_HW_EVENT\n"); 3726 mpi_hw_event(pm8001_ha, piomb); 3727 break; 3728 case OPC_OUB_SSP_COMP: 3729 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_COMP\n"); 3730 mpi_ssp_completion(pm8001_ha, piomb); 3731 break; 3732 case OPC_OUB_SMP_COMP: 3733 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_COMP\n"); 3734 mpi_smp_completion(pm8001_ha, piomb); 3735 break; 3736 case OPC_OUB_LOCAL_PHY_CNTRL: 3737 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_LOCAL_PHY_CNTRL\n"); 3738 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb); 3739 break; 3740 case OPC_OUB_DEV_REGIST: 3741 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_REGIST\n"); 3742 pm8001_mpi_reg_resp(pm8001_ha, piomb); 3743 break; 3744 case OPC_OUB_DEREG_DEV: 3745 pm8001_dbg(pm8001_ha, MSG, "unregister the device\n"); 3746 pm8001_mpi_dereg_resp(pm8001_ha, piomb); 3747 break; 3748 case OPC_OUB_GET_DEV_HANDLE: 3749 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEV_HANDLE\n"); 3750 break; 3751 case OPC_OUB_SATA_COMP: 3752 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_COMP\n"); 3753 mpi_sata_completion(pm8001_ha, piomb); 3754 break; 3755 case OPC_OUB_SATA_EVENT: 3756 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_EVENT\n"); 3757 mpi_sata_event(pm8001_ha, piomb); 3758 break; 3759 case OPC_OUB_SSP_EVENT: 3760 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_EVENT\n"); 3761 mpi_ssp_event(pm8001_ha, piomb); 3762 break; 3763 case OPC_OUB_DEV_HANDLE_ARRIV: 3764 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_HANDLE_ARRIV\n"); 3765 /*This is for target*/ 3766 break; 3767 case OPC_OUB_SSP_RECV_EVENT: 3768 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_RECV_EVENT\n"); 3769 /*This is for target*/ 3770 break; 3771 case OPC_OUB_DEV_INFO: 3772 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_INFO\n"); 3773 break; 3774 case OPC_OUB_FW_FLASH_UPDATE: 3775 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_FW_FLASH_UPDATE\n"); 3776 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb); 3777 break; 3778 case OPC_OUB_GPIO_RESPONSE: 3779 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_RESPONSE\n"); 3780 break; 3781 case OPC_OUB_GPIO_EVENT: 3782 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_EVENT\n"); 3783 break; 3784 case OPC_OUB_GENERAL_EVENT: 3785 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GENERAL_EVENT\n"); 3786 pm8001_mpi_general_event(pm8001_ha, piomb); 3787 break; 3788 case OPC_OUB_SSP_ABORT_RSP: 3789 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_ABORT_RSP\n"); 3790 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3791 break; 3792 case OPC_OUB_SATA_ABORT_RSP: 3793 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_ABORT_RSP\n"); 3794 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3795 break; 3796 case OPC_OUB_SAS_DIAG_MODE_START_END: 3797 pm8001_dbg(pm8001_ha, MSG, 3798 "OPC_OUB_SAS_DIAG_MODE_START_END\n"); 3799 break; 3800 case OPC_OUB_SAS_DIAG_EXECUTE: 3801 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_DIAG_EXECUTE\n"); 3802 break; 3803 case OPC_OUB_GET_TIME_STAMP: 3804 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_TIME_STAMP\n"); 3805 break; 3806 case OPC_OUB_SAS_HW_EVENT_ACK: 3807 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_HW_EVENT_ACK\n"); 3808 break; 3809 case OPC_OUB_PORT_CONTROL: 3810 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_PORT_CONTROL\n"); 3811 break; 3812 case OPC_OUB_SMP_ABORT_RSP: 3813 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_ABORT_RSP\n"); 3814 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3815 break; 3816 case OPC_OUB_GET_NVMD_DATA: 3817 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_NVMD_DATA\n"); 3818 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb); 3819 break; 3820 case OPC_OUB_SET_NVMD_DATA: 3821 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_NVMD_DATA\n"); 3822 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb); 3823 break; 3824 case OPC_OUB_DEVICE_HANDLE_REMOVAL: 3825 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEVICE_HANDLE_REMOVAL\n"); 3826 break; 3827 case OPC_OUB_SET_DEVICE_STATE: 3828 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEVICE_STATE\n"); 3829 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb); 3830 break; 3831 case OPC_OUB_GET_DEVICE_STATE: 3832 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEVICE_STATE\n"); 3833 break; 3834 case OPC_OUB_SET_DEV_INFO: 3835 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEV_INFO\n"); 3836 break; 3837 case OPC_OUB_SAS_RE_INITIALIZE: 3838 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_RE_INITIALIZE\n"); 3839 break; 3840 default: 3841 pm8001_dbg(pm8001_ha, DEVIO, 3842 "Unknown outbound Queue IOMB OPC = %x\n", 3843 opc); 3844 break; 3845 } 3846} 3847 3848static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec) 3849{ 3850 struct outbound_queue_table *circularQ; 3851 void *pMsg1 = NULL; 3852 u8 bc; 3853 u32 ret = MPI_IO_STATUS_FAIL; 3854 unsigned long flags; 3855 3856 spin_lock_irqsave(&pm8001_ha->lock, flags); 3857 circularQ = &pm8001_ha->outbnd_q_tbl[vec]; 3858 do { 3859 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc); 3860 if (MPI_IO_STATUS_SUCCESS == ret) { 3861 /* process the outbound message */ 3862 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4)); 3863 /* free the message from the outbound circular buffer */ 3864 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1, 3865 circularQ, bc); 3866 } 3867 if (MPI_IO_STATUS_BUSY == ret) { 3868 /* Update the producer index from SPC */ 3869 circularQ->producer_index = 3870 cpu_to_le32(pm8001_read_32(circularQ->pi_virt)); 3871 if (le32_to_cpu(circularQ->producer_index) == 3872 circularQ->consumer_idx) 3873 /* OQ is empty */ 3874 break; 3875 } 3876 } while (1); 3877 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 3878 return ret; 3879} 3880 3881/* DMA_... to our direction translation. */ 3882static const u8 data_dir_flags[] = { 3883 [DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */ 3884 [DMA_TO_DEVICE] = DATA_DIR_OUT, /* OUTBOUND */ 3885 [DMA_FROM_DEVICE] = DATA_DIR_IN, /* INBOUND */ 3886 [DMA_NONE] = DATA_DIR_NONE, /* NO TRANSFER */ 3887}; 3888void 3889pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd) 3890{ 3891 int i; 3892 struct scatterlist *sg; 3893 struct pm8001_prd *buf_prd = prd; 3894 3895 for_each_sg(scatter, sg, nr, i) { 3896 buf_prd->addr = cpu_to_le64(sg_dma_address(sg)); 3897 buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg)); 3898 buf_prd->im_len.e = 0; 3899 buf_prd++; 3900 } 3901} 3902 3903static void build_smp_cmd(u32 deviceID, __le32 hTag, struct smp_req *psmp_cmd) 3904{ 3905 psmp_cmd->tag = hTag; 3906 psmp_cmd->device_id = cpu_to_le32(deviceID); 3907 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1)); 3908} 3909 3910/** 3911 * pm8001_chip_smp_req - send a SMP task to FW 3912 * @pm8001_ha: our hba card information. 3913 * @ccb: the ccb information this request used. 3914 */ 3915static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha, 3916 struct pm8001_ccb_info *ccb) 3917{ 3918 int elem, rc; 3919 struct sas_task *task = ccb->task; 3920 struct domain_device *dev = task->dev; 3921 struct pm8001_device *pm8001_dev = dev->lldd_dev; 3922 struct scatterlist *sg_req, *sg_resp; 3923 u32 req_len, resp_len; 3924 struct smp_req smp_cmd; 3925 u32 opc; 3926 3927 memset(&smp_cmd, 0, sizeof(smp_cmd)); 3928 /* 3929 * DMA-map SMP request, response buffers 3930 */ 3931 sg_req = &task->smp_task.smp_req; 3932 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE); 3933 if (!elem) 3934 return -ENOMEM; 3935 req_len = sg_dma_len(sg_req); 3936 3937 sg_resp = &task->smp_task.smp_resp; 3938 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE); 3939 if (!elem) { 3940 rc = -ENOMEM; 3941 goto err_out; 3942 } 3943 resp_len = sg_dma_len(sg_resp); 3944 /* must be in dwords */ 3945 if ((req_len & 0x3) || (resp_len & 0x3)) { 3946 rc = -EINVAL; 3947 goto err_out_2; 3948 } 3949 3950 opc = OPC_INB_SMP_REQUEST; 3951 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag); 3952 smp_cmd.long_smp_req.long_req_addr = 3953 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req)); 3954 smp_cmd.long_smp_req.long_req_size = 3955 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4); 3956 smp_cmd.long_smp_req.long_resp_addr = 3957 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp)); 3958 smp_cmd.long_smp_req.long_resp_size = 3959 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4); 3960 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd); 3961 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, 3962 &smp_cmd, sizeof(smp_cmd), 0); 3963 if (rc) 3964 goto err_out_2; 3965 3966 return 0; 3967 3968err_out_2: 3969 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1, 3970 DMA_FROM_DEVICE); 3971err_out: 3972 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1, 3973 DMA_TO_DEVICE); 3974 return rc; 3975} 3976 3977/** 3978 * pm8001_chip_ssp_io_req - send a SSP task to FW 3979 * @pm8001_ha: our hba card information. 3980 * @ccb: the ccb information this request used. 3981 */ 3982static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha, 3983 struct pm8001_ccb_info *ccb) 3984{ 3985 struct sas_task *task = ccb->task; 3986 struct domain_device *dev = task->dev; 3987 struct pm8001_device *pm8001_dev = dev->lldd_dev; 3988 struct ssp_ini_io_start_req ssp_cmd; 3989 u32 tag = ccb->ccb_tag; 3990 u64 phys_addr; 3991 u32 opc = OPC_INB_SSPINIIOSTART; 3992 memset(&ssp_cmd, 0, sizeof(ssp_cmd)); 3993 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8); 3994 ssp_cmd.dir_m_tlr = 3995 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);/*0 for 3996 SAS 1.1 compatible TLR*/ 3997 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len); 3998 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id); 3999 ssp_cmd.tag = cpu_to_le32(tag); 4000 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7); 4001 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd, 4002 task->ssp_task.cmd->cmd_len); 4003 4004 /* fill in PRD (scatter/gather) table, if any */ 4005 if (task->num_scatter > 1) { 4006 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd); 4007 phys_addr = ccb->ccb_dma_handle; 4008 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(phys_addr)); 4009 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(phys_addr)); 4010 ssp_cmd.esgl = cpu_to_le32(1<<31); 4011 } else if (task->num_scatter == 1) { 4012 u64 dma_addr = sg_dma_address(task->scatter); 4013 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr)); 4014 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(dma_addr)); 4015 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 4016 ssp_cmd.esgl = 0; 4017 } else if (task->num_scatter == 0) { 4018 ssp_cmd.addr_low = 0; 4019 ssp_cmd.addr_high = 0; 4020 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 4021 ssp_cmd.esgl = 0; 4022 } 4023 4024 return pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &ssp_cmd, 4025 sizeof(ssp_cmd), 0); 4026} 4027 4028static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha, 4029 struct pm8001_ccb_info *ccb) 4030{ 4031 struct sas_task *task = ccb->task; 4032 struct domain_device *dev = task->dev; 4033 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev; 4034 u32 tag = ccb->ccb_tag; 4035 struct sata_start_req sata_cmd; 4036 u32 hdr_tag, ncg_tag = 0; 4037 u64 phys_addr; 4038 u32 ATAP = 0x0; 4039 u32 dir, retfis = 0; 4040 u32 opc = OPC_INB_SATA_HOST_OPSTART; 4041 4042 memset(&sata_cmd, 0, sizeof(sata_cmd)); 4043 4044 if (task->data_dir == DMA_NONE && !task->ata_task.use_ncq) { 4045 ATAP = 0x04; /* no data*/ 4046 pm8001_dbg(pm8001_ha, IO, "no data\n"); 4047 } else if (likely(!task->ata_task.device_control_reg_update)) { 4048 if (task->ata_task.use_ncq && 4049 dev->sata_dev.class != ATA_DEV_ATAPI) { 4050 ATAP = 0x07; /* FPDMA */ 4051 pm8001_dbg(pm8001_ha, IO, "FPDMA\n"); 4052 } else if (task->ata_task.dma_xfer) { 4053 ATAP = 0x06; /* DMA */ 4054 pm8001_dbg(pm8001_ha, IO, "DMA\n"); 4055 } else { 4056 ATAP = 0x05; /* PIO*/ 4057 pm8001_dbg(pm8001_ha, IO, "PIO\n"); 4058 } 4059 } 4060 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) { 4061 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); 4062 ncg_tag = hdr_tag; 4063 } 4064 dir = data_dir_flags[task->data_dir] << 8; 4065 sata_cmd.tag = cpu_to_le32(tag); 4066 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 4067 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len); 4068 if (task->ata_task.return_fis_on_success) 4069 retfis = 1; 4070 sata_cmd.retfis_ncqtag_atap_dir_m = 4071 cpu_to_le32((retfis << 24) | ((ncg_tag & 0xff) << 16) | 4072 ((ATAP & 0x3f) << 10) | dir); 4073 sata_cmd.sata_fis = task->ata_task.fis; 4074 if (likely(!task->ata_task.device_control_reg_update)) 4075 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */ 4076 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */ 4077 /* fill in PRD (scatter/gather) table, if any */ 4078 if (task->num_scatter > 1) { 4079 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd); 4080 phys_addr = ccb->ccb_dma_handle; 4081 sata_cmd.addr_low = lower_32_bits(phys_addr); 4082 sata_cmd.addr_high = upper_32_bits(phys_addr); 4083 sata_cmd.esgl = cpu_to_le32(1 << 31); 4084 } else if (task->num_scatter == 1) { 4085 u64 dma_addr = sg_dma_address(task->scatter); 4086 sata_cmd.addr_low = lower_32_bits(dma_addr); 4087 sata_cmd.addr_high = upper_32_bits(dma_addr); 4088 sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4089 sata_cmd.esgl = 0; 4090 } else if (task->num_scatter == 0) { 4091 sata_cmd.addr_low = 0; 4092 sata_cmd.addr_high = 0; 4093 sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4094 sata_cmd.esgl = 0; 4095 } 4096 4097 return pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &sata_cmd, 4098 sizeof(sata_cmd), 0); 4099} 4100 4101/** 4102 * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND 4103 * @pm8001_ha: our hba card information. 4104 * @phy_id: the phy id which we wanted to start up. 4105 */ 4106static int 4107pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id) 4108{ 4109 struct phy_start_req payload; 4110 u32 tag = 0x01; 4111 u32 opcode = OPC_INB_PHYSTART; 4112 4113 memset(&payload, 0, sizeof(payload)); 4114 payload.tag = cpu_to_le32(tag); 4115 /* 4116 ** [0:7] PHY Identifier 4117 ** [8:11] link rate 1.5G, 3G, 6G 4118 ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both 4119 ** [14] 0b disable spin up hold; 1b enable spin up hold 4120 */ 4121 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE | 4122 LINKMODE_AUTO | LINKRATE_15 | 4123 LINKRATE_30 | LINKRATE_60 | phy_id); 4124 payload.sas_identify.dev_type = SAS_END_DEVICE; 4125 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL; 4126 memcpy(payload.sas_identify.sas_addr, 4127 &pm8001_ha->phy[phy_id].dev_sas_addr, SAS_ADDR_SIZE); 4128 payload.sas_identify.phy_id = phy_id; 4129 4130 return pm8001_mpi_build_cmd(pm8001_ha, 0, opcode, &payload, 4131 sizeof(payload), 0); 4132} 4133 4134/** 4135 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND 4136 * @pm8001_ha: our hba card information. 4137 * @phy_id: the phy id which we wanted to start up. 4138 */ 4139static int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha, 4140 u8 phy_id) 4141{ 4142 struct phy_stop_req payload; 4143 u32 tag = 0x01; 4144 u32 opcode = OPC_INB_PHYSTOP; 4145 4146 memset(&payload, 0, sizeof(payload)); 4147 payload.tag = cpu_to_le32(tag); 4148 payload.phy_id = cpu_to_le32(phy_id); 4149 4150 return pm8001_mpi_build_cmd(pm8001_ha, 0, opcode, &payload, 4151 sizeof(payload), 0); 4152} 4153 4154/* 4155 * see comments on pm8001_mpi_reg_resp. 4156 */ 4157static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha, 4158 struct pm8001_device *pm8001_dev, u32 flag) 4159{ 4160 struct reg_dev_req payload; 4161 u32 opc; 4162 u32 stp_sspsmp_sata = 0x4; 4163 u32 linkrate, phy_id; 4164 int rc; 4165 struct pm8001_ccb_info *ccb; 4166 u8 retryFlag = 0x1; 4167 u16 firstBurstSize = 0; 4168 u16 ITNT = 2000; 4169 struct domain_device *dev = pm8001_dev->sas_device; 4170 struct pm8001_port *port = dev->port->lldd_port; 4171 4172 memset(&payload, 0, sizeof(payload)); 4173 ccb = pm8001_ccb_alloc(pm8001_ha, pm8001_dev, NULL); 4174 if (!ccb) 4175 return -SAS_QUEUE_FULL; 4176 4177 payload.tag = cpu_to_le32(ccb->ccb_tag); 4178 if (flag == 1) 4179 stp_sspsmp_sata = 0x02; /*direct attached sata */ 4180 else { 4181 if (pm8001_dev->dev_type == SAS_SATA_DEV) 4182 stp_sspsmp_sata = 0x00; /* stp*/ 4183 else if (pm8001_dev->dev_type == SAS_END_DEVICE || 4184 dev_is_expander(pm8001_dev->dev_type)) 4185 stp_sspsmp_sata = 0x01; /*ssp or smp*/ 4186 } 4187 4188 phy_id = pm80xx_get_local_phy_id(dev); 4189 4190 opc = OPC_INB_REG_DEV; 4191 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ? 4192 pm8001_dev->sas_device->linkrate : dev->port->linkrate; 4193 payload.phyid_portid = 4194 cpu_to_le32(((port->port_id) & 0x0F) | 4195 ((phy_id & 0x0F) << 4)); 4196 payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) | 4197 ((linkrate & 0x0F) * 0x1000000) | 4198 ((stp_sspsmp_sata & 0x03) * 0x10000000)); 4199 payload.firstburstsize_ITNexustimeout = 4200 cpu_to_le32(ITNT | (firstBurstSize * 0x10000)); 4201 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr, 4202 SAS_ADDR_SIZE); 4203 4204 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, 4205 sizeof(payload), 0); 4206 if (rc) 4207 pm8001_ccb_free(pm8001_ha, ccb); 4208 4209 return rc; 4210} 4211 4212/* 4213 * see comments on pm8001_mpi_reg_resp. 4214 */ 4215int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha, 4216 u32 device_id) 4217{ 4218 struct dereg_dev_req payload; 4219 u32 opc = OPC_INB_DEREG_DEV_HANDLE; 4220 4221 memset(&payload, 0, sizeof(payload)); 4222 payload.tag = cpu_to_le32(1); 4223 payload.device_id = cpu_to_le32(device_id); 4224 pm8001_dbg(pm8001_ha, INIT, "unregister device device_id %d\n", 4225 device_id); 4226 4227 return pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, 4228 sizeof(payload), 0); 4229} 4230 4231/** 4232 * pm8001_chip_phy_ctl_req - support the local phy operation 4233 * @pm8001_ha: our hba card information. 4234 * @phyId: the phy id which we wanted to operate 4235 * @phy_op: the phy operation to request 4236 */ 4237static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 4238 u32 phyId, u32 phy_op) 4239{ 4240 struct local_phy_ctl_req payload; 4241 u32 opc = OPC_INB_LOCAL_PHY_CONTROL; 4242 4243 memset(&payload, 0, sizeof(payload)); 4244 payload.tag = cpu_to_le32(1); 4245 payload.phyop_phyid = 4246 cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F)); 4247 4248 return pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, 4249 sizeof(payload), 0); 4250} 4251 4252static u32 pm8001_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha) 4253{ 4254 u32 value; 4255 4256 if (pm8001_ha->use_msix) 4257 return 1; 4258 4259 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR); 4260 if (value) 4261 return 1; 4262 return 0; 4263} 4264 4265/** 4266 * pm8001_chip_isr - PM8001 isr handler. 4267 * @pm8001_ha: our hba card information. 4268 * @vec: IRQ number 4269 */ 4270static irqreturn_t 4271pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec) 4272{ 4273 pm8001_chip_interrupt_disable(pm8001_ha, vec); 4274 pm8001_dbg(pm8001_ha, DEVIO, 4275 "irq vec %d, ODMR:0x%x\n", 4276 vec, pm8001_cr32(pm8001_ha, 0, 0x30)); 4277 process_oq(pm8001_ha, vec); 4278 pm8001_chip_interrupt_enable(pm8001_ha, vec); 4279 return IRQ_HANDLED; 4280} 4281 4282static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc, 4283 u32 dev_id, enum sas_internal_abort type, u32 task_tag, u32 cmd_tag) 4284{ 4285 struct task_abort_req task_abort; 4286 4287 memset(&task_abort, 0, sizeof(task_abort)); 4288 if (type == SAS_INTERNAL_ABORT_SINGLE) { 4289 task_abort.abort_all = 0; 4290 task_abort.device_id = cpu_to_le32(dev_id); 4291 task_abort.tag_to_abort = cpu_to_le32(task_tag); 4292 } else if (type == SAS_INTERNAL_ABORT_DEV) { 4293 task_abort.abort_all = cpu_to_le32(1); 4294 task_abort.device_id = cpu_to_le32(dev_id); 4295 } else { 4296 pm8001_dbg(pm8001_ha, EH, "unknown type (%d)\n", type); 4297 return -EIO; 4298 } 4299 4300 task_abort.tag = cpu_to_le32(cmd_tag); 4301 4302 return pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &task_abort, 4303 sizeof(task_abort), 0); 4304} 4305 4306/* 4307 * pm8001_chip_abort_task - SAS abort task when error or exception happened. 4308 */ 4309int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha, 4310 struct pm8001_ccb_info *ccb) 4311{ 4312 struct sas_task *task = ccb->task; 4313 struct sas_internal_abort_task *abort = &task->abort_task; 4314 struct pm8001_device *pm8001_dev = ccb->device; 4315 int rc = TMF_RESP_FUNC_FAILED; 4316 u32 opc, device_id; 4317 4318 pm8001_dbg(pm8001_ha, EH, "cmd_tag = %x, abort task tag = 0x%x\n", 4319 ccb->ccb_tag, abort->tag); 4320 if (pm8001_dev->dev_type == SAS_END_DEVICE) 4321 opc = OPC_INB_SSP_ABORT; 4322 else if (pm8001_dev->dev_type == SAS_SATA_DEV) 4323 opc = OPC_INB_SATA_ABORT; 4324 else 4325 opc = OPC_INB_SMP_ABORT;/* SMP */ 4326 device_id = pm8001_dev->device_id; 4327 rc = send_task_abort(pm8001_ha, opc, device_id, abort->type, 4328 abort->tag, ccb->ccb_tag); 4329 if (rc != TMF_RESP_FUNC_COMPLETE) 4330 pm8001_dbg(pm8001_ha, EH, "rc= %d\n", rc); 4331 return rc; 4332} 4333 4334/** 4335 * pm8001_chip_ssp_tm_req - built the task management command. 4336 * @pm8001_ha: our hba card information. 4337 * @ccb: the ccb information. 4338 * @tmf: task management function. 4339 */ 4340int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha, 4341 struct pm8001_ccb_info *ccb, struct sas_tmf_task *tmf) 4342{ 4343 struct sas_task *task = ccb->task; 4344 struct domain_device *dev = task->dev; 4345 struct pm8001_device *pm8001_dev = dev->lldd_dev; 4346 u32 opc = OPC_INB_SSPINITMSTART; 4347 struct ssp_ini_tm_start_req sspTMCmd; 4348 4349 memset(&sspTMCmd, 0, sizeof(sspTMCmd)); 4350 sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id); 4351 sspTMCmd.relate_tag = cpu_to_le32((u32)tmf->tag_of_task_to_be_managed); 4352 sspTMCmd.tmf = cpu_to_le32(tmf->tmf); 4353 memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8); 4354 sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag); 4355 if (pm8001_ha->chip_id != chip_8001) 4356 sspTMCmd.ds_ads_m = cpu_to_le32(0x08); 4357 4358 return pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &sspTMCmd, 4359 sizeof(sspTMCmd), 0); 4360} 4361 4362int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha, 4363 void *payload) 4364{ 4365 u32 opc = OPC_INB_GET_NVMD_DATA; 4366 u32 nvmd_type; 4367 int rc; 4368 struct pm8001_ccb_info *ccb; 4369 struct get_nvm_data_req nvmd_req; 4370 struct fw_control_ex *fw_control_context; 4371 struct pm8001_ioctl_payload *ioctl_payload = payload; 4372 4373 nvmd_type = ioctl_payload->minor_function; 4374 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL); 4375 if (!fw_control_context) 4376 return -ENOMEM; 4377 fw_control_context->usrAddr = (u8 *)ioctl_payload->func_specific; 4378 fw_control_context->len = ioctl_payload->rd_length; 4379 memset(&nvmd_req, 0, sizeof(nvmd_req)); 4380 4381 ccb = pm8001_ccb_alloc(pm8001_ha, NULL, NULL); 4382 if (!ccb) { 4383 kfree(fw_control_context); 4384 return -SAS_QUEUE_FULL; 4385 } 4386 ccb->fw_control_context = fw_control_context; 4387 4388 nvmd_req.tag = cpu_to_le32(ccb->ccb_tag); 4389 4390 switch (nvmd_type) { 4391 case TWI_DEVICE: { 4392 u32 twi_addr, twi_page_size; 4393 twi_addr = 0xa8; 4394 twi_page_size = 2; 4395 4396 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 | 4397 twi_page_size << 8 | TWI_DEVICE); 4398 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length); 4399 nvmd_req.resp_addr_hi = 4400 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4401 nvmd_req.resp_addr_lo = 4402 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4403 break; 4404 } 4405 case C_SEEPROM: { 4406 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM); 4407 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length); 4408 nvmd_req.resp_addr_hi = 4409 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4410 nvmd_req.resp_addr_lo = 4411 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4412 break; 4413 } 4414 case VPD_FLASH: { 4415 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH); 4416 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length); 4417 nvmd_req.resp_addr_hi = 4418 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4419 nvmd_req.resp_addr_lo = 4420 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4421 break; 4422 } 4423 case EXPAN_ROM: { 4424 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM); 4425 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length); 4426 nvmd_req.resp_addr_hi = 4427 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4428 nvmd_req.resp_addr_lo = 4429 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4430 break; 4431 } 4432 case IOP_RDUMP: { 4433 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | IOP_RDUMP); 4434 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length); 4435 nvmd_req.vpd_offset = cpu_to_le32(ioctl_payload->offset); 4436 nvmd_req.resp_addr_hi = 4437 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4438 nvmd_req.resp_addr_lo = 4439 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4440 break; 4441 } 4442 default: 4443 break; 4444 } 4445 4446 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &nvmd_req, 4447 sizeof(nvmd_req), 0); 4448 if (rc) { 4449 kfree(fw_control_context); 4450 pm8001_ccb_free(pm8001_ha, ccb); 4451 } 4452 return rc; 4453} 4454 4455int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha, 4456 void *payload) 4457{ 4458 u32 opc = OPC_INB_SET_NVMD_DATA; 4459 u32 nvmd_type; 4460 int rc; 4461 struct pm8001_ccb_info *ccb; 4462 struct set_nvm_data_req nvmd_req; 4463 struct fw_control_ex *fw_control_context; 4464 struct pm8001_ioctl_payload *ioctl_payload = payload; 4465 4466 nvmd_type = ioctl_payload->minor_function; 4467 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL); 4468 if (!fw_control_context) 4469 return -ENOMEM; 4470 4471 memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr, 4472 &ioctl_payload->func_specific, 4473 ioctl_payload->wr_length); 4474 memset(&nvmd_req, 0, sizeof(nvmd_req)); 4475 4476 ccb = pm8001_ccb_alloc(pm8001_ha, NULL, NULL); 4477 if (!ccb) { 4478 kfree(fw_control_context); 4479 return -SAS_QUEUE_FULL; 4480 } 4481 ccb->fw_control_context = fw_control_context; 4482 4483 nvmd_req.tag = cpu_to_le32(ccb->ccb_tag); 4484 switch (nvmd_type) { 4485 case TWI_DEVICE: { 4486 u32 twi_addr, twi_page_size; 4487 twi_addr = 0xa8; 4488 twi_page_size = 2; 4489 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); 4490 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 | 4491 twi_page_size << 8 | TWI_DEVICE); 4492 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length); 4493 nvmd_req.resp_addr_hi = 4494 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4495 nvmd_req.resp_addr_lo = 4496 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4497 break; 4498 } 4499 case C_SEEPROM: 4500 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM); 4501 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length); 4502 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); 4503 nvmd_req.resp_addr_hi = 4504 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4505 nvmd_req.resp_addr_lo = 4506 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4507 break; 4508 case VPD_FLASH: 4509 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH); 4510 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length); 4511 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); 4512 nvmd_req.resp_addr_hi = 4513 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4514 nvmd_req.resp_addr_lo = 4515 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4516 break; 4517 case EXPAN_ROM: 4518 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM); 4519 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length); 4520 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); 4521 nvmd_req.resp_addr_hi = 4522 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4523 nvmd_req.resp_addr_lo = 4524 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4525 break; 4526 default: 4527 break; 4528 } 4529 4530 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &nvmd_req, 4531 sizeof(nvmd_req), 0); 4532 if (rc) { 4533 kfree(fw_control_context); 4534 pm8001_ccb_free(pm8001_ha, ccb); 4535 } 4536 return rc; 4537} 4538 4539/** 4540 * pm8001_chip_fw_flash_update_build - support the firmware update operation 4541 * @pm8001_ha: our hba card information. 4542 * @fw_flash_updata_info: firmware flash update param 4543 * @tag: Tag to apply to the payload 4544 */ 4545int 4546pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha, 4547 void *fw_flash_updata_info, u32 tag) 4548{ 4549 struct fw_flash_Update_req payload; 4550 struct fw_flash_updata_info *info; 4551 u32 opc = OPC_INB_FW_FLASH_UPDATE; 4552 4553 memset(&payload, 0, sizeof(struct fw_flash_Update_req)); 4554 info = fw_flash_updata_info; 4555 payload.tag = cpu_to_le32(tag); 4556 payload.cur_image_len = cpu_to_le32(info->cur_image_len); 4557 payload.cur_image_offset = cpu_to_le32(info->cur_image_offset); 4558 payload.total_image_len = cpu_to_le32(info->total_image_len); 4559 payload.len = info->sgl.im_len.len ; 4560 payload.sgl_addr_lo = 4561 cpu_to_le32(lower_32_bits(le64_to_cpu(info->sgl.addr))); 4562 payload.sgl_addr_hi = 4563 cpu_to_le32(upper_32_bits(le64_to_cpu(info->sgl.addr))); 4564 4565 return pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, 4566 sizeof(payload), 0); 4567} 4568 4569int 4570pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha, 4571 void *payload) 4572{ 4573 struct fw_flash_updata_info flash_update_info; 4574 struct fw_control_info *fw_control; 4575 struct fw_control_ex *fw_control_context; 4576 int rc; 4577 struct pm8001_ccb_info *ccb; 4578 void *buffer = pm8001_ha->memoryMap.region[FW_FLASH].virt_ptr; 4579 dma_addr_t phys_addr = pm8001_ha->memoryMap.region[FW_FLASH].phys_addr; 4580 struct pm8001_ioctl_payload *ioctl_payload = payload; 4581 4582 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL); 4583 if (!fw_control_context) 4584 return -ENOMEM; 4585 fw_control = (struct fw_control_info *)&ioctl_payload->func_specific; 4586 pm8001_dbg(pm8001_ha, DEVIO, 4587 "dma fw_control context input length :%x\n", 4588 fw_control->len); 4589 memcpy(buffer, fw_control->buffer, fw_control->len); 4590 flash_update_info.sgl.addr = cpu_to_le64(phys_addr); 4591 flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len); 4592 flash_update_info.sgl.im_len.e = 0; 4593 flash_update_info.cur_image_offset = fw_control->offset; 4594 flash_update_info.cur_image_len = fw_control->len; 4595 flash_update_info.total_image_len = fw_control->size; 4596 fw_control_context->fw_control = fw_control; 4597 fw_control_context->virtAddr = buffer; 4598 fw_control_context->phys_addr = phys_addr; 4599 fw_control_context->len = fw_control->len; 4600 4601 ccb = pm8001_ccb_alloc(pm8001_ha, NULL, NULL); 4602 if (!ccb) { 4603 kfree(fw_control_context); 4604 return -SAS_QUEUE_FULL; 4605 } 4606 ccb->fw_control_context = fw_control_context; 4607 4608 rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info, 4609 ccb->ccb_tag); 4610 if (rc) { 4611 kfree(fw_control_context); 4612 pm8001_ccb_free(pm8001_ha, ccb); 4613 } 4614 4615 return rc; 4616} 4617 4618ssize_t 4619pm8001_get_gsm_dump(struct device *cdev, u32 length, char *buf) 4620{ 4621 u32 value, rem, offset = 0, bar = 0; 4622 u32 index, work_offset, dw_length; 4623 u32 shift_value, gsm_base, gsm_dump_offset; 4624 char *direct_data; 4625 struct Scsi_Host *shost = class_to_shost(cdev); 4626 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 4627 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 4628 4629 direct_data = buf; 4630 gsm_dump_offset = pm8001_ha->fatal_forensic_shift_offset; 4631 4632 /* check max is 1 Mbytes */ 4633 if ((length > 0x100000) || (gsm_dump_offset & 3) || 4634 ((gsm_dump_offset + length) > 0x1000000)) 4635 return -EINVAL; 4636 4637 if (pm8001_ha->chip_id == chip_8001) 4638 bar = 2; 4639 else 4640 bar = 1; 4641 4642 work_offset = gsm_dump_offset & 0xFFFF0000; 4643 offset = gsm_dump_offset & 0x0000FFFF; 4644 gsm_dump_offset = work_offset; 4645 /* adjust length to dword boundary */ 4646 rem = length & 3; 4647 dw_length = length >> 2; 4648 4649 for (index = 0; index < dw_length; index++) { 4650 if ((work_offset + offset) & 0xFFFF0000) { 4651 if (pm8001_ha->chip_id == chip_8001) 4652 shift_value = ((gsm_dump_offset + offset) & 4653 SHIFT_REG_64K_MASK); 4654 else 4655 shift_value = (((gsm_dump_offset + offset) & 4656 SHIFT_REG_64K_MASK) >> 4657 SHIFT_REG_BIT_SHIFT); 4658 4659 if (pm8001_ha->chip_id == chip_8001) { 4660 gsm_base = GSM_BASE; 4661 if (-1 == pm8001_bar4_shift(pm8001_ha, 4662 (gsm_base + shift_value))) 4663 return -EIO; 4664 } else { 4665 gsm_base = 0; 4666 if (-1 == pm80xx_bar4_shift(pm8001_ha, 4667 (gsm_base + shift_value))) 4668 return -EIO; 4669 } 4670 gsm_dump_offset = (gsm_dump_offset + offset) & 4671 0xFFFF0000; 4672 work_offset = 0; 4673 offset = offset & 0x0000FFFF; 4674 } 4675 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) & 4676 0x0000FFFF); 4677 direct_data += sprintf(direct_data, "%08x ", value); 4678 offset += 4; 4679 } 4680 if (rem != 0) { 4681 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) & 4682 0x0000FFFF); 4683 /* xfr for non_dw */ 4684 direct_data += sprintf(direct_data, "%08x ", value); 4685 } 4686 /* Shift back to BAR4 original address */ 4687 if (-1 == pm8001_bar4_shift(pm8001_ha, 0)) 4688 return -EIO; 4689 pm8001_ha->fatal_forensic_shift_offset += 1024; 4690 4691 if (pm8001_ha->fatal_forensic_shift_offset >= 0x100000) 4692 pm8001_ha->fatal_forensic_shift_offset = 0; 4693 return direct_data - buf; 4694} 4695 4696int 4697pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha, 4698 struct pm8001_device *pm8001_dev, u32 state) 4699{ 4700 struct set_dev_state_req payload; 4701 struct pm8001_ccb_info *ccb; 4702 int rc; 4703 u32 opc = OPC_INB_SET_DEVICE_STATE; 4704 4705 memset(&payload, 0, sizeof(payload)); 4706 4707 ccb = pm8001_ccb_alloc(pm8001_ha, pm8001_dev, NULL); 4708 if (!ccb) 4709 return -SAS_QUEUE_FULL; 4710 4711 payload.tag = cpu_to_le32(ccb->ccb_tag); 4712 payload.device_id = cpu_to_le32(pm8001_dev->device_id); 4713 payload.nds = cpu_to_le32(state); 4714 4715 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, 4716 sizeof(payload), 0); 4717 if (rc) 4718 pm8001_ccb_free(pm8001_ha, ccb); 4719 4720 return rc; 4721} 4722 4723static int 4724pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha) 4725{ 4726 struct sas_re_initialization_req payload; 4727 struct pm8001_ccb_info *ccb; 4728 int rc; 4729 u32 opc = OPC_INB_SAS_RE_INITIALIZE; 4730 4731 memset(&payload, 0, sizeof(payload)); 4732 4733 ccb = pm8001_ccb_alloc(pm8001_ha, NULL, NULL); 4734 if (!ccb) 4735 return -SAS_QUEUE_FULL; 4736 4737 payload.tag = cpu_to_le32(ccb->ccb_tag); 4738 payload.SSAHOLT = cpu_to_le32(0xd << 25); 4739 payload.sata_hol_tmo = cpu_to_le32(80); 4740 payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff); 4741 4742 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, 4743 sizeof(payload), 0); 4744 if (rc) 4745 pm8001_ccb_free(pm8001_ha, ccb); 4746 4747 return rc; 4748} 4749 4750const struct pm8001_dispatch pm8001_8001_dispatch = { 4751 .name = "pmc8001", 4752 .chip_init = pm8001_chip_init, 4753 .chip_post_init = pm8001_chip_post_init, 4754 .chip_soft_rst = pm8001_chip_soft_rst, 4755 .chip_rst = pm8001_hw_chip_rst, 4756 .chip_iounmap = pm8001_chip_iounmap, 4757 .isr = pm8001_chip_isr, 4758 .is_our_interrupt = pm8001_chip_is_our_interrupt, 4759 .isr_process_oq = process_oq, 4760 .interrupt_enable = pm8001_chip_interrupt_enable, 4761 .interrupt_disable = pm8001_chip_interrupt_disable, 4762 .make_prd = pm8001_chip_make_sg, 4763 .smp_req = pm8001_chip_smp_req, 4764 .ssp_io_req = pm8001_chip_ssp_io_req, 4765 .sata_req = pm8001_chip_sata_req, 4766 .phy_start_req = pm8001_chip_phy_start_req, 4767 .phy_stop_req = pm8001_chip_phy_stop_req, 4768 .reg_dev_req = pm8001_chip_reg_dev_req, 4769 .dereg_dev_req = pm8001_chip_dereg_dev_req, 4770 .phy_ctl_req = pm8001_chip_phy_ctl_req, 4771 .task_abort = pm8001_chip_abort_task, 4772 .ssp_tm_req = pm8001_chip_ssp_tm_req, 4773 .get_nvmd_req = pm8001_chip_get_nvmd_req, 4774 .set_nvmd_req = pm8001_chip_set_nvmd_req, 4775 .fw_flash_update_req = pm8001_chip_fw_flash_update_req, 4776 .set_dev_state_req = pm8001_chip_set_dev_state_req, 4777 .sas_re_init_req = pm8001_chip_sas_re_initialization, 4778 .fatal_errors = pm80xx_fatal_errors, 4779};
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