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mpi2_ioc.h
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linux-6.19.14/drivers/scsi/mpt3sas/mpi/mpi2_ioc.h
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright 2000-2020 Broadcom Inc. All rights reserved. 4 * 5 * 6 * Name: mpi2_ioc.h 7 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages 8 * Creation Date: October 11, 2006 9 * 10 * mpi2_ioc.h Version: 02.00.37 11 * 12 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 13 * prefix are for use only on MPI v2.5 products, and must not be used 14 * with MPI v2.0 products. Unless otherwise noted, names beginning with 15 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 16 * 17 * Version History 18 * --------------- 19 * 20 * Date Version Description 21 * -------- -------- ------------------------------------------------------ 22 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 23 * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to 24 * MaxTargets. 25 * Added TotalImageSize field to FWDownload Request. 26 * Added reserved words to FWUpload Request. 27 * 06-26-07 02.00.02 Added IR Configuration Change List Event. 28 * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit 29 * request and replaced it with 30 * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth. 31 * Replaced the MinReplyQueueDepth field of the IOCFacts 32 * reply with MaxReplyDescriptorPostQueueDepth. 33 * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum 34 * depth for the Reply Descriptor Post Queue. 35 * Added SASAddress field to Initiator Device Table 36 * Overflow Event data. 37 * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING 38 * for SAS Initiator Device Status Change Event data. 39 * Modified Reason Code defines for SAS Topology Change 40 * List Event data, including adding a bit for PHY Vacant 41 * status, and adding a mask for the Reason Code. 42 * Added define for 43 * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING. 44 * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID. 45 * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of 46 * the IOCFacts Reply. 47 * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define. 48 * Moved MPI2_VERSION_UNION to mpi2.h. 49 * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks 50 * instead of enables, and added SASBroadcastPrimitiveMasks 51 * field. 52 * Added Log Entry Added Event and related structure. 53 * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID. 54 * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET. 55 * Added MaxVolumes and MaxPersistentEntries fields to 56 * IOCFacts reply. 57 * Added ProtocalFlags and IOCCapabilities fields to 58 * MPI2_FW_IMAGE_HEADER. 59 * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT. 60 * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to 61 * a U16 (from a U32). 62 * Removed extra 's' from EventMasks name. 63 * 06-27-08 02.00.08 Fixed an offset in a comment. 64 * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST. 65 * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and 66 * renamed MinReplyFrameSize to ReplyFrameSize. 67 * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX. 68 * Added two new RAIDOperation values for Integrated RAID 69 * Operations Status Event data. 70 * Added four new IR Configuration Change List Event data 71 * ReasonCode values. 72 * Added two new ReasonCode defines for SAS Device Status 73 * Change Event data. 74 * Added three new DiscoveryStatus bits for the SAS 75 * Discovery event data. 76 * Added Multiplexing Status Change bit to the PhyStatus 77 * field of the SAS Topology Change List event data. 78 * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY. 79 * BootFlags are now product-specific. 80 * Added defines for the indivdual signature bytes 81 * for MPI2_INIT_IMAGE_FOOTER. 82 * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define. 83 * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR 84 * define. 85 * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE 86 * define. 87 * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define. 88 * 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define. 89 * Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define. 90 * Added two new reason codes for SAS Device Status Change 91 * Event. 92 * Added new event: SAS PHY Counter. 93 * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure. 94 * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define. 95 * Added new product id family for 2208. 96 * 10-28-09 02.00.13 Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST. 97 * Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY. 98 * Added MinDevHandle field to MPI2_IOC_FACTS_REPLY. 99 * Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY. 100 * Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define. 101 * Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define. 102 * Added Host Based Discovery Phy Event data. 103 * Added defines for ProductID Product field 104 * (MPI2_FW_HEADER_PID_). 105 * Modified values for SAS ProductID Family 106 * (MPI2_FW_HEADER_PID_FAMILY_). 107 * 02-10-10 02.00.14 Added SAS Quiesce Event structure and defines. 108 * Added PowerManagementControl Request structures and 109 * defines. 110 * 05-12-10 02.00.15 Marked Task Set Full Event as obsolete. 111 * Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define. 112 * 11-10-10 02.00.16 Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC. 113 * 02-23-11 02.00.17 Added SAS NOTIFY Primitive event, and added 114 * SASNotifyPrimitiveMasks field to 115 * MPI2_EVENT_NOTIFICATION_REQUEST. 116 * Added Temperature Threshold Event. 117 * Added Host Message Event. 118 * Added Send Host Message request and reply. 119 * 05-25-11 02.00.18 For Extended Image Header, added 120 * MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC and 121 * MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC defines. 122 * Deprecated MPI2_EXT_IMAGE_TYPE_MAX define. 123 * 08-24-11 02.00.19 Added PhysicalPort field to 124 * MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE structure. 125 * Marked MPI2_PM_CONTROL_FEATURE_PCIE_LINK as obsolete. 126 * 11-18-11 02.00.20 Incorporating additions for MPI v2.5. 127 * 03-29-12 02.00.21 Added a product specific range to event values. 128 * 07-26-12 02.00.22 Added MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE. 129 * Added ElapsedSeconds field to 130 * MPI2_EVENT_DATA_IR_OPERATION_STATUS. 131 * 08-19-13 02.00.23 For IOCInit, added MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE 132 * and MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY. 133 * Added MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE. 134 * Added MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY. 135 * Added Encrypted Hash Extended Image. 136 * 12-05-13 02.00.24 Added MPI25_HASH_IMAGE_TYPE_BIOS. 137 * 11-18-14 02.00.25 Updated copyright information. 138 * 03-16-15 02.00.26 Updated for MPI v2.6. 139 * Added MPI2_EVENT_ACTIVE_CABLE_EXCEPTION and 140 * MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT. 141 * Added MPI26_FW_HEADER_PID_FAMILY_3324_SAS and 142 * MPI26_FW_HEADER_PID_FAMILY_3516_SAS. 143 * Added MPI26_CTRL_OP_SHUTDOWN. 144 * 08-25-15 02.00.27 Added IC ARCH Class based signature defines. 145 * Added MPI26_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED event. 146 * Added ConigurationFlags field to IOCInit message to 147 * support NVMe SGL format control. 148 * Added PCIe SRIOV support. 149 * 02-17-16 02.00.28 Added SAS 4 22.5 gbs speed support. 150 * Added PCIe 4 16.0 GT/sec speec support. 151 * Removed AHCI support. 152 * Removed SOP support. 153 * 07-01-16 02.00.29 Added Archclass for 4008 product. 154 * Added IOCException MPI2_IOCFACTS_EXCEPT_PCIE_DISABLED 155 * 08-23-16 02.00.30 Added new defines for the ImageType field of FWDownload 156 * Request Message. 157 * Added new defines for the ImageType field of FWUpload 158 * Request Message. 159 * Added new values for the RegionType field in the Layout 160 * Data sections of the FLASH Layout Extended Image Data. 161 * Added new defines for the ReasonCode field of 162 * Active Cable Exception Event. 163 * Added MPI2_EVENT_ENCL_DEVICE_STATUS_CHANGE and 164 * MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE. 165 * 11-23-16 02.00.31 Added MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR and 166 * MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR. 167 * 02-02-17 02.00.32 Added MPI2_FW_DOWNLOAD_ITYPE_CBB_BACKUP. 168 * Added MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT and related 169 * defines for the ReasonCode field. 170 * 06-13-17 02.00.33 Added MPI2_FW_DOWNLOAD_ITYPE_CPLD. 171 * 09-29-17 02.00.34 Added MPI26_EVENT_PCIDEV_STAT_RC_PCIE_HOT_RESET_FAILED 172 * to the ReasonCode field in PCIe Device Status Change 173 * Event Data. 174 * 07-22-18 02.00.35 Added FW_DOWNLOAD_ITYPE_CPLD and _PSOC. 175 * Moved FW image definitions ionto new mpi2_image,h 176 * 08-14-18 02.00.36 Fixed definition of MPI2_FW_DOWNLOAD_ITYPE_PSOC (0x16) 177 * 09-07-18 02.00.37 Added MPI26_EVENT_PCIE_TOPO_PI_16_LANES 178 * 10-02-19 02.00.38 Added MPI26_IOCINIT_CFGFLAGS_COREDUMP_ENABLE 179 * Added MPI26_IOCFACTS_CAPABILITY_COREDUMP_ENABLED 180 * Added MPI2_FW_DOWNLOAD_ITYPE_COREDUMP 181 * Added MPI2_FW_UPLOAD_ITYPE_COREDUMP 182 * 9-13-24 02.00.39 Added MPI26_MCTP_PASSTHROUGH messages 183 * -------------------------------------------------------------------------- 184 */ 185 186#ifndef MPI2_IOC_H 187#define MPI2_IOC_H 188 189/***************************************************************************** 190* 191* IOC Messages 192* 193*****************************************************************************/ 194 195/**************************************************************************** 196* IOCInit message 197****************************************************************************/ 198 199/*IOCInit Request message */ 200typedef struct _MPI2_IOC_INIT_REQUEST { 201 U8 WhoInit; /*0x00 */ 202 U8 Reserved1; /*0x01 */ 203 U8 ChainOffset; /*0x02 */ 204 U8 Function; /*0x03 */ 205 U16 Reserved2; /*0x04 */ 206 U8 Reserved3; /*0x06 */ 207 U8 MsgFlags; /*0x07 */ 208 U8 VP_ID; /*0x08 */ 209 U8 VF_ID; /*0x09 */ 210 U16 Reserved4; /*0x0A */ 211 U16 MsgVersion; /*0x0C */ 212 U16 HeaderVersion; /*0x0E */ 213 U32 Reserved5; /*0x10 */ 214 U16 ConfigurationFlags; /* 0x14 */ 215 U8 HostPageSize; /*0x16 */ 216 U8 HostMSIxVectors; /*0x17 */ 217 U16 Reserved8; /*0x18 */ 218 U16 SystemRequestFrameSize; /*0x1A */ 219 U16 ReplyDescriptorPostQueueDepth; /*0x1C */ 220 U16 ReplyFreeQueueDepth; /*0x1E */ 221 U32 SenseBufferAddressHigh; /*0x20 */ 222 U32 SystemReplyAddressHigh; /*0x24 */ 223 U64 SystemRequestFrameBaseAddress; /*0x28 */ 224 U64 ReplyDescriptorPostQueueAddress; /*0x30 */ 225 U64 ReplyFreeQueueAddress; /*0x38 */ 226 U64 TimeStamp; /*0x40 */ 227} MPI2_IOC_INIT_REQUEST, *PTR_MPI2_IOC_INIT_REQUEST, 228 Mpi2IOCInitRequest_t, *pMpi2IOCInitRequest_t; 229 230/*WhoInit values */ 231#define MPI2_WHOINIT_NOT_INITIALIZED (0x00) 232#define MPI2_WHOINIT_SYSTEM_BIOS (0x01) 233#define MPI2_WHOINIT_ROM_BIOS (0x02) 234#define MPI2_WHOINIT_PCI_PEER (0x03) 235#define MPI2_WHOINIT_HOST_DRIVER (0x04) 236#define MPI2_WHOINIT_MANUFACTURER (0x05) 237 238/* MsgFlags */ 239#define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01) 240 241 242/*MsgVersion */ 243#define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00) 244#define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8) 245#define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF) 246#define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0) 247 248/*HeaderVersion */ 249#define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00) 250#define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8) 251#define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF) 252#define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0) 253 254/*ConfigurationFlags */ 255#define MPI26_IOCINIT_CFGFLAGS_NVME_SGL_FORMAT (0x0001) 256#define MPI26_IOCINIT_CFGFLAGS_COREDUMP_ENABLE (0x0002) 257 258/*minimum depth for a Reply Descriptor Post Queue */ 259#define MPI2_RDPQ_DEPTH_MIN (16) 260 261/* Reply Descriptor Post Queue Array Entry */ 262typedef struct _MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY { 263 U64 RDPQBaseAddress; /* 0x00 */ 264 U32 Reserved1; /* 0x08 */ 265 U32 Reserved2; /* 0x0C */ 266} MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY, 267*PTR_MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY, 268Mpi2IOCInitRDPQArrayEntry, *pMpi2IOCInitRDPQArrayEntry; 269 270 271/*IOCInit Reply message */ 272typedef struct _MPI2_IOC_INIT_REPLY { 273 U8 WhoInit; /*0x00 */ 274 U8 Reserved1; /*0x01 */ 275 U8 MsgLength; /*0x02 */ 276 U8 Function; /*0x03 */ 277 U16 Reserved2; /*0x04 */ 278 U8 Reserved3; /*0x06 */ 279 U8 MsgFlags; /*0x07 */ 280 U8 VP_ID; /*0x08 */ 281 U8 VF_ID; /*0x09 */ 282 U16 Reserved4; /*0x0A */ 283 U16 Reserved5; /*0x0C */ 284 U16 IOCStatus; /*0x0E */ 285 U32 IOCLogInfo; /*0x10 */ 286} MPI2_IOC_INIT_REPLY, *PTR_MPI2_IOC_INIT_REPLY, 287 Mpi2IOCInitReply_t, *pMpi2IOCInitReply_t; 288 289/**************************************************************************** 290* IOCFacts message 291****************************************************************************/ 292 293/*IOCFacts Request message */ 294typedef struct _MPI2_IOC_FACTS_REQUEST { 295 U16 Reserved1; /*0x00 */ 296 U8 ChainOffset; /*0x02 */ 297 U8 Function; /*0x03 */ 298 U16 Reserved2; /*0x04 */ 299 U8 Reserved3; /*0x06 */ 300 U8 MsgFlags; /*0x07 */ 301 U8 VP_ID; /*0x08 */ 302 U8 VF_ID; /*0x09 */ 303 U16 Reserved4; /*0x0A */ 304} MPI2_IOC_FACTS_REQUEST, *PTR_MPI2_IOC_FACTS_REQUEST, 305 Mpi2IOCFactsRequest_t, *pMpi2IOCFactsRequest_t; 306 307/*IOCFacts Reply message */ 308typedef struct _MPI2_IOC_FACTS_REPLY { 309 U16 MsgVersion; /*0x00 */ 310 U8 MsgLength; /*0x02 */ 311 U8 Function; /*0x03 */ 312 U16 HeaderVersion; /*0x04 */ 313 U8 IOCNumber; /*0x06 */ 314 U8 MsgFlags; /*0x07 */ 315 U8 VP_ID; /*0x08 */ 316 U8 VF_ID; /*0x09 */ 317 U16 Reserved1; /*0x0A */ 318 U16 IOCExceptions; /*0x0C */ 319 U16 IOCStatus; /*0x0E */ 320 U32 IOCLogInfo; /*0x10 */ 321 U8 MaxChainDepth; /*0x14 */ 322 U8 WhoInit; /*0x15 */ 323 U8 NumberOfPorts; /*0x16 */ 324 U8 MaxMSIxVectors; /*0x17 */ 325 U16 RequestCredit; /*0x18 */ 326 U16 ProductID; /*0x1A */ 327 U32 IOCCapabilities; /*0x1C */ 328 MPI2_VERSION_UNION FWVersion; /*0x20 */ 329 U16 IOCRequestFrameSize; /*0x24 */ 330 U16 IOCMaxChainSegmentSize; /*0x26 */ 331 U16 MaxInitiators; /*0x28 */ 332 U16 MaxTargets; /*0x2A */ 333 U16 MaxSasExpanders; /*0x2C */ 334 U16 MaxEnclosures; /*0x2E */ 335 U16 ProtocolFlags; /*0x30 */ 336 U16 HighPriorityCredit; /*0x32 */ 337 U16 MaxReplyDescriptorPostQueueDepth; /*0x34 */ 338 U8 ReplyFrameSize; /*0x36 */ 339 U8 MaxVolumes; /*0x37 */ 340 U16 MaxDevHandle; /*0x38 */ 341 U16 MaxPersistentEntries; /*0x3A */ 342 U16 MinDevHandle; /*0x3C */ 343 U8 CurrentHostPageSize; /* 0x3E */ 344 U8 Reserved4; /* 0x3F */ 345 U8 SGEModifierMask; /*0x40 */ 346 U8 SGEModifierValue; /*0x41 */ 347 U8 SGEModifierShift; /*0x42 */ 348 U8 Reserved5; /*0x43 */ 349} MPI2_IOC_FACTS_REPLY, *PTR_MPI2_IOC_FACTS_REPLY, 350 Mpi2IOCFactsReply_t, *pMpi2IOCFactsReply_t; 351 352/*MsgVersion */ 353#define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00) 354#define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8) 355#define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF) 356#define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0) 357 358/*HeaderVersion */ 359#define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00) 360#define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8) 361#define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF) 362#define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0) 363 364/*IOCExceptions */ 365#define MPI2_IOCFACTS_EXCEPT_PCIE_DISABLED (0x0400) 366#define MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE (0x0200) 367#define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100) 368 369#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0) 370#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000) 371#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020) 372#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040) 373#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060) 374 375#define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010) 376#define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008) 377#define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004) 378#define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002) 379#define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001) 380 381/*defines for WhoInit field are after the IOCInit Request */ 382 383/*ProductID field uses MPI2_FW_HEADER_PID_ */ 384 385/*IOCCapabilities */ 386#define MPI26_IOCFACTS_CAPABILITY_MCTP_PASSTHRU (0x00800000) 387#define MPI26_IOCFACTS_CAPABILITY_COREDUMP_ENABLED (0x00200000) 388#define MPI26_IOCFACTS_CAPABILITY_PCIE_SRIOV (0x00100000) 389#define MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ (0x00080000) 390#define MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE (0x00040000) 391#define MPI25_IOCFACTS_CAPABILITY_FAST_PATH_CAPABLE (0x00020000) 392#define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY (0x00010000) 393#define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000) 394#define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000) 395#define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000) 396#define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000) 397#define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800) 398#define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100) 399#define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080) 400#define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040) 401#define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020) 402#define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010) 403#define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008) 404#define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004) 405 406/*ProtocolFlags */ 407#define MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES (0x0008) 408#define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002) 409#define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001) 410 411/**************************************************************************** 412* PortFacts message 413****************************************************************************/ 414 415/*PortFacts Request message */ 416typedef struct _MPI2_PORT_FACTS_REQUEST { 417 U16 Reserved1; /*0x00 */ 418 U8 ChainOffset; /*0x02 */ 419 U8 Function; /*0x03 */ 420 U16 Reserved2; /*0x04 */ 421 U8 PortNumber; /*0x06 */ 422 U8 MsgFlags; /*0x07 */ 423 U8 VP_ID; /*0x08 */ 424 U8 VF_ID; /*0x09 */ 425 U16 Reserved3; /*0x0A */ 426} MPI2_PORT_FACTS_REQUEST, *PTR_MPI2_PORT_FACTS_REQUEST, 427 Mpi2PortFactsRequest_t, *pMpi2PortFactsRequest_t; 428 429/*PortFacts Reply message */ 430typedef struct _MPI2_PORT_FACTS_REPLY { 431 U16 Reserved1; /*0x00 */ 432 U8 MsgLength; /*0x02 */ 433 U8 Function; /*0x03 */ 434 U16 Reserved2; /*0x04 */ 435 U8 PortNumber; /*0x06 */ 436 U8 MsgFlags; /*0x07 */ 437 U8 VP_ID; /*0x08 */ 438 U8 VF_ID; /*0x09 */ 439 U16 Reserved3; /*0x0A */ 440 U16 Reserved4; /*0x0C */ 441 U16 IOCStatus; /*0x0E */ 442 U32 IOCLogInfo; /*0x10 */ 443 U8 Reserved5; /*0x14 */ 444 U8 PortType; /*0x15 */ 445 U16 Reserved6; /*0x16 */ 446 U16 MaxPostedCmdBuffers; /*0x18 */ 447 U16 Reserved7; /*0x1A */ 448} MPI2_PORT_FACTS_REPLY, *PTR_MPI2_PORT_FACTS_REPLY, 449 Mpi2PortFactsReply_t, *pMpi2PortFactsReply_t; 450 451/*PortType values */ 452#define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00) 453#define MPI2_PORTFACTS_PORTTYPE_FC (0x10) 454#define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20) 455#define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30) 456#define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31) 457#define MPI2_PORTFACTS_PORTTYPE_TRI_MODE (0x40) 458 459 460/**************************************************************************** 461* PortEnable message 462****************************************************************************/ 463 464/*PortEnable Request message */ 465typedef struct _MPI2_PORT_ENABLE_REQUEST { 466 U16 Reserved1; /*0x00 */ 467 U8 ChainOffset; /*0x02 */ 468 U8 Function; /*0x03 */ 469 U8 Reserved2; /*0x04 */ 470 U8 PortFlags; /*0x05 */ 471 U8 Reserved3; /*0x06 */ 472 U8 MsgFlags; /*0x07 */ 473 U8 VP_ID; /*0x08 */ 474 U8 VF_ID; /*0x09 */ 475 U16 Reserved4; /*0x0A */ 476} MPI2_PORT_ENABLE_REQUEST, *PTR_MPI2_PORT_ENABLE_REQUEST, 477 Mpi2PortEnableRequest_t, *pMpi2PortEnableRequest_t; 478 479/*PortEnable Reply message */ 480typedef struct _MPI2_PORT_ENABLE_REPLY { 481 U16 Reserved1; /*0x00 */ 482 U8 MsgLength; /*0x02 */ 483 U8 Function; /*0x03 */ 484 U8 Reserved2; /*0x04 */ 485 U8 PortFlags; /*0x05 */ 486 U8 Reserved3; /*0x06 */ 487 U8 MsgFlags; /*0x07 */ 488 U8 VP_ID; /*0x08 */ 489 U8 VF_ID; /*0x09 */ 490 U16 Reserved4; /*0x0A */ 491 U16 Reserved5; /*0x0C */ 492 U16 IOCStatus; /*0x0E */ 493 U32 IOCLogInfo; /*0x10 */ 494} MPI2_PORT_ENABLE_REPLY, *PTR_MPI2_PORT_ENABLE_REPLY, 495 Mpi2PortEnableReply_t, *pMpi2PortEnableReply_t; 496 497/**************************************************************************** 498* EventNotification message 499****************************************************************************/ 500 501/*EventNotification Request message */ 502#define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4) 503 504typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST { 505 U16 Reserved1; /*0x00 */ 506 U8 ChainOffset; /*0x02 */ 507 U8 Function; /*0x03 */ 508 U16 Reserved2; /*0x04 */ 509 U8 Reserved3; /*0x06 */ 510 U8 MsgFlags; /*0x07 */ 511 U8 VP_ID; /*0x08 */ 512 U8 VF_ID; /*0x09 */ 513 U16 Reserved4; /*0x0A */ 514 U32 Reserved5; /*0x0C */ 515 U32 Reserved6; /*0x10 */ 516 U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS]; /*0x14 */ 517 U16 SASBroadcastPrimitiveMasks; /*0x24 */ 518 U16 SASNotifyPrimitiveMasks; /*0x26 */ 519 U32 Reserved8; /*0x28 */ 520} MPI2_EVENT_NOTIFICATION_REQUEST, 521 *PTR_MPI2_EVENT_NOTIFICATION_REQUEST, 522 Mpi2EventNotificationRequest_t, 523 *pMpi2EventNotificationRequest_t; 524 525/*EventNotification Reply message */ 526typedef struct _MPI2_EVENT_NOTIFICATION_REPLY { 527 U16 EventDataLength; /*0x00 */ 528 U8 MsgLength; /*0x02 */ 529 U8 Function; /*0x03 */ 530 U16 Reserved1; /*0x04 */ 531 U8 AckRequired; /*0x06 */ 532 U8 MsgFlags; /*0x07 */ 533 U8 VP_ID; /*0x08 */ 534 U8 VF_ID; /*0x09 */ 535 U16 Reserved2; /*0x0A */ 536 U16 Reserved3; /*0x0C */ 537 U16 IOCStatus; /*0x0E */ 538 U32 IOCLogInfo; /*0x10 */ 539 U16 Event; /*0x14 */ 540 U16 Reserved4; /*0x16 */ 541 U32 EventContext; /*0x18 */ 542 U32 EventData[]; /*0x1C */ 543} MPI2_EVENT_NOTIFICATION_REPLY, *PTR_MPI2_EVENT_NOTIFICATION_REPLY, 544 Mpi2EventNotificationReply_t, 545 *pMpi2EventNotificationReply_t; 546 547/*AckRequired */ 548#define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00) 549#define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01) 550 551/*Event */ 552#define MPI2_EVENT_LOG_DATA (0x0001) 553#define MPI2_EVENT_STATE_CHANGE (0x0002) 554#define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005) 555#define MPI2_EVENT_EVENT_CHANGE (0x000A) 556#define MPI2_EVENT_TASK_SET_FULL (0x000E) /*obsolete */ 557#define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F) 558#define MPI2_EVENT_IR_OPERATION_STATUS (0x0014) 559#define MPI2_EVENT_SAS_DISCOVERY (0x0016) 560#define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017) 561#define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018) 562#define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019) 563#define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C) 564#define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D) 565#define MPI2_EVENT_ENCL_DEVICE_STATUS_CHANGE (0x001D) 566#define MPI2_EVENT_IR_VOLUME (0x001E) 567#define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F) 568#define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020) 569#define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021) 570#define MPI2_EVENT_SAS_PHY_COUNTER (0x0022) 571#define MPI2_EVENT_GPIO_INTERRUPT (0x0023) 572#define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024) 573#define MPI2_EVENT_SAS_QUIESCE (0x0025) 574#define MPI2_EVENT_SAS_NOTIFY_PRIMITIVE (0x0026) 575#define MPI2_EVENT_TEMP_THRESHOLD (0x0027) 576#define MPI2_EVENT_HOST_MESSAGE (0x0028) 577#define MPI2_EVENT_POWER_PERFORMANCE_CHANGE (0x0029) 578#define MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE (0x0030) 579#define MPI2_EVENT_PCIE_ENUMERATION (0x0031) 580#define MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST (0x0032) 581#define MPI2_EVENT_PCIE_LINK_COUNTER (0x0033) 582#define MPI2_EVENT_ACTIVE_CABLE_EXCEPTION (0x0034) 583#define MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR (0x0035) 584#define MPI2_EVENT_MIN_PRODUCT_SPECIFIC (0x006E) 585#define MPI2_EVENT_MAX_PRODUCT_SPECIFIC (0x007F) 586 587/*Log Entry Added Event data */ 588 589/*the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */ 590#define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C) 591 592typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED { 593 U64 TimeStamp; /*0x00 */ 594 U32 Reserved1; /*0x08 */ 595 U16 LogSequence; /*0x0C */ 596 U16 LogEntryQualifier; /*0x0E */ 597 U8 VP_ID; /*0x10 */ 598 U8 VF_ID; /*0x11 */ 599 U16 Reserved2; /*0x12 */ 600 U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH]; /*0x14 */ 601} MPI2_EVENT_DATA_LOG_ENTRY_ADDED, 602 *PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED, 603 Mpi2EventDataLogEntryAdded_t, 604 *pMpi2EventDataLogEntryAdded_t; 605 606/*GPIO Interrupt Event data */ 607 608typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT { 609 U8 GPIONum; /*0x00 */ 610 U8 Reserved1; /*0x01 */ 611 U16 Reserved2; /*0x02 */ 612} MPI2_EVENT_DATA_GPIO_INTERRUPT, 613 *PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT, 614 Mpi2EventDataGpioInterrupt_t, 615 *pMpi2EventDataGpioInterrupt_t; 616 617/*Temperature Threshold Event data */ 618 619typedef struct _MPI2_EVENT_DATA_TEMPERATURE { 620 U16 Status; /*0x00 */ 621 U8 SensorNum; /*0x02 */ 622 U8 Reserved1; /*0x03 */ 623 U16 CurrentTemperature; /*0x04 */ 624 U16 Reserved2; /*0x06 */ 625 U32 Reserved3; /*0x08 */ 626 U32 Reserved4; /*0x0C */ 627} MPI2_EVENT_DATA_TEMPERATURE, 628 *PTR_MPI2_EVENT_DATA_TEMPERATURE, 629 Mpi2EventDataTemperature_t, *pMpi2EventDataTemperature_t; 630 631/*Temperature Threshold Event data Status bits */ 632#define MPI2_EVENT_TEMPERATURE3_EXCEEDED (0x0008) 633#define MPI2_EVENT_TEMPERATURE2_EXCEEDED (0x0004) 634#define MPI2_EVENT_TEMPERATURE1_EXCEEDED (0x0002) 635#define MPI2_EVENT_TEMPERATURE0_EXCEEDED (0x0001) 636 637/*Host Message Event data */ 638 639typedef struct _MPI2_EVENT_DATA_HOST_MESSAGE { 640 U8 SourceVF_ID; /*0x00 */ 641 U8 Reserved1; /*0x01 */ 642 U16 Reserved2; /*0x02 */ 643 U32 Reserved3; /*0x04 */ 644 U32 HostData[]; /*0x08 */ 645} MPI2_EVENT_DATA_HOST_MESSAGE, *PTR_MPI2_EVENT_DATA_HOST_MESSAGE, 646 Mpi2EventDataHostMessage_t, *pMpi2EventDataHostMessage_t; 647 648/*Power Performance Change Event data */ 649 650typedef struct _MPI2_EVENT_DATA_POWER_PERF_CHANGE { 651 U8 CurrentPowerMode; /*0x00 */ 652 U8 PreviousPowerMode; /*0x01 */ 653 U16 Reserved1; /*0x02 */ 654} MPI2_EVENT_DATA_POWER_PERF_CHANGE, 655 *PTR_MPI2_EVENT_DATA_POWER_PERF_CHANGE, 656 Mpi2EventDataPowerPerfChange_t, 657 *pMpi2EventDataPowerPerfChange_t; 658 659/*defines for CurrentPowerMode and PreviousPowerMode fields */ 660#define MPI2_EVENT_PM_INIT_MASK (0xC0) 661#define MPI2_EVENT_PM_INIT_UNAVAILABLE (0x00) 662#define MPI2_EVENT_PM_INIT_HOST (0x40) 663#define MPI2_EVENT_PM_INIT_IO_UNIT (0x80) 664#define MPI2_EVENT_PM_INIT_PCIE_DPA (0xC0) 665 666#define MPI2_EVENT_PM_MODE_MASK (0x07) 667#define MPI2_EVENT_PM_MODE_UNAVAILABLE (0x00) 668#define MPI2_EVENT_PM_MODE_UNKNOWN (0x01) 669#define MPI2_EVENT_PM_MODE_FULL_POWER (0x04) 670#define MPI2_EVENT_PM_MODE_REDUCED_POWER (0x05) 671#define MPI2_EVENT_PM_MODE_STANDBY (0x06) 672 673/* Active Cable Exception Event data */ 674 675typedef struct _MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT { 676 U32 ActiveCablePowerRequirement; /* 0x00 */ 677 U8 ReasonCode; /* 0x04 */ 678 U8 ReceptacleID; /* 0x05 */ 679 U16 Reserved1; /* 0x06 */ 680} MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT, 681 *PTR_MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT, 682 Mpi25EventDataActiveCableExcept_t, 683 *pMpi25EventDataActiveCableExcept_t, 684 MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT, 685 *PTR_MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT, 686 Mpi26EventDataActiveCableExcept_t, 687 *pMpi26EventDataActiveCableExcept_t; 688 689/*MPI2.5 defines for the ReasonCode field */ 690#define MPI25_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER (0x00) 691#define MPI25_EVENT_ACTIVE_CABLE_PRESENT (0x01) 692#define MPI25_EVENT_ACTIVE_CABLE_DEGRADED (0x02) 693 694/* defines for ReasonCode field */ 695#define MPI26_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER (0x00) 696#define MPI26_EVENT_ACTIVE_CABLE_PRESENT (0x01) 697#define MPI26_EVENT_ACTIVE_CABLE_DEGRADED (0x02) 698 699/*Hard Reset Received Event data */ 700 701typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED { 702 U8 Reserved1; /*0x00 */ 703 U8 Port; /*0x01 */ 704 U16 Reserved2; /*0x02 */ 705} MPI2_EVENT_DATA_HARD_RESET_RECEIVED, 706 *PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED, 707 Mpi2EventDataHardResetReceived_t, 708 *pMpi2EventDataHardResetReceived_t; 709 710/*Task Set Full Event data */ 711/* this event is obsolete */ 712 713typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL { 714 U16 DevHandle; /*0x00 */ 715 U16 CurrentDepth; /*0x02 */ 716} MPI2_EVENT_DATA_TASK_SET_FULL, *PTR_MPI2_EVENT_DATA_TASK_SET_FULL, 717 Mpi2EventDataTaskSetFull_t, *pMpi2EventDataTaskSetFull_t; 718 719/*SAS Device Status Change Event data */ 720 721typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE { 722 U16 TaskTag; /*0x00 */ 723 U8 ReasonCode; /*0x02 */ 724 U8 PhysicalPort; /*0x03 */ 725 U8 ASC; /*0x04 */ 726 U8 ASCQ; /*0x05 */ 727 U16 DevHandle; /*0x06 */ 728 U32 Reserved2; /*0x08 */ 729 U64 SASAddress; /*0x0C */ 730 U8 LUN[8]; /*0x14 */ 731} MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, 732 *PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, 733 Mpi2EventDataSasDeviceStatusChange_t, 734 *pMpi2EventDataSasDeviceStatusChange_t; 735 736/*SAS Device Status Change Event data ReasonCode values */ 737#define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05) 738#define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07) 739#define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08) 740#define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09) 741#define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A) 742#define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B) 743#define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C) 744#define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D) 745#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E) 746#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F) 747#define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10) 748#define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY (0x11) 749#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY (0x12) 750 751/*Integrated RAID Operation Status Event data */ 752 753typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS { 754 U16 VolDevHandle; /*0x00 */ 755 U16 Reserved1; /*0x02 */ 756 U8 RAIDOperation; /*0x04 */ 757 U8 PercentComplete; /*0x05 */ 758 U16 Reserved2; /*0x06 */ 759 U32 ElapsedSeconds; /*0x08 */ 760} MPI2_EVENT_DATA_IR_OPERATION_STATUS, 761 *PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS, 762 Mpi2EventDataIrOperationStatus_t, 763 *pMpi2EventDataIrOperationStatus_t; 764 765/*Integrated RAID Operation Status Event data RAIDOperation values */ 766#define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00) 767#define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01) 768#define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02) 769#define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03) 770#define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04) 771 772/*Integrated RAID Volume Event data */ 773 774typedef struct _MPI2_EVENT_DATA_IR_VOLUME { 775 U16 VolDevHandle; /*0x00 */ 776 U8 ReasonCode; /*0x02 */ 777 U8 Reserved1; /*0x03 */ 778 U32 NewValue; /*0x04 */ 779 U32 PreviousValue; /*0x08 */ 780} MPI2_EVENT_DATA_IR_VOLUME, *PTR_MPI2_EVENT_DATA_IR_VOLUME, 781 Mpi2EventDataIrVolume_t, *pMpi2EventDataIrVolume_t; 782 783/*Integrated RAID Volume Event data ReasonCode values */ 784#define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01) 785#define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02) 786#define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03) 787 788/*Integrated RAID Physical Disk Event data */ 789 790typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK { 791 U16 Reserved1; /*0x00 */ 792 U8 ReasonCode; /*0x02 */ 793 U8 PhysDiskNum; /*0x03 */ 794 U16 PhysDiskDevHandle; /*0x04 */ 795 U16 Reserved2; /*0x06 */ 796 U16 Slot; /*0x08 */ 797 U16 EnclosureHandle; /*0x0A */ 798 U32 NewValue; /*0x0C */ 799 U32 PreviousValue; /*0x10 */ 800} MPI2_EVENT_DATA_IR_PHYSICAL_DISK, 801 *PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK, 802 Mpi2EventDataIrPhysicalDisk_t, 803 *pMpi2EventDataIrPhysicalDisk_t; 804 805/*Integrated RAID Physical Disk Event data ReasonCode values */ 806#define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01) 807#define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02) 808#define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03) 809 810/*Integrated RAID Configuration Change List Event data */ 811 812/* 813 *Host code (drivers, BIOS, utilities, etc.) should check NumElements at 814 *runtime before using ConfigElement[]. 815 */ 816 817typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT { 818 U16 ElementFlags; /*0x00 */ 819 U16 VolDevHandle; /*0x02 */ 820 U8 ReasonCode; /*0x04 */ 821 U8 PhysDiskNum; /*0x05 */ 822 U16 PhysDiskDevHandle; /*0x06 */ 823} MPI2_EVENT_IR_CONFIG_ELEMENT, *PTR_MPI2_EVENT_IR_CONFIG_ELEMENT, 824 Mpi2EventIrConfigElement_t, *pMpi2EventIrConfigElement_t; 825 826/*IR Configuration Change List Event data ElementFlags values */ 827#define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F) 828#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000) 829#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001) 830#define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002) 831 832/*IR Configuration Change List Event data ReasonCode values */ 833#define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01) 834#define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02) 835#define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03) 836#define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04) 837#define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05) 838#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06) 839#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07) 840#define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08) 841#define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09) 842 843typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST { 844 U8 NumElements; /*0x00 */ 845 U8 Reserved1; /*0x01 */ 846 U8 Reserved2; /*0x02 */ 847 U8 ConfigNum; /*0x03 */ 848 U32 Flags; /*0x04 */ 849 MPI2_EVENT_IR_CONFIG_ELEMENT 850 ConfigElement[];/*0x08 */ 851} MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST, 852 *PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST, 853 Mpi2EventDataIrConfigChangeList_t, 854 *pMpi2EventDataIrConfigChangeList_t; 855 856/*IR Configuration Change List Event data Flags values */ 857#define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001) 858 859/*SAS Discovery Event data */ 860 861typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY { 862 U8 Flags; /*0x00 */ 863 U8 ReasonCode; /*0x01 */ 864 U8 PhysicalPort; /*0x02 */ 865 U8 Reserved1; /*0x03 */ 866 U32 DiscoveryStatus; /*0x04 */ 867} MPI2_EVENT_DATA_SAS_DISCOVERY, 868 *PTR_MPI2_EVENT_DATA_SAS_DISCOVERY, 869 Mpi2EventDataSasDiscovery_t, *pMpi2EventDataSasDiscovery_t; 870 871/*SAS Discovery Event data Flags values */ 872#define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02) 873#define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01) 874 875/*SAS Discovery Event data ReasonCode values */ 876#define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01) 877#define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02) 878 879/*SAS Discovery Event data DiscoveryStatus values */ 880#define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 881#define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000) 882#define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000) 883#define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 884#define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000) 885#define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 886#define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 887#define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000) 888#define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 889#define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800) 890#define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400) 891#define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200) 892#define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100) 893#define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080) 894#define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040) 895#define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020) 896#define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010) 897#define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004) 898#define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002) 899#define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001) 900 901/*SAS Broadcast Primitive Event data */ 902 903typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE { 904 U8 PhyNum; /*0x00 */ 905 U8 Port; /*0x01 */ 906 U8 PortWidth; /*0x02 */ 907 U8 Primitive; /*0x03 */ 908} MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, 909 *PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, 910 Mpi2EventDataSasBroadcastPrimitive_t, 911 *pMpi2EventDataSasBroadcastPrimitive_t; 912 913/*defines for the Primitive field */ 914#define MPI2_EVENT_PRIMITIVE_CHANGE (0x01) 915#define MPI2_EVENT_PRIMITIVE_SES (0x02) 916#define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03) 917#define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04) 918#define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05) 919#define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06) 920#define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07) 921#define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08) 922 923/*SAS Notify Primitive Event data */ 924 925typedef struct _MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE { 926 U8 PhyNum; /*0x00 */ 927 U8 Port; /*0x01 */ 928 U8 Reserved1; /*0x02 */ 929 U8 Primitive; /*0x03 */ 930} MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE, 931 *PTR_MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE, 932 Mpi2EventDataSasNotifyPrimitive_t, 933 *pMpi2EventDataSasNotifyPrimitive_t; 934 935/*defines for the Primitive field */ 936#define MPI2_EVENT_NOTIFY_ENABLE_SPINUP (0x01) 937#define MPI2_EVENT_NOTIFY_POWER_LOSS_EXPECTED (0x02) 938#define MPI2_EVENT_NOTIFY_RESERVED1 (0x03) 939#define MPI2_EVENT_NOTIFY_RESERVED2 (0x04) 940 941/*SAS Initiator Device Status Change Event data */ 942 943typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE { 944 U8 ReasonCode; /*0x00 */ 945 U8 PhysicalPort; /*0x01 */ 946 U16 DevHandle; /*0x02 */ 947 U64 SASAddress; /*0x04 */ 948} MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, 949 *PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, 950 Mpi2EventDataSasInitDevStatusChange_t, 951 *pMpi2EventDataSasInitDevStatusChange_t; 952 953/*SAS Initiator Device Status Change event ReasonCode values */ 954#define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01) 955#define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02) 956 957/*SAS Initiator Device Table Overflow Event data */ 958 959typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW { 960 U16 MaxInit; /*0x00 */ 961 U16 CurrentInit; /*0x02 */ 962 U64 SASAddress; /*0x04 */ 963} MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, 964 *PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, 965 Mpi2EventDataSasInitTableOverflow_t, 966 *pMpi2EventDataSasInitTableOverflow_t; 967 968/*SAS Topology Change List Event data */ 969 970/* 971 *Host code (drivers, BIOS, utilities, etc.) should check NumEntries at 972 *runtime before using PHY[]. 973 */ 974 975typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY { 976 U16 AttachedDevHandle; /*0x00 */ 977 U8 LinkRate; /*0x02 */ 978 U8 PhyStatus; /*0x03 */ 979} MPI2_EVENT_SAS_TOPO_PHY_ENTRY, *PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY, 980 Mpi2EventSasTopoPhyEntry_t, *pMpi2EventSasTopoPhyEntry_t; 981 982typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST { 983 U16 EnclosureHandle; /*0x00 */ 984 U16 ExpanderDevHandle; /*0x02 */ 985 U8 NumPhys; /*0x04 */ 986 U8 Reserved1; /*0x05 */ 987 U16 Reserved2; /*0x06 */ 988 U8 NumEntries; /*0x08 */ 989 U8 StartPhyNum; /*0x09 */ 990 U8 ExpStatus; /*0x0A */ 991 U8 PhysicalPort; /*0x0B */ 992 MPI2_EVENT_SAS_TOPO_PHY_ENTRY 993 PHY[]; /*0x0C */ 994} MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST, 995 *PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST, 996 Mpi2EventDataSasTopologyChangeList_t, 997 *pMpi2EventDataSasTopologyChangeList_t; 998 999/*values for the ExpStatus field */ 1000#define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00) 1001#define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01) 1002#define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02) 1003#define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03) 1004#define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04) 1005 1006/*defines for the LinkRate field */ 1007#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0) 1008#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4) 1009#define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F) 1010#define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0) 1011 1012#define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00) 1013#define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01) 1014#define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02) 1015#define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03) 1016#define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04) 1017#define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05) 1018#define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06) 1019#define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08) 1020#define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09) 1021#define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A) 1022#define MPI25_EVENT_SAS_TOPO_LR_RATE_12_0 (0x0B) 1023#define MPI26_EVENT_SAS_TOPO_LR_RATE_22_5 (0x0C) 1024 1025/*values for the PhyStatus field */ 1026#define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80) 1027#define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10) 1028/*values for the PhyStatus ReasonCode sub-field */ 1029#define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F) 1030#define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01) 1031#define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02) 1032#define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03) 1033#define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04) 1034#define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05) 1035 1036/*SAS Enclosure Device Status Change Event data */ 1037 1038typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE { 1039 U16 EnclosureHandle; /*0x00 */ 1040 U8 ReasonCode; /*0x02 */ 1041 U8 PhysicalPort; /*0x03 */ 1042 U64 EnclosureLogicalID; /*0x04 */ 1043 U16 NumSlots; /*0x0C */ 1044 U16 StartSlot; /*0x0E */ 1045 U32 PhyBits; /*0x10 */ 1046} MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE, 1047 *PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE, 1048 Mpi2EventDataSasEnclDevStatusChange_t, 1049 *pMpi2EventDataSasEnclDevStatusChange_t, 1050 MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE, 1051 *PTR_MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE, 1052 Mpi26EventDataEnclDevStatusChange_t, 1053 *pMpi26EventDataEnclDevStatusChange_t; 1054 1055/*SAS Enclosure Device Status Change event ReasonCode values */ 1056#define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01) 1057#define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02) 1058 1059/*Enclosure Device Status Change event ReasonCode values */ 1060#define MPI26_EVENT_ENCL_RC_ADDED (0x01) 1061#define MPI26_EVENT_ENCL_RC_NOT_RESPONDING (0x02) 1062 1063 1064typedef struct _MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR { 1065 U16 DevHandle; /*0x00 */ 1066 U8 ReasonCode; /*0x02 */ 1067 U8 PhysicalPort; /*0x03 */ 1068 U32 Reserved1[2]; /*0x04 */ 1069 U64 SASAddress; /*0x0C */ 1070 U32 Reserved2[2]; /*0x14 */ 1071} MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR, 1072 *PTR_MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR, 1073 Mpi25EventDataSasDeviceDiscoveryError_t, 1074 *pMpi25EventDataSasDeviceDiscoveryError_t; 1075 1076/*SAS Device Discovery Error Event data ReasonCode values */ 1077#define MPI25_EVENT_SAS_DISC_ERR_SMP_FAILED (0x01) 1078#define MPI25_EVENT_SAS_DISC_ERR_SMP_TIMEOUT (0x02) 1079 1080/*SAS PHY Counter Event data */ 1081 1082typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER { 1083 U64 TimeStamp; /*0x00 */ 1084 U32 Reserved1; /*0x08 */ 1085 U8 PhyEventCode; /*0x0C */ 1086 U8 PhyNum; /*0x0D */ 1087 U16 Reserved2; /*0x0E */ 1088 U32 PhyEventInfo; /*0x10 */ 1089 U8 CounterType; /*0x14 */ 1090 U8 ThresholdWindow; /*0x15 */ 1091 U8 TimeUnits; /*0x16 */ 1092 U8 Reserved3; /*0x17 */ 1093 U32 EventThreshold; /*0x18 */ 1094 U16 ThresholdFlags; /*0x1C */ 1095 U16 Reserved4; /*0x1E */ 1096} MPI2_EVENT_DATA_SAS_PHY_COUNTER, 1097 *PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER, 1098 Mpi2EventDataSasPhyCounter_t, 1099 *pMpi2EventDataSasPhyCounter_t; 1100 1101/*use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h 1102 *for the PhyEventCode field */ 1103 1104/*use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h 1105 *for the CounterType field */ 1106 1107/*use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h 1108 *for the TimeUnits field */ 1109 1110/*use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h 1111 *for the ThresholdFlags field */ 1112 1113/*SAS Quiesce Event data */ 1114 1115typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE { 1116 U8 ReasonCode; /*0x00 */ 1117 U8 Reserved1; /*0x01 */ 1118 U16 Reserved2; /*0x02 */ 1119 U32 Reserved3; /*0x04 */ 1120} MPI2_EVENT_DATA_SAS_QUIESCE, 1121 *PTR_MPI2_EVENT_DATA_SAS_QUIESCE, 1122 Mpi2EventDataSasQuiesce_t, *pMpi2EventDataSasQuiesce_t; 1123 1124/*SAS Quiesce Event data ReasonCode values */ 1125#define MPI2_EVENT_SAS_QUIESCE_RC_STARTED (0x01) 1126#define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED (0x02) 1127 1128/*Host Based Discovery Phy Event data */ 1129 1130typedef struct _MPI2_EVENT_HBD_PHY_SAS { 1131 U8 Flags; /*0x00 */ 1132 U8 NegotiatedLinkRate; /*0x01 */ 1133 U8 PhyNum; /*0x02 */ 1134 U8 PhysicalPort; /*0x03 */ 1135 U32 Reserved1; /*0x04 */ 1136 U8 InitialFrame[28]; /*0x08 */ 1137} MPI2_EVENT_HBD_PHY_SAS, *PTR_MPI2_EVENT_HBD_PHY_SAS, 1138 Mpi2EventHbdPhySas_t, *pMpi2EventHbdPhySas_t; 1139 1140/*values for the Flags field */ 1141#define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID (0x02) 1142#define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME (0x01) 1143 1144/*use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h 1145 *for the NegotiatedLinkRate field */ 1146 1147typedef union _MPI2_EVENT_HBD_DESCRIPTOR { 1148 MPI2_EVENT_HBD_PHY_SAS Sas; 1149} MPI2_EVENT_HBD_DESCRIPTOR, *PTR_MPI2_EVENT_HBD_DESCRIPTOR, 1150 Mpi2EventHbdDescriptor_t, *pMpi2EventHbdDescriptor_t; 1151 1152typedef struct _MPI2_EVENT_DATA_HBD_PHY { 1153 U8 DescriptorType; /*0x00 */ 1154 U8 Reserved1; /*0x01 */ 1155 U16 Reserved2; /*0x02 */ 1156 U32 Reserved3; /*0x04 */ 1157 MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /*0x08 */ 1158} MPI2_EVENT_DATA_HBD_PHY, *PTR_MPI2_EVENT_DATA_HBD_PHY, 1159 Mpi2EventDataHbdPhy_t, 1160 *pMpi2EventDataMpi2EventDataHbdPhy_t; 1161 1162/*values for the DescriptorType field */ 1163#define MPI2_EVENT_HBD_DT_SAS (0x01) 1164 1165 1166/*PCIe Device Status Change Event data (MPI v2.6 and later) */ 1167 1168typedef struct _MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE { 1169 U16 TaskTag; /*0x00 */ 1170 U8 ReasonCode; /*0x02 */ 1171 U8 PhysicalPort; /*0x03 */ 1172 U8 ASC; /*0x04 */ 1173 U8 ASCQ; /*0x05 */ 1174 U16 DevHandle; /*0x06 */ 1175 U32 Reserved2; /*0x08 */ 1176 U64 WWID; /*0x0C */ 1177 U8 LUN[8]; /*0x14 */ 1178} MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE, 1179 *PTR_MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE, 1180 Mpi26EventDataPCIeDeviceStatusChange_t, 1181 *pMpi26EventDataPCIeDeviceStatusChange_t; 1182 1183/*PCIe Device Status Change Event data ReasonCode values */ 1184#define MPI26_EVENT_PCIDEV_STAT_RC_SMART_DATA (0x05) 1185#define MPI26_EVENT_PCIDEV_STAT_RC_UNSUPPORTED (0x07) 1186#define MPI26_EVENT_PCIDEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08) 1187#define MPI26_EVENT_PCIDEV_STAT_RC_TASK_ABORT_INTERNAL (0x09) 1188#define MPI26_EVENT_PCIDEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A) 1189#define MPI26_EVENT_PCIDEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B) 1190#define MPI26_EVENT_PCIDEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C) 1191#define MPI26_EVENT_PCIDEV_STAT_RC_ASYNC_NOTIFICATION (0x0D) 1192#define MPI26_EVENT_PCIDEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E) 1193#define MPI26_EVENT_PCIDEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F) 1194#define MPI26_EVENT_PCIDEV_STAT_RC_DEV_INIT_FAILURE (0x10) 1195#define MPI26_EVENT_PCIDEV_STAT_RC_PCIE_HOT_RESET_FAILED (0x11) 1196 1197 1198/*PCIe Enumeration Event data (MPI v2.6 and later) */ 1199 1200typedef struct _MPI26_EVENT_DATA_PCIE_ENUMERATION { 1201 U8 Flags; /*0x00 */ 1202 U8 ReasonCode; /*0x01 */ 1203 U8 PhysicalPort; /*0x02 */ 1204 U8 Reserved1; /*0x03 */ 1205 U32 EnumerationStatus; /*0x04 */ 1206} MPI26_EVENT_DATA_PCIE_ENUMERATION, 1207 *PTR_MPI26_EVENT_DATA_PCIE_ENUMERATION, 1208 Mpi26EventDataPCIeEnumeration_t, 1209 *pMpi26EventDataPCIeEnumeration_t; 1210 1211/*PCIe Enumeration Event data Flags values */ 1212#define MPI26_EVENT_PCIE_ENUM_DEVICE_CHANGE (0x02) 1213#define MPI26_EVENT_PCIE_ENUM_IN_PROGRESS (0x01) 1214 1215/*PCIe Enumeration Event data ReasonCode values */ 1216#define MPI26_EVENT_PCIE_ENUM_RC_STARTED (0x01) 1217#define MPI26_EVENT_PCIE_ENUM_RC_COMPLETED (0x02) 1218 1219/*PCIe Enumeration Event data EnumerationStatus values */ 1220#define MPI26_EVENT_PCIE_ENUM_ES_MAX_SWITCHES_EXCEED (0x40000000) 1221#define MPI26_EVENT_PCIE_ENUM_ES_MAX_DEVICES_EXCEED (0x20000000) 1222#define MPI26_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED (0x10000000) 1223 1224 1225/*PCIe Topology Change List Event data (MPI v2.6 and later) */ 1226 1227/* 1228 *Host code (drivers, BIOS, utilities, etc.) should check NumEntries at 1229 *runtime before using PortEntry[]. 1230 */ 1231 1232typedef struct _MPI26_EVENT_PCIE_TOPO_PORT_ENTRY { 1233 U16 AttachedDevHandle; /*0x00 */ 1234 U8 PortStatus; /*0x02 */ 1235 U8 Reserved1; /*0x03 */ 1236 U8 CurrentPortInfo; /*0x04 */ 1237 U8 Reserved2; /*0x05 */ 1238 U8 PreviousPortInfo; /*0x06 */ 1239 U8 Reserved3; /*0x07 */ 1240} MPI26_EVENT_PCIE_TOPO_PORT_ENTRY, 1241 *PTR_MPI26_EVENT_PCIE_TOPO_PORT_ENTRY, 1242 Mpi26EventPCIeTopoPortEntry_t, 1243 *pMpi26EventPCIeTopoPortEntry_t; 1244 1245/*PCIe Topology Change List Event data PortStatus values */ 1246#define MPI26_EVENT_PCIE_TOPO_PS_DEV_ADDED (0x01) 1247#define MPI26_EVENT_PCIE_TOPO_PS_NOT_RESPONDING (0x02) 1248#define MPI26_EVENT_PCIE_TOPO_PS_PORT_CHANGED (0x03) 1249#define MPI26_EVENT_PCIE_TOPO_PS_NO_CHANGE (0x04) 1250#define MPI26_EVENT_PCIE_TOPO_PS_DELAY_NOT_RESPONDING (0x05) 1251 1252/*PCIe Topology Change List Event data defines for CurrentPortInfo and 1253 *PreviousPortInfo 1254 */ 1255#define MPI26_EVENT_PCIE_TOPO_PI_LANE_MASK (0xF0) 1256#define MPI26_EVENT_PCIE_TOPO_PI_LANES_UNKNOWN (0x00) 1257#define MPI26_EVENT_PCIE_TOPO_PI_1_LANE (0x10) 1258#define MPI26_EVENT_PCIE_TOPO_PI_2_LANES (0x20) 1259#define MPI26_EVENT_PCIE_TOPO_PI_4_LANES (0x30) 1260#define MPI26_EVENT_PCIE_TOPO_PI_8_LANES (0x40) 1261#define MPI26_EVENT_PCIE_TOPO_PI_16_LANES (0x50) 1262 1263#define MPI26_EVENT_PCIE_TOPO_PI_RATE_MASK (0x0F) 1264#define MPI26_EVENT_PCIE_TOPO_PI_RATE_UNKNOWN (0x00) 1265#define MPI26_EVENT_PCIE_TOPO_PI_RATE_DISABLED (0x01) 1266#define MPI26_EVENT_PCIE_TOPO_PI_RATE_2_5 (0x02) 1267#define MPI26_EVENT_PCIE_TOPO_PI_RATE_5_0 (0x03) 1268#define MPI26_EVENT_PCIE_TOPO_PI_RATE_8_0 (0x04) 1269#define MPI26_EVENT_PCIE_TOPO_PI_RATE_16_0 (0x05) 1270 1271typedef struct _MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST { 1272 U16 EnclosureHandle; /*0x00 */ 1273 U16 SwitchDevHandle; /*0x02 */ 1274 U8 NumPorts; /*0x04 */ 1275 U8 Reserved1; /*0x05 */ 1276 U16 Reserved2; /*0x06 */ 1277 U8 NumEntries; /*0x08 */ 1278 U8 StartPortNum; /*0x09 */ 1279 U8 SwitchStatus; /*0x0A */ 1280 U8 PhysicalPort; /*0x0B */ 1281 MPI26_EVENT_PCIE_TOPO_PORT_ENTRY 1282 PortEntry[]; /*0x0C */ 1283} MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST, 1284 *PTR_MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST, 1285 Mpi26EventDataPCIeTopologyChangeList_t, 1286 *pMpi26EventDataPCIeTopologyChangeList_t; 1287 1288/*PCIe Topology Change List Event data SwitchStatus values */ 1289#define MPI26_EVENT_PCIE_TOPO_SS_NO_PCIE_SWITCH (0x00) 1290#define MPI26_EVENT_PCIE_TOPO_SS_ADDED (0x01) 1291#define MPI26_EVENT_PCIE_TOPO_SS_NOT_RESPONDING (0x02) 1292#define MPI26_EVENT_PCIE_TOPO_SS_RESPONDING (0x03) 1293#define MPI26_EVENT_PCIE_TOPO_SS_DELAY_NOT_RESPONDING (0x04) 1294 1295/*PCIe Link Counter Event data (MPI v2.6 and later) */ 1296 1297typedef struct _MPI26_EVENT_DATA_PCIE_LINK_COUNTER { 1298 U64 TimeStamp; /*0x00 */ 1299 U32 Reserved1; /*0x08 */ 1300 U8 LinkEventCode; /*0x0C */ 1301 U8 LinkNum; /*0x0D */ 1302 U16 Reserved2; /*0x0E */ 1303 U32 LinkEventInfo; /*0x10 */ 1304 U8 CounterType; /*0x14 */ 1305 U8 ThresholdWindow; /*0x15 */ 1306 U8 TimeUnits; /*0x16 */ 1307 U8 Reserved3; /*0x17 */ 1308 U32 EventThreshold; /*0x18 */ 1309 U16 ThresholdFlags; /*0x1C */ 1310 U16 Reserved4; /*0x1E */ 1311} MPI26_EVENT_DATA_PCIE_LINK_COUNTER, 1312 *PTR_MPI26_EVENT_DATA_PCIE_LINK_COUNTER, 1313 Mpi26EventDataPcieLinkCounter_t, *pMpi26EventDataPcieLinkCounter_t; 1314 1315 1316/*use MPI26_PCIELINK3_EVTCODE_ values from mpi2_cnfg.h for the LinkEventCode 1317 *field 1318 */ 1319 1320/*use MPI26_PCIELINK3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType 1321 *field 1322 */ 1323 1324/*use MPI26_PCIELINK3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits 1325 *field 1326 */ 1327 1328/*use MPI26_PCIELINK3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags 1329 *field 1330 */ 1331 1332/**************************************************************************** 1333* EventAck message 1334****************************************************************************/ 1335 1336/*EventAck Request message */ 1337typedef struct _MPI2_EVENT_ACK_REQUEST { 1338 U16 Reserved1; /*0x00 */ 1339 U8 ChainOffset; /*0x02 */ 1340 U8 Function; /*0x03 */ 1341 U16 Reserved2; /*0x04 */ 1342 U8 Reserved3; /*0x06 */ 1343 U8 MsgFlags; /*0x07 */ 1344 U8 VP_ID; /*0x08 */ 1345 U8 VF_ID; /*0x09 */ 1346 U16 Reserved4; /*0x0A */ 1347 U16 Event; /*0x0C */ 1348 U16 Reserved5; /*0x0E */ 1349 U32 EventContext; /*0x10 */ 1350} MPI2_EVENT_ACK_REQUEST, *PTR_MPI2_EVENT_ACK_REQUEST, 1351 Mpi2EventAckRequest_t, *pMpi2EventAckRequest_t; 1352 1353/*EventAck Reply message */ 1354typedef struct _MPI2_EVENT_ACK_REPLY { 1355 U16 Reserved1; /*0x00 */ 1356 U8 MsgLength; /*0x02 */ 1357 U8 Function; /*0x03 */ 1358 U16 Reserved2; /*0x04 */ 1359 U8 Reserved3; /*0x06 */ 1360 U8 MsgFlags; /*0x07 */ 1361 U8 VP_ID; /*0x08 */ 1362 U8 VF_ID; /*0x09 */ 1363 U16 Reserved4; /*0x0A */ 1364 U16 Reserved5; /*0x0C */ 1365 U16 IOCStatus; /*0x0E */ 1366 U32 IOCLogInfo; /*0x10 */ 1367} MPI2_EVENT_ACK_REPLY, *PTR_MPI2_EVENT_ACK_REPLY, 1368 Mpi2EventAckReply_t, *pMpi2EventAckReply_t; 1369 1370/**************************************************************************** 1371* SendHostMessage message 1372****************************************************************************/ 1373 1374/*SendHostMessage Request message */ 1375typedef struct _MPI2_SEND_HOST_MESSAGE_REQUEST { 1376 U16 HostDataLength; /*0x00 */ 1377 U8 ChainOffset; /*0x02 */ 1378 U8 Function; /*0x03 */ 1379 U16 Reserved1; /*0x04 */ 1380 U8 Reserved2; /*0x06 */ 1381 U8 MsgFlags; /*0x07 */ 1382 U8 VP_ID; /*0x08 */ 1383 U8 VF_ID; /*0x09 */ 1384 U16 Reserved3; /*0x0A */ 1385 U8 Reserved4; /*0x0C */ 1386 U8 DestVF_ID; /*0x0D */ 1387 U16 Reserved5; /*0x0E */ 1388 U32 Reserved6; /*0x10 */ 1389 U32 Reserved7; /*0x14 */ 1390 U32 Reserved8; /*0x18 */ 1391 U32 Reserved9; /*0x1C */ 1392 U32 Reserved10; /*0x20 */ 1393 U32 HostData[]; /*0x24 */ 1394} MPI2_SEND_HOST_MESSAGE_REQUEST, 1395 *PTR_MPI2_SEND_HOST_MESSAGE_REQUEST, 1396 Mpi2SendHostMessageRequest_t, 1397 *pMpi2SendHostMessageRequest_t; 1398 1399/*SendHostMessage Reply message */ 1400typedef struct _MPI2_SEND_HOST_MESSAGE_REPLY { 1401 U16 HostDataLength; /*0x00 */ 1402 U8 MsgLength; /*0x02 */ 1403 U8 Function; /*0x03 */ 1404 U16 Reserved1; /*0x04 */ 1405 U8 Reserved2; /*0x06 */ 1406 U8 MsgFlags; /*0x07 */ 1407 U8 VP_ID; /*0x08 */ 1408 U8 VF_ID; /*0x09 */ 1409 U16 Reserved3; /*0x0A */ 1410 U16 Reserved4; /*0x0C */ 1411 U16 IOCStatus; /*0x0E */ 1412 U32 IOCLogInfo; /*0x10 */ 1413} MPI2_SEND_HOST_MESSAGE_REPLY, *PTR_MPI2_SEND_HOST_MESSAGE_REPLY, 1414 Mpi2SendHostMessageReply_t, *pMpi2SendHostMessageReply_t; 1415 1416/**************************************************************************** 1417* FWDownload message 1418****************************************************************************/ 1419 1420/*MPI v2.0 FWDownload Request message */ 1421typedef struct _MPI2_FW_DOWNLOAD_REQUEST { 1422 U8 ImageType; /*0x00 */ 1423 U8 Reserved1; /*0x01 */ 1424 U8 ChainOffset; /*0x02 */ 1425 U8 Function; /*0x03 */ 1426 U16 Reserved2; /*0x04 */ 1427 U8 Reserved3; /*0x06 */ 1428 U8 MsgFlags; /*0x07 */ 1429 U8 VP_ID; /*0x08 */ 1430 U8 VF_ID; /*0x09 */ 1431 U16 Reserved4; /*0x0A */ 1432 U32 TotalImageSize; /*0x0C */ 1433 U32 Reserved5; /*0x10 */ 1434 MPI2_MPI_SGE_UNION SGL; /*0x14 */ 1435} MPI2_FW_DOWNLOAD_REQUEST, *PTR_MPI2_FW_DOWNLOAD_REQUEST, 1436 Mpi2FWDownloadRequest, *pMpi2FWDownloadRequest; 1437 1438#define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01) 1439 1440#define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01) 1441#define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02) 1442#define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06) 1443#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07) 1444#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08) 1445#define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09) 1446#define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A) 1447#define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) 1448#define MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY (0x0C) 1449#define MPI2_FW_DOWNLOAD_ITYPE_CBB_BACKUP (0x0D) 1450#define MPI2_FW_DOWNLOAD_ITYPE_SBR (0x0E) 1451#define MPI2_FW_DOWNLOAD_ITYPE_SBR_BACKUP (0x0F) 1452#define MPI2_FW_DOWNLOAD_ITYPE_HIIM (0x10) 1453#define MPI2_FW_DOWNLOAD_ITYPE_HIIA (0x11) 1454#define MPI2_FW_DOWNLOAD_ITYPE_CTLR (0x12) 1455#define MPI2_FW_DOWNLOAD_ITYPE_IMR_FIRMWARE (0x13) 1456#define MPI2_FW_DOWNLOAD_ITYPE_MR_NVDATA (0x14) 1457/*MPI v2.6 and newer */ 1458#define MPI2_FW_DOWNLOAD_ITYPE_CPLD (0x15) 1459#define MPI2_FW_DOWNLOAD_ITYPE_PSOC (0x16) 1460#define MPI2_FW_DOWNLOAD_ITYPE_COREDUMP (0x17) 1461#define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0) 1462 1463/*MPI v2.0 FWDownload TransactionContext Element */ 1464typedef struct _MPI2_FW_DOWNLOAD_TCSGE { 1465 U8 Reserved1; /*0x00 */ 1466 U8 ContextSize; /*0x01 */ 1467 U8 DetailsLength; /*0x02 */ 1468 U8 Flags; /*0x03 */ 1469 U32 Reserved2; /*0x04 */ 1470 U32 ImageOffset; /*0x08 */ 1471 U32 ImageSize; /*0x0C */ 1472} MPI2_FW_DOWNLOAD_TCSGE, *PTR_MPI2_FW_DOWNLOAD_TCSGE, 1473 Mpi2FWDownloadTCSGE_t, *pMpi2FWDownloadTCSGE_t; 1474 1475/*MPI v2.5 FWDownload Request message */ 1476typedef struct _MPI25_FW_DOWNLOAD_REQUEST { 1477 U8 ImageType; /*0x00 */ 1478 U8 Reserved1; /*0x01 */ 1479 U8 ChainOffset; /*0x02 */ 1480 U8 Function; /*0x03 */ 1481 U16 Reserved2; /*0x04 */ 1482 U8 Reserved3; /*0x06 */ 1483 U8 MsgFlags; /*0x07 */ 1484 U8 VP_ID; /*0x08 */ 1485 U8 VF_ID; /*0x09 */ 1486 U16 Reserved4; /*0x0A */ 1487 U32 TotalImageSize; /*0x0C */ 1488 U32 Reserved5; /*0x10 */ 1489 U32 Reserved6; /*0x14 */ 1490 U32 ImageOffset; /*0x18 */ 1491 U32 ImageSize; /*0x1C */ 1492 MPI25_SGE_IO_UNION SGL; /*0x20 */ 1493} MPI25_FW_DOWNLOAD_REQUEST, *PTR_MPI25_FW_DOWNLOAD_REQUEST, 1494 Mpi25FWDownloadRequest, *pMpi25FWDownloadRequest; 1495 1496/*FWDownload Reply message */ 1497typedef struct _MPI2_FW_DOWNLOAD_REPLY { 1498 U8 ImageType; /*0x00 */ 1499 U8 Reserved1; /*0x01 */ 1500 U8 MsgLength; /*0x02 */ 1501 U8 Function; /*0x03 */ 1502 U16 Reserved2; /*0x04 */ 1503 U8 Reserved3; /*0x06 */ 1504 U8 MsgFlags; /*0x07 */ 1505 U8 VP_ID; /*0x08 */ 1506 U8 VF_ID; /*0x09 */ 1507 U16 Reserved4; /*0x0A */ 1508 U16 Reserved5; /*0x0C */ 1509 U16 IOCStatus; /*0x0E */ 1510 U32 IOCLogInfo; /*0x10 */ 1511} MPI2_FW_DOWNLOAD_REPLY, *PTR_MPI2_FW_DOWNLOAD_REPLY, 1512 Mpi2FWDownloadReply_t, *pMpi2FWDownloadReply_t; 1513 1514/**************************************************************************** 1515* FWUpload message 1516****************************************************************************/ 1517 1518/*MPI v2.0 FWUpload Request message */ 1519typedef struct _MPI2_FW_UPLOAD_REQUEST { 1520 U8 ImageType; /*0x00 */ 1521 U8 Reserved1; /*0x01 */ 1522 U8 ChainOffset; /*0x02 */ 1523 U8 Function; /*0x03 */ 1524 U16 Reserved2; /*0x04 */ 1525 U8 Reserved3; /*0x06 */ 1526 U8 MsgFlags; /*0x07 */ 1527 U8 VP_ID; /*0x08 */ 1528 U8 VF_ID; /*0x09 */ 1529 U16 Reserved4; /*0x0A */ 1530 U32 Reserved5; /*0x0C */ 1531 U32 Reserved6; /*0x10 */ 1532 MPI2_MPI_SGE_UNION SGL; /*0x14 */ 1533} MPI2_FW_UPLOAD_REQUEST, *PTR_MPI2_FW_UPLOAD_REQUEST, 1534 Mpi2FWUploadRequest_t, *pMpi2FWUploadRequest_t; 1535 1536#define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00) 1537#define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01) 1538#define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02) 1539#define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05) 1540#define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06) 1541#define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07) 1542#define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08) 1543#define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09) 1544#define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A) 1545#define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) 1546#define MPI2_FW_UPLOAD_ITYPE_CBB_BACKUP (0x0D) 1547#define MPI2_FW_UPLOAD_ITYPE_SBR (0x0E) 1548#define MPI2_FW_UPLOAD_ITYPE_SBR_BACKUP (0x0F) 1549#define MPI2_FW_UPLOAD_ITYPE_HIIM (0x10) 1550#define MPI2_FW_UPLOAD_ITYPE_HIIA (0x11) 1551#define MPI2_FW_UPLOAD_ITYPE_CTLR (0x12) 1552#define MPI2_FW_UPLOAD_ITYPE_IMR_FIRMWARE (0x13) 1553#define MPI2_FW_UPLOAD_ITYPE_MR_NVDATA (0x14) 1554 1555 1556/*MPI v2.0 FWUpload TransactionContext Element */ 1557typedef struct _MPI2_FW_UPLOAD_TCSGE { 1558 U8 Reserved1; /*0x00 */ 1559 U8 ContextSize; /*0x01 */ 1560 U8 DetailsLength; /*0x02 */ 1561 U8 Flags; /*0x03 */ 1562 U32 Reserved2; /*0x04 */ 1563 U32 ImageOffset; /*0x08 */ 1564 U32 ImageSize; /*0x0C */ 1565} MPI2_FW_UPLOAD_TCSGE, *PTR_MPI2_FW_UPLOAD_TCSGE, 1566 Mpi2FWUploadTCSGE_t, *pMpi2FWUploadTCSGE_t; 1567 1568/*MPI v2.5 FWUpload Request message */ 1569typedef struct _MPI25_FW_UPLOAD_REQUEST { 1570 U8 ImageType; /*0x00 */ 1571 U8 Reserved1; /*0x01 */ 1572 U8 ChainOffset; /*0x02 */ 1573 U8 Function; /*0x03 */ 1574 U16 Reserved2; /*0x04 */ 1575 U8 Reserved3; /*0x06 */ 1576 U8 MsgFlags; /*0x07 */ 1577 U8 VP_ID; /*0x08 */ 1578 U8 VF_ID; /*0x09 */ 1579 U16 Reserved4; /*0x0A */ 1580 U32 Reserved5; /*0x0C */ 1581 U32 Reserved6; /*0x10 */ 1582 U32 Reserved7; /*0x14 */ 1583 U32 ImageOffset; /*0x18 */ 1584 U32 ImageSize; /*0x1C */ 1585 MPI25_SGE_IO_UNION SGL; /*0x20 */ 1586} MPI25_FW_UPLOAD_REQUEST, *PTR_MPI25_FW_UPLOAD_REQUEST, 1587 Mpi25FWUploadRequest_t, *pMpi25FWUploadRequest_t; 1588 1589/*FWUpload Reply message */ 1590typedef struct _MPI2_FW_UPLOAD_REPLY { 1591 U8 ImageType; /*0x00 */ 1592 U8 Reserved1; /*0x01 */ 1593 U8 MsgLength; /*0x02 */ 1594 U8 Function; /*0x03 */ 1595 U16 Reserved2; /*0x04 */ 1596 U8 Reserved3; /*0x06 */ 1597 U8 MsgFlags; /*0x07 */ 1598 U8 VP_ID; /*0x08 */ 1599 U8 VF_ID; /*0x09 */ 1600 U16 Reserved4; /*0x0A */ 1601 U16 Reserved5; /*0x0C */ 1602 U16 IOCStatus; /*0x0E */ 1603 U32 IOCLogInfo; /*0x10 */ 1604 U32 ActualImageSize; /*0x14 */ 1605} MPI2_FW_UPLOAD_REPLY, *PTR_MPI2_FW_UPLOAD_REPLY, 1606 Mpi2FWUploadReply_t, *pMPi2FWUploadReply_t; 1607 1608 1609/**************************************************************************** 1610* PowerManagementControl message 1611****************************************************************************/ 1612 1613/*PowerManagementControl Request message */ 1614typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST { 1615 U8 Feature; /*0x00 */ 1616 U8 Reserved1; /*0x01 */ 1617 U8 ChainOffset; /*0x02 */ 1618 U8 Function; /*0x03 */ 1619 U16 Reserved2; /*0x04 */ 1620 U8 Reserved3; /*0x06 */ 1621 U8 MsgFlags; /*0x07 */ 1622 U8 VP_ID; /*0x08 */ 1623 U8 VF_ID; /*0x09 */ 1624 U16 Reserved4; /*0x0A */ 1625 U8 Parameter1; /*0x0C */ 1626 U8 Parameter2; /*0x0D */ 1627 U8 Parameter3; /*0x0E */ 1628 U8 Parameter4; /*0x0F */ 1629 U32 Reserved5; /*0x10 */ 1630 U32 Reserved6; /*0x14 */ 1631} MPI2_PWR_MGMT_CONTROL_REQUEST, *PTR_MPI2_PWR_MGMT_CONTROL_REQUEST, 1632 Mpi2PwrMgmtControlRequest_t, *pMpi2PwrMgmtControlRequest_t; 1633 1634/*defines for the Feature field */ 1635#define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND (0x01) 1636#define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION (0x02) 1637#define MPI2_PM_CONTROL_FEATURE_PCIE_LINK (0x03) /*obsolete */ 1638#define MPI2_PM_CONTROL_FEATURE_IOC_SPEED (0x04) 1639#define MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE (0x05) 1640#define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC (0x80) 1641#define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC (0xFF) 1642 1643/*parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */ 1644/*Parameter1 contains a PHY number */ 1645/*Parameter2 indicates power condition action using these defines */ 1646#define MPI2_PM_CONTROL_PARAM2_PARTIAL (0x01) 1647#define MPI2_PM_CONTROL_PARAM2_SLUMBER (0x02) 1648#define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT (0x03) 1649/*Parameter3 and Parameter4 are reserved */ 1650 1651/*parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION 1652 * Feature */ 1653/*Parameter1 contains SAS port width modulation group number */ 1654/*Parameter2 indicates IOC action using these defines */ 1655#define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP (0x01) 1656#define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION (0x02) 1657#define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP (0x03) 1658/*Parameter3 indicates desired modulation level using these defines */ 1659#define MPI2_PM_CONTROL_PARAM3_25_PERCENT (0x00) 1660#define MPI2_PM_CONTROL_PARAM3_50_PERCENT (0x01) 1661#define MPI2_PM_CONTROL_PARAM3_75_PERCENT (0x02) 1662#define MPI2_PM_CONTROL_PARAM3_100_PERCENT (0x03) 1663/*Parameter4 is reserved */ 1664 1665/*this next set (_PCIE_LINK) is obsolete */ 1666/*parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */ 1667/*Parameter1 indicates desired PCIe link speed using these defines */ 1668#define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS (0x00) /*obsolete */ 1669#define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS (0x01) /*obsolete */ 1670#define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS (0x02) /*obsolete */ 1671/*Parameter2 indicates desired PCIe link width using these defines */ 1672#define MPI2_PM_CONTROL_PARAM2_WIDTH_X1 (0x01) /*obsolete */ 1673#define MPI2_PM_CONTROL_PARAM2_WIDTH_X2 (0x02) /*obsolete */ 1674#define MPI2_PM_CONTROL_PARAM2_WIDTH_X4 (0x04) /*obsolete */ 1675#define MPI2_PM_CONTROL_PARAM2_WIDTH_X8 (0x08) /*obsolete */ 1676/*Parameter3 and Parameter4 are reserved */ 1677 1678/*parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */ 1679/*Parameter1 indicates desired IOC hardware clock speed using these defines */ 1680#define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED (0x01) 1681#define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED (0x02) 1682#define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED (0x04) 1683#define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED (0x08) 1684/*Parameter2, Parameter3, and Parameter4 are reserved */ 1685 1686/*parameter usage for the MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE Feature*/ 1687/*Parameter1 indicates host action regarding global power management mode */ 1688#define MPI2_PM_CONTROL_PARAM1_TAKE_CONTROL (0x01) 1689#define MPI2_PM_CONTROL_PARAM1_CHANGE_GLOBAL_MODE (0x02) 1690#define MPI2_PM_CONTROL_PARAM1_RELEASE_CONTROL (0x03) 1691/*Parameter2 indicates the requested global power management mode */ 1692#define MPI2_PM_CONTROL_PARAM2_FULL_PWR_PERF (0x01) 1693#define MPI2_PM_CONTROL_PARAM2_REDUCED_PWR_PERF (0x08) 1694#define MPI2_PM_CONTROL_PARAM2_STANDBY (0x40) 1695/*Parameter3 and Parameter4 are reserved */ 1696 1697/*PowerManagementControl Reply message */ 1698typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY { 1699 U8 Feature; /*0x00 */ 1700 U8 Reserved1; /*0x01 */ 1701 U8 MsgLength; /*0x02 */ 1702 U8 Function; /*0x03 */ 1703 U16 Reserved2; /*0x04 */ 1704 U8 Reserved3; /*0x06 */ 1705 U8 MsgFlags; /*0x07 */ 1706 U8 VP_ID; /*0x08 */ 1707 U8 VF_ID; /*0x09 */ 1708 U16 Reserved4; /*0x0A */ 1709 U16 Reserved5; /*0x0C */ 1710 U16 IOCStatus; /*0x0E */ 1711 U32 IOCLogInfo; /*0x10 */ 1712} MPI2_PWR_MGMT_CONTROL_REPLY, *PTR_MPI2_PWR_MGMT_CONTROL_REPLY, 1713 Mpi2PwrMgmtControlReply_t, *pMpi2PwrMgmtControlReply_t; 1714 1715/**************************************************************************** 1716* IO Unit Control messages (MPI v2.6 and later only.) 1717****************************************************************************/ 1718 1719/* IO Unit Control Request Message */ 1720typedef struct _MPI26_IOUNIT_CONTROL_REQUEST { 1721 U8 Operation; /* 0x00 */ 1722 U8 Reserved1; /* 0x01 */ 1723 U8 ChainOffset; /* 0x02 */ 1724 U8 Function; /* 0x03 */ 1725 U16 DevHandle; /* 0x04 */ 1726 U8 IOCParameter; /* 0x06 */ 1727 U8 MsgFlags; /* 0x07 */ 1728 U8 VP_ID; /* 0x08 */ 1729 U8 VF_ID; /* 0x09 */ 1730 U16 Reserved3; /* 0x0A */ 1731 U16 Reserved4; /* 0x0C */ 1732 U8 PhyNum; /* 0x0E */ 1733 U8 PrimFlags; /* 0x0F */ 1734 U32 Primitive; /* 0x10 */ 1735 U8 LookupMethod; /* 0x14 */ 1736 U8 Reserved5; /* 0x15 */ 1737 U16 SlotNumber; /* 0x16 */ 1738 U64 LookupAddress; /* 0x18 */ 1739 U32 IOCParameterValue; /* 0x20 */ 1740 U32 Reserved7; /* 0x24 */ 1741 U32 Reserved8; /* 0x28 */ 1742} MPI26_IOUNIT_CONTROL_REQUEST, 1743 *PTR_MPI26_IOUNIT_CONTROL_REQUEST, 1744 Mpi26IoUnitControlRequest_t, 1745 *pMpi26IoUnitControlRequest_t; 1746 1747/* values for the Operation field */ 1748#define MPI26_CTRL_OP_CLEAR_ALL_PERSISTENT (0x02) 1749#define MPI26_CTRL_OP_SAS_PHY_LINK_RESET (0x06) 1750#define MPI26_CTRL_OP_SAS_PHY_HARD_RESET (0x07) 1751#define MPI26_CTRL_OP_PHY_CLEAR_ERROR_LOG (0x08) 1752#define MPI26_CTRL_OP_LINK_CLEAR_ERROR_LOG (0x09) 1753#define MPI26_CTRL_OP_SAS_SEND_PRIMITIVE (0x0A) 1754#define MPI26_CTRL_OP_FORCE_FULL_DISCOVERY (0x0B) 1755#define MPI26_CTRL_OP_REMOVE_DEVICE (0x0D) 1756#define MPI26_CTRL_OP_LOOKUP_MAPPING (0x0E) 1757#define MPI26_CTRL_OP_SET_IOC_PARAMETER (0x0F) 1758#define MPI26_CTRL_OP_ENABLE_FP_DEVICE (0x10) 1759#define MPI26_CTRL_OP_DISABLE_FP_DEVICE (0x11) 1760#define MPI26_CTRL_OP_ENABLE_FP_ALL (0x12) 1761#define MPI26_CTRL_OP_DISABLE_FP_ALL (0x13) 1762#define MPI26_CTRL_OP_DEV_ENABLE_NCQ (0x14) 1763#define MPI26_CTRL_OP_DEV_DISABLE_NCQ (0x15) 1764#define MPI26_CTRL_OP_SHUTDOWN (0x16) 1765#define MPI26_CTRL_OP_DEV_ENABLE_PERSIST_CONNECTION (0x17) 1766#define MPI26_CTRL_OP_DEV_DISABLE_PERSIST_CONNECTION (0x18) 1767#define MPI26_CTRL_OP_DEV_CLOSE_PERSIST_CONNECTION (0x19) 1768#define MPI26_CTRL_OP_ENABLE_NVME_SGL_FORMAT (0x1A) 1769#define MPI26_CTRL_OP_DISABLE_NVME_SGL_FORMAT (0x1B) 1770#define MPI26_CTRL_OP_PRODUCT_SPECIFIC_MIN (0x80) 1771 1772/* values for the PrimFlags field */ 1773#define MPI26_CTRL_PRIMFLAGS_SINGLE (0x08) 1774#define MPI26_CTRL_PRIMFLAGS_TRIPLE (0x02) 1775#define MPI26_CTRL_PRIMFLAGS_REDUNDANT (0x01) 1776 1777/* values for the LookupMethod field */ 1778#define MPI26_CTRL_LOOKUP_METHOD_WWID_ADDRESS (0x01) 1779#define MPI26_CTRL_LOOKUP_METHOD_ENCLOSURE_SLOT (0x02) 1780#define MPI26_CTRL_LOOKUP_METHOD_SAS_DEVICE_NAME (0x03) 1781 1782 1783/* IO Unit Control Reply Message */ 1784typedef struct _MPI26_IOUNIT_CONTROL_REPLY { 1785 U8 Operation; /* 0x00 */ 1786 U8 Reserved1; /* 0x01 */ 1787 U8 MsgLength; /* 0x02 */ 1788 U8 Function; /* 0x03 */ 1789 U16 DevHandle; /* 0x04 */ 1790 U8 IOCParameter; /* 0x06 */ 1791 U8 MsgFlags; /* 0x07 */ 1792 U8 VP_ID; /* 0x08 */ 1793 U8 VF_ID; /* 0x09 */ 1794 U16 Reserved3; /* 0x0A */ 1795 U16 Reserved4; /* 0x0C */ 1796 U16 IOCStatus; /* 0x0E */ 1797 U32 IOCLogInfo; /* 0x10 */ 1798} MPI26_IOUNIT_CONTROL_REPLY, 1799 *PTR_MPI26_IOUNIT_CONTROL_REPLY, 1800 Mpi26IoUnitControlReply_t, 1801 *pMpi26IoUnitControlReply_t; 1802 1803/**************************************************************************** 1804 * MCTP Passthrough messages (MPI v2.6 and later only.) 1805 ****************************************************************************/ 1806 1807/* MCTP Passthrough Request Message */ 1808typedef struct _MPI26_MCTP_PASSTHROUGH_REQUEST { 1809 U8 MsgContext; /* 0x00 */ 1810 U8 Reserved1[2]; /* 0x01 */ 1811 U8 Function; /* 0x03 */ 1812 U8 Reserved2[3]; /* 0x04 */ 1813 U8 MsgFlags; /* 0x07 */ 1814 U8 VP_ID; /* 0x08 */ 1815 U8 VF_ID; /* 0x09 */ 1816 U16 Reserved3; /* 0x0A */ 1817 U32 Reserved4; /* 0x0C */ 1818 U8 Flags; /* 0x10 */ 1819 U8 Reserved5[3]; /* 0x11 */ 1820 U32 Reserved6; /* 0x14 */ 1821 U32 H2DLength; /* 0x18 */ 1822 U32 D2HLength; /* 0x1C */ 1823 MPI25_SGE_IO_UNION H2DSGL; /* 0x20 */ 1824 MPI25_SGE_IO_UNION D2HSGL; /* 0x30 */ 1825} MPI26_MCTP_PASSTHROUGH_REQUEST, 1826 *PTR_MPI26_MCTP_PASSTHROUGH_REQUEST, 1827 Mpi26MctpPassthroughRequest_t, 1828 *pMpi26MctpPassthroughRequest_t; 1829 1830/* values for the MsgContext field */ 1831#define MPI26_MCTP_MSG_CONEXT_UNUSED (0x00) 1832 1833/* values for the Flags field */ 1834#define MPI26_MCTP_FLAGS_MSG_FORMAT_MPT (0x01) 1835 1836/* MCTP Passthrough Reply Message */ 1837typedef struct _MPI26_MCTP_PASSTHROUGH_REPLY { 1838 U8 MsgContext; /* 0x00 */ 1839 U8 Reserved1; /* 0x01 */ 1840 U8 MsgLength; /* 0x02 */ 1841 U8 Function; /* 0x03 */ 1842 U8 Reserved2[3]; /* 0x04 */ 1843 U8 MsgFlags; /* 0x07 */ 1844 U8 VP_ID; /* 0x08 */ 1845 U8 VF_ID; /* 0x09 */ 1846 U16 Reserved3; /* 0x0A */ 1847 U16 Reserved4; /* 0x0C */ 1848 U16 IOCStatus; /* 0x0E */ 1849 U32 IOCLogInfo; /* 0x10 */ 1850 U32 ResponseDataLength; /* 0x14 */ 1851} MPI26_MCTP_PASSTHROUGH_REPLY, 1852 *PTR_MPI26_MCTP_PASSTHROUGH_REPLY, 1853 Mpi26MctpPassthroughReply_t, 1854 *pMpi26MctpPassthroughReply_t; 1855 1856#endif
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