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mpi2.h
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linux-6.19.14/drivers/scsi/mpt3sas/mpi/mpi2.h
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright 2000-2020 Broadcom Inc. All rights reserved. 4 * 5 * 6 * Name: mpi2.h 7 * Title: MPI Message independent structures and definitions 8 * including System Interface Register Set and 9 * scatter/gather formats. 10 * Creation Date: June 21, 2006 11 * 12 * mpi2.h Version: 02.00.54 13 * 14 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 15 * prefix are for use only on MPI v2.5 products, and must not be used 16 * with MPI v2.0 products. Unless otherwise noted, names beginning with 17 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 18 * 19 * Version History 20 * --------------- 21 * 22 * Date Version Description 23 * -------- -------- ------------------------------------------------------ 24 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 25 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT. 26 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT. 27 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT. 28 * Moved ReplyPostHostIndex register to offset 0x6C of the 29 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for 30 * MPI2_REPLY_POST_HOST_INDEX_OFFSET. 31 * Added union of request descriptors. 32 * Added union of reply descriptors. 33 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT. 34 * Added define for MPI2_VERSION_02_00. 35 * Fixed the size of the FunctionDependent5 field in the 36 * MPI2_DEFAULT_REPLY structure. 37 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT. 38 * Removed the MPI-defined Fault Codes and extended the 39 * product specific codes up to 0xEFFF. 40 * Added a sixth key value for the WriteSequence register 41 * and changed the flush value to 0x0. 42 * Added message function codes for Diagnostic Buffer Post 43 * and Diagnsotic Release. 44 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED 45 * Moved MPI2_VERSION_UNION from mpi2_ioc.h. 46 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT. 47 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT. 48 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT. 49 * Added #defines for marking a reply descriptor as unused. 50 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT. 51 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT. 52 * Moved LUN field defines from mpi2_init.h. 53 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT. 54 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT. 55 * In all request and reply descriptors, replaced VF_ID 56 * field with MSIxIndex field. 57 * Removed DevHandle field from 58 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those 59 * bytes reserved. 60 * Added RAID Accelerator functionality. 61 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT. 62 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT. 63 * Added MSI-x index mask and shift for Reply Post Host 64 * Index register. 65 * Added function code for Host Based Discovery Action. 66 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT. 67 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL. 68 * Added defines for product-specific range of message 69 * function codes, 0xF0 to 0xFF. 70 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT. 71 * Added alternative defines for the SGE Direction bit. 72 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT. 73 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT. 74 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define. 75 * 02-23-11 02.00.19 Bumped MPI2_HEADER_VERSION_UNIT. 76 * Added MPI2_FUNCTION_SEND_HOST_MESSAGE. 77 * 03-09-11 02.00.20 Bumped MPI2_HEADER_VERSION_UNIT. 78 * 05-25-11 02.00.21 Bumped MPI2_HEADER_VERSION_UNIT. 79 * 08-24-11 02.00.22 Bumped MPI2_HEADER_VERSION_UNIT. 80 * 11-18-11 02.00.23 Bumped MPI2_HEADER_VERSION_UNIT. 81 * Incorporating additions for MPI v2.5. 82 * 02-06-12 02.00.24 Bumped MPI2_HEADER_VERSION_UNIT. 83 * 03-29-12 02.00.25 Bumped MPI2_HEADER_VERSION_UNIT. 84 * Added Hard Reset delay timings. 85 * 07-10-12 02.00.26 Bumped MPI2_HEADER_VERSION_UNIT. 86 * 07-26-12 02.00.27 Bumped MPI2_HEADER_VERSION_UNIT. 87 * 11-27-12 02.00.28 Bumped MPI2_HEADER_VERSION_UNIT. 88 * 12-20-12 02.00.29 Bumped MPI2_HEADER_VERSION_UNIT. 89 * Added MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET. 90 * 04-09-13 02.00.30 Bumped MPI2_HEADER_VERSION_UNIT. 91 * 04-17-13 02.00.31 Bumped MPI2_HEADER_VERSION_UNIT. 92 * 08-19-13 02.00.32 Bumped MPI2_HEADER_VERSION_UNIT. 93 * 12-05-13 02.00.33 Bumped MPI2_HEADER_VERSION_UNIT. 94 * 01-08-14 02.00.34 Bumped MPI2_HEADER_VERSION_UNIT 95 * 06-13-14 02.00.35 Bumped MPI2_HEADER_VERSION_UNIT. 96 * 11-18-14 02.00.36 Updated copyright information. 97 * Bumped MPI2_HEADER_VERSION_UNIT. 98 * 03-16-15 02.00.37 Bumped MPI2_HEADER_VERSION_UNIT. 99 * Added Scratchpad registers to 100 * MPI2_SYSTEM_INTERFACE_REGS. 101 * Added MPI2_DIAG_SBR_RELOAD. 102 * 03-19-15 02.00.38 Bumped MPI2_HEADER_VERSION_UNIT. 103 * 05-25-15 02.00.39 Bumped MPI2_HEADER_VERSION_UNIT. 104 * 08-25-15 02.00.40 Bumped MPI2_HEADER_VERSION_UNIT. 105 * 12-15-15 02.00.41 Bumped MPI_HEADER_VERSION_UNIT 106 * 01-01-16 02.00.42 Bumped MPI_HEADER_VERSION_UNIT 107 * 04-05-16 02.00.43 Modified MPI26_DIAG_BOOT_DEVICE_SELECT defines 108 * to be unique within first 32 characters. 109 * Removed AHCI support. 110 * Removed SOP support. 111 * Bumped MPI2_HEADER_VERSION_UNIT. 112 * 04-10-16 02.00.44 Bumped MPI2_HEADER_VERSION_UNIT. 113 * 07-06-16 02.00.45 Bumped MPI2_HEADER_VERSION_UNIT. 114 * 09-02-16 02.00.46 Bumped MPI2_HEADER_VERSION_UNIT. 115 * 11-23-16 02.00.47 Bumped MPI2_HEADER_VERSION_UNIT. 116 * 02-03-17 02.00.48 Bumped MPI2_HEADER_VERSION_UNIT. 117 * 06-13-17 02.00.49 Bumped MPI2_HEADER_VERSION_UNIT. 118 * 09-29-17 02.00.50 Bumped MPI2_HEADER_VERSION_UNIT. 119 * 07-22-18 02.00.51 Added SECURE_BOOT define. 120 * Bumped MPI2_HEADER_VERSION_UNIT 121 * 08-15-18 02.00.52 Bumped MPI2_HEADER_VERSION_UNIT. 122 * 08-28-18 02.00.53 Bumped MPI2_HEADER_VERSION_UNIT. 123 * Added MPI2_IOCSTATUS_FAILURE 124 * 12-17-18 02.00.54 Bumped MPI2_HEADER_VERSION_UNIT 125 * 06-24-19 02.00.55 Bumped MPI2_HEADER_VERSION_UNIT 126 * 08-01-19 02.00.56 Bumped MPI2_HEADER_VERSION_UNIT 127 * 10-02-19 02.00.57 Bumped MPI2_HEADER_VERSION_UNIT 128 * 07-20-20 02.00.58 Bumped MPI2_HEADER_VERSION_UNIT 129 * 03-30-21 02.00.59 Bumped MPI2_HEADER_VERSION_UNIT 130 * 06-03-22 02.00.60 Bumped MPI2_HEADER_VERSION_UNIT 131 * 09-20-23 02.00.61 Bumped MPI2_HEADER_VERSION_UNIT 132 * 09-13-24 02.00.62 Bumped MPI2_HEADER_VERSION_UNIT 133 * Added MPI2_FUNCTION_MCTP_PASSTHROUGH 134 * -------------------------------------------------------------------------- 135 */ 136 137#ifndef MPI2_H 138#define MPI2_H 139 140/***************************************************************************** 141* 142* MPI Version Definitions 143* 144*****************************************************************************/ 145 146#define MPI2_VERSION_MAJOR_MASK (0xFF00) 147#define MPI2_VERSION_MAJOR_SHIFT (8) 148#define MPI2_VERSION_MINOR_MASK (0x00FF) 149#define MPI2_VERSION_MINOR_SHIFT (0) 150 151/*major version for all MPI v2.x */ 152#define MPI2_VERSION_MAJOR (0x02) 153 154/*minor version for MPI v2.0 compatible products */ 155#define MPI2_VERSION_MINOR (0x00) 156#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 157 MPI2_VERSION_MINOR) 158#define MPI2_VERSION_02_00 (0x0200) 159 160/*minor version for MPI v2.5 compatible products */ 161#define MPI25_VERSION_MINOR (0x05) 162#define MPI25_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 163 MPI25_VERSION_MINOR) 164#define MPI2_VERSION_02_05 (0x0205) 165 166/*minor version for MPI v2.6 compatible products */ 167#define MPI26_VERSION_MINOR (0x06) 168#define MPI26_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 169 MPI26_VERSION_MINOR) 170#define MPI2_VERSION_02_06 (0x0206) 171 172 173/* Unit and Dev versioning for this MPI header set */ 174#define MPI2_HEADER_VERSION_UNIT (0x3E) 175#define MPI2_HEADER_VERSION_DEV (0x00) 176#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 177#define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 178#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 179#define MPI2_HEADER_VERSION_DEV_SHIFT (0) 180#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \ 181 MPI2_HEADER_VERSION_DEV) 182 183/***************************************************************************** 184* 185* IOC State Definitions 186* 187*****************************************************************************/ 188 189#define MPI2_IOC_STATE_RESET (0x00000000) 190#define MPI2_IOC_STATE_READY (0x10000000) 191#define MPI2_IOC_STATE_OPERATIONAL (0x20000000) 192#define MPI2_IOC_STATE_FAULT (0x40000000) 193#define MPI2_IOC_STATE_COREDUMP (0x50000000) 194 195#define MPI2_IOC_STATE_MASK (0xF0000000) 196#define MPI2_IOC_STATE_SHIFT (28) 197 198/*Fault state range for prodcut specific codes */ 199#define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000) 200#define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF) 201 202/***************************************************************************** 203* 204* System Interface Register Definitions 205* 206*****************************************************************************/ 207 208typedef struct _MPI2_SYSTEM_INTERFACE_REGS { 209 U32 Doorbell; /*0x00 */ 210 U32 WriteSequence; /*0x04 */ 211 U32 HostDiagnostic; /*0x08 */ 212 U32 Reserved1; /*0x0C */ 213 U32 DiagRWData; /*0x10 */ 214 U32 DiagRWAddressLow; /*0x14 */ 215 U32 DiagRWAddressHigh; /*0x18 */ 216 U32 Reserved2[5]; /*0x1C */ 217 U32 HostInterruptStatus; /*0x30 */ 218 U32 HostInterruptMask; /*0x34 */ 219 U32 DCRData; /*0x38 */ 220 U32 DCRAddress; /*0x3C */ 221 U32 Reserved3[2]; /*0x40 */ 222 U32 ReplyFreeHostIndex; /*0x48 */ 223 U32 Reserved4[8]; /*0x4C */ 224 U32 ReplyPostHostIndex; /*0x6C */ 225 U32 Reserved5; /*0x70 */ 226 U32 HCBSize; /*0x74 */ 227 U32 HCBAddressLow; /*0x78 */ 228 U32 HCBAddressHigh; /*0x7C */ 229 U32 Reserved6[12]; /*0x80 */ 230 U32 Scratchpad[4]; /*0xB0 */ 231 U32 RequestDescriptorPostLow; /*0xC0 */ 232 U32 RequestDescriptorPostHigh; /*0xC4 */ 233 U32 AtomicRequestDescriptorPost;/*0xC8 */ 234 U32 Reserved7[13]; /*0xCC */ 235} MPI2_SYSTEM_INTERFACE_REGS, 236 *PTR_MPI2_SYSTEM_INTERFACE_REGS, 237 Mpi2SystemInterfaceRegs_t, 238 *pMpi2SystemInterfaceRegs_t; 239 240/* 241 *Defines for working with the Doorbell register. 242 */ 243#define MPI2_DOORBELL_OFFSET (0x00000000) 244 245/*IOC --> System values */ 246#define MPI2_DOORBELL_USED (0x08000000) 247#define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000) 248#define MPI2_DOORBELL_WHO_INIT_SHIFT (24) 249#define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF) 250#define MPI2_DOORBELL_DATA_MASK (0x0000FFFF) 251 252/*System --> IOC values */ 253#define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000) 254#define MPI2_DOORBELL_FUNCTION_SHIFT (24) 255#define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000) 256#define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16) 257 258/* 259 *Defines for the WriteSequence register 260 */ 261#define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 262#define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F) 263#define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 264#define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 265#define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 266#define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 267#define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 268#define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 269#define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 270 271/* 272 *Defines for the HostDiagnostic register 273 */ 274#define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008) 275 276#define MPI26_DIAG_SECURE_BOOT (0x80000000) 277 278#define MPI2_DIAG_SBR_RELOAD (0x00002000) 279 280#define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800) 281#define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000) 282#define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800) 283 284/* Defines for V7A/V7R HostDiagnostic Register */ 285#define MPI26_DIAG_BOOT_DEVICE_SEL_64FLASH (0x00000000) 286#define MPI26_DIAG_BOOT_DEVICE_SEL_64HCDW (0x00000800) 287#define MPI26_DIAG_BOOT_DEVICE_SEL_32FLASH (0x00001000) 288#define MPI26_DIAG_BOOT_DEVICE_SEL_32HCDW (0x00001800) 289 290#define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400) 291#define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200) 292#define MPI2_DIAG_HCB_MODE (0x00000100) 293#define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080) 294#define MPI2_DIAG_FLASH_BAD_SIG (0x00000040) 295#define MPI2_DIAG_RESET_HISTORY (0x00000020) 296#define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010) 297#define MPI2_DIAG_RESET_ADAPTER (0x00000004) 298#define MPI2_DIAG_HOLD_IOC_RESET (0x00000002) 299 300/* 301 *Offsets for DiagRWData and address 302 */ 303#define MPI2_DIAG_RW_DATA_OFFSET (0x00000010) 304#define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014) 305#define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018) 306 307/* 308 *Defines for the HostInterruptStatus register 309 */ 310#define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030) 311#define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000) 312#define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS 313#define MPI2_HIS_RESET_IRQ_STATUS (0x40000000) 314#define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008) 315#define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001) 316#define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS 317 318/* 319 *Defines for the HostInterruptMask register 320 */ 321#define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034) 322#define MPI2_HIM_RESET_IRQ_MASK (0x40000000) 323#define MPI2_HIM_REPLY_INT_MASK (0x00000008) 324#define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK 325#define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001) 326#define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK 327 328/* 329 *Offsets for DCRData and address 330 */ 331#define MPI2_DCR_DATA_OFFSET (0x00000038) 332#define MPI2_DCR_ADDRESS_OFFSET (0x0000003C) 333 334/* 335 *Offset for the Reply Free Queue 336 */ 337#define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048) 338 339/* 340 *Defines for the Reply Descriptor Post Queue 341 */ 342#define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C) 343#define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF) 344#define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000) 345#define MPI2_RPHI_MSIX_INDEX_SHIFT (24) 346#define MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) /*MPI v2.5 only*/ 347 348 349/* 350 *Defines for the HCBSize and address 351 */ 352#define MPI2_HCB_SIZE_OFFSET (0x00000074) 353#define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000) 354#define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001) 355 356#define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078) 357#define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C) 358 359/* 360 *Offsets for the Scratchpad registers 361 */ 362#define MPI26_SCRATCHPAD0_OFFSET (0x000000B0) 363#define MPI26_SCRATCHPAD1_OFFSET (0x000000B4) 364#define MPI26_SCRATCHPAD2_OFFSET (0x000000B8) 365#define MPI26_SCRATCHPAD3_OFFSET (0x000000BC) 366 367/* 368 *Offsets for the Request Descriptor Post Queue 369 */ 370#define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0) 371#define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4) 372#define MPI26_ATOMIC_REQUEST_DESCRIPTOR_POST_OFFSET (0x000000C8) 373 374/*Hard Reset delay timings */ 375#define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000) 376#define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC (255000) 377#define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC (256000) 378 379/***************************************************************************** 380* 381* Message Descriptors 382* 383*****************************************************************************/ 384 385/*Request Descriptors */ 386 387/*Default Request Descriptor */ 388typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR { 389 U8 RequestFlags; /*0x00 */ 390 U8 MSIxIndex; /*0x01 */ 391 U16 SMID; /*0x02 */ 392 U16 LMID; /*0x04 */ 393 U16 DescriptorTypeDependent; /*0x06 */ 394} MPI2_DEFAULT_REQUEST_DESCRIPTOR, 395 *PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR, 396 Mpi2DefaultRequestDescriptor_t, 397 *pMpi2DefaultRequestDescriptor_t; 398 399/*defines for the RequestFlags field */ 400#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x1E) 401#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_RSHIFT (1) 402#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 403#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 404#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 405#define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 406#define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 407#define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO (0x0C) 408#define MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED (0x10) 409 410#define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 411 412/*High Priority Request Descriptor */ 413typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR { 414 U8 RequestFlags; /*0x00 */ 415 U8 MSIxIndex; /*0x01 */ 416 U16 SMID; /*0x02 */ 417 U16 LMID; /*0x04 */ 418 U16 Reserved1; /*0x06 */ 419} MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 420 *PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 421 Mpi2HighPriorityRequestDescriptor_t, 422 *pMpi2HighPriorityRequestDescriptor_t; 423 424/*SCSI IO Request Descriptor */ 425typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR { 426 U8 RequestFlags; /*0x00 */ 427 U8 MSIxIndex; /*0x01 */ 428 U16 SMID; /*0x02 */ 429 U16 LMID; /*0x04 */ 430 U16 DevHandle; /*0x06 */ 431} MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 432 *PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 433 Mpi2SCSIIORequestDescriptor_t, 434 *pMpi2SCSIIORequestDescriptor_t; 435 436/*SCSI Target Request Descriptor */ 437typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR { 438 U8 RequestFlags; /*0x00 */ 439 U8 MSIxIndex; /*0x01 */ 440 U16 SMID; /*0x02 */ 441 U16 LMID; /*0x04 */ 442 U16 IoIndex; /*0x06 */ 443} MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 444 *PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 445 Mpi2SCSITargetRequestDescriptor_t, 446 *pMpi2SCSITargetRequestDescriptor_t; 447 448/*RAID Accelerator Request Descriptor */ 449typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR { 450 U8 RequestFlags; /*0x00 */ 451 U8 MSIxIndex; /*0x01 */ 452 U16 SMID; /*0x02 */ 453 U16 LMID; /*0x04 */ 454 U16 Reserved; /*0x06 */ 455} MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 456 *PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 457 Mpi2RAIDAcceleratorRequestDescriptor_t, 458 *pMpi2RAIDAcceleratorRequestDescriptor_t; 459 460/*Fast Path SCSI IO Request Descriptor */ 461typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR 462 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR, 463 *PTR_MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR, 464 Mpi25FastPathSCSIIORequestDescriptor_t, 465 *pMpi25FastPathSCSIIORequestDescriptor_t; 466 467/*PCIe Encapsulated Request Descriptor */ 468typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR 469 MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR, 470 *PTR_MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR, 471 Mpi26PCIeEncapsulatedRequestDescriptor_t, 472 *pMpi26PCIeEncapsulatedRequestDescriptor_t; 473 474/*union of Request Descriptors */ 475typedef union _MPI2_REQUEST_DESCRIPTOR_UNION { 476 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 477 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 478 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 479 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 480 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 481 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR FastPathSCSIIO; 482 MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR PCIeEncapsulated; 483 U64 Words; 484} MPI2_REQUEST_DESCRIPTOR_UNION, 485 *PTR_MPI2_REQUEST_DESCRIPTOR_UNION, 486 Mpi2RequestDescriptorUnion_t, 487 *pMpi2RequestDescriptorUnion_t; 488 489/*Atomic Request Descriptors */ 490 491/* 492 * All Atomic Request Descriptors have the same format, so the following 493 * structure is used for all Atomic Request Descriptors: 494 * Atomic Default Request Descriptor 495 * Atomic High Priority Request Descriptor 496 * Atomic SCSI IO Request Descriptor 497 * Atomic SCSI Target Request Descriptor 498 * Atomic RAID Accelerator Request Descriptor 499 * Atomic Fast Path SCSI IO Request Descriptor 500 * Atomic PCIe Encapsulated Request Descriptor 501 */ 502 503/*Atomic Request Descriptor */ 504typedef struct _MPI26_ATOMIC_REQUEST_DESCRIPTOR { 505 U8 RequestFlags; /* 0x00 */ 506 U8 MSIxIndex; /* 0x01 */ 507 U16 SMID; /* 0x02 */ 508} MPI26_ATOMIC_REQUEST_DESCRIPTOR, 509 *PTR_MPI26_ATOMIC_REQUEST_DESCRIPTOR, 510 Mpi26AtomicRequestDescriptor_t, 511 *pMpi26AtomicRequestDescriptor_t; 512 513/*for the RequestFlags field, use the same 514 *defines as MPI2_DEFAULT_REQUEST_DESCRIPTOR 515 */ 516 517/*Reply Descriptors */ 518 519/*Default Reply Descriptor */ 520typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR { 521 U8 ReplyFlags; /*0x00 */ 522 U8 MSIxIndex; /*0x01 */ 523 U16 DescriptorTypeDependent1; /*0x02 */ 524 U32 DescriptorTypeDependent2; /*0x04 */ 525} MPI2_DEFAULT_REPLY_DESCRIPTOR, 526 *PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR, 527 Mpi2DefaultReplyDescriptor_t, 528 *pMpi2DefaultReplyDescriptor_t; 529 530/*defines for the ReplyFlags field */ 531#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 532#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 533#define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 534#define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 535#define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 536#define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 537#define MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS (0x06) 538#define MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS (0x08) 539#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 540 541/*values for marking a reply descriptor as unused */ 542#define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 543#define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 544 545/*Address Reply Descriptor */ 546typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR { 547 U8 ReplyFlags; /*0x00 */ 548 U8 MSIxIndex; /*0x01 */ 549 U16 SMID; /*0x02 */ 550 U32 ReplyFrameAddress; /*0x04 */ 551} MPI2_ADDRESS_REPLY_DESCRIPTOR, 552 *PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR, 553 Mpi2AddressReplyDescriptor_t, 554 *pMpi2AddressReplyDescriptor_t; 555 556#define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00) 557 558/*SCSI IO Success Reply Descriptor */ 559typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR { 560 U8 ReplyFlags; /*0x00 */ 561 U8 MSIxIndex; /*0x01 */ 562 U16 SMID; /*0x02 */ 563 U16 TaskTag; /*0x04 */ 564 U16 Reserved1; /*0x06 */ 565} MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 566 *PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 567 Mpi2SCSIIOSuccessReplyDescriptor_t, 568 *pMpi2SCSIIOSuccessReplyDescriptor_t; 569 570/*TargetAssist Success Reply Descriptor */ 571typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR { 572 U8 ReplyFlags; /*0x00 */ 573 U8 MSIxIndex; /*0x01 */ 574 U16 SMID; /*0x02 */ 575 U8 SequenceNumber; /*0x04 */ 576 U8 Reserved1; /*0x05 */ 577 U16 IoIndex; /*0x06 */ 578} MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 579 *PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 580 Mpi2TargetAssistSuccessReplyDescriptor_t, 581 *pMpi2TargetAssistSuccessReplyDescriptor_t; 582 583/*Target Command Buffer Reply Descriptor */ 584typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR { 585 U8 ReplyFlags; /*0x00 */ 586 U8 MSIxIndex; /*0x01 */ 587 U8 VP_ID; /*0x02 */ 588 U8 Flags; /*0x03 */ 589 U16 InitiatorDevHandle; /*0x04 */ 590 U16 IoIndex; /*0x06 */ 591} MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 592 *PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 593 Mpi2TargetCommandBufferReplyDescriptor_t, 594 *pMpi2TargetCommandBufferReplyDescriptor_t; 595 596/*defines for Flags field */ 597#define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F) 598 599/*RAID Accelerator Success Reply Descriptor */ 600typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR { 601 U8 ReplyFlags; /*0x00 */ 602 U8 MSIxIndex; /*0x01 */ 603 U16 SMID; /*0x02 */ 604 U32 Reserved; /*0x04 */ 605} MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 606 *PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 607 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, 608 *pMpi2RAIDAcceleratorSuccessReplyDescriptor_t; 609 610/*Fast Path SCSI IO Success Reply Descriptor */ 611typedef MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR 612 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 613 *PTR_MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 614 Mpi25FastPathSCSIIOSuccessReplyDescriptor_t, 615 *pMpi25FastPathSCSIIOSuccessReplyDescriptor_t; 616 617/*PCIe Encapsulated Success Reply Descriptor */ 618typedef MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR 619 MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR, 620 *PTR_MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR, 621 Mpi26PCIeEncapsulatedSuccessReplyDescriptor_t, 622 *pMpi26PCIeEncapsulatedSuccessReplyDescriptor_t; 623 624/*union of Reply Descriptors */ 625typedef union _MPI2_REPLY_DESCRIPTORS_UNION { 626 MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 627 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 628 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 629 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 630 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 631 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess; 632 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR FastPathSCSIIOSuccess; 633 MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR 634 PCIeEncapsulatedSuccess; 635 U64 Words; 636} MPI2_REPLY_DESCRIPTORS_UNION, 637 *PTR_MPI2_REPLY_DESCRIPTORS_UNION, 638 Mpi2ReplyDescriptorsUnion_t, 639 *pMpi2ReplyDescriptorsUnion_t; 640 641/***************************************************************************** 642* 643* Message Functions 644* 645*****************************************************************************/ 646 647#define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) 648#define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) 649#define MPI2_FUNCTION_IOC_INIT (0x02) 650#define MPI2_FUNCTION_IOC_FACTS (0x03) 651#define MPI2_FUNCTION_CONFIG (0x04) 652#define MPI2_FUNCTION_PORT_FACTS (0x05) 653#define MPI2_FUNCTION_PORT_ENABLE (0x06) 654#define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) 655#define MPI2_FUNCTION_EVENT_ACK (0x08) 656#define MPI2_FUNCTION_FW_DOWNLOAD (0x09) 657#define MPI2_FUNCTION_TARGET_ASSIST (0x0B) 658#define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) 659#define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) 660#define MPI2_FUNCTION_FW_UPLOAD (0x12) 661#define MPI2_FUNCTION_RAID_ACTION (0x15) 662#define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) 663#define MPI2_FUNCTION_TOOLBOX (0x17) 664#define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) 665#define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) 666#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) 667#define MPI2_FUNCTION_IO_UNIT_CONTROL (0x1B) 668#define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) 669#define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) 670#define MPI2_FUNCTION_DIAG_RELEASE (0x1E) 671#define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) 672#define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) 673#define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) 674#define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) 675#define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) 676#define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31) 677#define MPI2_FUNCTION_NVME_ENCAPSULATED (0x33) 678#define MPI2_FUNCTION_MCTP_PASSTHROUGH (0x34) 679#define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) 680#define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) 681 682/*Doorbell functions */ 683#define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 684#define MPI2_FUNCTION_HANDSHAKE (0x42) 685 686/***************************************************************************** 687* 688* IOC Status Values 689* 690*****************************************************************************/ 691 692/*mask for IOCStatus status value */ 693#define MPI2_IOCSTATUS_MASK (0x7FFF) 694 695/**************************************************************************** 696* Common IOCStatus values for all replies 697****************************************************************************/ 698 699#define MPI2_IOCSTATUS_SUCCESS (0x0000) 700#define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001) 701#define MPI2_IOCSTATUS_BUSY (0x0002) 702#define MPI2_IOCSTATUS_INVALID_SGL (0x0003) 703#define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004) 704#define MPI2_IOCSTATUS_INVALID_VPID (0x0005) 705#define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) 706#define MPI2_IOCSTATUS_INVALID_FIELD (0x0007) 707#define MPI2_IOCSTATUS_INVALID_STATE (0x0008) 708#define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009) 709/*MPI v2.6 and later */ 710#define MPI2_IOCSTATUS_INSUFFICIENT_POWER (0x000A) 711#define MPI2_IOCSTATUS_FAILURE (0x000F) 712 713/**************************************************************************** 714* Config IOCStatus values 715****************************************************************************/ 716 717#define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) 718#define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) 719#define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) 720#define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) 721#define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) 722#define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) 723 724/**************************************************************************** 725* SCSI IO Reply 726****************************************************************************/ 727 728#define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) 729#define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042) 730#define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) 731#define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) 732#define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) 733#define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) 734#define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) 735#define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) 736#define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) 737#define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A) 738#define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B) 739#define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C) 740 741/**************************************************************************** 742* For use by SCSI Initiator and SCSI Target end-to-end data protection 743****************************************************************************/ 744 745#define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D) 746#define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E) 747#define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F) 748 749/**************************************************************************** 750* SCSI Target values 751****************************************************************************/ 752 753#define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062) 754#define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063) 755#define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) 756#define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) 757#define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A) 758#define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D) 759#define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E) 760#define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F) 761#define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070) 762#define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071) 763 764/**************************************************************************** 765* Serial Attached SCSI values 766****************************************************************************/ 767 768#define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090) 769#define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091) 770 771/**************************************************************************** 772* Diagnostic Buffer Post / Diagnostic Release values 773****************************************************************************/ 774 775#define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0) 776 777/**************************************************************************** 778* RAID Accelerator values 779****************************************************************************/ 780 781#define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0) 782 783/**************************************************************************** 784* IOCStatus flag to indicate that log info is available 785****************************************************************************/ 786 787#define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000) 788 789/**************************************************************************** 790* IOCLogInfo Types 791****************************************************************************/ 792 793#define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000) 794#define MPI2_IOCLOGINFO_TYPE_SHIFT (28) 795#define MPI2_IOCLOGINFO_TYPE_NONE (0x0) 796#define MPI2_IOCLOGINFO_TYPE_SCSI (0x1) 797#define MPI2_IOCLOGINFO_TYPE_FC (0x2) 798#define MPI2_IOCLOGINFO_TYPE_SAS (0x3) 799#define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4) 800#define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF) 801 802/***************************************************************************** 803* 804* Standard Message Structures 805* 806*****************************************************************************/ 807 808/**************************************************************************** 809*Request Message Header for all request messages 810****************************************************************************/ 811 812typedef struct _MPI2_REQUEST_HEADER { 813 U16 FunctionDependent1; /*0x00 */ 814 U8 ChainOffset; /*0x02 */ 815 U8 Function; /*0x03 */ 816 U16 FunctionDependent2; /*0x04 */ 817 U8 FunctionDependent3; /*0x06 */ 818 U8 MsgFlags; /*0x07 */ 819 U8 VP_ID; /*0x08 */ 820 U8 VF_ID; /*0x09 */ 821 U16 Reserved1; /*0x0A */ 822} MPI2_REQUEST_HEADER, *PTR_MPI2_REQUEST_HEADER, 823 MPI2RequestHeader_t, *pMPI2RequestHeader_t; 824 825/**************************************************************************** 826* Default Reply 827****************************************************************************/ 828 829typedef struct _MPI2_DEFAULT_REPLY { 830 U16 FunctionDependent1; /*0x00 */ 831 U8 MsgLength; /*0x02 */ 832 U8 Function; /*0x03 */ 833 U16 FunctionDependent2; /*0x04 */ 834 U8 FunctionDependent3; /*0x06 */ 835 U8 MsgFlags; /*0x07 */ 836 U8 VP_ID; /*0x08 */ 837 U8 VF_ID; /*0x09 */ 838 U16 Reserved1; /*0x0A */ 839 U16 FunctionDependent5; /*0x0C */ 840 U16 IOCStatus; /*0x0E */ 841 U32 IOCLogInfo; /*0x10 */ 842} MPI2_DEFAULT_REPLY, *PTR_MPI2_DEFAULT_REPLY, 843 MPI2DefaultReply_t, *pMPI2DefaultReply_t; 844 845/*common version structure/union used in messages and configuration pages */ 846 847typedef struct _MPI2_VERSION_STRUCT { 848 U8 Dev; /*0x00 */ 849 U8 Unit; /*0x01 */ 850 U8 Minor; /*0x02 */ 851 U8 Major; /*0x03 */ 852} MPI2_VERSION_STRUCT; 853 854typedef union _MPI2_VERSION_UNION { 855 MPI2_VERSION_STRUCT Struct; 856 U32 Word; 857} MPI2_VERSION_UNION; 858 859/*LUN field defines, common to many structures */ 860#define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF) 861#define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000) 862#define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF) 863#define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000) 864#define MPI2_LUN_LEVEL_1_WORD (0xFF00) 865#define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00) 866 867/***************************************************************************** 868* 869* Fusion-MPT MPI Scatter Gather Elements 870* 871*****************************************************************************/ 872 873/**************************************************************************** 874* MPI Simple Element structures 875****************************************************************************/ 876 877typedef struct _MPI2_SGE_SIMPLE32 { 878 U32 FlagsLength; 879 U32 Address; 880} MPI2_SGE_SIMPLE32, *PTR_MPI2_SGE_SIMPLE32, 881 Mpi2SGESimple32_t, *pMpi2SGESimple32_t; 882 883typedef struct _MPI2_SGE_SIMPLE64 { 884 U32 FlagsLength; 885 U64 Address; 886} MPI2_SGE_SIMPLE64, *PTR_MPI2_SGE_SIMPLE64, 887 Mpi2SGESimple64_t, *pMpi2SGESimple64_t; 888 889typedef struct _MPI2_SGE_SIMPLE_UNION { 890 U32 FlagsLength; 891 union { 892 U32 Address32; 893 U64 Address64; 894 } u; 895} MPI2_SGE_SIMPLE_UNION, 896 *PTR_MPI2_SGE_SIMPLE_UNION, 897 Mpi2SGESimpleUnion_t, 898 *pMpi2SGESimpleUnion_t; 899 900/**************************************************************************** 901* MPI Chain Element structures - for MPI v2.0 products only 902****************************************************************************/ 903 904typedef struct _MPI2_SGE_CHAIN32 { 905 U16 Length; 906 U8 NextChainOffset; 907 U8 Flags; 908 U32 Address; 909} MPI2_SGE_CHAIN32, *PTR_MPI2_SGE_CHAIN32, 910 Mpi2SGEChain32_t, *pMpi2SGEChain32_t; 911 912typedef struct _MPI2_SGE_CHAIN64 { 913 U16 Length; 914 U8 NextChainOffset; 915 U8 Flags; 916 U64 Address; 917} MPI2_SGE_CHAIN64, *PTR_MPI2_SGE_CHAIN64, 918 Mpi2SGEChain64_t, *pMpi2SGEChain64_t; 919 920typedef struct _MPI2_SGE_CHAIN_UNION { 921 U16 Length; 922 U8 NextChainOffset; 923 U8 Flags; 924 union { 925 U32 Address32; 926 U64 Address64; 927 } u; 928} MPI2_SGE_CHAIN_UNION, 929 *PTR_MPI2_SGE_CHAIN_UNION, 930 Mpi2SGEChainUnion_t, 931 *pMpi2SGEChainUnion_t; 932 933/**************************************************************************** 934* MPI Transaction Context Element structures - for MPI v2.0 products only 935****************************************************************************/ 936 937typedef struct _MPI2_SGE_TRANSACTION32 { 938 U8 Reserved; 939 U8 ContextSize; 940 U8 DetailsLength; 941 U8 Flags; 942 U32 TransactionContext[1]; 943 U32 TransactionDetails[1]; 944} MPI2_SGE_TRANSACTION32, 945 *PTR_MPI2_SGE_TRANSACTION32, 946 Mpi2SGETransaction32_t, 947 *pMpi2SGETransaction32_t; 948 949typedef struct _MPI2_SGE_TRANSACTION64 { 950 U8 Reserved; 951 U8 ContextSize; 952 U8 DetailsLength; 953 U8 Flags; 954 U32 TransactionContext[2]; 955 U32 TransactionDetails[1]; 956} MPI2_SGE_TRANSACTION64, 957 *PTR_MPI2_SGE_TRANSACTION64, 958 Mpi2SGETransaction64_t, 959 *pMpi2SGETransaction64_t; 960 961typedef struct _MPI2_SGE_TRANSACTION96 { 962 U8 Reserved; 963 U8 ContextSize; 964 U8 DetailsLength; 965 U8 Flags; 966 U32 TransactionContext[3]; 967 U32 TransactionDetails[1]; 968} MPI2_SGE_TRANSACTION96, *PTR_MPI2_SGE_TRANSACTION96, 969 Mpi2SGETransaction96_t, *pMpi2SGETransaction96_t; 970 971typedef struct _MPI2_SGE_TRANSACTION128 { 972 U8 Reserved; 973 U8 ContextSize; 974 U8 DetailsLength; 975 U8 Flags; 976 U32 TransactionContext[4]; 977 U32 TransactionDetails[1]; 978} MPI2_SGE_TRANSACTION128, *PTR_MPI2_SGE_TRANSACTION128, 979 Mpi2SGETransaction_t128, *pMpi2SGETransaction_t128; 980 981typedef struct _MPI2_SGE_TRANSACTION_UNION { 982 U8 Reserved; 983 U8 ContextSize; 984 U8 DetailsLength; 985 U8 Flags; 986 union { 987 U32 TransactionContext32[1]; 988 U32 TransactionContext64[2]; 989 U32 TransactionContext96[3]; 990 U32 TransactionContext128[4]; 991 } u; 992 U32 TransactionDetails[1]; 993} MPI2_SGE_TRANSACTION_UNION, 994 *PTR_MPI2_SGE_TRANSACTION_UNION, 995 Mpi2SGETransactionUnion_t, 996 *pMpi2SGETransactionUnion_t; 997 998/**************************************************************************** 999* MPI SGE union for IO SGL's - for MPI v2.0 products only 1000****************************************************************************/ 1001 1002typedef struct _MPI2_MPI_SGE_IO_UNION { 1003 union { 1004 MPI2_SGE_SIMPLE_UNION Simple; 1005 MPI2_SGE_CHAIN_UNION Chain; 1006 } u; 1007} MPI2_MPI_SGE_IO_UNION, *PTR_MPI2_MPI_SGE_IO_UNION, 1008 Mpi2MpiSGEIOUnion_t, *pMpi2MpiSGEIOUnion_t; 1009 1010/**************************************************************************** 1011* MPI SGE union for SGL's with Simple and Transaction elements - for MPI v2.0 products only 1012****************************************************************************/ 1013 1014typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION { 1015 union { 1016 MPI2_SGE_SIMPLE_UNION Simple; 1017 MPI2_SGE_TRANSACTION_UNION Transaction; 1018 } u; 1019} MPI2_SGE_TRANS_SIMPLE_UNION, 1020 *PTR_MPI2_SGE_TRANS_SIMPLE_UNION, 1021 Mpi2SGETransSimpleUnion_t, 1022 *pMpi2SGETransSimpleUnion_t; 1023 1024/**************************************************************************** 1025* All MPI SGE types union 1026****************************************************************************/ 1027 1028typedef struct _MPI2_MPI_SGE_UNION { 1029 union { 1030 MPI2_SGE_SIMPLE_UNION Simple; 1031 MPI2_SGE_CHAIN_UNION Chain; 1032 MPI2_SGE_TRANSACTION_UNION Transaction; 1033 } u; 1034} MPI2_MPI_SGE_UNION, *PTR_MPI2_MPI_SGE_UNION, 1035 Mpi2MpiSgeUnion_t, *pMpi2MpiSgeUnion_t; 1036 1037/**************************************************************************** 1038* MPI SGE field definition and masks 1039****************************************************************************/ 1040 1041/*Flags field bit definitions */ 1042 1043#define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80) 1044#define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40) 1045#define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30) 1046#define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08) 1047#define MPI2_SGE_FLAGS_DIRECTION (0x04) 1048#define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02) 1049#define MPI2_SGE_FLAGS_END_OF_LIST (0x01) 1050 1051#define MPI2_SGE_FLAGS_SHIFT (24) 1052 1053#define MPI2_SGE_LENGTH_MASK (0x00FFFFFF) 1054#define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF) 1055 1056/*Element Type */ 1057 1058#define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00) 1059#define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10) 1060#define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30) 1061#define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30) 1062 1063/*Address location */ 1064 1065#define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00) 1066 1067/*Direction */ 1068 1069#define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00) 1070#define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04) 1071 1072#define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST) 1073#define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC) 1074 1075/*Address Size */ 1076 1077#define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 1078#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 1079 1080/*Context Size */ 1081 1082#define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00) 1083#define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02) 1084#define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04) 1085#define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06) 1086 1087#define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000) 1088#define MPI2_SGE_CHAIN_OFFSET_SHIFT (16) 1089 1090/**************************************************************************** 1091* MPI SGE operation Macros 1092****************************************************************************/ 1093 1094/*SIMPLE FlagsLength manipulations... */ 1095#define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT) 1096#define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> \ 1097 MPI2_SGE_FLAGS_SHIFT) 1098#define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK) 1099#define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK) 1100 1101#define MPI2_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_SGE_SET_FLAGS(f) | \ 1102 MPI2_SGE_LENGTH(l)) 1103 1104#define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength) 1105#define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength) 1106#define MPI2_pSGE_SET_FLAGS_LENGTH(psg, f, l) ((psg)->FlagsLength = \ 1107 MPI2_SGE_SET_FLAGS_LENGTH(f, l)) 1108 1109/*CAUTION - The following are READ-MODIFY-WRITE! */ 1110#define MPI2_pSGE_SET_FLAGS(psg, f) ((psg)->FlagsLength |= \ 1111 MPI2_SGE_SET_FLAGS(f)) 1112#define MPI2_pSGE_SET_LENGTH(psg, l) ((psg)->FlagsLength |= \ 1113 MPI2_SGE_LENGTH(l)) 1114 1115#define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> \ 1116 MPI2_SGE_CHAIN_OFFSET_SHIFT) 1117 1118/***************************************************************************** 1119* 1120* Fusion-MPT IEEE Scatter Gather Elements 1121* 1122*****************************************************************************/ 1123 1124/**************************************************************************** 1125* IEEE Simple Element structures 1126****************************************************************************/ 1127 1128/*MPI2_IEEE_SGE_SIMPLE32 is for MPI v2.0 products only */ 1129typedef struct _MPI2_IEEE_SGE_SIMPLE32 { 1130 U32 Address; 1131 U32 FlagsLength; 1132} MPI2_IEEE_SGE_SIMPLE32, *PTR_MPI2_IEEE_SGE_SIMPLE32, 1133 Mpi2IeeeSgeSimple32_t, *pMpi2IeeeSgeSimple32_t; 1134 1135typedef struct _MPI2_IEEE_SGE_SIMPLE64 { 1136 U64 Address; 1137 U32 Length; 1138 U16 Reserved1; 1139 U8 Reserved2; 1140 U8 Flags; 1141} MPI2_IEEE_SGE_SIMPLE64, *PTR_MPI2_IEEE_SGE_SIMPLE64, 1142 Mpi2IeeeSgeSimple64_t, *pMpi2IeeeSgeSimple64_t; 1143 1144typedef union _MPI2_IEEE_SGE_SIMPLE_UNION { 1145 MPI2_IEEE_SGE_SIMPLE32 Simple32; 1146 MPI2_IEEE_SGE_SIMPLE64 Simple64; 1147} MPI2_IEEE_SGE_SIMPLE_UNION, 1148 *PTR_MPI2_IEEE_SGE_SIMPLE_UNION, 1149 Mpi2IeeeSgeSimpleUnion_t, 1150 *pMpi2IeeeSgeSimpleUnion_t; 1151 1152/**************************************************************************** 1153* IEEE Chain Element structures 1154****************************************************************************/ 1155 1156/*MPI2_IEEE_SGE_CHAIN32 is for MPI v2.0 products only */ 1157typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32; 1158 1159/*MPI2_IEEE_SGE_CHAIN64 is for MPI v2.0 products only */ 1160typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64; 1161 1162typedef union _MPI2_IEEE_SGE_CHAIN_UNION { 1163 MPI2_IEEE_SGE_CHAIN32 Chain32; 1164 MPI2_IEEE_SGE_CHAIN64 Chain64; 1165} MPI2_IEEE_SGE_CHAIN_UNION, 1166 *PTR_MPI2_IEEE_SGE_CHAIN_UNION, 1167 Mpi2IeeeSgeChainUnion_t, 1168 *pMpi2IeeeSgeChainUnion_t; 1169 1170/*MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 and later */ 1171typedef struct _MPI25_IEEE_SGE_CHAIN64 { 1172 U64 Address; 1173 U32 Length; 1174 U16 Reserved1; 1175 U8 NextChainOffset; 1176 U8 Flags; 1177} MPI25_IEEE_SGE_CHAIN64, 1178 *PTR_MPI25_IEEE_SGE_CHAIN64, 1179 Mpi25IeeeSgeChain64_t, 1180 *pMpi25IeeeSgeChain64_t; 1181 1182/**************************************************************************** 1183* All IEEE SGE types union 1184****************************************************************************/ 1185 1186/*MPI2_IEEE_SGE_UNION is for MPI v2.0 products only */ 1187typedef struct _MPI2_IEEE_SGE_UNION { 1188 union { 1189 MPI2_IEEE_SGE_SIMPLE_UNION Simple; 1190 MPI2_IEEE_SGE_CHAIN_UNION Chain; 1191 } u; 1192} MPI2_IEEE_SGE_UNION, *PTR_MPI2_IEEE_SGE_UNION, 1193 Mpi2IeeeSgeUnion_t, *pMpi2IeeeSgeUnion_t; 1194 1195/**************************************************************************** 1196* IEEE SGE union for IO SGL's 1197****************************************************************************/ 1198 1199typedef union _MPI25_SGE_IO_UNION { 1200 MPI2_IEEE_SGE_SIMPLE64 IeeeSimple; 1201 MPI25_IEEE_SGE_CHAIN64 IeeeChain; 1202} MPI25_SGE_IO_UNION, *PTR_MPI25_SGE_IO_UNION, 1203 Mpi25SGEIOUnion_t, *pMpi25SGEIOUnion_t; 1204 1205/**************************************************************************** 1206* IEEE SGE field definitions and masks 1207****************************************************************************/ 1208 1209/*Flags field bit definitions */ 1210 1211#define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1212#define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40) 1213 1214#define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1215 1216#define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1217 1218/*Element Type */ 1219 1220#define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1221#define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1222 1223/*Next Segment Format */ 1224 1225#define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C) 1226#define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00) 1227#define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP (0x08) 1228#define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL (0x10) 1229 1230/*Data Location Address Space */ 1231 1232#define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1233#define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 1234#define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 1235#define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1236#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 1237#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03) 1238#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR \ 1239 (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR) 1240#define MPI26_IEEE_SGE_FLAGS_IOCCTL_ADDR (0x02) 1241 1242/**************************************************************************** 1243* IEEE SGE operation Macros 1244****************************************************************************/ 1245 1246/*SIMPLE FlagsLength manipulations... */ 1247#define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT) 1248#define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) \ 1249 >> MPI2_IEEE32_SGE_FLAGS_SHIFT) 1250#define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK) 1251 1252#define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) |\ 1253 MPI2_IEEE32_SGE_LENGTH(l)) 1254 1255#define MPI2_IEEE32_pSGE_GET_FLAGS(psg) \ 1256 MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength) 1257#define MPI2_IEEE32_pSGE_GET_LENGTH(psg) \ 1258 MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength) 1259#define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg, f, l) ((psg)->FlagsLength = \ 1260 MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l)) 1261 1262/*CAUTION - The following are READ-MODIFY-WRITE! */ 1263#define MPI2_IEEE32_pSGE_SET_FLAGS(psg, f) ((psg)->FlagsLength |= \ 1264 MPI2_IEEE32_SGE_SET_FLAGS(f)) 1265#define MPI2_IEEE32_pSGE_SET_LENGTH(psg, l) ((psg)->FlagsLength |= \ 1266 MPI2_IEEE32_SGE_LENGTH(l)) 1267 1268/***************************************************************************** 1269* 1270* Fusion-MPT MPI/IEEE Scatter Gather Unions 1271* 1272*****************************************************************************/ 1273 1274typedef union _MPI2_SIMPLE_SGE_UNION { 1275 MPI2_SGE_SIMPLE_UNION MpiSimple; 1276 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1277} MPI2_SIMPLE_SGE_UNION, *PTR_MPI2_SIMPLE_SGE_UNION, 1278 Mpi2SimpleSgeUntion_t, *pMpi2SimpleSgeUntion_t; 1279 1280typedef union _MPI2_SGE_IO_UNION { 1281 MPI2_SGE_SIMPLE_UNION MpiSimple; 1282 MPI2_SGE_CHAIN_UNION MpiChain; 1283 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1284 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 1285} MPI2_SGE_IO_UNION, *PTR_MPI2_SGE_IO_UNION, 1286 Mpi2SGEIOUnion_t, *pMpi2SGEIOUnion_t; 1287 1288/**************************************************************************** 1289* 1290* Values for SGLFlags field, used in many request messages with an SGL 1291* 1292****************************************************************************/ 1293 1294/*values for MPI SGL Data Location Address Space subfield */ 1295#define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C) 1296#define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00) 1297#define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04) 1298#define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) 1299#define MPI26_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) 1300#define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C) 1301/*values for SGL Type subfield */ 1302#define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03) 1303#define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00) 1304#define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01) 1305#define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02) 1306 1307#endif
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