mpi3mr_fw.c

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * Driver for Broadcom MPI3 Storage Controllers
   4 *
   5 * Copyright (C) 2017-2023 Broadcom Inc.
   6 *  (mailto: mpi3mr-linuxdrv.pdl@broadcom.com)
   7 *
   8 */
   9
  10#include "mpi3mr.h"
  11#include <linux/io-64-nonatomic-lo-hi.h>
  12
  13static int
  14mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type, u16 reset_reason);
  15static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc);
  16static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc,
  17	struct mpi3_ioc_facts_data *facts_data);
  18static void mpi3mr_pel_wait_complete(struct mpi3mr_ioc *mrioc,
  19	struct mpi3mr_drv_cmd *drv_cmd);
  20static int mpi3mr_check_op_admin_proc(struct mpi3mr_ioc *mrioc);
  21static int poll_queues;
  22module_param(poll_queues, int, 0444);
  23MODULE_PARM_DESC(poll_queues, "Number of queues for io_uring poll mode. (Range 1 - 126)");
  24
  25#if defined(writeq) && defined(CONFIG_64BIT)
  26static inline void mpi3mr_writeq(__u64 b, void __iomem *addr,
  27	spinlock_t *write_queue_lock)
  28{
  29	writeq(b, addr);
  30}
  31#else
  32static inline void mpi3mr_writeq(__u64 b, void __iomem *addr,
  33	spinlock_t *write_queue_lock)
  34{
  35	__u64 data_out = b;
  36	unsigned long flags;
  37
  38	spin_lock_irqsave(write_queue_lock, flags);
  39	writel((u32)(data_out), addr);
  40	writel((u32)(data_out >> 32), (addr + 4));
  41	spin_unlock_irqrestore(write_queue_lock, flags);
  42}
  43#endif
  44
  45static inline bool
  46mpi3mr_check_req_qfull(struct op_req_qinfo *op_req_q)
  47{
  48	u16 pi, ci, max_entries;
  49	bool is_qfull = false;
  50
  51	pi = op_req_q->pi;
  52	ci = READ_ONCE(op_req_q->ci);
  53	max_entries = op_req_q->num_requests;
  54
  55	if ((ci == (pi + 1)) || ((!ci) && (pi == (max_entries - 1))))
  56		is_qfull = true;
  57
  58	return is_qfull;
  59}
  60
  61static void mpi3mr_sync_irqs(struct mpi3mr_ioc *mrioc)
  62{
  63	u16 i, max_vectors;
  64
  65	max_vectors = mrioc->intr_info_count;
  66
  67	for (i = 0; i < max_vectors; i++)
  68		synchronize_irq(pci_irq_vector(mrioc->pdev, i));
  69}
  70
  71void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc)
  72{
  73	mrioc->intr_enabled = 0;
  74	mpi3mr_sync_irqs(mrioc);
  75}
  76
  77void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc)
  78{
  79	mrioc->intr_enabled = 1;
  80}
  81
  82static void mpi3mr_cleanup_isr(struct mpi3mr_ioc *mrioc)
  83{
  84	u16 i;
  85
  86	mpi3mr_ioc_disable_intr(mrioc);
  87
  88	if (!mrioc->intr_info)
  89		return;
  90
  91	for (i = 0; i < mrioc->intr_info_count; i++)
  92		free_irq(pci_irq_vector(mrioc->pdev, i),
  93		    (mrioc->intr_info + i));
  94
  95	kfree(mrioc->intr_info);
  96	mrioc->intr_info = NULL;
  97	mrioc->intr_info_count = 0;
  98	mrioc->is_intr_info_set = false;
  99	pci_free_irq_vectors(mrioc->pdev);
 100}
 101
 102void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length,
 103	dma_addr_t dma_addr)
 104{
 105	struct mpi3_sge_common *sgel = paddr;
 106
 107	sgel->flags = flags;
 108	sgel->length = cpu_to_le32(length);
 109	sgel->address = cpu_to_le64(dma_addr);
 110}
 111
 112void mpi3mr_build_zero_len_sge(void *paddr)
 113{
 114	u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
 115
 116	mpi3mr_add_sg_single(paddr, sgl_flags, 0, -1);
 117}
 118
 119void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc,
 120	dma_addr_t phys_addr)
 121{
 122	if (!phys_addr)
 123		return NULL;
 124
 125	if ((phys_addr < mrioc->reply_buf_dma) ||
 126	    (phys_addr > mrioc->reply_buf_dma_max_address))
 127		return NULL;
 128
 129	return mrioc->reply_buf + (phys_addr - mrioc->reply_buf_dma);
 130}
 131
 132void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc,
 133	dma_addr_t phys_addr)
 134{
 135	if (!phys_addr)
 136		return NULL;
 137
 138	return mrioc->sense_buf + (phys_addr - mrioc->sense_buf_dma);
 139}
 140
 141static void mpi3mr_repost_reply_buf(struct mpi3mr_ioc *mrioc,
 142	u64 reply_dma)
 143{
 144	u32 old_idx = 0;
 145	unsigned long flags;
 146
 147	spin_lock_irqsave(&mrioc->reply_free_queue_lock, flags);
 148	old_idx  =  mrioc->reply_free_queue_host_index;
 149	mrioc->reply_free_queue_host_index = (
 150	    (mrioc->reply_free_queue_host_index ==
 151	    (mrioc->reply_free_qsz - 1)) ? 0 :
 152	    (mrioc->reply_free_queue_host_index + 1));
 153	mrioc->reply_free_q[old_idx] = cpu_to_le64(reply_dma);
 154	writel(mrioc->reply_free_queue_host_index,
 155	    &mrioc->sysif_regs->reply_free_host_index);
 156	spin_unlock_irqrestore(&mrioc->reply_free_queue_lock, flags);
 157}
 158
 159void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc,
 160	u64 sense_buf_dma)
 161{
 162	u32 old_idx = 0;
 163	unsigned long flags;
 164
 165	spin_lock_irqsave(&mrioc->sbq_lock, flags);
 166	old_idx  =  mrioc->sbq_host_index;
 167	mrioc->sbq_host_index = ((mrioc->sbq_host_index ==
 168	    (mrioc->sense_buf_q_sz - 1)) ? 0 :
 169	    (mrioc->sbq_host_index + 1));
 170	mrioc->sense_buf_q[old_idx] = cpu_to_le64(sense_buf_dma);
 171	writel(mrioc->sbq_host_index,
 172	    &mrioc->sysif_regs->sense_buffer_free_host_index);
 173	spin_unlock_irqrestore(&mrioc->sbq_lock, flags);
 174}
 175
 176static void mpi3mr_print_event_data(struct mpi3mr_ioc *mrioc,
 177	struct mpi3_event_notification_reply *event_reply)
 178{
 179	char *desc = NULL;
 180	u16 event;
 181
 182	if (!(mrioc->logging_level & MPI3_DEBUG_EVENT))
 183		return;
 184
 185	event = event_reply->event;
 186
 187	switch (event) {
 188	case MPI3_EVENT_LOG_DATA:
 189		desc = "Log Data";
 190		break;
 191	case MPI3_EVENT_CHANGE:
 192		desc = "Event Change";
 193		break;
 194	case MPI3_EVENT_GPIO_INTERRUPT:
 195		desc = "GPIO Interrupt";
 196		break;
 197	case MPI3_EVENT_CABLE_MGMT:
 198		desc = "Cable Management";
 199		break;
 200	case MPI3_EVENT_ENERGY_PACK_CHANGE:
 201		desc = "Energy Pack Change";
 202		break;
 203	case MPI3_EVENT_DEVICE_ADDED:
 204	{
 205		struct mpi3_device_page0 *event_data =
 206		    (struct mpi3_device_page0 *)event_reply->event_data;
 207		ioc_info(mrioc, "Device Added: dev=0x%04x Form=0x%x\n",
 208		    event_data->dev_handle, event_data->device_form);
 209		return;
 210	}
 211	case MPI3_EVENT_DEVICE_INFO_CHANGED:
 212	{
 213		struct mpi3_device_page0 *event_data =
 214		    (struct mpi3_device_page0 *)event_reply->event_data;
 215		ioc_info(mrioc, "Device Info Changed: dev=0x%04x Form=0x%x\n",
 216		    event_data->dev_handle, event_data->device_form);
 217		return;
 218	}
 219	case MPI3_EVENT_DEVICE_STATUS_CHANGE:
 220	{
 221		struct mpi3_event_data_device_status_change *event_data =
 222		    (struct mpi3_event_data_device_status_change *)event_reply->event_data;
 223		ioc_info(mrioc, "Device status Change: dev=0x%04x RC=0x%x\n",
 224		    event_data->dev_handle, event_data->reason_code);
 225		return;
 226	}
 227	case MPI3_EVENT_SAS_DISCOVERY:
 228	{
 229		struct mpi3_event_data_sas_discovery *event_data =
 230		    (struct mpi3_event_data_sas_discovery *)event_reply->event_data;
 231		ioc_info(mrioc, "SAS Discovery: (%s) status (0x%08x)\n",
 232		    (event_data->reason_code == MPI3_EVENT_SAS_DISC_RC_STARTED) ?
 233		    "start" : "stop",
 234		    le32_to_cpu(event_data->discovery_status));
 235		return;
 236	}
 237	case MPI3_EVENT_SAS_BROADCAST_PRIMITIVE:
 238		desc = "SAS Broadcast Primitive";
 239		break;
 240	case MPI3_EVENT_SAS_NOTIFY_PRIMITIVE:
 241		desc = "SAS Notify Primitive";
 242		break;
 243	case MPI3_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
 244		desc = "SAS Init Device Status Change";
 245		break;
 246	case MPI3_EVENT_SAS_INIT_TABLE_OVERFLOW:
 247		desc = "SAS Init Table Overflow";
 248		break;
 249	case MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
 250		desc = "SAS Topology Change List";
 251		break;
 252	case MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE:
 253		desc = "Enclosure Device Status Change";
 254		break;
 255	case MPI3_EVENT_ENCL_DEVICE_ADDED:
 256		desc = "Enclosure Added";
 257		break;
 258	case MPI3_EVENT_HARD_RESET_RECEIVED:
 259		desc = "Hard Reset Received";
 260		break;
 261	case MPI3_EVENT_SAS_PHY_COUNTER:
 262		desc = "SAS PHY Counter";
 263		break;
 264	case MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR:
 265		desc = "SAS Device Discovery Error";
 266		break;
 267	case MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST:
 268		desc = "PCIE Topology Change List";
 269		break;
 270	case MPI3_EVENT_PCIE_ENUMERATION:
 271	{
 272		struct mpi3_event_data_pcie_enumeration *event_data =
 273		    (struct mpi3_event_data_pcie_enumeration *)event_reply->event_data;
 274		ioc_info(mrioc, "PCIE Enumeration: (%s)",
 275		    (event_data->reason_code ==
 276		    MPI3_EVENT_PCIE_ENUM_RC_STARTED) ? "start" : "stop");
 277		if (event_data->enumeration_status)
 278			ioc_info(mrioc, "enumeration_status(0x%08x)\n",
 279			    le32_to_cpu(event_data->enumeration_status));
 280		return;
 281	}
 282	case MPI3_EVENT_PREPARE_FOR_RESET:
 283		desc = "Prepare For Reset";
 284		break;
 285	case MPI3_EVENT_DIAGNOSTIC_BUFFER_STATUS_CHANGE:
 286		desc = "Diagnostic Buffer Status Change";
 287		break;
 288	}
 289
 290	if (!desc)
 291		return;
 292
 293	ioc_info(mrioc, "%s\n", desc);
 294}
 295
 296static void mpi3mr_handle_events(struct mpi3mr_ioc *mrioc,
 297	struct mpi3_default_reply *def_reply)
 298{
 299	struct mpi3_event_notification_reply *event_reply =
 300	    (struct mpi3_event_notification_reply *)def_reply;
 301
 302	mrioc->change_count = le16_to_cpu(event_reply->ioc_change_count);
 303	mpi3mr_print_event_data(mrioc, event_reply);
 304	mpi3mr_os_handle_events(mrioc, event_reply);
 305}
 306
 307static struct mpi3mr_drv_cmd *
 308mpi3mr_get_drv_cmd(struct mpi3mr_ioc *mrioc, u16 host_tag,
 309	struct mpi3_default_reply *def_reply)
 310{
 311	u16 idx;
 312
 313	switch (host_tag) {
 314	case MPI3MR_HOSTTAG_INITCMDS:
 315		return &mrioc->init_cmds;
 316	case MPI3MR_HOSTTAG_CFG_CMDS:
 317		return &mrioc->cfg_cmds;
 318	case MPI3MR_HOSTTAG_BSG_CMDS:
 319		return &mrioc->bsg_cmds;
 320	case MPI3MR_HOSTTAG_BLK_TMS:
 321		return &mrioc->host_tm_cmds;
 322	case MPI3MR_HOSTTAG_PEL_ABORT:
 323		return &mrioc->pel_abort_cmd;
 324	case MPI3MR_HOSTTAG_PEL_WAIT:
 325		return &mrioc->pel_cmds;
 326	case MPI3MR_HOSTTAG_TRANSPORT_CMDS:
 327		return &mrioc->transport_cmds;
 328	case MPI3MR_HOSTTAG_INVALID:
 329		if (def_reply && def_reply->function ==
 330		    MPI3_FUNCTION_EVENT_NOTIFICATION)
 331			mpi3mr_handle_events(mrioc, def_reply);
 332		return NULL;
 333	default:
 334		break;
 335	}
 336	if (host_tag >= MPI3MR_HOSTTAG_DEVRMCMD_MIN &&
 337	    host_tag <= MPI3MR_HOSTTAG_DEVRMCMD_MAX) {
 338		idx = host_tag - MPI3MR_HOSTTAG_DEVRMCMD_MIN;
 339		return &mrioc->dev_rmhs_cmds[idx];
 340	}
 341
 342	if (host_tag >= MPI3MR_HOSTTAG_EVTACKCMD_MIN &&
 343	    host_tag <= MPI3MR_HOSTTAG_EVTACKCMD_MAX) {
 344		idx = host_tag - MPI3MR_HOSTTAG_EVTACKCMD_MIN;
 345		return &mrioc->evtack_cmds[idx];
 346	}
 347
 348	return NULL;
 349}
 350
 351static void mpi3mr_process_admin_reply_desc(struct mpi3mr_ioc *mrioc,
 352	struct mpi3_default_reply_descriptor *reply_desc, u64 *reply_dma)
 353{
 354	u16 reply_desc_type, host_tag = 0;
 355	u16 ioc_status = MPI3_IOCSTATUS_SUCCESS;
 356	u16 masked_ioc_status = MPI3_IOCSTATUS_SUCCESS;
 357	u32 ioc_loginfo = 0, sense_count = 0;
 358	struct mpi3_status_reply_descriptor *status_desc;
 359	struct mpi3_address_reply_descriptor *addr_desc;
 360	struct mpi3_success_reply_descriptor *success_desc;
 361	struct mpi3_default_reply *def_reply = NULL;
 362	struct mpi3mr_drv_cmd *cmdptr = NULL;
 363	struct mpi3_scsi_io_reply *scsi_reply;
 364	struct scsi_sense_hdr sshdr;
 365	u8 *sense_buf = NULL;
 366
 367	*reply_dma = 0;
 368	reply_desc_type = le16_to_cpu(reply_desc->reply_flags) &
 369	    MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK;
 370	switch (reply_desc_type) {
 371	case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS:
 372		status_desc = (struct mpi3_status_reply_descriptor *)reply_desc;
 373		host_tag = le16_to_cpu(status_desc->host_tag);
 374		ioc_status = le16_to_cpu(status_desc->ioc_status);
 375		if (ioc_status &
 376		    MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL)
 377			ioc_loginfo = le32_to_cpu(status_desc->ioc_log_info);
 378		masked_ioc_status = ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
 379		mpi3mr_reply_trigger(mrioc, masked_ioc_status, ioc_loginfo);
 380		break;
 381	case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY:
 382		addr_desc = (struct mpi3_address_reply_descriptor *)reply_desc;
 383		*reply_dma = le64_to_cpu(addr_desc->reply_frame_address);
 384		def_reply = mpi3mr_get_reply_virt_addr(mrioc, *reply_dma);
 385		if (!def_reply)
 386			goto out;
 387		host_tag = le16_to_cpu(def_reply->host_tag);
 388		ioc_status = le16_to_cpu(def_reply->ioc_status);
 389		if (ioc_status &
 390		    MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL)
 391			ioc_loginfo = le32_to_cpu(def_reply->ioc_log_info);
 392		masked_ioc_status = ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
 393		if (def_reply->function == MPI3_FUNCTION_SCSI_IO) {
 394			scsi_reply = (struct mpi3_scsi_io_reply *)def_reply;
 395			sense_buf = mpi3mr_get_sensebuf_virt_addr(mrioc,
 396			    le64_to_cpu(scsi_reply->sense_data_buffer_address));
 397			sense_count = le32_to_cpu(scsi_reply->sense_count);
 398			if (sense_buf) {
 399				scsi_normalize_sense(sense_buf, sense_count,
 400				    &sshdr);
 401				mpi3mr_scsisense_trigger(mrioc, sshdr.sense_key,
 402				    sshdr.asc, sshdr.ascq);
 403			}
 404		}
 405		mpi3mr_reply_trigger(mrioc, masked_ioc_status, ioc_loginfo);
 406		break;
 407	case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS:
 408		success_desc = (struct mpi3_success_reply_descriptor *)reply_desc;
 409		host_tag = le16_to_cpu(success_desc->host_tag);
 410		break;
 411	default:
 412		break;
 413	}
 414
 415	cmdptr = mpi3mr_get_drv_cmd(mrioc, host_tag, def_reply);
 416	if (cmdptr) {
 417		if (cmdptr->state & MPI3MR_CMD_PENDING) {
 418			cmdptr->state |= MPI3MR_CMD_COMPLETE;
 419			cmdptr->ioc_loginfo = ioc_loginfo;
 420			if (host_tag == MPI3MR_HOSTTAG_BSG_CMDS)
 421				cmdptr->ioc_status = ioc_status;
 422			else
 423				cmdptr->ioc_status = masked_ioc_status;
 424			cmdptr->state &= ~MPI3MR_CMD_PENDING;
 425			if (def_reply) {
 426				cmdptr->state |= MPI3MR_CMD_REPLY_VALID;
 427				memcpy((u8 *)cmdptr->reply, (u8 *)def_reply,
 428				    mrioc->reply_sz);
 429			}
 430			if (sense_buf && cmdptr->sensebuf) {
 431				cmdptr->is_sense = 1;
 432				memcpy(cmdptr->sensebuf, sense_buf,
 433				       MPI3MR_SENSE_BUF_SZ);
 434			}
 435			if (cmdptr->is_waiting) {
 436				cmdptr->is_waiting = 0;
 437				complete(&cmdptr->done);
 438			} else if (cmdptr->callback)
 439				cmdptr->callback(mrioc, cmdptr);
 440		}
 441	}
 442out:
 443	if (sense_buf)
 444		mpi3mr_repost_sense_buf(mrioc,
 445		    le64_to_cpu(scsi_reply->sense_data_buffer_address));
 446}
 447
 448int mpi3mr_process_admin_reply_q(struct mpi3mr_ioc *mrioc)
 449{
 450	u32 exp_phase = mrioc->admin_reply_ephase;
 451	u32 admin_reply_ci = mrioc->admin_reply_ci;
 452	u32 num_admin_replies = 0;
 453	u64 reply_dma = 0;
 454	u16 threshold_comps = 0;
 455	struct mpi3_default_reply_descriptor *reply_desc;
 456
 457	if (!atomic_add_unless(&mrioc->admin_reply_q_in_use, 1, 1)) {
 458		atomic_inc(&mrioc->admin_pend_isr);
 459		return 0;
 460	}
 461
 462	atomic_set(&mrioc->admin_pend_isr, 0);
 463	reply_desc = (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base +
 464	    admin_reply_ci;
 465
 466	if ((le16_to_cpu(reply_desc->reply_flags) &
 467	    MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) {
 468		atomic_dec(&mrioc->admin_reply_q_in_use);
 469		return 0;
 470	}
 471
 472	do {
 473		if (mrioc->unrecoverable || mrioc->io_admin_reset_sync)
 474			break;
 475
 476		mrioc->admin_req_ci = le16_to_cpu(reply_desc->request_queue_ci);
 477		mpi3mr_process_admin_reply_desc(mrioc, reply_desc, &reply_dma);
 478		if (reply_dma)
 479			mpi3mr_repost_reply_buf(mrioc, reply_dma);
 480		num_admin_replies++;
 481		threshold_comps++;
 482		if (++admin_reply_ci == mrioc->num_admin_replies) {
 483			admin_reply_ci = 0;
 484			exp_phase ^= 1;
 485		}
 486		reply_desc =
 487		    (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base +
 488		    admin_reply_ci;
 489		if ((le16_to_cpu(reply_desc->reply_flags) &
 490		    MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase)
 491			break;
 492		if (threshold_comps == MPI3MR_THRESHOLD_REPLY_COUNT) {
 493			writel(admin_reply_ci,
 494			    &mrioc->sysif_regs->admin_reply_queue_ci);
 495			threshold_comps = 0;
 496		}
 497	} while (1);
 498
 499	writel(admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci);
 500	mrioc->admin_reply_ci = admin_reply_ci;
 501	mrioc->admin_reply_ephase = exp_phase;
 502	atomic_dec(&mrioc->admin_reply_q_in_use);
 503
 504	return num_admin_replies;
 505}
 506
 507/**
 508 * mpi3mr_get_reply_desc - get reply descriptor frame corresponding to
 509 *	queue's consumer index from operational reply descriptor queue.
 510 * @op_reply_q: op_reply_qinfo object
 511 * @reply_ci: operational reply descriptor's queue consumer index
 512 *
 513 * Returns: reply descriptor frame address
 514 */
 515static inline struct mpi3_default_reply_descriptor *
 516mpi3mr_get_reply_desc(struct op_reply_qinfo *op_reply_q, u32 reply_ci)
 517{
 518	void *segment_base_addr;
 519	struct segments *segments = op_reply_q->q_segments;
 520	struct mpi3_default_reply_descriptor *reply_desc = NULL;
 521
 522	segment_base_addr =
 523	    segments[reply_ci / op_reply_q->segment_qd].segment;
 524	reply_desc = (struct mpi3_default_reply_descriptor *)segment_base_addr +
 525	    (reply_ci % op_reply_q->segment_qd);
 526	return reply_desc;
 527}
 528
 529/**
 530 * mpi3mr_process_op_reply_q - Operational reply queue handler
 531 * @mrioc: Adapter instance reference
 532 * @op_reply_q: Operational reply queue info
 533 *
 534 * Checks the specific operational reply queue and drains the
 535 * reply queue entries until the queue is empty and process the
 536 * individual reply descriptors.
 537 *
 538 * Return: 0 if queue is already processed,or number of reply
 539 *	    descriptors processed.
 540 */
 541int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc,
 542	struct op_reply_qinfo *op_reply_q)
 543{
 544	struct op_req_qinfo *op_req_q;
 545	u32 exp_phase;
 546	u32 reply_ci;
 547	u32 num_op_reply = 0;
 548	u64 reply_dma = 0;
 549	struct mpi3_default_reply_descriptor *reply_desc;
 550	u16 req_q_idx = 0, reply_qidx, threshold_comps = 0;
 551
 552	reply_qidx = op_reply_q->qid - 1;
 553
 554	if (!atomic_add_unless(&op_reply_q->in_use, 1, 1))
 555		return 0;
 556
 557	exp_phase = op_reply_q->ephase;
 558	reply_ci = op_reply_q->ci;
 559
 560	reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci);
 561	if ((le16_to_cpu(reply_desc->reply_flags) &
 562	    MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) {
 563		atomic_dec(&op_reply_q->in_use);
 564		return 0;
 565	}
 566
 567	do {
 568		if (mrioc->unrecoverable || mrioc->io_admin_reset_sync)
 569			break;
 570
 571		req_q_idx = le16_to_cpu(reply_desc->request_queue_id) - 1;
 572		op_req_q = &mrioc->req_qinfo[req_q_idx];
 573
 574		WRITE_ONCE(op_req_q->ci, le16_to_cpu(reply_desc->request_queue_ci));
 575		mpi3mr_process_op_reply_desc(mrioc, reply_desc, &reply_dma,
 576		    reply_qidx);
 577
 578		if (reply_dma)
 579			mpi3mr_repost_reply_buf(mrioc, reply_dma);
 580		num_op_reply++;
 581		threshold_comps++;
 582
 583		if (++reply_ci == op_reply_q->num_replies) {
 584			reply_ci = 0;
 585			exp_phase ^= 1;
 586		}
 587
 588		reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci);
 589
 590		if ((le16_to_cpu(reply_desc->reply_flags) &
 591		    MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase)
 592			break;
 593#ifndef CONFIG_PREEMPT_RT
 594		/*
 595		 * Exit completion loop to avoid CPU lockup
 596		 * Ensure remaining completion happens from threaded ISR.
 597		 */
 598		if (num_op_reply > mrioc->max_host_ios) {
 599			op_reply_q->enable_irq_poll = true;
 600			break;
 601		}
 602#endif
 603		if (threshold_comps == MPI3MR_THRESHOLD_REPLY_COUNT) {
 604			writel(reply_ci,
 605			    &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].consumer_index);
 606			atomic_sub(threshold_comps, &op_reply_q->pend_ios);
 607			threshold_comps = 0;
 608		}
 609	} while (1);
 610
 611	writel(reply_ci,
 612	    &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].consumer_index);
 613	op_reply_q->ci = reply_ci;
 614	op_reply_q->ephase = exp_phase;
 615	atomic_sub(threshold_comps, &op_reply_q->pend_ios);
 616	atomic_dec(&op_reply_q->in_use);
 617	return num_op_reply;
 618}
 619
 620/**
 621 * mpi3mr_blk_mq_poll - Operational reply queue handler
 622 * @shost: SCSI Host reference
 623 * @queue_num: Request queue number (w.r.t OS it is hardware context number)
 624 *
 625 * Checks the specific operational reply queue and drains the
 626 * reply queue entries until the queue is empty and process the
 627 * individual reply descriptors.
 628 *
 629 * Return: 0 if queue is already processed,or number of reply
 630 *	    descriptors processed.
 631 */
 632int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num)
 633{
 634	int num_entries = 0;
 635	struct mpi3mr_ioc *mrioc;
 636
 637	mrioc = (struct mpi3mr_ioc *)shost->hostdata;
 638
 639	if ((mrioc->reset_in_progress || mrioc->prepare_for_reset ||
 640	    mrioc->unrecoverable || mrioc->pci_err_recovery))
 641		return 0;
 642
 643	num_entries = mpi3mr_process_op_reply_q(mrioc,
 644			&mrioc->op_reply_qinfo[queue_num]);
 645
 646	return num_entries;
 647}
 648
 649static irqreturn_t mpi3mr_isr_primary(int irq, void *privdata)
 650{
 651	struct mpi3mr_intr_info *intr_info = privdata;
 652	struct mpi3mr_ioc *mrioc;
 653	u16 midx;
 654	u32 num_admin_replies = 0, num_op_reply = 0;
 655
 656	if (!intr_info)
 657		return IRQ_NONE;
 658
 659	mrioc = intr_info->mrioc;
 660
 661	if (!mrioc->intr_enabled)
 662		return IRQ_NONE;
 663
 664	midx = intr_info->msix_index;
 665
 666	if (!midx)
 667		num_admin_replies = mpi3mr_process_admin_reply_q(mrioc);
 668	if (intr_info->op_reply_q)
 669		num_op_reply = mpi3mr_process_op_reply_q(mrioc,
 670		    intr_info->op_reply_q);
 671
 672	if (num_admin_replies || num_op_reply)
 673		return IRQ_HANDLED;
 674	else
 675		return IRQ_NONE;
 676}
 677
 678#ifndef CONFIG_PREEMPT_RT
 679
 680static irqreturn_t mpi3mr_isr(int irq, void *privdata)
 681{
 682	struct mpi3mr_intr_info *intr_info = privdata;
 683	int ret;
 684
 685	if (!intr_info)
 686		return IRQ_NONE;
 687
 688	/* Call primary ISR routine */
 689	ret = mpi3mr_isr_primary(irq, privdata);
 690
 691	/*
 692	 * If more IOs are expected, schedule IRQ polling thread.
 693	 * Otherwise exit from ISR.
 694	 */
 695	if (!intr_info->op_reply_q)
 696		return ret;
 697
 698	if (!intr_info->op_reply_q->enable_irq_poll ||
 699	    !atomic_read(&intr_info->op_reply_q->pend_ios))
 700		return ret;
 701
 702	disable_irq_nosync(intr_info->os_irq);
 703
 704	return IRQ_WAKE_THREAD;
 705}
 706
 707/**
 708 * mpi3mr_isr_poll - Reply queue polling routine
 709 * @irq: IRQ
 710 * @privdata: Interrupt info
 711 *
 712 * poll for pending I/O completions in a loop until pending I/Os
 713 * present or controller queue depth I/Os are processed.
 714 *
 715 * Return: IRQ_NONE or IRQ_HANDLED
 716 */
 717static irqreturn_t mpi3mr_isr_poll(int irq, void *privdata)
 718{
 719	struct mpi3mr_intr_info *intr_info = privdata;
 720	struct mpi3mr_ioc *mrioc;
 721	u16 midx;
 722	u32 num_op_reply = 0;
 723
 724	if (!intr_info || !intr_info->op_reply_q)
 725		return IRQ_NONE;
 726
 727	mrioc = intr_info->mrioc;
 728	midx = intr_info->msix_index;
 729
 730	/* Poll for pending IOs completions */
 731	do {
 732		if (!mrioc->intr_enabled || mrioc->unrecoverable)
 733			break;
 734
 735		if (!midx)
 736			mpi3mr_process_admin_reply_q(mrioc);
 737		if (intr_info->op_reply_q)
 738			num_op_reply +=
 739			    mpi3mr_process_op_reply_q(mrioc,
 740				intr_info->op_reply_q);
 741
 742		usleep_range(MPI3MR_IRQ_POLL_SLEEP, MPI3MR_IRQ_POLL_SLEEP + 1);
 743
 744	} while (atomic_read(&intr_info->op_reply_q->pend_ios) &&
 745	    (num_op_reply < mrioc->max_host_ios));
 746
 747	intr_info->op_reply_q->enable_irq_poll = false;
 748	enable_irq(intr_info->os_irq);
 749
 750	return IRQ_HANDLED;
 751}
 752
 753#endif
 754
 755/**
 756 * mpi3mr_request_irq - Request IRQ and register ISR
 757 * @mrioc: Adapter instance reference
 758 * @index: IRQ vector index
 759 *
 760 * Request threaded ISR with primary ISR and secondary
 761 *
 762 * Return: 0 on success and non zero on failures.
 763 */
 764static inline int mpi3mr_request_irq(struct mpi3mr_ioc *mrioc, u16 index)
 765{
 766	struct pci_dev *pdev = mrioc->pdev;
 767	struct mpi3mr_intr_info *intr_info = mrioc->intr_info + index;
 768	int retval = 0;
 769
 770	intr_info->mrioc = mrioc;
 771	intr_info->msix_index = index;
 772	intr_info->op_reply_q = NULL;
 773
 774	snprintf(intr_info->name, MPI3MR_NAME_LENGTH, "%s%d-msix%d",
 775	    mrioc->driver_name, mrioc->id, index);
 776
 777#ifndef CONFIG_PREEMPT_RT
 778	retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr,
 779	    mpi3mr_isr_poll, IRQF_SHARED, intr_info->name, intr_info);
 780#else
 781	retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr_primary,
 782	    NULL, IRQF_SHARED, intr_info->name, intr_info);
 783#endif
 784	if (retval) {
 785		ioc_err(mrioc, "%s: Unable to allocate interrupt %d!\n",
 786		    intr_info->name, pci_irq_vector(pdev, index));
 787		return retval;
 788	}
 789
 790	intr_info->os_irq = pci_irq_vector(pdev, index);
 791	return retval;
 792}
 793
 794static void mpi3mr_calc_poll_queues(struct mpi3mr_ioc *mrioc, u16 max_vectors)
 795{
 796	if (!mrioc->requested_poll_qcount)
 797		return;
 798
 799	/* Reserved for Admin and Default Queue */
 800	if (max_vectors > 2 &&
 801		(mrioc->requested_poll_qcount < max_vectors - 2)) {
 802		ioc_info(mrioc,
 803		    "enabled polled queues (%d) msix (%d)\n",
 804		    mrioc->requested_poll_qcount, max_vectors);
 805	} else {
 806		ioc_info(mrioc,
 807		    "disabled polled queues (%d) msix (%d) because of no resources for default queue\n",
 808		    mrioc->requested_poll_qcount, max_vectors);
 809		mrioc->requested_poll_qcount = 0;
 810	}
 811}
 812
 813/**
 814 * mpi3mr_setup_isr - Setup ISR for the controller
 815 * @mrioc: Adapter instance reference
 816 * @setup_one: Request one IRQ or more
 817 *
 818 * Allocate IRQ vectors and call mpi3mr_request_irq to setup ISR
 819 *
 820 * Return: 0 on success and non zero on failures.
 821 */
 822static int mpi3mr_setup_isr(struct mpi3mr_ioc *mrioc, u8 setup_one)
 823{
 824	unsigned int irq_flags = PCI_IRQ_MSIX;
 825	int max_vectors, min_vec;
 826	int retval;
 827	int i;
 828	struct irq_affinity desc = { .pre_vectors =  1, .post_vectors = 1 };
 829
 830	if (mrioc->is_intr_info_set)
 831		return 0;
 832
 833	mpi3mr_cleanup_isr(mrioc);
 834
 835	if (setup_one || reset_devices) {
 836		max_vectors = 1;
 837		retval = pci_alloc_irq_vectors(mrioc->pdev,
 838		    1, max_vectors, irq_flags);
 839		if (retval < 0) {
 840			ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n",
 841			    retval);
 842			goto out_failed;
 843		}
 844	} else {
 845		max_vectors =
 846		    min_t(int, mrioc->cpu_count + 1 +
 847			mrioc->requested_poll_qcount, mrioc->msix_count);
 848
 849		mpi3mr_calc_poll_queues(mrioc, max_vectors);
 850
 851		ioc_info(mrioc,
 852		    "MSI-X vectors supported: %d, no of cores: %d,",
 853		    mrioc->msix_count, mrioc->cpu_count);
 854		ioc_info(mrioc,
 855		    "MSI-x vectors requested: %d poll_queues %d\n",
 856		    max_vectors, mrioc->requested_poll_qcount);
 857
 858		desc.post_vectors = mrioc->requested_poll_qcount;
 859		min_vec = desc.pre_vectors + desc.post_vectors;
 860		irq_flags |= PCI_IRQ_AFFINITY | PCI_IRQ_ALL_TYPES;
 861
 862		retval = pci_alloc_irq_vectors_affinity(mrioc->pdev,
 863			min_vec, max_vectors, irq_flags, &desc);
 864
 865		if (retval < 0) {
 866			ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n",
 867			    retval);
 868			goto out_failed;
 869		}
 870
 871
 872		/*
 873		 * If only one MSI-x is allocated, then MSI-x 0 will be shared
 874		 * between Admin queue and operational queue
 875		 */
 876		if (retval == min_vec)
 877			mrioc->op_reply_q_offset = 0;
 878		else if (retval != (max_vectors)) {
 879			ioc_info(mrioc,
 880			    "allocated vectors (%d) are less than configured (%d)\n",
 881			    retval, max_vectors);
 882		}
 883
 884		max_vectors = retval;
 885		mrioc->op_reply_q_offset = (max_vectors > 1) ? 1 : 0;
 886
 887		mpi3mr_calc_poll_queues(mrioc, max_vectors);
 888
 889	}
 890
 891	mrioc->intr_info = kzalloc(sizeof(struct mpi3mr_intr_info) * max_vectors,
 892	    GFP_KERNEL);
 893	if (!mrioc->intr_info) {
 894		retval = -ENOMEM;
 895		pci_free_irq_vectors(mrioc->pdev);
 896		goto out_failed;
 897	}
 898	for (i = 0; i < max_vectors; i++) {
 899		retval = mpi3mr_request_irq(mrioc, i);
 900		if (retval) {
 901			mrioc->intr_info_count = i;
 902			goto out_failed;
 903		}
 904	}
 905	if (reset_devices || !setup_one)
 906		mrioc->is_intr_info_set = true;
 907	mrioc->intr_info_count = max_vectors;
 908	mpi3mr_ioc_enable_intr(mrioc);
 909	return 0;
 910
 911out_failed:
 912	mpi3mr_cleanup_isr(mrioc);
 913
 914	return retval;
 915}
 916
 917static const struct {
 918	enum mpi3mr_iocstate value;
 919	char *name;
 920} mrioc_states[] = {
 921	{ MRIOC_STATE_READY, "ready" },
 922	{ MRIOC_STATE_FAULT, "fault" },
 923	{ MRIOC_STATE_RESET, "reset" },
 924	{ MRIOC_STATE_BECOMING_READY, "becoming ready" },
 925	{ MRIOC_STATE_RESET_REQUESTED, "reset requested" },
 926	{ MRIOC_STATE_UNRECOVERABLE, "unrecoverable error" },
 927};
 928
 929static const char *mpi3mr_iocstate_name(enum mpi3mr_iocstate mrioc_state)
 930{
 931	int i;
 932	char *name = NULL;
 933
 934	for (i = 0; i < ARRAY_SIZE(mrioc_states); i++) {
 935		if (mrioc_states[i].value == mrioc_state) {
 936			name = mrioc_states[i].name;
 937			break;
 938		}
 939	}
 940	return name;
 941}
 942
 943/* Reset reason to name mapper structure*/
 944static const struct {
 945	enum mpi3mr_reset_reason value;
 946	char *name;
 947} mpi3mr_reset_reason_codes[] = {
 948	{ MPI3MR_RESET_FROM_BRINGUP, "timeout in bringup" },
 949	{ MPI3MR_RESET_FROM_FAULT_WATCH, "fault" },
 950	{ MPI3MR_RESET_FROM_APP, "application invocation" },
 951	{ MPI3MR_RESET_FROM_EH_HOS, "error handling" },
 952	{ MPI3MR_RESET_FROM_TM_TIMEOUT, "TM timeout" },
 953	{ MPI3MR_RESET_FROM_APP_TIMEOUT, "application command timeout" },
 954	{ MPI3MR_RESET_FROM_MUR_FAILURE, "MUR failure" },
 955	{ MPI3MR_RESET_FROM_CTLR_CLEANUP, "timeout in controller cleanup" },
 956	{ MPI3MR_RESET_FROM_CIACTIV_FAULT, "component image activation fault" },
 957	{ MPI3MR_RESET_FROM_PE_TIMEOUT, "port enable timeout" },
 958	{ MPI3MR_RESET_FROM_TSU_TIMEOUT, "time stamp update timeout" },
 959	{ MPI3MR_RESET_FROM_DELREQQ_TIMEOUT, "delete request queue timeout" },
 960	{ MPI3MR_RESET_FROM_DELREPQ_TIMEOUT, "delete reply queue timeout" },
 961	{
 962		MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT,
 963		"create request queue timeout"
 964	},
 965	{
 966		MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT,
 967		"create reply queue timeout"
 968	},
 969	{ MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT, "IOC facts timeout" },
 970	{ MPI3MR_RESET_FROM_IOCINIT_TIMEOUT, "IOC init timeout" },
 971	{ MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT, "event notify timeout" },
 972	{ MPI3MR_RESET_FROM_EVTACK_TIMEOUT, "event acknowledgment timeout" },
 973	{
 974		MPI3MR_RESET_FROM_CIACTVRST_TIMER,
 975		"component image activation timeout"
 976	},
 977	{
 978		MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT,
 979		"get package version timeout"
 980	},
 981	{ MPI3MR_RESET_FROM_SYSFS, "sysfs invocation" },
 982	{ MPI3MR_RESET_FROM_SYSFS_TIMEOUT, "sysfs TM timeout" },
 983	{
 984		MPI3MR_RESET_FROM_DIAG_BUFFER_POST_TIMEOUT,
 985		"diagnostic buffer post timeout"
 986	},
 987	{
 988		MPI3MR_RESET_FROM_DIAG_BUFFER_RELEASE_TIMEOUT,
 989		"diagnostic buffer release timeout"
 990	},
 991	{ MPI3MR_RESET_FROM_FIRMWARE, "firmware asynchronous reset" },
 992	{ MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT, "configuration request timeout"},
 993	{ MPI3MR_RESET_FROM_SAS_TRANSPORT_TIMEOUT, "timeout of a SAS transport layer request" },
 994};
 995
 996/**
 997 * mpi3mr_reset_rc_name - get reset reason code name
 998 * @reason_code: reset reason code value
 999 *
1000 * Map reset reason to an NULL terminated ASCII string
1001 *
1002 * Return: name corresponding to reset reason value or NULL.
1003 */
1004static const char *mpi3mr_reset_rc_name(enum mpi3mr_reset_reason reason_code)
1005{
1006	int i;
1007	char *name = NULL;
1008
1009	for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_reason_codes); i++) {
1010		if (mpi3mr_reset_reason_codes[i].value == reason_code) {
1011			name = mpi3mr_reset_reason_codes[i].name;
1012			break;
1013		}
1014	}
1015	return name;
1016}
1017
1018/* Reset type to name mapper structure*/
1019static const struct {
1020	u16 reset_type;
1021	char *name;
1022} mpi3mr_reset_types[] = {
1023	{ MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, "soft" },
1024	{ MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, "diag fault" },
1025};
1026
1027/**
1028 * mpi3mr_reset_type_name - get reset type name
1029 * @reset_type: reset type value
1030 *
1031 * Map reset type to an NULL terminated ASCII string
1032 *
1033 * Return: name corresponding to reset type value or NULL.
1034 */
1035static const char *mpi3mr_reset_type_name(u16 reset_type)
1036{
1037	int i;
1038	char *name = NULL;
1039
1040	for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_types); i++) {
1041		if (mpi3mr_reset_types[i].reset_type == reset_type) {
1042			name = mpi3mr_reset_types[i].name;
1043			break;
1044		}
1045	}
1046	return name;
1047}
1048
1049/**
1050 * mpi3mr_is_fault_recoverable - Read fault code and decide
1051 * whether the controller can be recoverable
1052 * @mrioc: Adapter instance reference
1053 * Return: true if fault is recoverable, false otherwise.
1054 */
1055static inline bool mpi3mr_is_fault_recoverable(struct mpi3mr_ioc *mrioc)
1056{
1057	u32 fault;
1058
1059	fault = (readl(&mrioc->sysif_regs->fault) &
1060		      MPI3_SYSIF_FAULT_CODE_MASK);
1061
1062	switch (fault) {
1063	case MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED:
1064	case MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED:
1065		ioc_warn(mrioc,
1066		    "controller requires system power cycle, marking controller as unrecoverable\n");
1067		return false;
1068	case MPI3_SYSIF_FAULT_CODE_INSUFFICIENT_PCI_SLOT_POWER:
1069		ioc_warn(mrioc,
1070		    "controller faulted due to insufficient power,\n"
1071		    " try by connecting it to a different slot\n");
1072		return false;
1073	default:
1074		break;
1075	}
1076	return true;
1077}
1078
1079/**
1080 * mpi3mr_print_fault_info - Display fault information
1081 * @mrioc: Adapter instance reference
1082 *
1083 * Display the controller fault information if there is a
1084 * controller fault.
1085 *
1086 * Return: Nothing.
1087 */
1088void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc)
1089{
1090	u32 ioc_status, code, code1, code2, code3;
1091
1092	ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1093
1094	if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) {
1095		code = readl(&mrioc->sysif_regs->fault);
1096		code1 = readl(&mrioc->sysif_regs->fault_info[0]);
1097		code2 = readl(&mrioc->sysif_regs->fault_info[1]);
1098		code3 = readl(&mrioc->sysif_regs->fault_info[2]);
1099
1100		ioc_info(mrioc,
1101		    "fault code(0x%08X): Additional code: (0x%08X:0x%08X:0x%08X)\n",
1102		    code, code1, code2, code3);
1103	}
1104}
1105
1106/**
1107 * mpi3mr_get_iocstate - Get IOC State
1108 * @mrioc: Adapter instance reference
1109 *
1110 * Return a proper IOC state enum based on the IOC status and
1111 * IOC configuration and unrcoverable state of the controller.
1112 *
1113 * Return: Current IOC state.
1114 */
1115enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc)
1116{
1117	u32 ioc_status, ioc_config;
1118	u8 ready, enabled;
1119
1120	ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1121	ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1122
1123	if (mrioc->unrecoverable)
1124		return MRIOC_STATE_UNRECOVERABLE;
1125	if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)
1126		return MRIOC_STATE_FAULT;
1127
1128	ready = (ioc_status & MPI3_SYSIF_IOC_STATUS_READY);
1129	enabled = (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC);
1130
1131	if (ready && enabled)
1132		return MRIOC_STATE_READY;
1133	if ((!ready) && (!enabled))
1134		return MRIOC_STATE_RESET;
1135	if ((!ready) && (enabled))
1136		return MRIOC_STATE_BECOMING_READY;
1137
1138	return MRIOC_STATE_RESET_REQUESTED;
1139}
1140
1141/**
1142 * mpi3mr_free_ioctl_dma_memory - free memory for ioctl dma
1143 * @mrioc: Adapter instance reference
1144 *
1145 * Free the DMA memory allocated for IOCTL handling purpose.
1146 *
1147 * Return: None
1148 */
1149static void mpi3mr_free_ioctl_dma_memory(struct mpi3mr_ioc *mrioc)
1150{
1151	struct dma_memory_desc *mem_desc;
1152	u16 i;
1153
1154	if (!mrioc->ioctl_dma_pool)
1155		return;
1156
1157	for (i = 0; i < MPI3MR_NUM_IOCTL_SGE; i++) {
1158		mem_desc = &mrioc->ioctl_sge[i];
1159		if (mem_desc->addr) {
1160			dma_pool_free(mrioc->ioctl_dma_pool,
1161				      mem_desc->addr,
1162				      mem_desc->dma_addr);
1163			mem_desc->addr = NULL;
1164		}
1165	}
1166	dma_pool_destroy(mrioc->ioctl_dma_pool);
1167	mrioc->ioctl_dma_pool = NULL;
1168	mem_desc = &mrioc->ioctl_chain_sge;
1169
1170	if (mem_desc->addr) {
1171		dma_free_coherent(&mrioc->pdev->dev, mem_desc->size,
1172				  mem_desc->addr, mem_desc->dma_addr);
1173		mem_desc->addr = NULL;
1174	}
1175	mem_desc = &mrioc->ioctl_resp_sge;
1176	if (mem_desc->addr) {
1177		dma_free_coherent(&mrioc->pdev->dev, mem_desc->size,
1178				  mem_desc->addr, mem_desc->dma_addr);
1179		mem_desc->addr = NULL;
1180	}
1181
1182	mrioc->ioctl_sges_allocated = false;
1183}
1184
1185/**
1186 * mpi3mr_alloc_ioctl_dma_memory - Alloc memory for ioctl dma
1187 * @mrioc: Adapter instance reference
1188 *
1189 * This function allocates dmaable memory required to handle the
1190 * application issued MPI3 IOCTL requests.
1191 *
1192 * Return: None
1193 */
1194static void mpi3mr_alloc_ioctl_dma_memory(struct mpi3mr_ioc *mrioc)
1195
1196{
1197	struct dma_memory_desc *mem_desc;
1198	u16 i;
1199
1200	mrioc->ioctl_dma_pool = dma_pool_create("ioctl dma pool",
1201						&mrioc->pdev->dev,
1202						MPI3MR_IOCTL_SGE_SIZE,
1203						MPI3MR_PAGE_SIZE_4K, 0);
1204
1205	if (!mrioc->ioctl_dma_pool) {
1206		ioc_err(mrioc, "ioctl_dma_pool: dma_pool_create failed\n");
1207		goto out_failed;
1208	}
1209
1210	for (i = 0; i < MPI3MR_NUM_IOCTL_SGE; i++) {
1211		mem_desc = &mrioc->ioctl_sge[i];
1212		mem_desc->size = MPI3MR_IOCTL_SGE_SIZE;
1213		mem_desc->addr = dma_pool_zalloc(mrioc->ioctl_dma_pool,
1214						 GFP_KERNEL,
1215						 &mem_desc->dma_addr);
1216		if (!mem_desc->addr)
1217			goto out_failed;
1218	}
1219
1220	mem_desc = &mrioc->ioctl_chain_sge;
1221	mem_desc->size = MPI3MR_PAGE_SIZE_4K;
1222	mem_desc->addr = dma_alloc_coherent(&mrioc->pdev->dev,
1223					    mem_desc->size,
1224					    &mem_desc->dma_addr,
1225					    GFP_KERNEL);
1226	if (!mem_desc->addr)
1227		goto out_failed;
1228
1229	mem_desc = &mrioc->ioctl_resp_sge;
1230	mem_desc->size = MPI3MR_PAGE_SIZE_4K;
1231	mem_desc->addr = dma_alloc_coherent(&mrioc->pdev->dev,
1232					    mem_desc->size,
1233					    &mem_desc->dma_addr,
1234					    GFP_KERNEL);
1235	if (!mem_desc->addr)
1236		goto out_failed;
1237
1238	mrioc->ioctl_sges_allocated = true;
1239
1240	return;
1241out_failed:
1242	ioc_warn(mrioc, "cannot allocate DMA memory for the mpt commands\n"
1243		 "from the applications, application interface for MPT command is disabled\n");
1244	mpi3mr_free_ioctl_dma_memory(mrioc);
1245}
1246
1247/**
1248 * mpi3mr_clear_reset_history - clear reset history
1249 * @mrioc: Adapter instance reference
1250 *
1251 * Write the reset history bit in IOC status to clear the bit,
1252 * if it is already set.
1253 *
1254 * Return: Nothing.
1255 */
1256static inline void mpi3mr_clear_reset_history(struct mpi3mr_ioc *mrioc)
1257{
1258	u32 ioc_status;
1259
1260	ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1261	if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)
1262		writel(ioc_status, &mrioc->sysif_regs->ioc_status);
1263}
1264
1265/**
1266 * mpi3mr_issue_and_process_mur - Message unit Reset handler
1267 * @mrioc: Adapter instance reference
1268 * @reset_reason: Reset reason code
1269 *
1270 * Issue Message unit Reset to the controller and wait for it to
1271 * be complete.
1272 *
1273 * Return: 0 on success, -1 on failure.
1274 */
1275static int mpi3mr_issue_and_process_mur(struct mpi3mr_ioc *mrioc,
1276	u32 reset_reason)
1277{
1278	u32 ioc_config, timeout, ioc_status, scratch_pad0;
1279	int retval = -1;
1280
1281	ioc_info(mrioc, "Issuing Message unit Reset(MUR)\n");
1282	if (mrioc->unrecoverable) {
1283		ioc_info(mrioc, "IOC is unrecoverable MUR not issued\n");
1284		return retval;
1285	}
1286	mpi3mr_clear_reset_history(mrioc);
1287	scratch_pad0 = ((MPI3MR_RESET_REASON_OSTYPE_LINUX <<
1288			 MPI3MR_RESET_REASON_OSTYPE_SHIFT) |
1289			(mrioc->facts.ioc_num <<
1290			 MPI3MR_RESET_REASON_IOCNUM_SHIFT) | reset_reason);
1291	writel(scratch_pad0, &mrioc->sysif_regs->scratchpad[0]);
1292	ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1293	ioc_config &= ~MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC;
1294	writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1295
1296	timeout = MPI3MR_MUR_TIMEOUT * 10;
1297	do {
1298		ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1299		if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)) {
1300			mpi3mr_clear_reset_history(mrioc);
1301			break;
1302		}
1303		if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) {
1304			mpi3mr_print_fault_info(mrioc);
1305			break;
1306		}
1307		msleep(100);
1308	} while (--timeout);
1309
1310	ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1311	if (timeout && !((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) ||
1312	      (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) ||
1313	      (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC)))
1314		retval = 0;
1315
1316	ioc_info(mrioc, "Base IOC Sts/Config after %s MUR is (0x%08x)/(0x%08x)\n",
1317	    (!retval) ? "successful" : "failed", ioc_status, ioc_config);
1318	return retval;
1319}
1320
1321/**
1322 * mpi3mr_revalidate_factsdata - validate IOCFacts parameters
1323 * during reset/resume
1324 * @mrioc: Adapter instance reference
1325 *
1326 * Return: zero if the new IOCFacts parameters value is compatible with
1327 * older values else return -EPERM
1328 */
1329static int
1330mpi3mr_revalidate_factsdata(struct mpi3mr_ioc *mrioc)
1331{
1332	unsigned long *removepend_bitmap;
1333
1334	if (mrioc->facts.reply_sz > mrioc->reply_sz) {
1335		ioc_err(mrioc,
1336		    "cannot increase reply size from %d to %d\n",
1337		    mrioc->reply_sz, mrioc->facts.reply_sz);
1338		return -EPERM;
1339	}
1340
1341	if (mrioc->facts.max_op_reply_q < mrioc->num_op_reply_q) {
1342		ioc_err(mrioc,
1343		    "cannot reduce number of operational reply queues from %d to %d\n",
1344		    mrioc->num_op_reply_q,
1345		    mrioc->facts.max_op_reply_q);
1346		return -EPERM;
1347	}
1348
1349	if (mrioc->facts.max_op_req_q < mrioc->num_op_req_q) {
1350		ioc_err(mrioc,
1351		    "cannot reduce number of operational request queues from %d to %d\n",
1352		    mrioc->num_op_req_q, mrioc->facts.max_op_req_q);
1353		return -EPERM;
1354	}
1355
1356	if (mrioc->shost->max_sectors != (mrioc->facts.max_data_length / 512))
1357		ioc_err(mrioc, "Warning: The maximum data transfer length\n"
1358			    "\tchanged after reset: previous(%d), new(%d),\n"
1359			    "the driver cannot change this at run time\n",
1360			    mrioc->shost->max_sectors * 512, mrioc->facts.max_data_length);
1361
1362	if ((mrioc->sas_transport_enabled) && (mrioc->facts.ioc_capabilities &
1363	    MPI3_IOCFACTS_CAPABILITY_MULTIPATH_SUPPORTED))
1364		ioc_err(mrioc,
1365		    "critical error: multipath capability is enabled at the\n"
1366		    "\tcontroller while sas transport support is enabled at the\n"
1367		    "\tdriver, please reboot the system or reload the driver\n");
1368
1369	if (mrioc->seg_tb_support) {
1370		if (!(mrioc->facts.ioc_capabilities &
1371		     MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_TRACE_SUPPORTED)) {
1372			ioc_err(mrioc,
1373			    "critical error: previously enabled segmented trace\n"
1374			    " buffer capability is disabled after reset. Please\n"
1375			    " update the firmware or reboot the system or\n"
1376			    " reload the driver to enable trace diag buffer\n");
1377			mrioc->diag_buffers[0].disabled_after_reset = true;
1378		} else
1379			mrioc->diag_buffers[0].disabled_after_reset = false;
1380	}
1381
1382	if (mrioc->facts.max_devhandle > mrioc->dev_handle_bitmap_bits) {
1383		removepend_bitmap = bitmap_zalloc(mrioc->facts.max_devhandle,
1384						  GFP_KERNEL);
1385		if (!removepend_bitmap) {
1386			ioc_err(mrioc,
1387				"failed to increase removepend_bitmap bits from %d to %d\n",
1388				mrioc->dev_handle_bitmap_bits,
1389				mrioc->facts.max_devhandle);
1390			return -EPERM;
1391		}
1392		bitmap_free(mrioc->removepend_bitmap);
1393		mrioc->removepend_bitmap = removepend_bitmap;
1394		ioc_info(mrioc,
1395			 "increased bits of dev_handle_bitmap from %d to %d\n",
1396			 mrioc->dev_handle_bitmap_bits,
1397			 mrioc->facts.max_devhandle);
1398		mrioc->dev_handle_bitmap_bits = mrioc->facts.max_devhandle;
1399	}
1400
1401	return 0;
1402}
1403
1404/**
1405 * mpi3mr_bring_ioc_ready - Bring controller to ready state
1406 * @mrioc: Adapter instance reference
1407 *
1408 * Set Enable IOC bit in IOC configuration register and wait for
1409 * the controller to become ready.
1410 *
1411 * Return: 0 on success, appropriate error on failure.
1412 */
1413static int mpi3mr_bring_ioc_ready(struct mpi3mr_ioc *mrioc)
1414{
1415	u32 ioc_config, ioc_status, timeout, host_diagnostic;
1416	int retval = 0;
1417	enum mpi3mr_iocstate ioc_state;
1418	u64 base_info;
1419	u8 retry = 0;
1420	u64 start_time, elapsed_time_sec;
1421
1422retry_bring_ioc_ready:
1423
1424	ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1425	ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1426	base_info = lo_hi_readq(&mrioc->sysif_regs->ioc_information);
1427	ioc_info(mrioc, "ioc_status(0x%08x), ioc_config(0x%08x), ioc_info(0x%016llx) at the bringup\n",
1428	    ioc_status, ioc_config, base_info);
1429
1430	if (!mpi3mr_is_fault_recoverable(mrioc)) {
1431		mrioc->unrecoverable = 1;
1432		goto out_device_not_present;
1433	}
1434
1435	/*The timeout value is in 2sec unit, changing it to seconds*/
1436	mrioc->ready_timeout =
1437	    ((base_info & MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK) >>
1438	    MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT) * 2;
1439
1440	ioc_info(mrioc, "ready timeout: %d seconds\n", mrioc->ready_timeout);
1441
1442	ioc_state = mpi3mr_get_iocstate(mrioc);
1443	ioc_info(mrioc, "controller is in %s state during detection\n",
1444	    mpi3mr_iocstate_name(ioc_state));
1445
1446	timeout = mrioc->ready_timeout * 10;
1447
1448	do {
1449		ioc_state = mpi3mr_get_iocstate(mrioc);
1450
1451		if (ioc_state != MRIOC_STATE_BECOMING_READY &&
1452		    ioc_state != MRIOC_STATE_RESET_REQUESTED)
1453			break;
1454
1455		if (!pci_device_is_present(mrioc->pdev)) {
1456			mrioc->unrecoverable = 1;
1457			ioc_err(mrioc, "controller is not present while waiting to reset\n");
1458			goto out_device_not_present;
1459		}
1460
1461		msleep(100);
1462	} while (--timeout);
1463
1464	if (ioc_state == MRIOC_STATE_READY) {
1465		ioc_info(mrioc, "issuing message unit reset (MUR) to bring to reset state\n");
1466		retval = mpi3mr_issue_and_process_mur(mrioc,
1467		    MPI3MR_RESET_FROM_BRINGUP);
1468		ioc_state = mpi3mr_get_iocstate(mrioc);
1469		if (retval)
1470			ioc_err(mrioc,
1471			    "message unit reset failed with error %d current state %s\n",
1472			    retval, mpi3mr_iocstate_name(ioc_state));
1473	}
1474	if (ioc_state != MRIOC_STATE_RESET) {
1475		if (ioc_state == MRIOC_STATE_FAULT) {
1476			timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
1477			mpi3mr_print_fault_info(mrioc);
1478			do {
1479				host_diagnostic =
1480					readl(&mrioc->sysif_regs->host_diagnostic);
1481				if (!(host_diagnostic &
1482				      MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
1483					break;
1484				if (!pci_device_is_present(mrioc->pdev)) {
1485					mrioc->unrecoverable = 1;
1486					ioc_err(mrioc, "controller is not present at the bringup\n");
1487					goto out_device_not_present;
1488				}
1489				msleep(100);
1490			} while (--timeout);
1491		}
1492		mpi3mr_print_fault_info(mrioc);
1493		ioc_info(mrioc, "issuing soft reset to bring to reset state\n");
1494		retval = mpi3mr_issue_reset(mrioc,
1495		    MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET,
1496		    MPI3MR_RESET_FROM_BRINGUP);
1497		if (retval) {
1498			ioc_err(mrioc,
1499			    "soft reset failed with error %d\n", retval);
1500			goto out_failed;
1501		}
1502	}
1503	ioc_state = mpi3mr_get_iocstate(mrioc);
1504	if (ioc_state != MRIOC_STATE_RESET) {
1505		ioc_err(mrioc,
1506		    "cannot bring controller to reset state, current state: %s\n",
1507		    mpi3mr_iocstate_name(ioc_state));
1508		goto out_failed;
1509	}
1510	mpi3mr_clear_reset_history(mrioc);
1511	retval = mpi3mr_setup_admin_qpair(mrioc);
1512	if (retval) {
1513		ioc_err(mrioc, "failed to setup admin queues: error %d\n",
1514		    retval);
1515		goto out_failed;
1516	}
1517
1518	ioc_info(mrioc, "bringing controller to ready state\n");
1519	ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1520	ioc_config |= MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC;
1521	writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1522
1523	if (retry == 0)
1524		start_time = jiffies;
1525
1526	timeout = mrioc->ready_timeout * 10;
1527	do {
1528		ioc_state = mpi3mr_get_iocstate(mrioc);
1529		if (ioc_state == MRIOC_STATE_READY) {
1530			ioc_info(mrioc,
1531			    "successfully transitioned to %s state\n",
1532			    mpi3mr_iocstate_name(ioc_state));
1533			mpi3mr_clear_reset_history(mrioc);
1534			return 0;
1535		}
1536		ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1537		if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) ||
1538		    (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) {
1539			mpi3mr_print_fault_info(mrioc);
1540			goto out_failed;
1541		}
1542		if (!pci_device_is_present(mrioc->pdev)) {
1543			mrioc->unrecoverable = 1;
1544			ioc_err(mrioc,
1545			    "controller is not present at the bringup\n");
1546			retval = -1;
1547			goto out_device_not_present;
1548		}
1549		msleep(100);
1550		elapsed_time_sec = jiffies_to_msecs(jiffies - start_time)/1000;
1551	} while (elapsed_time_sec < mrioc->ready_timeout);
1552
1553	ioc_state = mpi3mr_get_iocstate(mrioc);
1554	if (ioc_state == MRIOC_STATE_READY) {
1555		ioc_info(mrioc,
1556		    "successfully transitioned to %s state after %llu seconds\n",
1557		    mpi3mr_iocstate_name(ioc_state), elapsed_time_sec);
1558		mpi3mr_clear_reset_history(mrioc);
1559		return 0;
1560	}
1561
1562out_failed:
1563	elapsed_time_sec = jiffies_to_msecs(jiffies - start_time)/1000;
1564	if ((retry < 2) && (elapsed_time_sec < (mrioc->ready_timeout - 60))) {
1565		retry++;
1566
1567		ioc_warn(mrioc, "retrying to bring IOC ready, retry_count:%d\n"
1568				" elapsed time =%llu\n", retry, elapsed_time_sec);
1569
1570		goto retry_bring_ioc_ready;
1571	}
1572	ioc_state = mpi3mr_get_iocstate(mrioc);
1573	ioc_err(mrioc,
1574	    "failed to bring to ready state,  current state: %s\n",
1575	    mpi3mr_iocstate_name(ioc_state));
1576out_device_not_present:
1577	return retval;
1578}
1579
1580/**
1581 * mpi3mr_soft_reset_success - Check softreset is success or not
1582 * @ioc_status: IOC status register value
1583 * @ioc_config: IOC config register value
1584 *
1585 * Check whether the soft reset is successful or not based on
1586 * IOC status and IOC config register values.
1587 *
1588 * Return: True when the soft reset is success, false otherwise.
1589 */
1590static inline bool
1591mpi3mr_soft_reset_success(u32 ioc_status, u32 ioc_config)
1592{
1593	if (!((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) ||
1594	    (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC)))
1595		return true;
1596	return false;
1597}
1598
1599/**
1600 * mpi3mr_diagfault_success - Check diag fault is success or not
1601 * @mrioc: Adapter reference
1602 * @ioc_status: IOC status register value
1603 *
1604 * Check whether the controller hit diag reset fault code.
1605 *
1606 * Return: True when there is diag fault, false otherwise.
1607 */
1608static inline bool mpi3mr_diagfault_success(struct mpi3mr_ioc *mrioc,
1609	u32 ioc_status)
1610{
1611	u32 fault;
1612
1613	if (!(ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT))
1614		return false;
1615	fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK;
1616	if (fault == MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET) {
1617		mpi3mr_print_fault_info(mrioc);
1618		return true;
1619	}
1620	return false;
1621}
1622
1623/**
1624 * mpi3mr_set_diagsave - Set diag save bit for snapdump
1625 * @mrioc: Adapter reference
1626 *
1627 * Set diag save bit in IOC configuration register to enable
1628 * snapdump.
1629 *
1630 * Return: Nothing.
1631 */
1632static inline void mpi3mr_set_diagsave(struct mpi3mr_ioc *mrioc)
1633{
1634	u32 ioc_config;
1635
1636	ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1637	ioc_config |= MPI3_SYSIF_IOC_CONFIG_DIAG_SAVE;
1638	writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1639}
1640
1641/**
1642 * mpi3mr_issue_reset - Issue reset to the controller
1643 * @mrioc: Adapter reference
1644 * @reset_type: Reset type
1645 * @reset_reason: Reset reason code
1646 *
1647 * Unlock the host diagnostic registers and write the specific
1648 * reset type to that, wait for reset acknowledgment from the
1649 * controller, if the reset is not successful retry for the
1650 * predefined number of times.
1651 *
1652 * Return: 0 on success, non-zero on failure.
1653 */
1654static int mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type,
1655	u16 reset_reason)
1656{
1657	int retval = -1;
1658	u8 unlock_retry_count = 0;
1659	u32 host_diagnostic, ioc_status, ioc_config, scratch_pad0;
1660	u32 timeout = MPI3MR_RESET_ACK_TIMEOUT * 10;
1661
1662	if ((reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET) &&
1663	    (reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT))
1664		return retval;
1665	if (mrioc->unrecoverable)
1666		return retval;
1667	if (reset_reason == MPI3MR_RESET_FROM_FIRMWARE) {
1668		retval = 0;
1669		return retval;
1670	}
1671
1672	ioc_info(mrioc, "%s reset due to %s(0x%x)\n",
1673	    mpi3mr_reset_type_name(reset_type),
1674	    mpi3mr_reset_rc_name(reset_reason), reset_reason);
1675
1676	mpi3mr_clear_reset_history(mrioc);
1677	do {
1678		ioc_info(mrioc,
1679		    "Write magic sequence to unlock host diag register (retry=%d)\n",
1680		    ++unlock_retry_count);
1681		if (unlock_retry_count >= MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT) {
1682			ioc_err(mrioc,
1683			    "%s reset failed due to unlock failure, host_diagnostic(0x%08x)\n",
1684			    mpi3mr_reset_type_name(reset_type),
1685			    host_diagnostic);
1686			mrioc->unrecoverable = 1;
1687			return retval;
1688		}
1689
1690		writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH,
1691		    &mrioc->sysif_regs->write_sequence);
1692		writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_1ST,
1693		    &mrioc->sysif_regs->write_sequence);
1694		writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND,
1695		    &mrioc->sysif_regs->write_sequence);
1696		writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_3RD,
1697		    &mrioc->sysif_regs->write_sequence);
1698		writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_4TH,
1699		    &mrioc->sysif_regs->write_sequence);
1700		writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_5TH,
1701		    &mrioc->sysif_regs->write_sequence);
1702		writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_6TH,
1703		    &mrioc->sysif_regs->write_sequence);
1704		usleep_range(1000, 1100);
1705		host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
1706		ioc_info(mrioc,
1707		    "wrote magic sequence: retry_count(%d), host_diagnostic(0x%08x)\n",
1708		    unlock_retry_count, host_diagnostic);
1709	} while (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE));
1710
1711	scratch_pad0 = ((MPI3MR_RESET_REASON_OSTYPE_LINUX <<
1712	    MPI3MR_RESET_REASON_OSTYPE_SHIFT) | (mrioc->facts.ioc_num <<
1713	    MPI3MR_RESET_REASON_IOCNUM_SHIFT) | reset_reason);
1714	writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]);
1715	writel(host_diagnostic | reset_type,
1716	    &mrioc->sysif_regs->host_diagnostic);
1717	switch (reset_type) {
1718	case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET:
1719		do {
1720			ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1721			ioc_config =
1722			    readl(&mrioc->sysif_regs->ioc_configuration);
1723			if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)
1724			    && mpi3mr_soft_reset_success(ioc_status, ioc_config)
1725			    ) {
1726				mpi3mr_clear_reset_history(mrioc);
1727				retval = 0;
1728				break;
1729			}
1730			msleep(100);
1731		} while (--timeout);
1732		mpi3mr_print_fault_info(mrioc);
1733		break;
1734	case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT:
1735		do {
1736			ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1737			if (mpi3mr_diagfault_success(mrioc, ioc_status)) {
1738				retval = 0;
1739				break;
1740			}
1741			msleep(100);
1742		} while (--timeout);
1743		break;
1744	default:
1745		break;
1746	}
1747
1748	writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND,
1749	    &mrioc->sysif_regs->write_sequence);
1750
1751	ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1752	ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1753	ioc_info(mrioc,
1754	    "ioc_status/ioc_config after %s reset is (0x%08x)/(0x%08x)\n",
1755	    (!retval)?"successful":"failed", ioc_status,
1756	    ioc_config);
1757	if (retval)
1758		mrioc->unrecoverable = 1;
1759	return retval;
1760}
1761
1762/**
1763 * mpi3mr_admin_request_post - Post request to admin queue
1764 * @mrioc: Adapter reference
1765 * @admin_req: MPI3 request
1766 * @admin_req_sz: Request size
1767 * @ignore_reset: Ignore reset in process
1768 *
1769 * Post the MPI3 request into admin request queue and
1770 * inform the controller, if the queue is full return
1771 * appropriate error.
1772 *
1773 * Return: 0 on success, non-zero on failure.
1774 */
1775int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req,
1776	u16 admin_req_sz, u8 ignore_reset)
1777{
1778	u16 areq_pi = 0, areq_ci = 0, max_entries = 0;
1779	int retval = 0;
1780	unsigned long flags;
1781	u8 *areq_entry;
1782
1783	if (mrioc->unrecoverable) {
1784		ioc_err(mrioc, "%s : Unrecoverable controller\n", __func__);
1785		return -EFAULT;
1786	}
1787
1788	spin_lock_irqsave(&mrioc->admin_req_lock, flags);
1789	areq_pi = mrioc->admin_req_pi;
1790	areq_ci = mrioc->admin_req_ci;
1791	max_entries = mrioc->num_admin_req;
1792	if ((areq_ci == (areq_pi + 1)) || ((!areq_ci) &&
1793	    (areq_pi == (max_entries - 1)))) {
1794		ioc_err(mrioc, "AdminReqQ full condition detected\n");
1795		retval = -EAGAIN;
1796		goto out;
1797	}
1798	if (!ignore_reset && mrioc->reset_in_progress) {
1799		ioc_err(mrioc, "AdminReqQ submit reset in progress\n");
1800		retval = -EAGAIN;
1801		goto out;
1802	}
1803	if (mrioc->pci_err_recovery) {
1804		ioc_err(mrioc, "admin request queue submission failed due to pci error recovery in progress\n");
1805		retval = -EAGAIN;
1806		goto out;
1807	}
1808
1809	areq_entry = (u8 *)mrioc->admin_req_base +
1810	    (areq_pi * MPI3MR_ADMIN_REQ_FRAME_SZ);
1811	memset(areq_entry, 0, MPI3MR_ADMIN_REQ_FRAME_SZ);
1812	memcpy(areq_entry, (u8 *)admin_req, admin_req_sz);
1813
1814	if (++areq_pi == max_entries)
1815		areq_pi = 0;
1816	mrioc->admin_req_pi = areq_pi;
1817
1818	writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi);
1819
1820out:
1821	spin_unlock_irqrestore(&mrioc->admin_req_lock, flags);
1822
1823	return retval;
1824}
1825
1826/**
1827 * mpi3mr_free_op_req_q_segments - free request memory segments
1828 * @mrioc: Adapter instance reference
1829 * @q_idx: operational request queue index
1830 *
1831 * Free memory segments allocated for operational request queue
1832 *
1833 * Return: Nothing.
1834 */
1835static void mpi3mr_free_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx)
1836{
1837	u16 j;
1838	int size;
1839	struct segments *segments;
1840
1841	segments = mrioc->req_qinfo[q_idx].q_segments;
1842	if (!segments)
1843		return;
1844
1845	if (mrioc->enable_segqueue) {
1846		size = MPI3MR_OP_REQ_Q_SEG_SIZE;
1847		if (mrioc->req_qinfo[q_idx].q_segment_list) {
1848			dma_free_coherent(&mrioc->pdev->dev,
1849			    MPI3MR_MAX_SEG_LIST_SIZE,
1850			    mrioc->req_qinfo[q_idx].q_segment_list,
1851			    mrioc->req_qinfo[q_idx].q_segment_list_dma);
1852			mrioc->req_qinfo[q_idx].q_segment_list = NULL;
1853		}
1854	} else
1855		size = mrioc->req_qinfo[q_idx].segment_qd *
1856		    mrioc->facts.op_req_sz;
1857
1858	for (j = 0; j < mrioc->req_qinfo[q_idx].num_segments; j++) {
1859		if (!segments[j].segment)
1860			continue;
1861		dma_free_coherent(&mrioc->pdev->dev,
1862		    size, segments[j].segment, segments[j].segment_dma);
1863		segments[j].segment = NULL;
1864	}
1865	kfree(mrioc->req_qinfo[q_idx].q_segments);
1866	mrioc->req_qinfo[q_idx].q_segments = NULL;
1867	mrioc->req_qinfo[q_idx].qid = 0;
1868}
1869
1870/**
1871 * mpi3mr_free_op_reply_q_segments - free reply memory segments
1872 * @mrioc: Adapter instance reference
1873 * @q_idx: operational reply queue index
1874 *
1875 * Free memory segments allocated for operational reply queue
1876 *
1877 * Return: Nothing.
1878 */
1879static void mpi3mr_free_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx)
1880{
1881	u16 j;
1882	int size;
1883	struct segments *segments;
1884
1885	segments = mrioc->op_reply_qinfo[q_idx].q_segments;
1886	if (!segments)
1887		return;
1888
1889	if (mrioc->enable_segqueue) {
1890		size = MPI3MR_OP_REP_Q_SEG_SIZE;
1891		if (mrioc->op_reply_qinfo[q_idx].q_segment_list) {
1892			dma_free_coherent(&mrioc->pdev->dev,
1893			    MPI3MR_MAX_SEG_LIST_SIZE,
1894			    mrioc->op_reply_qinfo[q_idx].q_segment_list,
1895			    mrioc->op_reply_qinfo[q_idx].q_segment_list_dma);
1896			mrioc->op_reply_qinfo[q_idx].q_segment_list = NULL;
1897		}
1898	} else
1899		size = mrioc->op_reply_qinfo[q_idx].segment_qd *
1900		    mrioc->op_reply_desc_sz;
1901
1902	for (j = 0; j < mrioc->op_reply_qinfo[q_idx].num_segments; j++) {
1903		if (!segments[j].segment)
1904			continue;
1905		dma_free_coherent(&mrioc->pdev->dev,
1906		    size, segments[j].segment, segments[j].segment_dma);
1907		segments[j].segment = NULL;
1908	}
1909
1910	kfree(mrioc->op_reply_qinfo[q_idx].q_segments);
1911	mrioc->op_reply_qinfo[q_idx].q_segments = NULL;
1912	mrioc->op_reply_qinfo[q_idx].qid = 0;
1913}
1914
1915/**
1916 * mpi3mr_delete_op_reply_q - delete operational reply queue
1917 * @mrioc: Adapter instance reference
1918 * @qidx: operational reply queue index
1919 *
1920 * Delete operatinal reply queue by issuing MPI request
1921 * through admin queue.
1922 *
1923 * Return:  0 on success, non-zero on failure.
1924 */
1925static int mpi3mr_delete_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx)
1926{
1927	struct mpi3_delete_reply_queue_request delq_req;
1928	struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
1929	int retval = 0;
1930	u16 reply_qid = 0, midx;
1931
1932	reply_qid = op_reply_q->qid;
1933
1934	midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset);
1935
1936	if (!reply_qid)	{
1937		retval = -1;
1938		ioc_err(mrioc, "Issue DelRepQ: called with invalid ReqQID\n");
1939		goto out;
1940	}
1941
1942	(op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount-- :
1943	    mrioc->active_poll_qcount--;
1944
1945	memset(&delq_req, 0, sizeof(delq_req));
1946	mutex_lock(&mrioc->init_cmds.mutex);
1947	if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
1948		retval = -1;
1949		ioc_err(mrioc, "Issue DelRepQ: Init command is in use\n");
1950		mutex_unlock(&mrioc->init_cmds.mutex);
1951		goto out;
1952	}
1953	mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
1954	mrioc->init_cmds.is_waiting = 1;
1955	mrioc->init_cmds.callback = NULL;
1956	delq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
1957	delq_req.function = MPI3_FUNCTION_DELETE_REPLY_QUEUE;
1958	delq_req.queue_id = cpu_to_le16(reply_qid);
1959
1960	init_completion(&mrioc->init_cmds.done);
1961	retval = mpi3mr_admin_request_post(mrioc, &delq_req, sizeof(delq_req),
1962	    1);
1963	if (retval) {
1964		ioc_err(mrioc, "Issue DelRepQ: Admin Post failed\n");
1965		goto out_unlock;
1966	}
1967	wait_for_completion_timeout(&mrioc->init_cmds.done,
1968	    (MPI3MR_INTADMCMD_TIMEOUT * HZ));
1969	if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
1970		ioc_err(mrioc, "delete reply queue timed out\n");
1971		mpi3mr_check_rh_fault_ioc(mrioc,
1972		    MPI3MR_RESET_FROM_DELREPQ_TIMEOUT);
1973		retval = -1;
1974		goto out_unlock;
1975	}
1976	if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
1977	    != MPI3_IOCSTATUS_SUCCESS) {
1978		ioc_err(mrioc,
1979		    "Issue DelRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
1980		    (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
1981		    mrioc->init_cmds.ioc_loginfo);
1982		retval = -1;
1983		goto out_unlock;
1984	}
1985	mrioc->intr_info[midx].op_reply_q = NULL;
1986
1987	mpi3mr_free_op_reply_q_segments(mrioc, qidx);
1988out_unlock:
1989	mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
1990	mutex_unlock(&mrioc->init_cmds.mutex);
1991out:
1992
1993	return retval;
1994}
1995
1996/**
1997 * mpi3mr_alloc_op_reply_q_segments -Alloc segmented reply pool
1998 * @mrioc: Adapter instance reference
1999 * @qidx: request queue index
2000 *
2001 * Allocate segmented memory pools for operational reply
2002 * queue.
2003 *
2004 * Return: 0 on success, non-zero on failure.
2005 */
2006static int mpi3mr_alloc_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx)
2007{
2008	struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
2009	int i, size;
2010	u64 *q_segment_list_entry = NULL;
2011	struct segments *segments;
2012
2013	if (mrioc->enable_segqueue) {
2014		op_reply_q->segment_qd =
2015		    MPI3MR_OP_REP_Q_SEG_SIZE / mrioc->op_reply_desc_sz;
2016
2017		size = MPI3MR_OP_REP_Q_SEG_SIZE;
2018
2019		op_reply_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev,
2020		    MPI3MR_MAX_SEG_LIST_SIZE, &op_reply_q->q_segment_list_dma,
2021		    GFP_KERNEL);
2022		if (!op_reply_q->q_segment_list)
2023			return -ENOMEM;
2024		q_segment_list_entry = (u64 *)op_reply_q->q_segment_list;
2025	} else {
2026		op_reply_q->segment_qd = op_reply_q->num_replies;
2027		size = op_reply_q->num_replies * mrioc->op_reply_desc_sz;
2028	}
2029
2030	op_reply_q->num_segments = DIV_ROUND_UP(op_reply_q->num_replies,
2031	    op_reply_q->segment_qd);
2032
2033	op_reply_q->q_segments = kcalloc(op_reply_q->num_segments,
2034	    sizeof(struct segments), GFP_KERNEL);
2035	if (!op_reply_q->q_segments)
2036		return -ENOMEM;
2037
2038	segments = op_reply_q->q_segments;
2039	for (i = 0; i < op_reply_q->num_segments; i++) {
2040		segments[i].segment =
2041		    dma_alloc_coherent(&mrioc->pdev->dev,
2042		    size, &segments[i].segment_dma, GFP_KERNEL);
2043		if (!segments[i].segment)
2044			return -ENOMEM;
2045		if (mrioc->enable_segqueue)
2046			q_segment_list_entry[i] =
2047			    (unsigned long)segments[i].segment_dma;
2048	}
2049
2050	return 0;
2051}
2052
2053/**
2054 * mpi3mr_alloc_op_req_q_segments - Alloc segmented req pool.
2055 * @mrioc: Adapter instance reference
2056 * @qidx: request queue index
2057 *
2058 * Allocate segmented memory pools for operational request
2059 * queue.
2060 *
2061 * Return: 0 on success, non-zero on failure.
2062 */
2063static int mpi3mr_alloc_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx)
2064{
2065	struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx;
2066	int i, size;
2067	u64 *q_segment_list_entry = NULL;
2068	struct segments *segments;
2069
2070	if (mrioc->enable_segqueue) {
2071		op_req_q->segment_qd =
2072		    MPI3MR_OP_REQ_Q_SEG_SIZE / mrioc->facts.op_req_sz;
2073
2074		size = MPI3MR_OP_REQ_Q_SEG_SIZE;
2075
2076		op_req_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev,
2077		    MPI3MR_MAX_SEG_LIST_SIZE, &op_req_q->q_segment_list_dma,
2078		    GFP_KERNEL);
2079		if (!op_req_q->q_segment_list)
2080			return -ENOMEM;
2081		q_segment_list_entry = (u64 *)op_req_q->q_segment_list;
2082
2083	} else {
2084		op_req_q->segment_qd = op_req_q->num_requests;
2085		size = op_req_q->num_requests * mrioc->facts.op_req_sz;
2086	}
2087
2088	op_req_q->num_segments = DIV_ROUND_UP(op_req_q->num_requests,
2089	    op_req_q->segment_qd);
2090
2091	op_req_q->q_segments = kcalloc(op_req_q->num_segments,
2092	    sizeof(struct segments), GFP_KERNEL);
2093	if (!op_req_q->q_segments)
2094		return -ENOMEM;
2095
2096	segments = op_req_q->q_segments;
2097	for (i = 0; i < op_req_q->num_segments; i++) {
2098		segments[i].segment =
2099		    dma_alloc_coherent(&mrioc->pdev->dev,
2100		    size, &segments[i].segment_dma, GFP_KERNEL);
2101		if (!segments[i].segment)
2102			return -ENOMEM;
2103		if (mrioc->enable_segqueue)
2104			q_segment_list_entry[i] =
2105			    (unsigned long)segments[i].segment_dma;
2106	}
2107
2108	return 0;
2109}
2110
2111/**
2112 * mpi3mr_create_op_reply_q - create operational reply queue
2113 * @mrioc: Adapter instance reference
2114 * @qidx: operational reply queue index
2115 *
2116 * Create operatinal reply queue by issuing MPI request
2117 * through admin queue.
2118 *
2119 * Return:  0 on success, non-zero on failure.
2120 */
2121static int mpi3mr_create_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx)
2122{
2123	struct mpi3_create_reply_queue_request create_req;
2124	struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
2125	int retval = 0;
2126	u16 reply_qid = 0, midx;
2127
2128	reply_qid = op_reply_q->qid;
2129
2130	midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset);
2131
2132	if (reply_qid) {
2133		retval = -1;
2134		ioc_err(mrioc, "CreateRepQ: called for duplicate qid %d\n",
2135		    reply_qid);
2136
2137		return retval;
2138	}
2139
2140	reply_qid = qidx + 1;
2141
2142	if (mrioc->pdev->device == MPI3_MFGPAGE_DEVID_SAS4116) {
2143		if (mrioc->pdev->revision)
2144			op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD;
2145		else
2146			op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD4K;
2147	} else
2148		op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD2K;
2149
2150	op_reply_q->ci = 0;
2151	op_reply_q->ephase = 1;
2152	atomic_set(&op_reply_q->pend_ios, 0);
2153	atomic_set(&op_reply_q->in_use, 0);
2154	op_reply_q->enable_irq_poll = false;
2155	op_reply_q->qfull_watermark =
2156		op_reply_q->num_replies - (MPI3MR_THRESHOLD_REPLY_COUNT * 2);
2157
2158	if (!op_reply_q->q_segments) {
2159		retval = mpi3mr_alloc_op_reply_q_segments(mrioc, qidx);
2160		if (retval) {
2161			mpi3mr_free_op_reply_q_segments(mrioc, qidx);
2162			goto out;
2163		}
2164	}
2165
2166	memset(&create_req, 0, sizeof(create_req));
2167	mutex_lock(&mrioc->init_cmds.mutex);
2168	if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2169		retval = -1;
2170		ioc_err(mrioc, "CreateRepQ: Init command is in use\n");
2171		goto out_unlock;
2172	}
2173	mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2174	mrioc->init_cmds.is_waiting = 1;
2175	mrioc->init_cmds.callback = NULL;
2176	create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2177	create_req.function = MPI3_FUNCTION_CREATE_REPLY_QUEUE;
2178	create_req.queue_id = cpu_to_le16(reply_qid);
2179
2180	if (midx < (mrioc->intr_info_count - mrioc->requested_poll_qcount))
2181		op_reply_q->qtype = MPI3MR_DEFAULT_QUEUE;
2182	else
2183		op_reply_q->qtype = MPI3MR_POLL_QUEUE;
2184
2185	if (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) {
2186		create_req.flags =
2187			MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE;
2188		create_req.msix_index =
2189			cpu_to_le16(mrioc->intr_info[midx].msix_index);
2190	} else {
2191		create_req.msix_index = cpu_to_le16(mrioc->intr_info_count - 1);
2192		ioc_info(mrioc, "create reply queue(polled): for qid(%d), midx(%d)\n",
2193			reply_qid, midx);
2194		if (!mrioc->active_poll_qcount)
2195			disable_irq_nosync(pci_irq_vector(mrioc->pdev,
2196			    mrioc->intr_info_count - 1));
2197	}
2198
2199	if (mrioc->enable_segqueue) {
2200		create_req.flags |=
2201		    MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED;
2202		create_req.base_address = cpu_to_le64(
2203		    op_reply_q->q_segment_list_dma);
2204	} else
2205		create_req.base_address = cpu_to_le64(
2206		    op_reply_q->q_segments[0].segment_dma);
2207
2208	create_req.size = cpu_to_le16(op_reply_q->num_replies);
2209
2210	init_completion(&mrioc->init_cmds.done);
2211	retval = mpi3mr_admin_request_post(mrioc, &create_req,
2212	    sizeof(create_req), 1);
2213	if (retval) {
2214		ioc_err(mrioc, "CreateRepQ: Admin Post failed\n");
2215		goto out_unlock;
2216	}
2217	wait_for_completion_timeout(&mrioc->init_cmds.done,
2218	    (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2219	if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2220		ioc_err(mrioc, "create reply queue timed out\n");
2221		mpi3mr_check_rh_fault_ioc(mrioc,
2222		    MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT);
2223		retval = -1;
2224		goto out_unlock;
2225	}
2226	if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2227	    != MPI3_IOCSTATUS_SUCCESS) {
2228		ioc_err(mrioc,
2229		    "CreateRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2230		    (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2231		    mrioc->init_cmds.ioc_loginfo);
2232		retval = -1;
2233		goto out_unlock;
2234	}
2235	op_reply_q->qid = reply_qid;
2236	if (midx < mrioc->intr_info_count)
2237		mrioc->intr_info[midx].op_reply_q = op_reply_q;
2238
2239	(op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount++ :
2240	    mrioc->active_poll_qcount++;
2241
2242out_unlock:
2243	mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2244	mutex_unlock(&mrioc->init_cmds.mutex);
2245out:
2246
2247	return retval;
2248}
2249
2250/**
2251 * mpi3mr_create_op_req_q - create operational request queue
2252 * @mrioc: Adapter instance reference
2253 * @idx: operational request queue index
2254 * @reply_qid: Reply queue ID
2255 *
2256 * Create operatinal request queue by issuing MPI request
2257 * through admin queue.
2258 *
2259 * Return:  0 on success, non-zero on failure.
2260 */
2261static int mpi3mr_create_op_req_q(struct mpi3mr_ioc *mrioc, u16 idx,
2262	u16 reply_qid)
2263{
2264	struct mpi3_create_request_queue_request create_req;
2265	struct op_req_qinfo *op_req_q = mrioc->req_qinfo + idx;
2266	int retval = 0;
2267	u16 req_qid = 0;
2268
2269	req_qid = op_req_q->qid;
2270
2271	if (req_qid) {
2272		retval = -1;
2273		ioc_err(mrioc, "CreateReqQ: called for duplicate qid %d\n",
2274		    req_qid);
2275
2276		return retval;
2277	}
2278	req_qid = idx + 1;
2279
2280	op_req_q->num_requests = MPI3MR_OP_REQ_Q_QD;
2281	op_req_q->ci = 0;
2282	op_req_q->pi = 0;
2283	op_req_q->reply_qid = reply_qid;
2284	spin_lock_init(&op_req_q->q_lock);
2285
2286	if (!op_req_q->q_segments) {
2287		retval = mpi3mr_alloc_op_req_q_segments(mrioc, idx);
2288		if (retval) {
2289			mpi3mr_free_op_req_q_segments(mrioc, idx);
2290			goto out;
2291		}
2292	}
2293
2294	memset(&create_req, 0, sizeof(create_req));
2295	mutex_lock(&mrioc->init_cmds.mutex);
2296	if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2297		retval = -1;
2298		ioc_err(mrioc, "CreateReqQ: Init command is in use\n");
2299		goto out_unlock;
2300	}
2301	mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2302	mrioc->init_cmds.is_waiting = 1;
2303	mrioc->init_cmds.callback = NULL;
2304	create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2305	create_req.function = MPI3_FUNCTION_CREATE_REQUEST_QUEUE;
2306	create_req.queue_id = cpu_to_le16(req_qid);
2307	if (mrioc->enable_segqueue) {
2308		create_req.flags =
2309		    MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED;
2310		create_req.base_address = cpu_to_le64(
2311		    op_req_q->q_segment_list_dma);
2312	} else
2313		create_req.base_address = cpu_to_le64(
2314		    op_req_q->q_segments[0].segment_dma);
2315	create_req.reply_queue_id = cpu_to_le16(reply_qid);
2316	create_req.size = cpu_to_le16(op_req_q->num_requests);
2317
2318	init_completion(&mrioc->init_cmds.done);
2319	retval = mpi3mr_admin_request_post(mrioc, &create_req,
2320	    sizeof(create_req), 1);
2321	if (retval) {
2322		ioc_err(mrioc, "CreateReqQ: Admin Post failed\n");
2323		goto out_unlock;
2324	}
2325	wait_for_completion_timeout(&mrioc->init_cmds.done,
2326	    (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2327	if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2328		ioc_err(mrioc, "create request queue timed out\n");
2329		mpi3mr_check_rh_fault_ioc(mrioc,
2330		    MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT);
2331		retval = -1;
2332		goto out_unlock;
2333	}
2334	if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2335	    != MPI3_IOCSTATUS_SUCCESS) {
2336		ioc_err(mrioc,
2337		    "CreateReqQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2338		    (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2339		    mrioc->init_cmds.ioc_loginfo);
2340		retval = -1;
2341		goto out_unlock;
2342	}
2343	op_req_q->qid = req_qid;
2344
2345out_unlock:
2346	mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2347	mutex_unlock(&mrioc->init_cmds.mutex);
2348out:
2349
2350	return retval;
2351}
2352
2353/**
2354 * mpi3mr_create_op_queues - create operational queue pairs
2355 * @mrioc: Adapter instance reference
2356 *
2357 * Allocate memory for operational queue meta data and call
2358 * create request and reply queue functions.
2359 *
2360 * Return: 0 on success, non-zero on failures.
2361 */
2362static int mpi3mr_create_op_queues(struct mpi3mr_ioc *mrioc)
2363{
2364	int retval = 0;
2365	u16 num_queues = 0, i = 0, msix_count_op_q = 1;
2366	u32 ioc_status;
2367	enum mpi3mr_iocstate ioc_state;
2368
2369	num_queues = min_t(int, mrioc->facts.max_op_reply_q,
2370	    mrioc->facts.max_op_req_q);
2371
2372	msix_count_op_q =
2373	    mrioc->intr_info_count - mrioc->op_reply_q_offset;
2374	if (!mrioc->num_queues)
2375		mrioc->num_queues = min_t(int, num_queues, msix_count_op_q);
2376	/*
2377	 * During reset set the num_queues to the number of queues
2378	 * that was set before the reset.
2379	 */
2380	num_queues = mrioc->num_op_reply_q ?
2381	    mrioc->num_op_reply_q : mrioc->num_queues;
2382	ioc_info(mrioc, "trying to create %d operational queue pairs\n",
2383	    num_queues);
2384
2385	if (!mrioc->req_qinfo) {
2386		mrioc->req_qinfo = kcalloc(num_queues,
2387		    sizeof(struct op_req_qinfo), GFP_KERNEL);
2388		if (!mrioc->req_qinfo) {
2389			retval = -1;
2390			goto out_failed;
2391		}
2392
2393		mrioc->op_reply_qinfo = kzalloc(sizeof(struct op_reply_qinfo) *
2394		    num_queues, GFP_KERNEL);
2395		if (!mrioc->op_reply_qinfo) {
2396			retval = -1;
2397			goto out_failed;
2398		}
2399	}
2400
2401	if (mrioc->enable_segqueue)
2402		ioc_info(mrioc,
2403		    "allocating operational queues through segmented queues\n");
2404
2405	for (i = 0; i < num_queues; i++) {
2406		if (mpi3mr_create_op_reply_q(mrioc, i)) {
2407			ioc_err(mrioc, "Cannot create OP RepQ %d\n", i);
2408			break;
2409		}
2410		if (mpi3mr_create_op_req_q(mrioc, i,
2411		    mrioc->op_reply_qinfo[i].qid)) {
2412			ioc_err(mrioc, "Cannot create OP ReqQ %d\n", i);
2413			mpi3mr_delete_op_reply_q(mrioc, i);
2414			break;
2415		}
2416	}
2417
2418	if (i == 0) {
2419		/* Not even one queue is created successfully*/
2420		retval = -1;
2421		goto out_failed;
2422	}
2423	ioc_status = readl(&mrioc->sysif_regs->ioc_status);
2424	ioc_state = mpi3mr_get_iocstate(mrioc);
2425	if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) ||
2426	    ioc_state != MRIOC_STATE_READY) {
2427		mpi3mr_print_fault_info(mrioc);
2428		retval = -1;
2429		goto out_failed;
2430	}
2431	mrioc->num_op_reply_q = mrioc->num_op_req_q = i;
2432	ioc_info(mrioc,
2433	    "successfully created %d operational queue pairs(default/polled) queue = (%d/%d)\n",
2434	    mrioc->num_op_reply_q, mrioc->default_qcount,
2435	    mrioc->active_poll_qcount);
2436
2437	return retval;
2438out_failed:
2439	kfree(mrioc->req_qinfo);
2440	mrioc->req_qinfo = NULL;
2441
2442	kfree(mrioc->op_reply_qinfo);
2443	mrioc->op_reply_qinfo = NULL;
2444
2445	return retval;
2446}
2447
2448/**
2449 * mpi3mr_op_request_post - Post request to operational queue
2450 * @mrioc: Adapter reference
2451 * @op_req_q: Operational request queue info
2452 * @req: MPI3 request
2453 *
2454 * Post the MPI3 request into operational request queue and
2455 * inform the controller, if the queue is full return
2456 * appropriate error.
2457 *
2458 * Return: 0 on success, non-zero on failure.
2459 */
2460int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc,
2461	struct op_req_qinfo *op_req_q, u8 *req)
2462{
2463	u16 pi = 0, max_entries, reply_qidx = 0, midx;
2464	int retval = 0;
2465	unsigned long flags;
2466	u8 *req_entry;
2467	void *segment_base_addr;
2468	u16 req_sz = mrioc->facts.op_req_sz;
2469	struct segments *segments = op_req_q->q_segments;
2470	struct op_reply_qinfo *op_reply_q = NULL;
2471
2472	reply_qidx = op_req_q->reply_qid - 1;
2473	op_reply_q = mrioc->op_reply_qinfo + reply_qidx;
2474
2475	if (mrioc->unrecoverable)
2476		return -EFAULT;
2477
2478	spin_lock_irqsave(&op_req_q->q_lock, flags);
2479	pi = op_req_q->pi;
2480	max_entries = op_req_q->num_requests;
2481
2482	if (mpi3mr_check_req_qfull(op_req_q)) {
2483		midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(
2484		    reply_qidx, mrioc->op_reply_q_offset);
2485		mpi3mr_process_op_reply_q(mrioc, mrioc->intr_info[midx].op_reply_q);
2486
2487		if (mpi3mr_check_req_qfull(op_req_q)) {
2488			retval = -EAGAIN;
2489			goto out;
2490		}
2491	}
2492
2493	if (mrioc->reset_in_progress) {
2494		ioc_err(mrioc, "OpReqQ submit reset in progress\n");
2495		retval = -EAGAIN;
2496		goto out;
2497	}
2498	if (mrioc->pci_err_recovery) {
2499		ioc_err(mrioc, "operational request queue submission failed due to pci error recovery in progress\n");
2500		retval = -EAGAIN;
2501		goto out;
2502	}
2503
2504	/* Reply queue is nearing to get full, push back IOs to SML */
2505	if ((mrioc->prevent_reply_qfull == true) &&
2506		(atomic_read(&op_reply_q->pend_ios) >
2507	     (op_reply_q->qfull_watermark))) {
2508		atomic_inc(&mrioc->reply_qfull_count);
2509		retval = -EAGAIN;
2510		goto out;
2511	}
2512
2513	segment_base_addr = segments[pi / op_req_q->segment_qd].segment;
2514	req_entry = (u8 *)segment_base_addr +
2515	    ((pi % op_req_q->segment_qd) * req_sz);
2516
2517	memset(req_entry, 0, req_sz);
2518	memcpy(req_entry, req, MPI3MR_ADMIN_REQ_FRAME_SZ);
2519
2520	if (++pi == max_entries)
2521		pi = 0;
2522	op_req_q->pi = pi;
2523
2524#ifndef CONFIG_PREEMPT_RT
2525	if (atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios)
2526	    > MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT)
2527		mrioc->op_reply_qinfo[reply_qidx].enable_irq_poll = true;
2528#else
2529	atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios);
2530#endif
2531
2532	writel(op_req_q->pi,
2533	    &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].producer_index);
2534
2535out:
2536	spin_unlock_irqrestore(&op_req_q->q_lock, flags);
2537	return retval;
2538}
2539
2540/**
2541 * mpi3mr_check_rh_fault_ioc - check reset history and fault
2542 * controller
2543 * @mrioc: Adapter instance reference
2544 * @reason_code: reason code for the fault.
2545 *
2546 * This routine will save snapdump and fault the controller with
2547 * the given reason code if it is not already in the fault or
2548 * not asynchronosuly reset. This will be used to handle
2549 * initilaization time faults/resets/timeout as in those cases
2550 * immediate soft reset invocation is not required.
2551 *
2552 * Return:  None.
2553 */
2554void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code)
2555{
2556	u32 ioc_status, host_diagnostic, timeout;
2557	union mpi3mr_trigger_data trigger_data;
2558
2559	if (mrioc->unrecoverable) {
2560		ioc_err(mrioc, "controller is unrecoverable\n");
2561		return;
2562	}
2563
2564	if (!pci_device_is_present(mrioc->pdev)) {
2565		mrioc->unrecoverable = 1;
2566		ioc_err(mrioc, "controller is not present\n");
2567		return;
2568	}
2569	memset(&trigger_data, 0, sizeof(trigger_data));
2570	ioc_status = readl(&mrioc->sysif_regs->ioc_status);
2571
2572	if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) {
2573		mpi3mr_set_trigger_data_in_all_hdb(mrioc,
2574		    MPI3MR_HDB_TRIGGER_TYPE_FW_RELEASED, NULL, 0);
2575		return;
2576	} else if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) {
2577		trigger_data.fault = (readl(&mrioc->sysif_regs->fault) &
2578		      MPI3_SYSIF_FAULT_CODE_MASK);
2579
2580		mpi3mr_set_trigger_data_in_all_hdb(mrioc,
2581		    MPI3MR_HDB_TRIGGER_TYPE_FAULT, &trigger_data, 0);
2582		mpi3mr_print_fault_info(mrioc);
2583		return;
2584	}
2585
2586	mpi3mr_set_diagsave(mrioc);
2587	mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
2588	    reason_code);
2589	trigger_data.fault = (readl(&mrioc->sysif_regs->fault) &
2590		      MPI3_SYSIF_FAULT_CODE_MASK);
2591	mpi3mr_set_trigger_data_in_all_hdb(mrioc, MPI3MR_HDB_TRIGGER_TYPE_FAULT,
2592	    &trigger_data, 0);
2593	timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
2594	do {
2595		host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
2596		if (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
2597			break;
2598		msleep(100);
2599	} while (--timeout);
2600}
2601
2602/**
2603 * mpi3mr_sync_timestamp - Issue time stamp sync request
2604 * @mrioc: Adapter reference
2605 *
2606 * Issue IO unit control MPI request to synchornize firmware
2607 * timestamp with host time.
2608 *
2609 * Return: 0 on success, non-zero on failure.
2610 */
2611static int mpi3mr_sync_timestamp(struct mpi3mr_ioc *mrioc)
2612{
2613	ktime_t current_time;
2614	struct mpi3_iounit_control_request iou_ctrl;
2615	int retval = 0;
2616
2617	memset(&iou_ctrl, 0, sizeof(iou_ctrl));
2618	mutex_lock(&mrioc->init_cmds.mutex);
2619	if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2620		retval = -1;
2621		ioc_err(mrioc, "Issue IOUCTL time_stamp: command is in use\n");
2622		mutex_unlock(&mrioc->init_cmds.mutex);
2623		goto out;
2624	}
2625	mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2626	mrioc->init_cmds.is_waiting = 1;
2627	mrioc->init_cmds.callback = NULL;
2628	iou_ctrl.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2629	iou_ctrl.function = MPI3_FUNCTION_IO_UNIT_CONTROL;
2630	iou_ctrl.operation = MPI3_CTRL_OP_UPDATE_TIMESTAMP;
2631	current_time = ktime_get_real();
2632	iou_ctrl.param64[0] = cpu_to_le64(ktime_to_ms(current_time));
2633
2634	init_completion(&mrioc->init_cmds.done);
2635	retval = mpi3mr_admin_request_post(mrioc, &iou_ctrl,
2636	    sizeof(iou_ctrl), 0);
2637	if (retval) {
2638		ioc_err(mrioc, "Issue IOUCTL time_stamp: Admin Post failed\n");
2639		goto out_unlock;
2640	}
2641
2642	wait_for_completion_timeout(&mrioc->init_cmds.done,
2643	    (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2644	if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2645		ioc_err(mrioc, "Issue IOUCTL time_stamp: command timed out\n");
2646		mrioc->init_cmds.is_waiting = 0;
2647		if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET))
2648			mpi3mr_check_rh_fault_ioc(mrioc,
2649			    MPI3MR_RESET_FROM_TSU_TIMEOUT);
2650		retval = -1;
2651		goto out_unlock;
2652	}
2653	if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2654	    != MPI3_IOCSTATUS_SUCCESS) {
2655		ioc_err(mrioc,
2656		    "Issue IOUCTL time_stamp: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2657		    (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2658		    mrioc->init_cmds.ioc_loginfo);
2659		retval = -1;
2660		goto out_unlock;
2661	}
2662
2663out_unlock:
2664	mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2665	mutex_unlock(&mrioc->init_cmds.mutex);
2666
2667out:
2668	return retval;
2669}
2670
2671/**
2672 * mpi3mr_print_pkg_ver - display controller fw package version
2673 * @mrioc: Adapter reference
2674 *
2675 * Retrieve firmware package version from the component image
2676 * header of the controller flash and display it.
2677 *
2678 * Return: 0 on success and non-zero on failure.
2679 */
2680static int mpi3mr_print_pkg_ver(struct mpi3mr_ioc *mrioc)
2681{
2682	struct mpi3_ci_upload_request ci_upload;
2683	int retval = -1;
2684	void *data = NULL;
2685	dma_addr_t data_dma;
2686	struct mpi3_ci_manifest_mpi *manifest;
2687	u32 data_len = sizeof(struct mpi3_ci_manifest_mpi);
2688	u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
2689
2690	data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
2691	    GFP_KERNEL);
2692	if (!data)
2693		return -ENOMEM;
2694
2695	memset(&ci_upload, 0, sizeof(ci_upload));
2696	mutex_lock(&mrioc->init_cmds.mutex);
2697	if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2698		ioc_err(mrioc, "sending get package version failed due to command in use\n");
2699		mutex_unlock(&mrioc->init_cmds.mutex);
2700		goto out;
2701	}
2702	mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2703	mrioc->init_cmds.is_waiting = 1;
2704	mrioc->init_cmds.callback = NULL;
2705	ci_upload.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2706	ci_upload.function = MPI3_FUNCTION_CI_UPLOAD;
2707	ci_upload.msg_flags = MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_PRIMARY;
2708	ci_upload.signature1 = cpu_to_le32(MPI3_IMAGE_HEADER_SIGNATURE1_MANIFEST);
2709	ci_upload.image_offset = cpu_to_le32(MPI3_IMAGE_HEADER_SIZE);
2710	ci_upload.segment_size = cpu_to_le32(data_len);
2711
2712	mpi3mr_add_sg_single(&ci_upload.sgl, sgl_flags, data_len,
2713	    data_dma);
2714	init_completion(&mrioc->init_cmds.done);
2715	retval = mpi3mr_admin_request_post(mrioc, &ci_upload,
2716	    sizeof(ci_upload), 1);
2717	if (retval) {
2718		ioc_err(mrioc, "posting get package version failed\n");
2719		goto out_unlock;
2720	}
2721	wait_for_completion_timeout(&mrioc->init_cmds.done,
2722	    (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2723	if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2724		ioc_err(mrioc, "get package version timed out\n");
2725		mpi3mr_check_rh_fault_ioc(mrioc,
2726		    MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT);
2727		retval = -1;
2728		goto out_unlock;
2729	}
2730	if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2731	    == MPI3_IOCSTATUS_SUCCESS) {
2732		manifest = (struct mpi3_ci_manifest_mpi *) data;
2733		if (manifest->manifest_type == MPI3_CI_MANIFEST_TYPE_MPI) {
2734			ioc_info(mrioc,
2735			    "firmware package version(%d.%d.%d.%d.%05d-%05d)\n",
2736			    manifest->package_version.gen_major,
2737			    manifest->package_version.gen_minor,
2738			    manifest->package_version.phase_major,
2739			    manifest->package_version.phase_minor,
2740			    manifest->package_version.customer_id,
2741			    manifest->package_version.build_num);
2742		}
2743	}
2744	retval = 0;
2745out_unlock:
2746	mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2747	mutex_unlock(&mrioc->init_cmds.mutex);
2748
2749out:
2750	if (data)
2751		dma_free_coherent(&mrioc->pdev->dev, data_len, data,
2752		    data_dma);
2753	return retval;
2754}
2755
2756/**
2757 * mpi3mr_watchdog_work - watchdog thread to monitor faults
2758 * @work: work struct
2759 *
2760 * Watch dog work periodically executed (1 second interval) to
2761 * monitor firmware fault and to issue periodic timer sync to
2762 * the firmware.
2763 *
2764 * Return: Nothing.
2765 */
2766static void mpi3mr_watchdog_work(struct work_struct *work)
2767{
2768	struct mpi3mr_ioc *mrioc =
2769	    container_of(work, struct mpi3mr_ioc, watchdog_work.work);
2770	unsigned long flags;
2771	enum mpi3mr_iocstate ioc_state;
2772	u32 host_diagnostic, ioc_status;
2773	union mpi3mr_trigger_data trigger_data;
2774	u16 reset_reason = MPI3MR_RESET_FROM_FAULT_WATCH;
2775
2776	if (mrioc->reset_in_progress || mrioc->pci_err_recovery)
2777		return;
2778
2779	if (!mrioc->unrecoverable && !pci_device_is_present(mrioc->pdev)) {
2780		ioc_err(mrioc, "watchdog could not detect the controller\n");
2781		mrioc->unrecoverable = 1;
2782	}
2783
2784	if (mrioc->unrecoverable) {
2785		ioc_err(mrioc,
2786		    "flush pending commands for unrecoverable controller\n");
2787		mpi3mr_flush_cmds_for_unrecovered_controller(mrioc);
2788		return;
2789	}
2790
2791	if (atomic_read(&mrioc->admin_pend_isr)) {
2792		ioc_err(mrioc, "Unprocessed admin ISR instance found\n"
2793				"flush admin replies\n");
2794		mpi3mr_process_admin_reply_q(mrioc);
2795	}
2796
2797	if (!(mrioc->facts.ioc_capabilities &
2798		MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_IOC) &&
2799		(mrioc->ts_update_counter++ >= mrioc->ts_update_interval)) {
2800
2801		mrioc->ts_update_counter = 0;
2802		mpi3mr_sync_timestamp(mrioc);
2803	}
2804
2805	if ((mrioc->prepare_for_reset) &&
2806	    ((mrioc->prepare_for_reset_timeout_counter++) >=
2807	     MPI3MR_PREPARE_FOR_RESET_TIMEOUT)) {
2808		mpi3mr_soft_reset_handler(mrioc,
2809		    MPI3MR_RESET_FROM_CIACTVRST_TIMER, 1);
2810		return;
2811	}
2812
2813	memset(&trigger_data, 0, sizeof(trigger_data));
2814	ioc_status = readl(&mrioc->sysif_regs->ioc_status);
2815	if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) {
2816		mpi3mr_set_trigger_data_in_all_hdb(mrioc,
2817		    MPI3MR_HDB_TRIGGER_TYPE_FW_RELEASED, NULL, 0);
2818		mpi3mr_soft_reset_handler(mrioc, MPI3MR_RESET_FROM_FIRMWARE, 0);
2819		return;
2820	}
2821
2822	/*Check for fault state every one second and issue Soft reset*/
2823	ioc_state = mpi3mr_get_iocstate(mrioc);
2824	if (ioc_state != MRIOC_STATE_FAULT)
2825		goto schedule_work;
2826
2827	trigger_data.fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK;
2828	mpi3mr_set_trigger_data_in_all_hdb(mrioc,
2829	    MPI3MR_HDB_TRIGGER_TYPE_FAULT, &trigger_data, 0);
2830	host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
2831	if (host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS) {
2832		if (!mrioc->diagsave_timeout) {
2833			mpi3mr_print_fault_info(mrioc);
2834			ioc_warn(mrioc, "diag save in progress\n");
2835		}
2836		if ((mrioc->diagsave_timeout++) <= MPI3_SYSIF_DIAG_SAVE_TIMEOUT)
2837			goto schedule_work;
2838	}
2839
2840	mpi3mr_print_fault_info(mrioc);
2841	mrioc->diagsave_timeout = 0;
2842
2843	if (!mpi3mr_is_fault_recoverable(mrioc)) {
2844		mrioc->unrecoverable = 1;
2845		goto schedule_work;
2846	}
2847
2848	switch (trigger_data.fault) {
2849	case MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED:
2850	case MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED:
2851		ioc_warn(mrioc,
2852		    "controller requires system power cycle, marking controller as unrecoverable\n");
2853		mrioc->unrecoverable = 1;
2854		goto schedule_work;
2855	case MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS:
2856		goto schedule_work;
2857	case MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET:
2858		reset_reason = MPI3MR_RESET_FROM_CIACTIV_FAULT;
2859		break;
2860	default:
2861		break;
2862	}
2863	mpi3mr_soft_reset_handler(mrioc, reset_reason, 0);
2864	return;
2865
2866schedule_work:
2867	spin_lock_irqsave(&mrioc->watchdog_lock, flags);
2868	if (mrioc->watchdog_work_q)
2869		queue_delayed_work(mrioc->watchdog_work_q,
2870		    &mrioc->watchdog_work,
2871		    msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
2872	spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
2873	return;
2874}
2875
2876/**
2877 * mpi3mr_start_watchdog - Start watchdog
2878 * @mrioc: Adapter instance reference
2879 *
2880 * Create and start the watchdog thread to monitor controller
2881 * faults.
2882 *
2883 * Return: Nothing.
2884 */
2885void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc)
2886{
2887	if (mrioc->watchdog_work_q)
2888		return;
2889
2890	INIT_DELAYED_WORK(&mrioc->watchdog_work, mpi3mr_watchdog_work);
2891	snprintf(mrioc->watchdog_work_q_name,
2892	    sizeof(mrioc->watchdog_work_q_name), "watchdog_%s%d", mrioc->name,
2893	    mrioc->id);
2894	mrioc->watchdog_work_q = alloc_ordered_workqueue(
2895		"%s", WQ_MEM_RECLAIM, mrioc->watchdog_work_q_name);
2896	if (!mrioc->watchdog_work_q) {
2897		ioc_err(mrioc, "%s: failed (line=%d)\n", __func__, __LINE__);
2898		return;
2899	}
2900
2901	if (mrioc->watchdog_work_q)
2902		queue_delayed_work(mrioc->watchdog_work_q,
2903		    &mrioc->watchdog_work,
2904		    msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
2905}
2906
2907/**
2908 * mpi3mr_stop_watchdog - Stop watchdog
2909 * @mrioc: Adapter instance reference
2910 *
2911 * Stop the watchdog thread created to monitor controller
2912 * faults.
2913 *
2914 * Return: Nothing.
2915 */
2916void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc)
2917{
2918	unsigned long flags;
2919	struct workqueue_struct *wq;
2920
2921	spin_lock_irqsave(&mrioc->watchdog_lock, flags);
2922	wq = mrioc->watchdog_work_q;
2923	mrioc->watchdog_work_q = NULL;
2924	spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
2925	if (wq) {
2926		if (!cancel_delayed_work_sync(&mrioc->watchdog_work))
2927			flush_workqueue(wq);
2928		destroy_workqueue(wq);
2929	}
2930}
2931
2932/**
2933 * mpi3mr_setup_admin_qpair - Setup admin queue pair
2934 * @mrioc: Adapter instance reference
2935 *
2936 * Allocate memory for admin queue pair if required and register
2937 * the admin queue with the controller.
2938 *
2939 * Return: 0 on success, non-zero on failures.
2940 */
2941static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc)
2942{
2943	int retval = 0;
2944	u32 num_admin_entries = 0;
2945
2946	mrioc->admin_req_q_sz = MPI3MR_ADMIN_REQ_Q_SIZE;
2947	mrioc->num_admin_req = mrioc->admin_req_q_sz /
2948	    MPI3MR_ADMIN_REQ_FRAME_SZ;
2949	mrioc->admin_req_ci = mrioc->admin_req_pi = 0;
2950
2951	mrioc->admin_reply_q_sz = MPI3MR_ADMIN_REPLY_Q_SIZE;
2952	mrioc->num_admin_replies = mrioc->admin_reply_q_sz /
2953	    MPI3MR_ADMIN_REPLY_FRAME_SZ;
2954	mrioc->admin_reply_ci = 0;
2955	mrioc->admin_reply_ephase = 1;
2956	atomic_set(&mrioc->admin_reply_q_in_use, 0);
2957	atomic_set(&mrioc->admin_pend_isr, 0);
2958
2959	if (!mrioc->admin_req_base) {
2960		mrioc->admin_req_base = dma_alloc_coherent(&mrioc->pdev->dev,
2961		    mrioc->admin_req_q_sz, &mrioc->admin_req_dma, GFP_KERNEL);
2962
2963		if (!mrioc->admin_req_base) {
2964			retval = -1;
2965			goto out_failed;
2966		}
2967
2968		mrioc->admin_reply_base = dma_alloc_coherent(&mrioc->pdev->dev,
2969		    mrioc->admin_reply_q_sz, &mrioc->admin_reply_dma,
2970		    GFP_KERNEL);
2971
2972		if (!mrioc->admin_reply_base) {
2973			retval = -1;
2974			goto out_failed;
2975		}
2976	}
2977
2978	num_admin_entries = (mrioc->num_admin_replies << 16) |
2979	    (mrioc->num_admin_req);
2980	writel(num_admin_entries, &mrioc->sysif_regs->admin_queue_num_entries);
2981	mpi3mr_writeq(mrioc->admin_req_dma,
2982		&mrioc->sysif_regs->admin_request_queue_address,
2983		&mrioc->adm_req_q_bar_writeq_lock);
2984	mpi3mr_writeq(mrioc->admin_reply_dma,
2985		&mrioc->sysif_regs->admin_reply_queue_address,
2986		&mrioc->adm_reply_q_bar_writeq_lock);
2987	writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi);
2988	writel(mrioc->admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci);
2989	return retval;
2990
2991out_failed:
2992
2993	if (mrioc->admin_reply_base) {
2994		dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz,
2995		    mrioc->admin_reply_base, mrioc->admin_reply_dma);
2996		mrioc->admin_reply_base = NULL;
2997	}
2998	if (mrioc->admin_req_base) {
2999		dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz,
3000		    mrioc->admin_req_base, mrioc->admin_req_dma);
3001		mrioc->admin_req_base = NULL;
3002	}
3003	return retval;
3004}
3005
3006/**
3007 * mpi3mr_issue_iocfacts - Send IOC Facts
3008 * @mrioc: Adapter instance reference
3009 * @facts_data: Cached IOC facts data
3010 *
3011 * Issue IOC Facts MPI request through admin queue and wait for
3012 * the completion of it or time out.
3013 *
3014 * Return: 0 on success, non-zero on failures.
3015 */
3016static int mpi3mr_issue_iocfacts(struct mpi3mr_ioc *mrioc,
3017	struct mpi3_ioc_facts_data *facts_data)
3018{
3019	struct mpi3_ioc_facts_request iocfacts_req;
3020	void *data = NULL;
3021	dma_addr_t data_dma;
3022	u32 data_len = sizeof(*facts_data);
3023	int retval = 0;
3024	u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
3025
3026	data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
3027	    GFP_KERNEL);
3028
3029	if (!data) {
3030		retval = -1;
3031		goto out;
3032	}
3033
3034	memset(&iocfacts_req, 0, sizeof(iocfacts_req));
3035	mutex_lock(&mrioc->init_cmds.mutex);
3036	if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3037		retval = -1;
3038		ioc_err(mrioc, "Issue IOCFacts: Init command is in use\n");
3039		mutex_unlock(&mrioc->init_cmds.mutex);
3040		goto out;
3041	}
3042	mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3043	mrioc->init_cmds.is_waiting = 1;
3044	mrioc->init_cmds.callback = NULL;
3045	iocfacts_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3046	iocfacts_req.function = MPI3_FUNCTION_IOC_FACTS;
3047
3048	mpi3mr_add_sg_single(&iocfacts_req.sgl, sgl_flags, data_len,
3049	    data_dma);
3050
3051	init_completion(&mrioc->init_cmds.done);
3052	retval = mpi3mr_admin_request_post(mrioc, &iocfacts_req,
3053	    sizeof(iocfacts_req), 1);
3054	if (retval) {
3055		ioc_err(mrioc, "Issue IOCFacts: Admin Post failed\n");
3056		goto out_unlock;
3057	}
3058	wait_for_completion_timeout(&mrioc->init_cmds.done,
3059	    (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3060	if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3061		ioc_err(mrioc, "ioc_facts timed out\n");
3062		mpi3mr_check_rh_fault_ioc(mrioc,
3063		    MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT);
3064		retval = -1;
3065		goto out_unlock;
3066	}
3067	if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3068	    != MPI3_IOCSTATUS_SUCCESS) {
3069		ioc_err(mrioc,
3070		    "Issue IOCFacts: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3071		    (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3072		    mrioc->init_cmds.ioc_loginfo);
3073		retval = -1;
3074		goto out_unlock;
3075	}
3076	memcpy(facts_data, (u8 *)data, data_len);
3077	mpi3mr_process_factsdata(mrioc, facts_data);
3078out_unlock:
3079	mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3080	mutex_unlock(&mrioc->init_cmds.mutex);
3081
3082out:
3083	if (data)
3084		dma_free_coherent(&mrioc->pdev->dev, data_len, data, data_dma);
3085
3086	return retval;
3087}
3088
3089/**
3090 * mpi3mr_check_reset_dma_mask - Process IOC facts data
3091 * @mrioc: Adapter instance reference
3092 *
3093 * Check whether the new DMA mask requested through IOCFacts by
3094 * firmware needs to be set, if so set it .
3095 *
3096 * Return: 0 on success, non-zero on failure.
3097 */
3098static inline int mpi3mr_check_reset_dma_mask(struct mpi3mr_ioc *mrioc)
3099{
3100	struct pci_dev *pdev = mrioc->pdev;
3101	int r;
3102	u64 facts_dma_mask = DMA_BIT_MASK(mrioc->facts.dma_mask);
3103
3104	if (!mrioc->facts.dma_mask || (mrioc->dma_mask <= facts_dma_mask))
3105		return 0;
3106
3107	ioc_info(mrioc, "Changing DMA mask from 0x%016llx to 0x%016llx\n",
3108	    mrioc->dma_mask, facts_dma_mask);
3109
3110	r = dma_set_mask_and_coherent(&pdev->dev, facts_dma_mask);
3111	if (r) {
3112		ioc_err(mrioc, "Setting DMA mask to 0x%016llx failed: %d\n",
3113		    facts_dma_mask, r);
3114		return r;
3115	}
3116	mrioc->dma_mask = facts_dma_mask;
3117	return r;
3118}
3119
3120/**
3121 * mpi3mr_process_factsdata - Process IOC facts data
3122 * @mrioc: Adapter instance reference
3123 * @facts_data: Cached IOC facts data
3124 *
3125 * Convert IOC facts data into cpu endianness and cache it in
3126 * the driver .
3127 *
3128 * Return: Nothing.
3129 */
3130static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc,
3131	struct mpi3_ioc_facts_data *facts_data)
3132{
3133	u32 ioc_config, req_sz, facts_flags;
3134
3135	if ((le16_to_cpu(facts_data->ioc_facts_data_length)) !=
3136	    (sizeof(*facts_data) / 4)) {
3137		ioc_warn(mrioc,
3138		    "IOCFactsdata length mismatch driver_sz(%zu) firmware_sz(%d)\n",
3139		    sizeof(*facts_data),
3140		    le16_to_cpu(facts_data->ioc_facts_data_length) * 4);
3141	}
3142
3143	ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
3144	req_sz = 1 << ((ioc_config & MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ) >>
3145	    MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ_SHIFT);
3146	if (le16_to_cpu(facts_data->ioc_request_frame_size) != (req_sz / 4)) {
3147		ioc_err(mrioc,
3148		    "IOCFacts data reqFrameSize mismatch hw_size(%d) firmware_sz(%d)\n",
3149		    req_sz / 4, le16_to_cpu(facts_data->ioc_request_frame_size));
3150	}
3151
3152	memset(&mrioc->facts, 0, sizeof(mrioc->facts));
3153
3154	facts_flags = le32_to_cpu(facts_data->flags);
3155	mrioc->facts.op_req_sz = req_sz;
3156	mrioc->op_reply_desc_sz = 1 << ((ioc_config &
3157	    MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ) >>
3158	    MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ_SHIFT);
3159
3160	mrioc->facts.ioc_num = facts_data->ioc_number;
3161	mrioc->facts.who_init = facts_data->who_init;
3162	mrioc->facts.max_msix_vectors = le16_to_cpu(facts_data->max_msix_vectors);
3163	mrioc->facts.personality = (facts_flags &
3164	    MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK);
3165	mrioc->facts.dma_mask = (facts_flags &
3166	    MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK) >>
3167	    MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT;
3168	mrioc->facts.dma_mask = (facts_flags &
3169	    MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK) >>
3170	    MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT;
3171	mrioc->facts.max_req_limit = (facts_flags &
3172			MPI3_IOCFACTS_FLAGS_MAX_REQ_PER_REPLY_QUEUE_LIMIT);
3173	mrioc->facts.protocol_flags = facts_data->protocol_flags;
3174	mrioc->facts.mpi_version = le32_to_cpu(facts_data->mpi_version.word);
3175	mrioc->facts.max_reqs = le16_to_cpu(facts_data->max_outstanding_requests);
3176	mrioc->facts.product_id = le16_to_cpu(facts_data->product_id);
3177	mrioc->facts.reply_sz = le16_to_cpu(facts_data->reply_frame_size) * 4;
3178	mrioc->facts.exceptions = le16_to_cpu(facts_data->ioc_exceptions);
3179	mrioc->facts.max_perids = le16_to_cpu(facts_data->max_persistent_id);
3180	mrioc->facts.max_vds = le16_to_cpu(facts_data->max_vds);
3181	mrioc->facts.max_hpds = le16_to_cpu(facts_data->max_host_pds);
3182	mrioc->facts.max_advhpds = le16_to_cpu(facts_data->max_adv_host_pds);
3183	mrioc->facts.max_raid_pds = le16_to_cpu(facts_data->max_raid_pds);
3184	mrioc->facts.max_nvme = le16_to_cpu(facts_data->max_nvme);
3185	mrioc->facts.max_pcie_switches =
3186	    le16_to_cpu(facts_data->max_pcie_switches);
3187	mrioc->facts.max_sasexpanders =
3188	    le16_to_cpu(facts_data->max_sas_expanders);
3189	mrioc->facts.max_data_length = le16_to_cpu(facts_data->max_data_length);
3190	mrioc->facts.max_sasinitiators =
3191	    le16_to_cpu(facts_data->max_sas_initiators);
3192	mrioc->facts.max_enclosures = le16_to_cpu(facts_data->max_enclosures);
3193	mrioc->facts.min_devhandle = le16_to_cpu(facts_data->min_dev_handle);
3194	mrioc->facts.max_devhandle = le16_to_cpu(facts_data->max_dev_handle);
3195	mrioc->facts.max_op_req_q =
3196	    le16_to_cpu(facts_data->max_operational_request_queues);
3197	mrioc->facts.max_op_reply_q =
3198	    le16_to_cpu(facts_data->max_operational_reply_queues);
3199	mrioc->facts.ioc_capabilities =
3200	    le32_to_cpu(facts_data->ioc_capabilities);
3201	mrioc->facts.fw_ver.build_num =
3202	    le16_to_cpu(facts_data->fw_version.build_num);
3203	mrioc->facts.fw_ver.cust_id =
3204	    le16_to_cpu(facts_data->fw_version.customer_id);
3205	mrioc->facts.fw_ver.ph_minor = facts_data->fw_version.phase_minor;
3206	mrioc->facts.fw_ver.ph_major = facts_data->fw_version.phase_major;
3207	mrioc->facts.fw_ver.gen_minor = facts_data->fw_version.gen_minor;
3208	mrioc->facts.fw_ver.gen_major = facts_data->fw_version.gen_major;
3209	mrioc->msix_count = min_t(int, mrioc->msix_count,
3210	    mrioc->facts.max_msix_vectors);
3211	mrioc->facts.sge_mod_mask = facts_data->sge_modifier_mask;
3212	mrioc->facts.sge_mod_value = facts_data->sge_modifier_value;
3213	mrioc->facts.sge_mod_shift = facts_data->sge_modifier_shift;
3214	mrioc->facts.shutdown_timeout =
3215	    le16_to_cpu(facts_data->shutdown_timeout);
3216	mrioc->facts.diag_trace_sz =
3217	    le32_to_cpu(facts_data->diag_trace_size);
3218	mrioc->facts.diag_fw_sz =
3219	    le32_to_cpu(facts_data->diag_fw_size);
3220	mrioc->facts.diag_drvr_sz = le32_to_cpu(facts_data->diag_driver_size);
3221	mrioc->facts.max_dev_per_tg =
3222	    facts_data->max_devices_per_throttle_group;
3223	mrioc->facts.io_throttle_data_length =
3224	    le16_to_cpu(facts_data->io_throttle_data_length);
3225	mrioc->facts.max_io_throttle_group =
3226	    le16_to_cpu(facts_data->max_io_throttle_group);
3227	mrioc->facts.io_throttle_low = le16_to_cpu(facts_data->io_throttle_low);
3228	mrioc->facts.io_throttle_high =
3229	    le16_to_cpu(facts_data->io_throttle_high);
3230
3231	if (mrioc->facts.max_data_length ==
3232	    MPI3_IOCFACTS_MAX_DATA_LENGTH_NOT_REPORTED)
3233		mrioc->facts.max_data_length = MPI3MR_DEFAULT_MAX_IO_SIZE;
3234	else
3235		mrioc->facts.max_data_length *= MPI3MR_PAGE_SIZE_4K;
3236	/* Store in 512b block count */
3237	if (mrioc->facts.io_throttle_data_length)
3238		mrioc->io_throttle_data_length =
3239		    (mrioc->facts.io_throttle_data_length * 2 * 4);
3240	else
3241		/* set the length to 1MB + 1K to disable throttle */
3242		mrioc->io_throttle_data_length = (mrioc->facts.max_data_length / 512) + 2;
3243
3244	mrioc->io_throttle_high = (mrioc->facts.io_throttle_high * 2 * 1024);
3245	mrioc->io_throttle_low = (mrioc->facts.io_throttle_low * 2 * 1024);
3246
3247	ioc_info(mrioc, "ioc_num(%d), maxopQ(%d), maxopRepQ(%d), maxdh(%d),",
3248	    mrioc->facts.ioc_num, mrioc->facts.max_op_req_q,
3249	    mrioc->facts.max_op_reply_q, mrioc->facts.max_devhandle);
3250	ioc_info(mrioc,
3251	    "maxreqs(%d), mindh(%d) maxvectors(%d) maxperids(%d)\n",
3252	    mrioc->facts.max_reqs, mrioc->facts.min_devhandle,
3253	    mrioc->facts.max_msix_vectors, mrioc->facts.max_perids);
3254	ioc_info(mrioc, "SGEModMask 0x%x SGEModVal 0x%x SGEModShift 0x%x ",
3255	    mrioc->facts.sge_mod_mask, mrioc->facts.sge_mod_value,
3256	    mrioc->facts.sge_mod_shift);
3257	ioc_info(mrioc, "DMA mask %d InitialPE status 0x%x max_data_len (%d)\n",
3258	    mrioc->facts.dma_mask, (facts_flags &
3259	    MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK), mrioc->facts.max_data_length);
3260	ioc_info(mrioc,
3261	    "max_dev_per_throttle_group(%d), max_throttle_groups(%d)\n",
3262	    mrioc->facts.max_dev_per_tg, mrioc->facts.max_io_throttle_group);
3263	ioc_info(mrioc,
3264	   "io_throttle_data_len(%dKiB), io_throttle_high(%dMiB), io_throttle_low(%dMiB)\n",
3265	   mrioc->facts.io_throttle_data_length * 4,
3266	   mrioc->facts.io_throttle_high, mrioc->facts.io_throttle_low);
3267}
3268
3269/**
3270 * mpi3mr_alloc_reply_sense_bufs - Send IOC Init
3271 * @mrioc: Adapter instance reference
3272 *
3273 * Allocate and initialize the reply free buffers, sense
3274 * buffers, reply free queue and sense buffer queue.
3275 *
3276 * Return: 0 on success, non-zero on failures.
3277 */
3278static int mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc *mrioc)
3279{
3280	int retval = 0;
3281	u32 sz, i;
3282
3283	if (mrioc->init_cmds.reply)
3284		return retval;
3285
3286	mrioc->init_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
3287	if (!mrioc->init_cmds.reply)
3288		goto out_failed;
3289
3290	mrioc->bsg_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
3291	if (!mrioc->bsg_cmds.reply)
3292		goto out_failed;
3293
3294	mrioc->transport_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
3295	if (!mrioc->transport_cmds.reply)
3296		goto out_failed;
3297
3298	for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
3299		mrioc->dev_rmhs_cmds[i].reply = kzalloc(mrioc->reply_sz,
3300		    GFP_KERNEL);
3301		if (!mrioc->dev_rmhs_cmds[i].reply)
3302			goto out_failed;
3303	}
3304
3305	for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
3306		mrioc->evtack_cmds[i].reply = kzalloc(mrioc->reply_sz,
3307		    GFP_KERNEL);
3308		if (!mrioc->evtack_cmds[i].reply)
3309			goto out_failed;
3310	}
3311
3312	mrioc->host_tm_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
3313	if (!mrioc->host_tm_cmds.reply)
3314		goto out_failed;
3315
3316	mrioc->pel_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
3317	if (!mrioc->pel_cmds.reply)
3318		goto out_failed;
3319
3320	mrioc->pel_abort_cmd.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
3321	if (!mrioc->pel_abort_cmd.reply)
3322		goto out_failed;
3323
3324	mrioc->dev_handle_bitmap_bits = mrioc->facts.max_devhandle;
3325	mrioc->removepend_bitmap = bitmap_zalloc(mrioc->dev_handle_bitmap_bits,
3326						 GFP_KERNEL);
3327	if (!mrioc->removepend_bitmap)
3328		goto out_failed;
3329
3330	mrioc->devrem_bitmap = bitmap_zalloc(MPI3MR_NUM_DEVRMCMD, GFP_KERNEL);
3331	if (!mrioc->devrem_bitmap)
3332		goto out_failed;
3333
3334	mrioc->evtack_cmds_bitmap = bitmap_zalloc(MPI3MR_NUM_EVTACKCMD,
3335						  GFP_KERNEL);
3336	if (!mrioc->evtack_cmds_bitmap)
3337		goto out_failed;
3338
3339	mrioc->num_reply_bufs = mrioc->facts.max_reqs + MPI3MR_NUM_EVT_REPLIES;
3340	mrioc->reply_free_qsz = mrioc->num_reply_bufs + 1;
3341	mrioc->num_sense_bufs = mrioc->facts.max_reqs / MPI3MR_SENSEBUF_FACTOR;
3342	mrioc->sense_buf_q_sz = mrioc->num_sense_bufs + 1;
3343
3344	/* reply buffer pool, 16 byte align */
3345	sz = mrioc->num_reply_bufs * mrioc->reply_sz;
3346	mrioc->reply_buf_pool = dma_pool_create("reply_buf pool",
3347	    &mrioc->pdev->dev, sz, 16, 0);
3348	if (!mrioc->reply_buf_pool) {
3349		ioc_err(mrioc, "reply buf pool: dma_pool_create failed\n");
3350		goto out_failed;
3351	}
3352
3353	mrioc->reply_buf = dma_pool_zalloc(mrioc->reply_buf_pool, GFP_KERNEL,
3354	    &mrioc->reply_buf_dma);
3355	if (!mrioc->reply_buf)
3356		goto out_failed;
3357
3358	mrioc->reply_buf_dma_max_address = mrioc->reply_buf_dma + sz;
3359
3360	/* reply free queue, 8 byte align */
3361	sz = mrioc->reply_free_qsz * 8;
3362	mrioc->reply_free_q_pool = dma_pool_create("reply_free_q pool",
3363	    &mrioc->pdev->dev, sz, 8, 0);
3364	if (!mrioc->reply_free_q_pool) {
3365		ioc_err(mrioc, "reply_free_q pool: dma_pool_create failed\n");
3366		goto out_failed;
3367	}
3368	mrioc->reply_free_q = dma_pool_zalloc(mrioc->reply_free_q_pool,
3369	    GFP_KERNEL, &mrioc->reply_free_q_dma);
3370	if (!mrioc->reply_free_q)
3371		goto out_failed;
3372
3373	/* sense buffer pool,  4 byte align */
3374	sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ;
3375	mrioc->sense_buf_pool = dma_pool_create("sense_buf pool",
3376	    &mrioc->pdev->dev, sz, 4, 0);
3377	if (!mrioc->sense_buf_pool) {
3378		ioc_err(mrioc, "sense_buf pool: dma_pool_create failed\n");
3379		goto out_failed;
3380	}
3381	mrioc->sense_buf = dma_pool_zalloc(mrioc->sense_buf_pool, GFP_KERNEL,
3382	    &mrioc->sense_buf_dma);
3383	if (!mrioc->sense_buf)
3384		goto out_failed;
3385
3386	/* sense buffer queue, 8 byte align */
3387	sz = mrioc->sense_buf_q_sz * 8;
3388	mrioc->sense_buf_q_pool = dma_pool_create("sense_buf_q pool",
3389	    &mrioc->pdev->dev, sz, 8, 0);
3390	if (!mrioc->sense_buf_q_pool) {
3391		ioc_err(mrioc, "sense_buf_q pool: dma_pool_create failed\n");
3392		goto out_failed;
3393	}
3394	mrioc->sense_buf_q = dma_pool_zalloc(mrioc->sense_buf_q_pool,
3395	    GFP_KERNEL, &mrioc->sense_buf_q_dma);
3396	if (!mrioc->sense_buf_q)
3397		goto out_failed;
3398
3399	return retval;
3400
3401out_failed:
3402	retval = -1;
3403	return retval;
3404}
3405
3406/**
3407 * mpimr_initialize_reply_sbuf_queues - initialize reply sense
3408 * buffers
3409 * @mrioc: Adapter instance reference
3410 *
3411 * Helper function to initialize reply and sense buffers along
3412 * with some debug prints.
3413 *
3414 * Return:  None.
3415 */
3416static void mpimr_initialize_reply_sbuf_queues(struct mpi3mr_ioc *mrioc)
3417{
3418	u32 sz, i;
3419	dma_addr_t phy_addr;
3420
3421	sz = mrioc->num_reply_bufs * mrioc->reply_sz;
3422	ioc_info(mrioc,
3423	    "reply buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n",
3424	    mrioc->reply_buf, mrioc->num_reply_bufs, mrioc->reply_sz,
3425	    (sz / 1024), (unsigned long long)mrioc->reply_buf_dma);
3426	sz = mrioc->reply_free_qsz * 8;
3427	ioc_info(mrioc,
3428	    "reply_free_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n",
3429	    mrioc->reply_free_q, mrioc->reply_free_qsz, 8, (sz / 1024),
3430	    (unsigned long long)mrioc->reply_free_q_dma);
3431	sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ;
3432	ioc_info(mrioc,
3433	    "sense_buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n",
3434	    mrioc->sense_buf, mrioc->num_sense_bufs, MPI3MR_SENSE_BUF_SZ,
3435	    (sz / 1024), (unsigned long long)mrioc->sense_buf_dma);
3436	sz = mrioc->sense_buf_q_sz * 8;
3437	ioc_info(mrioc,
3438	    "sense_buf_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n",
3439	    mrioc->sense_buf_q, mrioc->sense_buf_q_sz, 8, (sz / 1024),
3440	    (unsigned long long)mrioc->sense_buf_q_dma);
3441
3442	/* initialize Reply buffer Queue */
3443	for (i = 0, phy_addr = mrioc->reply_buf_dma;
3444	    i < mrioc->num_reply_bufs; i++, phy_addr += mrioc->reply_sz)
3445		mrioc->reply_free_q[i] = cpu_to_le64(phy_addr);
3446	mrioc->reply_free_q[i] = cpu_to_le64(0);
3447
3448	/* initialize Sense Buffer Queue */
3449	for (i = 0, phy_addr = mrioc->sense_buf_dma;
3450	    i < mrioc->num_sense_bufs; i++, phy_addr += MPI3MR_SENSE_BUF_SZ)
3451		mrioc->sense_buf_q[i] = cpu_to_le64(phy_addr);
3452	mrioc->sense_buf_q[i] = cpu_to_le64(0);
3453}
3454
3455/**
3456 * mpi3mr_issue_iocinit - Send IOC Init
3457 * @mrioc: Adapter instance reference
3458 *
3459 * Issue IOC Init MPI request through admin queue and wait for
3460 * the completion of it or time out.
3461 *
3462 * Return: 0 on success, non-zero on failures.
3463 */
3464static int mpi3mr_issue_iocinit(struct mpi3mr_ioc *mrioc)
3465{
3466	struct mpi3_ioc_init_request iocinit_req;
3467	struct mpi3_driver_info_layout *drv_info;
3468	dma_addr_t data_dma;
3469	u32 data_len = sizeof(*drv_info);
3470	int retval = 0;
3471	ktime_t current_time;
3472
3473	drv_info = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
3474	    GFP_KERNEL);
3475	if (!drv_info) {
3476		retval = -1;
3477		goto out;
3478	}
3479	mpimr_initialize_reply_sbuf_queues(mrioc);
3480
3481	drv_info->information_length = cpu_to_le32(data_len);
3482	strscpy(drv_info->driver_signature, "Broadcom", sizeof(drv_info->driver_signature));
3483	strscpy(drv_info->os_name, utsname()->sysname, sizeof(drv_info->os_name));
3484	strscpy(drv_info->os_version, utsname()->release, sizeof(drv_info->os_version));
3485	strscpy(drv_info->driver_name, MPI3MR_DRIVER_NAME, sizeof(drv_info->driver_name));
3486	strscpy(drv_info->driver_version, MPI3MR_DRIVER_VERSION, sizeof(drv_info->driver_version));
3487	strscpy(drv_info->driver_release_date, MPI3MR_DRIVER_RELDATE,
3488	    sizeof(drv_info->driver_release_date));
3489	drv_info->driver_capabilities = 0;
3490	memcpy((u8 *)&mrioc->driver_info, (u8 *)drv_info,
3491	    sizeof(mrioc->driver_info));
3492
3493	memset(&iocinit_req, 0, sizeof(iocinit_req));
3494	mutex_lock(&mrioc->init_cmds.mutex);
3495	if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3496		retval = -1;
3497		ioc_err(mrioc, "Issue IOCInit: Init command is in use\n");
3498		mutex_unlock(&mrioc->init_cmds.mutex);
3499		goto out;
3500	}
3501	mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3502	mrioc->init_cmds.is_waiting = 1;
3503	mrioc->init_cmds.callback = NULL;
3504	iocinit_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3505	iocinit_req.function = MPI3_FUNCTION_IOC_INIT;
3506	iocinit_req.mpi_version.mpi3_version.dev = MPI3_VERSION_DEV;
3507	iocinit_req.mpi_version.mpi3_version.unit = MPI3_VERSION_UNIT;
3508	iocinit_req.mpi_version.mpi3_version.major = MPI3_VERSION_MAJOR;
3509	iocinit_req.mpi_version.mpi3_version.minor = MPI3_VERSION_MINOR;
3510	iocinit_req.who_init = MPI3_WHOINIT_HOST_DRIVER;
3511	iocinit_req.reply_free_queue_depth = cpu_to_le16(mrioc->reply_free_qsz);
3512	iocinit_req.reply_free_queue_address =
3513	    cpu_to_le64(mrioc->reply_free_q_dma);
3514	iocinit_req.sense_buffer_length = cpu_to_le16(MPI3MR_SENSE_BUF_SZ);
3515	iocinit_req.sense_buffer_free_queue_depth =
3516	    cpu_to_le16(mrioc->sense_buf_q_sz);
3517	iocinit_req.sense_buffer_free_queue_address =
3518	    cpu_to_le64(mrioc->sense_buf_q_dma);
3519	iocinit_req.driver_information_address = cpu_to_le64(data_dma);
3520
3521	current_time = ktime_get_real();
3522	iocinit_req.time_stamp = cpu_to_le64(ktime_to_ms(current_time));
3523
3524	iocinit_req.msg_flags |=
3525	    MPI3_IOCINIT_MSGFLAGS_SCSIIOSTATUSREPLY_SUPPORTED;
3526	iocinit_req.msg_flags |=
3527		MPI3_IOCINIT_MSGFLAGS_WRITESAMEDIVERT_SUPPORTED;
3528
3529	init_completion(&mrioc->init_cmds.done);
3530	retval = mpi3mr_admin_request_post(mrioc, &iocinit_req,
3531	    sizeof(iocinit_req), 1);
3532	if (retval) {
3533		ioc_err(mrioc, "Issue IOCInit: Admin Post failed\n");
3534		goto out_unlock;
3535	}
3536	wait_for_completion_timeout(&mrioc->init_cmds.done,
3537	    (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3538	if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3539		mpi3mr_check_rh_fault_ioc(mrioc,
3540		    MPI3MR_RESET_FROM_IOCINIT_TIMEOUT);
3541		ioc_err(mrioc, "ioc_init timed out\n");
3542		retval = -1;
3543		goto out_unlock;
3544	}
3545	if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3546	    != MPI3_IOCSTATUS_SUCCESS) {
3547		ioc_err(mrioc,
3548		    "Issue IOCInit: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3549		    (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3550		    mrioc->init_cmds.ioc_loginfo);
3551		retval = -1;
3552		goto out_unlock;
3553	}
3554
3555	mrioc->reply_free_queue_host_index = mrioc->num_reply_bufs;
3556	writel(mrioc->reply_free_queue_host_index,
3557	    &mrioc->sysif_regs->reply_free_host_index);
3558
3559	mrioc->sbq_host_index = mrioc->num_sense_bufs;
3560	writel(mrioc->sbq_host_index,
3561	    &mrioc->sysif_regs->sense_buffer_free_host_index);
3562out_unlock:
3563	mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3564	mutex_unlock(&mrioc->init_cmds.mutex);
3565
3566out:
3567	if (drv_info)
3568		dma_free_coherent(&mrioc->pdev->dev, data_len, drv_info,
3569		    data_dma);
3570
3571	return retval;
3572}
3573
3574/**
3575 * mpi3mr_unmask_events - Unmask events in event mask bitmap
3576 * @mrioc: Adapter instance reference
3577 * @event: MPI event ID
3578 *
3579 * Un mask the specific event by resetting the event_mask
3580 * bitmap.
3581 *
3582 * Return: 0 on success, non-zero on failures.
3583 */
3584static void mpi3mr_unmask_events(struct mpi3mr_ioc *mrioc, u16 event)
3585{
3586	u32 desired_event;
3587	u8 word;
3588
3589	if (event >= 128)
3590		return;
3591
3592	desired_event = (1 << (event % 32));
3593	word = event / 32;
3594
3595	mrioc->event_masks[word] &= ~desired_event;
3596}
3597
3598/**
3599 * mpi3mr_issue_event_notification - Send event notification
3600 * @mrioc: Adapter instance reference
3601 *
3602 * Issue event notification MPI request through admin queue and
3603 * wait for the completion of it or time out.
3604 *
3605 * Return: 0 on success, non-zero on failures.
3606 */
3607static int mpi3mr_issue_event_notification(struct mpi3mr_ioc *mrioc)
3608{
3609	struct mpi3_event_notification_request evtnotify_req;
3610	int retval = 0;
3611	u8 i;
3612
3613	memset(&evtnotify_req, 0, sizeof(evtnotify_req));
3614	mutex_lock(&mrioc->init_cmds.mutex);
3615	if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3616		retval = -1;
3617		ioc_err(mrioc, "Issue EvtNotify: Init command is in use\n");
3618		mutex_unlock(&mrioc->init_cmds.mutex);
3619		goto out;
3620	}
3621	mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3622	mrioc->init_cmds.is_waiting = 1;
3623	mrioc->init_cmds.callback = NULL;
3624	evtnotify_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3625	evtnotify_req.function = MPI3_FUNCTION_EVENT_NOTIFICATION;
3626	for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
3627		evtnotify_req.event_masks[i] =
3628		    cpu_to_le32(mrioc->event_masks[i]);
3629	init_completion(&mrioc->init_cmds.done);
3630	retval = mpi3mr_admin_request_post(mrioc, &evtnotify_req,
3631	    sizeof(evtnotify_req), 1);
3632	if (retval) {
3633		ioc_err(mrioc, "Issue EvtNotify: Admin Post failed\n");
3634		goto out_unlock;
3635	}
3636	wait_for_completion_timeout(&mrioc->init_cmds.done,
3637	    (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3638	if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3639		ioc_err(mrioc, "event notification timed out\n");
3640		mpi3mr_check_rh_fault_ioc(mrioc,
3641		    MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT);
3642		retval = -1;
3643		goto out_unlock;
3644	}
3645	if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3646	    != MPI3_IOCSTATUS_SUCCESS) {
3647		ioc_err(mrioc,
3648		    "Issue EvtNotify: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3649		    (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3650		    mrioc->init_cmds.ioc_loginfo);
3651		retval = -1;
3652		goto out_unlock;
3653	}
3654
3655out_unlock:
3656	mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3657	mutex_unlock(&mrioc->init_cmds.mutex);
3658out:
3659	return retval;
3660}
3661
3662/**
3663 * mpi3mr_process_event_ack - Process event acknowledgment
3664 * @mrioc: Adapter instance reference
3665 * @event: MPI3 event ID
3666 * @event_ctx: event context
3667 *
3668 * Send event acknowledgment through admin queue and wait for
3669 * it to complete.
3670 *
3671 * Return: 0 on success, non-zero on failures.
3672 */
3673int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event,
3674	u32 event_ctx)
3675{
3676	struct mpi3_event_ack_request evtack_req;
3677	int retval = 0;
3678
3679	memset(&evtack_req, 0, sizeof(evtack_req));
3680	mutex_lock(&mrioc->init_cmds.mutex);
3681	if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3682		retval = -1;
3683		ioc_err(mrioc, "Send EvtAck: Init command is in use\n");
3684		mutex_unlock(&mrioc->init_cmds.mutex);
3685		goto out;
3686	}
3687	mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3688	mrioc->init_cmds.is_waiting = 1;
3689	mrioc->init_cmds.callback = NULL;
3690	evtack_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3691	evtack_req.function = MPI3_FUNCTION_EVENT_ACK;
3692	evtack_req.event = event;
3693	evtack_req.event_context = cpu_to_le32(event_ctx);
3694
3695	init_completion(&mrioc->init_cmds.done);
3696	retval = mpi3mr_admin_request_post(mrioc, &evtack_req,
3697	    sizeof(evtack_req), 1);
3698	if (retval) {
3699		ioc_err(mrioc, "Send EvtAck: Admin Post failed\n");
3700		goto out_unlock;
3701	}
3702	wait_for_completion_timeout(&mrioc->init_cmds.done,
3703	    (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3704	if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3705		ioc_err(mrioc, "Issue EvtNotify: command timed out\n");
3706		if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET))
3707			mpi3mr_check_rh_fault_ioc(mrioc,
3708			    MPI3MR_RESET_FROM_EVTACK_TIMEOUT);
3709		retval = -1;
3710		goto out_unlock;
3711	}
3712	if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3713	    != MPI3_IOCSTATUS_SUCCESS) {
3714		ioc_err(mrioc,
3715		    "Send EvtAck: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3716		    (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3717		    mrioc->init_cmds.ioc_loginfo);
3718		retval = -1;
3719		goto out_unlock;
3720	}
3721
3722out_unlock:
3723	mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3724	mutex_unlock(&mrioc->init_cmds.mutex);
3725out:
3726	return retval;
3727}
3728
3729/**
3730 * mpi3mr_alloc_chain_bufs - Allocate chain buffers
3731 * @mrioc: Adapter instance reference
3732 *
3733 * Allocate chain buffers and set a bitmap to indicate free
3734 * chain buffers. Chain buffers are used to pass the SGE
3735 * information along with MPI3 SCSI IO requests for host I/O.
3736 *
3737 * Return: 0 on success, non-zero on failure
3738 */
3739static int mpi3mr_alloc_chain_bufs(struct mpi3mr_ioc *mrioc)
3740{
3741	int retval = 0;
3742	u32 sz, i;
3743	u16 num_chains;
3744
3745	if (mrioc->chain_sgl_list)
3746		return retval;
3747
3748	num_chains = mrioc->max_host_ios / MPI3MR_CHAINBUF_FACTOR;
3749
3750	if (prot_mask & (SHOST_DIX_TYPE0_PROTECTION
3751	    | SHOST_DIX_TYPE1_PROTECTION
3752	    | SHOST_DIX_TYPE2_PROTECTION
3753	    | SHOST_DIX_TYPE3_PROTECTION))
3754		num_chains += (num_chains / MPI3MR_CHAINBUFDIX_FACTOR);
3755
3756	mrioc->chain_buf_count = num_chains;
3757	sz = sizeof(struct chain_element) * num_chains;
3758	mrioc->chain_sgl_list = kzalloc(sz, GFP_KERNEL);
3759	if (!mrioc->chain_sgl_list)
3760		goto out_failed;
3761
3762	if (mrioc->max_sgl_entries > (mrioc->facts.max_data_length /
3763		MPI3MR_PAGE_SIZE_4K))
3764		mrioc->max_sgl_entries = mrioc->facts.max_data_length /
3765			MPI3MR_PAGE_SIZE_4K;
3766	sz = mrioc->max_sgl_entries * sizeof(struct mpi3_sge_common);
3767	ioc_info(mrioc, "number of sgl entries=%d chain buffer size=%dKB\n",
3768			mrioc->max_sgl_entries, sz/1024);
3769
3770	mrioc->chain_buf_pool = dma_pool_create("chain_buf pool",
3771	    &mrioc->pdev->dev, sz, 16, 0);
3772	if (!mrioc->chain_buf_pool) {
3773		ioc_err(mrioc, "chain buf pool: dma_pool_create failed\n");
3774		goto out_failed;
3775	}
3776
3777	for (i = 0; i < num_chains; i++) {
3778		mrioc->chain_sgl_list[i].addr =
3779		    dma_pool_zalloc(mrioc->chain_buf_pool, GFP_KERNEL,
3780		    &mrioc->chain_sgl_list[i].dma_addr);
3781
3782		if (!mrioc->chain_sgl_list[i].addr)
3783			goto out_failed;
3784	}
3785	mrioc->chain_bitmap = bitmap_zalloc(num_chains, GFP_KERNEL);
3786	if (!mrioc->chain_bitmap)
3787		goto out_failed;
3788	return retval;
3789out_failed:
3790	retval = -1;
3791	return retval;
3792}
3793
3794/**
3795 * mpi3mr_port_enable_complete - Mark port enable complete
3796 * @mrioc: Adapter instance reference
3797 * @drv_cmd: Internal command tracker
3798 *
3799 * Call back for asynchronous port enable request sets the
3800 * driver command to indicate port enable request is complete.
3801 *
3802 * Return: Nothing
3803 */
3804static void mpi3mr_port_enable_complete(struct mpi3mr_ioc *mrioc,
3805	struct mpi3mr_drv_cmd *drv_cmd)
3806{
3807	drv_cmd->callback = NULL;
3808	mrioc->scan_started = 0;
3809	if (drv_cmd->state & MPI3MR_CMD_RESET)
3810		mrioc->scan_failed = MPI3_IOCSTATUS_INTERNAL_ERROR;
3811	else
3812		mrioc->scan_failed = drv_cmd->ioc_status;
3813	drv_cmd->state = MPI3MR_CMD_NOTUSED;
3814}
3815
3816/**
3817 * mpi3mr_issue_port_enable - Issue Port Enable
3818 * @mrioc: Adapter instance reference
3819 * @async: Flag to wait for completion or not
3820 *
3821 * Issue Port Enable MPI request through admin queue and if the
3822 * async flag is not set wait for the completion of the port
3823 * enable or time out.
3824 *
3825 * Return: 0 on success, non-zero on failures.
3826 */
3827int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async)
3828{
3829	struct mpi3_port_enable_request pe_req;
3830	int retval = 0;
3831	u32 pe_timeout = MPI3MR_PORTENABLE_TIMEOUT;
3832
3833	memset(&pe_req, 0, sizeof(pe_req));
3834	mutex_lock(&mrioc->init_cmds.mutex);
3835	if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3836		retval = -1;
3837		ioc_err(mrioc, "Issue PortEnable: Init command is in use\n");
3838		mutex_unlock(&mrioc->init_cmds.mutex);
3839		goto out;
3840	}
3841	mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3842	if (async) {
3843		mrioc->init_cmds.is_waiting = 0;
3844		mrioc->init_cmds.callback = mpi3mr_port_enable_complete;
3845	} else {
3846		mrioc->init_cmds.is_waiting = 1;
3847		mrioc->init_cmds.callback = NULL;
3848		init_completion(&mrioc->init_cmds.done);
3849	}
3850	pe_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3851	pe_req.function = MPI3_FUNCTION_PORT_ENABLE;
3852
3853	retval = mpi3mr_admin_request_post(mrioc, &pe_req, sizeof(pe_req), 1);
3854	if (retval) {
3855		ioc_err(mrioc, "Issue PortEnable: Admin Post failed\n");
3856		goto out_unlock;
3857	}
3858	if (async) {
3859		mutex_unlock(&mrioc->init_cmds.mutex);
3860		goto out;
3861	}
3862
3863	wait_for_completion_timeout(&mrioc->init_cmds.done, (pe_timeout * HZ));
3864	if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3865		ioc_err(mrioc, "port enable timed out\n");
3866		retval = -1;
3867		mpi3mr_check_rh_fault_ioc(mrioc, MPI3MR_RESET_FROM_PE_TIMEOUT);
3868		goto out_unlock;
3869	}
3870	mpi3mr_port_enable_complete(mrioc, &mrioc->init_cmds);
3871
3872out_unlock:
3873	mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3874	mutex_unlock(&mrioc->init_cmds.mutex);
3875out:
3876	return retval;
3877}
3878
3879/* Protocol type to name mapper structure */
3880static const struct {
3881	u8 protocol;
3882	char *name;
3883} mpi3mr_protocols[] = {
3884	{ MPI3_IOCFACTS_PROTOCOL_SCSI_INITIATOR, "Initiator" },
3885	{ MPI3_IOCFACTS_PROTOCOL_SCSI_TARGET, "Target" },
3886	{ MPI3_IOCFACTS_PROTOCOL_NVME, "NVMe attachment" },
3887};
3888
3889/* Capability to name mapper structure*/
3890static const struct {
3891	u32 capability;
3892	char *name;
3893} mpi3mr_capabilities[] = {
3894	{ MPI3_IOCFACTS_CAPABILITY_RAID_SUPPORTED, "RAID" },
3895	{ MPI3_IOCFACTS_CAPABILITY_MULTIPATH_SUPPORTED, "MultiPath" },
3896};
3897
3898/**
3899 * mpi3mr_repost_diag_bufs - repost host diag buffers
3900 * @mrioc: Adapter instance reference
3901 *
3902 * repost firmware and trace diag buffers based on global
3903 * trigger flag from driver page 2
3904 *
3905 * Return: 0 on success, non-zero on failures.
3906 */
3907static int mpi3mr_repost_diag_bufs(struct mpi3mr_ioc *mrioc)
3908{
3909	u64 global_trigger;
3910	union mpi3mr_trigger_data prev_trigger_data;
3911	struct diag_buffer_desc *trace_hdb = NULL;
3912	struct diag_buffer_desc *fw_hdb = NULL;
3913	int retval = 0;
3914	bool trace_repost_needed = false;
3915	bool fw_repost_needed = false;
3916	u8 prev_trigger_type;
3917
3918	retval = mpi3mr_refresh_trigger(mrioc, MPI3_CONFIG_ACTION_READ_CURRENT);
3919	if (retval)
3920		return -1;
3921
3922	trace_hdb = mpi3mr_diag_buffer_for_type(mrioc,
3923	    MPI3_DIAG_BUFFER_TYPE_TRACE);
3924
3925	if (trace_hdb &&
3926	    trace_hdb->status != MPI3MR_HDB_BUFSTATUS_NOT_ALLOCATED &&
3927	    trace_hdb->trigger_type != MPI3MR_HDB_TRIGGER_TYPE_GLOBAL &&
3928	    trace_hdb->trigger_type != MPI3MR_HDB_TRIGGER_TYPE_ELEMENT)
3929		trace_repost_needed = true;
3930
3931	fw_hdb = mpi3mr_diag_buffer_for_type(mrioc, MPI3_DIAG_BUFFER_TYPE_FW);
3932
3933	if (fw_hdb && fw_hdb->status != MPI3MR_HDB_BUFSTATUS_NOT_ALLOCATED &&
3934	    fw_hdb->trigger_type != MPI3MR_HDB_TRIGGER_TYPE_GLOBAL &&
3935	    fw_hdb->trigger_type != MPI3MR_HDB_TRIGGER_TYPE_ELEMENT)
3936		fw_repost_needed = true;
3937
3938	if (trace_repost_needed || fw_repost_needed) {
3939		global_trigger = le64_to_cpu(mrioc->driver_pg2->global_trigger);
3940		if (global_trigger &
3941		      MPI3_DRIVER2_GLOBALTRIGGER_POST_DIAG_TRACE_DISABLED)
3942			trace_repost_needed = false;
3943		if (global_trigger &
3944		     MPI3_DRIVER2_GLOBALTRIGGER_POST_DIAG_FW_DISABLED)
3945			fw_repost_needed = false;
3946	}
3947
3948	if (trace_repost_needed) {
3949		prev_trigger_type = trace_hdb->trigger_type;
3950		memcpy(&prev_trigger_data, &trace_hdb->trigger_data,
3951		    sizeof(trace_hdb->trigger_data));
3952		retval = mpi3mr_issue_diag_buf_post(mrioc, trace_hdb);
3953		if (!retval) {
3954			dprint_init(mrioc, "trace diag buffer reposted");
3955			mpi3mr_set_trigger_data_in_hdb(trace_hdb,
3956				    MPI3MR_HDB_TRIGGER_TYPE_UNKNOWN, NULL, 1);
3957		} else {
3958			trace_hdb->trigger_type = prev_trigger_type;
3959			memcpy(&trace_hdb->trigger_data, &prev_trigger_data,
3960			    sizeof(prev_trigger_data));
3961			ioc_err(mrioc, "trace diag buffer repost failed");
3962			return -1;
3963		}
3964	}
3965
3966	if (fw_repost_needed) {
3967		prev_trigger_type = fw_hdb->trigger_type;
3968		memcpy(&prev_trigger_data, &fw_hdb->trigger_data,
3969		    sizeof(fw_hdb->trigger_data));
3970		retval = mpi3mr_issue_diag_buf_post(mrioc, fw_hdb);
3971		if (!retval) {
3972			dprint_init(mrioc, "firmware diag buffer reposted");
3973			mpi3mr_set_trigger_data_in_hdb(fw_hdb,
3974				    MPI3MR_HDB_TRIGGER_TYPE_UNKNOWN, NULL, 1);
3975		} else {
3976			fw_hdb->trigger_type = prev_trigger_type;
3977			memcpy(&fw_hdb->trigger_data, &prev_trigger_data,
3978			    sizeof(prev_trigger_data));
3979			ioc_err(mrioc, "firmware diag buffer repost failed");
3980			return -1;
3981		}
3982	}
3983	return retval;
3984}
3985
3986/**
3987 * mpi3mr_read_tsu_interval - Update time stamp interval
3988 * @mrioc: Adapter instance reference
3989 *
3990 * Update time stamp interval if its defined in driver page 1,
3991 * otherwise use default value.
3992 *
3993 * Return: Nothing
3994 */
3995static void
3996mpi3mr_read_tsu_interval(struct mpi3mr_ioc *mrioc)
3997{
3998	struct mpi3_driver_page1 driver_pg1;
3999	u16 pg_sz = sizeof(driver_pg1);
4000	int retval = 0;
4001
4002	mrioc->ts_update_interval = MPI3MR_TSUPDATE_INTERVAL;
4003
4004	retval = mpi3mr_cfg_get_driver_pg1(mrioc, &driver_pg1, pg_sz);
4005	if (!retval && driver_pg1.time_stamp_update)
4006		mrioc->ts_update_interval = (driver_pg1.time_stamp_update * 60);
4007}
4008
4009/**
4010 * mpi3mr_print_ioc_info - Display controller information
4011 * @mrioc: Adapter instance reference
4012 *
4013 * Display controller personality, capability, supported
4014 * protocols etc.
4015 *
4016 * Return: Nothing
4017 */
4018static void
4019mpi3mr_print_ioc_info(struct mpi3mr_ioc *mrioc)
4020{
4021	int i = 0, bytes_written = 0;
4022	const char *personality;
4023	char protocol[50] = {0};
4024	char capabilities[100] = {0};
4025	struct mpi3mr_compimg_ver *fwver = &mrioc->facts.fw_ver;
4026
4027	switch (mrioc->facts.personality) {
4028	case MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA:
4029		personality = "Enhanced HBA";
4030		break;
4031	case MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR:
4032		personality = "RAID";
4033		break;
4034	default:
4035		personality = "Unknown";
4036		break;
4037	}
4038
4039	ioc_info(mrioc, "Running in %s Personality", personality);
4040
4041	ioc_info(mrioc, "FW version(%d.%d.%d.%d.%d.%d)\n",
4042	    fwver->gen_major, fwver->gen_minor, fwver->ph_major,
4043	    fwver->ph_minor, fwver->cust_id, fwver->build_num);
4044
4045	for (i = 0; i < ARRAY_SIZE(mpi3mr_protocols); i++) {
4046		if (mrioc->facts.protocol_flags &
4047		    mpi3mr_protocols[i].protocol) {
4048			bytes_written += scnprintf(protocol + bytes_written,
4049				    sizeof(protocol) - bytes_written, "%s%s",
4050				    bytes_written ? "," : "",
4051				    mpi3mr_protocols[i].name);
4052		}
4053	}
4054
4055	bytes_written = 0;
4056	for (i = 0; i < ARRAY_SIZE(mpi3mr_capabilities); i++) {
4057		if (mrioc->facts.protocol_flags &
4058		    mpi3mr_capabilities[i].capability) {
4059			bytes_written += scnprintf(capabilities + bytes_written,
4060				    sizeof(capabilities) - bytes_written, "%s%s",
4061				    bytes_written ? "," : "",
4062				    mpi3mr_capabilities[i].name);
4063		}
4064	}
4065
4066	ioc_info(mrioc, "Protocol=(%s), Capabilities=(%s)\n",
4067		 protocol, capabilities);
4068}
4069
4070/**
4071 * mpi3mr_cleanup_resources - Free PCI resources
4072 * @mrioc: Adapter instance reference
4073 *
4074 * Unmap PCI device memory and disable PCI device.
4075 *
4076 * Return: 0 on success and non-zero on failure.
4077 */
4078void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc)
4079{
4080	struct pci_dev *pdev = mrioc->pdev;
4081
4082	mpi3mr_cleanup_isr(mrioc);
4083
4084	if (mrioc->sysif_regs) {
4085		iounmap((void __iomem *)mrioc->sysif_regs);
4086		mrioc->sysif_regs = NULL;
4087	}
4088
4089	if (pci_is_enabled(pdev)) {
4090		if (mrioc->bars)
4091			pci_release_selected_regions(pdev, mrioc->bars);
4092		pci_disable_device(pdev);
4093	}
4094}
4095
4096/**
4097 * mpi3mr_setup_resources - Enable PCI resources
4098 * @mrioc: Adapter instance reference
4099 *
4100 * Enable PCI device memory, MSI-x registers and set DMA mask.
4101 *
4102 * Return: 0 on success and non-zero on failure.
4103 */
4104int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc)
4105{
4106	struct pci_dev *pdev = mrioc->pdev;
4107	u32 memap_sz = 0;
4108	int i, retval = 0, capb = 0;
4109	u16 message_control;
4110	u64 dma_mask = mrioc->dma_mask ? mrioc->dma_mask :
4111	    ((sizeof(dma_addr_t) > 4) ? DMA_BIT_MASK(64) : DMA_BIT_MASK(32));
4112
4113	if (pci_enable_device_mem(pdev)) {
4114		ioc_err(mrioc, "pci_enable_device_mem: failed\n");
4115		retval = -ENODEV;
4116		goto out_failed;
4117	}
4118
4119	capb = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
4120	if (!capb) {
4121		ioc_err(mrioc, "Unable to find MSI-X Capabilities\n");
4122		retval = -ENODEV;
4123		goto out_failed;
4124	}
4125	mrioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
4126
4127	if (pci_request_selected_regions(pdev, mrioc->bars,
4128	    mrioc->driver_name)) {
4129		ioc_err(mrioc, "pci_request_selected_regions: failed\n");
4130		retval = -ENODEV;
4131		goto out_failed;
4132	}
4133
4134	for (i = 0; (i < DEVICE_COUNT_RESOURCE); i++) {
4135		if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
4136			mrioc->sysif_regs_phys = pci_resource_start(pdev, i);
4137			memap_sz = pci_resource_len(pdev, i);
4138			mrioc->sysif_regs =
4139			    ioremap(mrioc->sysif_regs_phys, memap_sz);
4140			break;
4141		}
4142	}
4143
4144	pci_set_master(pdev);
4145
4146	retval = dma_set_mask_and_coherent(&pdev->dev, dma_mask);
4147	if (retval) {
4148		if (dma_mask != DMA_BIT_MASK(32)) {
4149			ioc_warn(mrioc, "Setting 64 bit DMA mask failed\n");
4150			dma_mask = DMA_BIT_MASK(32);
4151			retval = dma_set_mask_and_coherent(&pdev->dev,
4152			    dma_mask);
4153		}
4154		if (retval) {
4155			mrioc->dma_mask = 0;
4156			ioc_err(mrioc, "Setting 32 bit DMA mask also failed\n");
4157			goto out_failed;
4158		}
4159	}
4160	mrioc->dma_mask = dma_mask;
4161
4162	if (!mrioc->sysif_regs) {
4163		ioc_err(mrioc,
4164		    "Unable to map adapter memory or resource not found\n");
4165		retval = -EINVAL;
4166		goto out_failed;
4167	}
4168
4169	pci_read_config_word(pdev, capb + 2, &message_control);
4170	mrioc->msix_count = (message_control & 0x3FF) + 1;
4171
4172	pci_save_state(pdev);
4173
4174	pci_set_drvdata(pdev, mrioc->shost);
4175
4176	mpi3mr_ioc_disable_intr(mrioc);
4177
4178	ioc_info(mrioc, "iomem(0x%016llx), mapped(0x%p), size(%d)\n",
4179	    (unsigned long long)mrioc->sysif_regs_phys,
4180	    mrioc->sysif_regs, memap_sz);
4181	ioc_info(mrioc, "Number of MSI-X vectors found in capabilities: (%d)\n",
4182	    mrioc->msix_count);
4183
4184	if (!reset_devices && poll_queues > 0)
4185		mrioc->requested_poll_qcount = min_t(int, poll_queues,
4186				mrioc->msix_count - 2);
4187	return retval;
4188
4189out_failed:
4190	mpi3mr_cleanup_resources(mrioc);
4191	return retval;
4192}
4193
4194/**
4195 * mpi3mr_enable_events - Enable required events
4196 * @mrioc: Adapter instance reference
4197 *
4198 * This routine unmasks the events required by the driver by
4199 * sennding appropriate event mask bitmapt through an event
4200 * notification request.
4201 *
4202 * Return: 0 on success and non-zero on failure.
4203 */
4204static int mpi3mr_enable_events(struct mpi3mr_ioc *mrioc)
4205{
4206	int retval = 0;
4207	u32  i;
4208
4209	for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
4210		mrioc->event_masks[i] = -1;
4211
4212	mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_ADDED);
4213	mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_INFO_CHANGED);
4214	mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_STATUS_CHANGE);
4215	mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE);
4216	mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_ADDED);
4217	mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
4218	mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DISCOVERY);
4219	mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR);
4220	mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_BROADCAST_PRIMITIVE);
4221	mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST);
4222	mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_ENUMERATION);
4223	mpi3mr_unmask_events(mrioc, MPI3_EVENT_PREPARE_FOR_RESET);
4224	mpi3mr_unmask_events(mrioc, MPI3_EVENT_CABLE_MGMT);
4225	mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENERGY_PACK_CHANGE);
4226	mpi3mr_unmask_events(mrioc, MPI3_EVENT_DIAGNOSTIC_BUFFER_STATUS_CHANGE);
4227
4228	retval = mpi3mr_issue_event_notification(mrioc);
4229	if (retval)
4230		ioc_err(mrioc, "failed to issue event notification %d\n",
4231		    retval);
4232	return retval;
4233}
4234
4235/**
4236 * mpi3mr_init_ioc - Initialize the controller
4237 * @mrioc: Adapter instance reference
4238 *
4239 * This the controller initialization routine, executed either
4240 * after soft reset or from pci probe callback.
4241 * Setup the required resources, memory map the controller
4242 * registers, create admin and operational reply queue pairs,
4243 * allocate required memory for reply pool, sense buffer pool,
4244 * issue IOC init request to the firmware, unmask the events and
4245 * issue port enable to discover SAS/SATA/NVMe devies and RAID
4246 * volumes.
4247 *
4248 * Return: 0 on success and non-zero on failure.
4249 */
4250int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc)
4251{
4252	int retval = 0;
4253	u8 retry = 0;
4254	struct mpi3_ioc_facts_data facts_data;
4255	u32 sz;
4256
4257retry_init:
4258	retval = mpi3mr_bring_ioc_ready(mrioc);
4259	if (retval) {
4260		ioc_err(mrioc, "Failed to bring ioc ready: error %d\n",
4261		    retval);
4262		goto out_failed_noretry;
4263	}
4264
4265	retval = mpi3mr_setup_isr(mrioc, 1);
4266	if (retval) {
4267		ioc_err(mrioc, "Failed to setup ISR error %d\n",
4268		    retval);
4269		goto out_failed_noretry;
4270	}
4271
4272	retval = mpi3mr_issue_iocfacts(mrioc, &facts_data);
4273	if (retval) {
4274		ioc_err(mrioc, "Failed to Issue IOC Facts %d\n",
4275		    retval);
4276		goto out_failed;
4277	}
4278
4279	mrioc->max_host_ios = mrioc->facts.max_reqs - MPI3MR_INTERNAL_CMDS_RESVD;
4280	mrioc->shost->max_sectors = mrioc->facts.max_data_length / 512;
4281	mrioc->num_io_throttle_group = mrioc->facts.max_io_throttle_group;
4282	atomic_set(&mrioc->pend_large_data_sz, 0);
4283
4284	if (reset_devices)
4285		mrioc->max_host_ios = min_t(int, mrioc->max_host_ios,
4286		    MPI3MR_HOST_IOS_KDUMP);
4287
4288	if (!(mrioc->facts.ioc_capabilities &
4289	    MPI3_IOCFACTS_CAPABILITY_MULTIPATH_SUPPORTED)) {
4290		mrioc->sas_transport_enabled = 1;
4291		mrioc->scsi_device_channel = 1;
4292		mrioc->shost->max_channel = 1;
4293		mrioc->shost->transportt = mpi3mr_transport_template;
4294	}
4295
4296	if (mrioc->facts.max_req_limit)
4297		mrioc->prevent_reply_qfull = true;
4298
4299	if (mrioc->facts.ioc_capabilities &
4300		MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_TRACE_SUPPORTED)
4301		mrioc->seg_tb_support = true;
4302
4303	mrioc->reply_sz = mrioc->facts.reply_sz;
4304
4305	retval = mpi3mr_check_reset_dma_mask(mrioc);
4306	if (retval) {
4307		ioc_err(mrioc, "Resetting dma mask failed %d\n",
4308		    retval);
4309		goto out_failed_noretry;
4310	}
4311
4312	mpi3mr_read_tsu_interval(mrioc);
4313	mpi3mr_print_ioc_info(mrioc);
4314
4315	dprint_init(mrioc, "allocating host diag buffers\n");
4316	mpi3mr_alloc_diag_bufs(mrioc);
4317
4318	dprint_init(mrioc, "allocating ioctl dma buffers\n");
4319	mpi3mr_alloc_ioctl_dma_memory(mrioc);
4320
4321	dprint_init(mrioc, "posting host diag buffers\n");
4322	retval = mpi3mr_post_diag_bufs(mrioc);
4323
4324	if (retval)
4325		ioc_warn(mrioc, "failed to post host diag buffers\n");
4326
4327	if (!mrioc->init_cmds.reply) {
4328		retval = mpi3mr_alloc_reply_sense_bufs(mrioc);
4329		if (retval) {
4330			ioc_err(mrioc,
4331			    "%s :Failed to allocated reply sense buffers %d\n",
4332			    __func__, retval);
4333			goto out_failed_noretry;
4334		}
4335	}
4336
4337	if (!mrioc->chain_sgl_list) {
4338		retval = mpi3mr_alloc_chain_bufs(mrioc);
4339		if (retval) {
4340			ioc_err(mrioc, "Failed to allocated chain buffers %d\n",
4341			    retval);
4342			goto out_failed_noretry;
4343		}
4344	}
4345
4346	retval = mpi3mr_issue_iocinit(mrioc);
4347	if (retval) {
4348		ioc_err(mrioc, "Failed to Issue IOC Init %d\n",
4349		    retval);
4350		goto out_failed;
4351	}
4352
4353	retval = mpi3mr_print_pkg_ver(mrioc);
4354	if (retval) {
4355		ioc_err(mrioc, "failed to get package version\n");
4356		goto out_failed;
4357	}
4358
4359	retval = mpi3mr_setup_isr(mrioc, 0);
4360	if (retval) {
4361		ioc_err(mrioc, "Failed to re-setup ISR, error %d\n",
4362		    retval);
4363		goto out_failed_noretry;
4364	}
4365
4366	retval = mpi3mr_create_op_queues(mrioc);
4367	if (retval) {
4368		ioc_err(mrioc, "Failed to create OpQueues error %d\n",
4369		    retval);
4370		goto out_failed;
4371	}
4372
4373	if (!mrioc->pel_seqnum_virt) {
4374		dprint_init(mrioc, "allocating memory for pel_seqnum_virt\n");
4375		mrioc->pel_seqnum_sz = sizeof(struct mpi3_pel_seq);
4376		mrioc->pel_seqnum_virt = dma_alloc_coherent(&mrioc->pdev->dev,
4377		    mrioc->pel_seqnum_sz, &mrioc->pel_seqnum_dma,
4378		    GFP_KERNEL);
4379		if (!mrioc->pel_seqnum_virt) {
4380			retval = -ENOMEM;
4381			goto out_failed_noretry;
4382		}
4383	}
4384
4385	if (!mrioc->throttle_groups && mrioc->num_io_throttle_group) {
4386		dprint_init(mrioc, "allocating memory for throttle groups\n");
4387		sz = sizeof(struct mpi3mr_throttle_group_info);
4388		mrioc->throttle_groups = kcalloc(mrioc->num_io_throttle_group, sz, GFP_KERNEL);
4389		if (!mrioc->throttle_groups) {
4390			retval = -1;
4391			goto out_failed_noretry;
4392		}
4393	}
4394
4395	retval = mpi3mr_enable_events(mrioc);
4396	if (retval) {
4397		ioc_err(mrioc, "failed to enable events %d\n",
4398		    retval);
4399		goto out_failed;
4400	}
4401
4402	retval = mpi3mr_refresh_trigger(mrioc, MPI3_CONFIG_ACTION_READ_CURRENT);
4403	if (retval) {
4404		ioc_err(mrioc, "failed to refresh triggers\n");
4405		goto out_failed;
4406	}
4407
4408	ioc_info(mrioc, "controller initialization completed successfully\n");
4409	return retval;
4410out_failed:
4411	if (retry < 2) {
4412		retry++;
4413		ioc_warn(mrioc, "retrying controller initialization, retry_count:%d\n",
4414		    retry);
4415		mpi3mr_memset_buffers(mrioc);
4416		goto retry_init;
4417	}
4418	retval = -1;
4419out_failed_noretry:
4420	ioc_err(mrioc, "controller initialization failed\n");
4421	mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
4422	    MPI3MR_RESET_FROM_CTLR_CLEANUP);
4423	mrioc->unrecoverable = 1;
4424	return retval;
4425}
4426
4427/**
4428 * mpi3mr_reinit_ioc - Re-Initialize the controller
4429 * @mrioc: Adapter instance reference
4430 * @is_resume: Called from resume or reset path
4431 *
4432 * This the controller re-initialization routine, executed from
4433 * the soft reset handler or resume callback. Creates
4434 * operational reply queue pairs, allocate required memory for
4435 * reply pool, sense buffer pool, issue IOC init request to the
4436 * firmware, unmask the events and issue port enable to discover
4437 * SAS/SATA/NVMe devices and RAID volumes.
4438 *
4439 * Return: 0 on success and non-zero on failure.
4440 */
4441int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume)
4442{
4443	int retval = 0;
4444	u8 retry = 0;
4445	struct mpi3_ioc_facts_data facts_data;
4446	u32 pe_timeout, ioc_status;
4447
4448retry_init:
4449	pe_timeout =
4450	    (MPI3MR_PORTENABLE_TIMEOUT / MPI3MR_PORTENABLE_POLL_INTERVAL);
4451
4452	dprint_reset(mrioc, "bringing up the controller to ready state\n");
4453	retval = mpi3mr_bring_ioc_ready(mrioc);
4454	if (retval) {
4455		ioc_err(mrioc, "failed to bring to ready state\n");
4456		goto out_failed_noretry;
4457	}
4458
4459	mrioc->io_admin_reset_sync = 0;
4460	if (is_resume || mrioc->block_on_pci_err) {
4461		dprint_reset(mrioc, "setting up single ISR\n");
4462		retval = mpi3mr_setup_isr(mrioc, 1);
4463		if (retval) {
4464			ioc_err(mrioc, "failed to setup ISR\n");
4465			goto out_failed_noretry;
4466		}
4467	} else
4468		mpi3mr_ioc_enable_intr(mrioc);
4469
4470	dprint_reset(mrioc, "getting ioc_facts\n");
4471	retval = mpi3mr_issue_iocfacts(mrioc, &facts_data);
4472	if (retval) {
4473		ioc_err(mrioc, "failed to get ioc_facts\n");
4474		goto out_failed;
4475	}
4476
4477	dprint_reset(mrioc, "validating ioc_facts\n");
4478	retval = mpi3mr_revalidate_factsdata(mrioc);
4479	if (retval) {
4480		ioc_err(mrioc, "failed to revalidate ioc_facts data\n");
4481		goto out_failed_noretry;
4482	}
4483
4484	mpi3mr_read_tsu_interval(mrioc);
4485	mpi3mr_print_ioc_info(mrioc);
4486
4487	if (is_resume) {
4488		dprint_reset(mrioc, "posting host diag buffers\n");
4489		retval = mpi3mr_post_diag_bufs(mrioc);
4490		if (retval)
4491			ioc_warn(mrioc, "failed to post host diag buffers\n");
4492	} else {
4493		retval = mpi3mr_repost_diag_bufs(mrioc);
4494		if (retval)
4495			ioc_warn(mrioc, "failed to re post host diag buffers\n");
4496	}
4497
4498	dprint_reset(mrioc, "sending ioc_init\n");
4499	retval = mpi3mr_issue_iocinit(mrioc);
4500	if (retval) {
4501		ioc_err(mrioc, "failed to send ioc_init\n");
4502		goto out_failed;
4503	}
4504
4505	dprint_reset(mrioc, "getting package version\n");
4506	retval = mpi3mr_print_pkg_ver(mrioc);
4507	if (retval) {
4508		ioc_err(mrioc, "failed to get package version\n");
4509		goto out_failed;
4510	}
4511
4512	if (is_resume || mrioc->block_on_pci_err) {
4513		dprint_reset(mrioc, "setting up multiple ISR\n");
4514		retval = mpi3mr_setup_isr(mrioc, 0);
4515		if (retval) {
4516			ioc_err(mrioc, "failed to re-setup ISR\n");
4517			goto out_failed_noretry;
4518		}
4519	}
4520
4521	dprint_reset(mrioc, "creating operational queue pairs\n");
4522	retval = mpi3mr_create_op_queues(mrioc);
4523	if (retval) {
4524		ioc_err(mrioc, "failed to create operational queue pairs\n");
4525		goto out_failed;
4526	}
4527
4528	if (!mrioc->pel_seqnum_virt) {
4529		dprint_reset(mrioc, "allocating memory for pel_seqnum_virt\n");
4530		mrioc->pel_seqnum_sz = sizeof(struct mpi3_pel_seq);
4531		mrioc->pel_seqnum_virt = dma_alloc_coherent(&mrioc->pdev->dev,
4532		    mrioc->pel_seqnum_sz, &mrioc->pel_seqnum_dma,
4533		    GFP_KERNEL);
4534		if (!mrioc->pel_seqnum_virt) {
4535			retval = -ENOMEM;
4536			goto out_failed_noretry;
4537		}
4538	}
4539
4540	if (mrioc->shost->nr_hw_queues > mrioc->num_op_reply_q) {
4541		ioc_err(mrioc,
4542		    "cannot create minimum number of operational queues expected:%d created:%d\n",
4543		    mrioc->shost->nr_hw_queues, mrioc->num_op_reply_q);
4544		retval = -1;
4545		goto out_failed_noretry;
4546	}
4547
4548	dprint_reset(mrioc, "enabling events\n");
4549	retval = mpi3mr_enable_events(mrioc);
4550	if (retval) {
4551		ioc_err(mrioc, "failed to enable events\n");
4552		goto out_failed;
4553	}
4554
4555	mrioc->device_refresh_on = 1;
4556	mpi3mr_add_event_wait_for_device_refresh(mrioc);
4557
4558	ioc_info(mrioc, "sending port enable\n");
4559	retval = mpi3mr_issue_port_enable(mrioc, 1);
4560	if (retval) {
4561		ioc_err(mrioc, "failed to issue port enable\n");
4562		goto out_failed;
4563	}
4564	do {
4565		ssleep(MPI3MR_PORTENABLE_POLL_INTERVAL);
4566		if (mrioc->init_cmds.state == MPI3MR_CMD_NOTUSED)
4567			break;
4568		if (!pci_device_is_present(mrioc->pdev))
4569			mrioc->unrecoverable = 1;
4570		if (mrioc->unrecoverable) {
4571			retval = -1;
4572			goto out_failed_noretry;
4573		}
4574		ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4575		if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) ||
4576		    (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) {
4577			mpi3mr_print_fault_info(mrioc);
4578			mrioc->init_cmds.is_waiting = 0;
4579			mrioc->init_cmds.callback = NULL;
4580			mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
4581			goto out_failed;
4582		}
4583	} while (--pe_timeout);
4584
4585	if (!pe_timeout) {
4586		ioc_err(mrioc, "port enable timed out\n");
4587		mpi3mr_check_rh_fault_ioc(mrioc,
4588		    MPI3MR_RESET_FROM_PE_TIMEOUT);
4589		mrioc->init_cmds.is_waiting = 0;
4590		mrioc->init_cmds.callback = NULL;
4591		mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
4592		goto out_failed;
4593	} else if (mrioc->scan_failed) {
4594		ioc_err(mrioc,
4595		    "port enable failed with status=0x%04x\n",
4596		    mrioc->scan_failed);
4597	} else
4598		ioc_info(mrioc, "port enable completed successfully\n");
4599
4600	ioc_info(mrioc, "controller %s completed successfully\n",
4601	    (is_resume)?"resume":"re-initialization");
4602	return retval;
4603out_failed:
4604	if (retry < 2) {
4605		retry++;
4606		ioc_warn(mrioc, "retrying controller %s, retry_count:%d\n",
4607		    (is_resume)?"resume":"re-initialization", retry);
4608		mpi3mr_memset_buffers(mrioc);
4609		goto retry_init;
4610	}
4611	retval = -1;
4612out_failed_noretry:
4613	ioc_err(mrioc, "controller %s is failed\n",
4614	    (is_resume)?"resume":"re-initialization");
4615	mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
4616	    MPI3MR_RESET_FROM_CTLR_CLEANUP);
4617	mrioc->unrecoverable = 1;
4618	return retval;
4619}
4620
4621/**
4622 * mpi3mr_memset_op_reply_q_buffers - memset the operational reply queue's
4623 *					segments
4624 * @mrioc: Adapter instance reference
4625 * @qidx: Operational reply queue index
4626 *
4627 * Return: Nothing.
4628 */
4629static void mpi3mr_memset_op_reply_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx)
4630{
4631	struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
4632	struct segments *segments;
4633	int i, size;
4634
4635	if (!op_reply_q->q_segments)
4636		return;
4637
4638	size = op_reply_q->segment_qd * mrioc->op_reply_desc_sz;
4639	segments = op_reply_q->q_segments;
4640	for (i = 0; i < op_reply_q->num_segments; i++)
4641		memset(segments[i].segment, 0, size);
4642}
4643
4644/**
4645 * mpi3mr_memset_op_req_q_buffers - memset the operational request queue's
4646 *					segments
4647 * @mrioc: Adapter instance reference
4648 * @qidx: Operational request queue index
4649 *
4650 * Return: Nothing.
4651 */
4652static void mpi3mr_memset_op_req_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx)
4653{
4654	struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx;
4655	struct segments *segments;
4656	int i, size;
4657
4658	if (!op_req_q->q_segments)
4659		return;
4660
4661	size = op_req_q->segment_qd * mrioc->facts.op_req_sz;
4662	segments = op_req_q->q_segments;
4663	for (i = 0; i < op_req_q->num_segments; i++)
4664		memset(segments[i].segment, 0, size);
4665}
4666
4667/**
4668 * mpi3mr_memset_buffers - memset memory for a controller
4669 * @mrioc: Adapter instance reference
4670 *
4671 * clear all the memory allocated for a controller, typically
4672 * called post reset to reuse the memory allocated during the
4673 * controller init.
4674 *
4675 * Return: Nothing.
4676 */
4677void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc)
4678{
4679	u16 i;
4680	struct mpi3mr_throttle_group_info *tg;
4681
4682	mrioc->change_count = 0;
4683	mrioc->active_poll_qcount = 0;
4684	mrioc->default_qcount = 0;
4685	if (mrioc->admin_req_base)
4686		memset(mrioc->admin_req_base, 0, mrioc->admin_req_q_sz);
4687	if (mrioc->admin_reply_base)
4688		memset(mrioc->admin_reply_base, 0, mrioc->admin_reply_q_sz);
4689	atomic_set(&mrioc->admin_reply_q_in_use, 0);
4690	atomic_set(&mrioc->admin_pend_isr, 0);
4691
4692	if (mrioc->init_cmds.reply) {
4693		memset(mrioc->init_cmds.reply, 0, sizeof(*mrioc->init_cmds.reply));
4694		memset(mrioc->bsg_cmds.reply, 0,
4695		    sizeof(*mrioc->bsg_cmds.reply));
4696		memset(mrioc->host_tm_cmds.reply, 0,
4697		    sizeof(*mrioc->host_tm_cmds.reply));
4698		memset(mrioc->pel_cmds.reply, 0,
4699		    sizeof(*mrioc->pel_cmds.reply));
4700		memset(mrioc->pel_abort_cmd.reply, 0,
4701		    sizeof(*mrioc->pel_abort_cmd.reply));
4702		memset(mrioc->transport_cmds.reply, 0,
4703		    sizeof(*mrioc->transport_cmds.reply));
4704		for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++)
4705			memset(mrioc->dev_rmhs_cmds[i].reply, 0,
4706			    sizeof(*mrioc->dev_rmhs_cmds[i].reply));
4707		for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++)
4708			memset(mrioc->evtack_cmds[i].reply, 0,
4709			    sizeof(*mrioc->evtack_cmds[i].reply));
4710		bitmap_clear(mrioc->removepend_bitmap, 0,
4711			     mrioc->dev_handle_bitmap_bits);
4712		bitmap_clear(mrioc->devrem_bitmap, 0, MPI3MR_NUM_DEVRMCMD);
4713		bitmap_clear(mrioc->evtack_cmds_bitmap, 0,
4714			     MPI3MR_NUM_EVTACKCMD);
4715	}
4716
4717	for (i = 0; i < mrioc->num_queues; i++) {
4718		if (mrioc->op_reply_qinfo) {
4719			mrioc->op_reply_qinfo[i].qid = 0;
4720			mrioc->op_reply_qinfo[i].ci = 0;
4721			mrioc->op_reply_qinfo[i].num_replies = 0;
4722			mrioc->op_reply_qinfo[i].ephase = 0;
4723			atomic_set(&mrioc->op_reply_qinfo[i].pend_ios, 0);
4724			atomic_set(&mrioc->op_reply_qinfo[i].in_use, 0);
4725			mpi3mr_memset_op_reply_q_buffers(mrioc, i);
4726		}
4727
4728		if (mrioc->req_qinfo) {
4729			mrioc->req_qinfo[i].ci = 0;
4730			mrioc->req_qinfo[i].pi = 0;
4731			mrioc->req_qinfo[i].num_requests = 0;
4732			mrioc->req_qinfo[i].qid = 0;
4733			mrioc->req_qinfo[i].reply_qid = 0;
4734			spin_lock_init(&mrioc->req_qinfo[i].q_lock);
4735			mpi3mr_memset_op_req_q_buffers(mrioc, i);
4736		}
4737	}
4738
4739	atomic_set(&mrioc->pend_large_data_sz, 0);
4740	if (mrioc->throttle_groups) {
4741		tg = mrioc->throttle_groups;
4742		for (i = 0; i < mrioc->num_io_throttle_group; i++, tg++) {
4743			tg->id = 0;
4744			tg->fw_qd = 0;
4745			tg->modified_qd = 0;
4746			tg->io_divert = 0;
4747			tg->need_qd_reduction = 0;
4748			tg->high = 0;
4749			tg->low = 0;
4750			tg->qd_reduction = 0;
4751			atomic_set(&tg->pend_large_data_sz, 0);
4752		}
4753	}
4754}
4755
4756/**
4757 * mpi3mr_free_mem - Free memory allocated for a controller
4758 * @mrioc: Adapter instance reference
4759 *
4760 * Free all the memory allocated for a controller.
4761 *
4762 * Return: Nothing.
4763 */
4764void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc)
4765{
4766	u16 i, j;
4767	struct mpi3mr_intr_info *intr_info;
4768	struct diag_buffer_desc *diag_buffer;
4769
4770	mpi3mr_free_enclosure_list(mrioc);
4771	mpi3mr_free_ioctl_dma_memory(mrioc);
4772
4773	if (mrioc->sense_buf_pool) {
4774		if (mrioc->sense_buf)
4775			dma_pool_free(mrioc->sense_buf_pool, mrioc->sense_buf,
4776			    mrioc->sense_buf_dma);
4777		dma_pool_destroy(mrioc->sense_buf_pool);
4778		mrioc->sense_buf = NULL;
4779		mrioc->sense_buf_pool = NULL;
4780	}
4781	if (mrioc->sense_buf_q_pool) {
4782		if (mrioc->sense_buf_q)
4783			dma_pool_free(mrioc->sense_buf_q_pool,
4784			    mrioc->sense_buf_q, mrioc->sense_buf_q_dma);
4785		dma_pool_destroy(mrioc->sense_buf_q_pool);
4786		mrioc->sense_buf_q = NULL;
4787		mrioc->sense_buf_q_pool = NULL;
4788	}
4789
4790	if (mrioc->reply_buf_pool) {
4791		if (mrioc->reply_buf)
4792			dma_pool_free(mrioc->reply_buf_pool, mrioc->reply_buf,
4793			    mrioc->reply_buf_dma);
4794		dma_pool_destroy(mrioc->reply_buf_pool);
4795		mrioc->reply_buf = NULL;
4796		mrioc->reply_buf_pool = NULL;
4797	}
4798	if (mrioc->reply_free_q_pool) {
4799		if (mrioc->reply_free_q)
4800			dma_pool_free(mrioc->reply_free_q_pool,
4801			    mrioc->reply_free_q, mrioc->reply_free_q_dma);
4802		dma_pool_destroy(mrioc->reply_free_q_pool);
4803		mrioc->reply_free_q = NULL;
4804		mrioc->reply_free_q_pool = NULL;
4805	}
4806
4807	for (i = 0; i < mrioc->num_op_req_q; i++)
4808		mpi3mr_free_op_req_q_segments(mrioc, i);
4809
4810	for (i = 0; i < mrioc->num_op_reply_q; i++)
4811		mpi3mr_free_op_reply_q_segments(mrioc, i);
4812
4813	for (i = 0; i < mrioc->intr_info_count; i++) {
4814		intr_info = mrioc->intr_info + i;
4815		intr_info->op_reply_q = NULL;
4816	}
4817
4818	kfree(mrioc->req_qinfo);
4819	mrioc->req_qinfo = NULL;
4820	mrioc->num_op_req_q = 0;
4821
4822	kfree(mrioc->op_reply_qinfo);
4823	mrioc->op_reply_qinfo = NULL;
4824	mrioc->num_op_reply_q = 0;
4825
4826	kfree(mrioc->init_cmds.reply);
4827	mrioc->init_cmds.reply = NULL;
4828
4829	kfree(mrioc->bsg_cmds.reply);
4830	mrioc->bsg_cmds.reply = NULL;
4831
4832	kfree(mrioc->host_tm_cmds.reply);
4833	mrioc->host_tm_cmds.reply = NULL;
4834
4835	kfree(mrioc->pel_cmds.reply);
4836	mrioc->pel_cmds.reply = NULL;
4837
4838	kfree(mrioc->pel_abort_cmd.reply);
4839	mrioc->pel_abort_cmd.reply = NULL;
4840
4841	for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
4842		kfree(mrioc->evtack_cmds[i].reply);
4843		mrioc->evtack_cmds[i].reply = NULL;
4844	}
4845
4846	bitmap_free(mrioc->removepend_bitmap);
4847	mrioc->removepend_bitmap = NULL;
4848
4849	bitmap_free(mrioc->devrem_bitmap);
4850	mrioc->devrem_bitmap = NULL;
4851
4852	bitmap_free(mrioc->evtack_cmds_bitmap);
4853	mrioc->evtack_cmds_bitmap = NULL;
4854
4855	bitmap_free(mrioc->chain_bitmap);
4856	mrioc->chain_bitmap = NULL;
4857
4858	kfree(mrioc->transport_cmds.reply);
4859	mrioc->transport_cmds.reply = NULL;
4860
4861	for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
4862		kfree(mrioc->dev_rmhs_cmds[i].reply);
4863		mrioc->dev_rmhs_cmds[i].reply = NULL;
4864	}
4865
4866	if (mrioc->chain_buf_pool) {
4867		for (i = 0; i < mrioc->chain_buf_count; i++) {
4868			if (mrioc->chain_sgl_list[i].addr) {
4869				dma_pool_free(mrioc->chain_buf_pool,
4870				    mrioc->chain_sgl_list[i].addr,
4871				    mrioc->chain_sgl_list[i].dma_addr);
4872				mrioc->chain_sgl_list[i].addr = NULL;
4873			}
4874		}
4875		dma_pool_destroy(mrioc->chain_buf_pool);
4876		mrioc->chain_buf_pool = NULL;
4877	}
4878
4879	kfree(mrioc->chain_sgl_list);
4880	mrioc->chain_sgl_list = NULL;
4881
4882	if (mrioc->admin_reply_base) {
4883		dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz,
4884		    mrioc->admin_reply_base, mrioc->admin_reply_dma);
4885		mrioc->admin_reply_base = NULL;
4886	}
4887	if (mrioc->admin_req_base) {
4888		dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz,
4889		    mrioc->admin_req_base, mrioc->admin_req_dma);
4890		mrioc->admin_req_base = NULL;
4891	}
4892
4893	if (mrioc->pel_seqnum_virt) {
4894		dma_free_coherent(&mrioc->pdev->dev, mrioc->pel_seqnum_sz,
4895		    mrioc->pel_seqnum_virt, mrioc->pel_seqnum_dma);
4896		mrioc->pel_seqnum_virt = NULL;
4897	}
4898
4899	for (i = 0; i < MPI3MR_MAX_NUM_HDB; i++) {
4900		diag_buffer = &mrioc->diag_buffers[i];
4901		if ((i == 0) && mrioc->seg_tb_support) {
4902			if (mrioc->trace_buf_pool) {
4903				for (j = 0; j < mrioc->num_tb_segs; j++) {
4904					if (mrioc->trace_buf[j].segment) {
4905						dma_pool_free(mrioc->trace_buf_pool,
4906						    mrioc->trace_buf[j].segment,
4907						    mrioc->trace_buf[j].segment_dma);
4908						mrioc->trace_buf[j].segment = NULL;
4909					}
4910
4911					mrioc->trace_buf[j].segment = NULL;
4912				}
4913				dma_pool_destroy(mrioc->trace_buf_pool);
4914				mrioc->trace_buf_pool = NULL;
4915			}
4916
4917			kfree(mrioc->trace_buf);
4918			mrioc->trace_buf = NULL;
4919			diag_buffer->size = sizeof(u64) * mrioc->num_tb_segs;
4920		}
4921		if (diag_buffer->addr) {
4922			dma_free_coherent(&mrioc->pdev->dev,
4923			    diag_buffer->size, diag_buffer->addr,
4924			    diag_buffer->dma_addr);
4925			diag_buffer->addr = NULL;
4926			diag_buffer->size = 0;
4927			diag_buffer->type = 0;
4928			diag_buffer->status = 0;
4929		}
4930	}
4931
4932	kfree(mrioc->throttle_groups);
4933	mrioc->throttle_groups = NULL;
4934
4935	kfree(mrioc->logdata_buf);
4936	mrioc->logdata_buf = NULL;
4937
4938}
4939
4940/**
4941 * mpi3mr_issue_ioc_shutdown - shutdown controller
4942 * @mrioc: Adapter instance reference
4943 *
4944 * Send shutodwn notification to the controller and wait for the
4945 * shutdown_timeout for it to be completed.
4946 *
4947 * Return: Nothing.
4948 */
4949static void mpi3mr_issue_ioc_shutdown(struct mpi3mr_ioc *mrioc)
4950{
4951	u32 ioc_config, ioc_status;
4952	u8 retval = 1;
4953	u32 timeout = MPI3MR_DEFAULT_SHUTDOWN_TIME * 10;
4954
4955	ioc_info(mrioc, "Issuing shutdown Notification\n");
4956	if (mrioc->unrecoverable) {
4957		ioc_warn(mrioc,
4958		    "IOC is unrecoverable shutdown is not issued\n");
4959		return;
4960	}
4961	ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4962	if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
4963	    == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS) {
4964		ioc_info(mrioc, "shutdown already in progress\n");
4965		return;
4966	}
4967
4968	ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
4969	ioc_config |= MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL;
4970	ioc_config |= MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN_SEND_REQ;
4971
4972	writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
4973
4974	if (mrioc->facts.shutdown_timeout)
4975		timeout = mrioc->facts.shutdown_timeout * 10;
4976
4977	do {
4978		ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4979		if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
4980		    == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_COMPLETE) {
4981			retval = 0;
4982			break;
4983		}
4984		msleep(100);
4985	} while (--timeout);
4986
4987	ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4988	ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
4989
4990	if (retval) {
4991		if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
4992		    == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS)
4993			ioc_warn(mrioc,
4994			    "shutdown still in progress after timeout\n");
4995	}
4996
4997	ioc_info(mrioc,
4998	    "Base IOC Sts/Config after %s shutdown is (0x%08x)/(0x%08x)\n",
4999	    (!retval) ? "successful" : "failed", ioc_status,
5000	    ioc_config);
5001}
5002
5003/**
5004 * mpi3mr_cleanup_ioc - Cleanup controller
5005 * @mrioc: Adapter instance reference
5006 *
5007 * controller cleanup handler, Message unit reset or soft reset
5008 * and shutdown notification is issued to the controller.
5009 *
5010 * Return: Nothing.
5011 */
5012void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc)
5013{
5014	enum mpi3mr_iocstate ioc_state;
5015
5016	dprint_exit(mrioc, "cleaning up the controller\n");
5017	mpi3mr_ioc_disable_intr(mrioc);
5018
5019	ioc_state = mpi3mr_get_iocstate(mrioc);
5020
5021	if (!mrioc->unrecoverable && !mrioc->reset_in_progress &&
5022	    !mrioc->pci_err_recovery &&
5023	    (ioc_state == MRIOC_STATE_READY)) {
5024		if (mpi3mr_issue_and_process_mur(mrioc,
5025		    MPI3MR_RESET_FROM_CTLR_CLEANUP))
5026			mpi3mr_issue_reset(mrioc,
5027			    MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET,
5028			    MPI3MR_RESET_FROM_MUR_FAILURE);
5029		mpi3mr_issue_ioc_shutdown(mrioc);
5030	}
5031	dprint_exit(mrioc, "controller cleanup completed\n");
5032}
5033
5034/**
5035 * mpi3mr_drv_cmd_comp_reset - Flush a internal driver command
5036 * @mrioc: Adapter instance reference
5037 * @cmdptr: Internal command tracker
5038 *
5039 * Complete an internal driver commands with state indicating it
5040 * is completed due to reset.
5041 *
5042 * Return: Nothing.
5043 */
5044static inline void mpi3mr_drv_cmd_comp_reset(struct mpi3mr_ioc *mrioc,
5045	struct mpi3mr_drv_cmd *cmdptr)
5046{
5047	if (cmdptr->state & MPI3MR_CMD_PENDING) {
5048		cmdptr->state |= MPI3MR_CMD_RESET;
5049		cmdptr->state &= ~MPI3MR_CMD_PENDING;
5050		if (cmdptr->is_waiting) {
5051			complete(&cmdptr->done);
5052			cmdptr->is_waiting = 0;
5053		} else if (cmdptr->callback)
5054			cmdptr->callback(mrioc, cmdptr);
5055	}
5056}
5057
5058/**
5059 * mpi3mr_flush_drv_cmds - Flush internaldriver commands
5060 * @mrioc: Adapter instance reference
5061 *
5062 * Flush all internal driver commands post reset
5063 *
5064 * Return: Nothing.
5065 */
5066void mpi3mr_flush_drv_cmds(struct mpi3mr_ioc *mrioc)
5067{
5068	struct mpi3mr_drv_cmd *cmdptr;
5069	u8 i;
5070
5071	cmdptr = &mrioc->init_cmds;
5072	mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
5073
5074	cmdptr = &mrioc->cfg_cmds;
5075	mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
5076
5077	cmdptr = &mrioc->bsg_cmds;
5078	mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
5079	cmdptr = &mrioc->host_tm_cmds;
5080	mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
5081
5082	for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
5083		cmdptr = &mrioc->dev_rmhs_cmds[i];
5084		mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
5085	}
5086
5087	for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
5088		cmdptr = &mrioc->evtack_cmds[i];
5089		mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
5090	}
5091
5092	cmdptr = &mrioc->pel_cmds;
5093	mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
5094
5095	cmdptr = &mrioc->pel_abort_cmd;
5096	mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
5097
5098	cmdptr = &mrioc->transport_cmds;
5099	mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
5100}
5101
5102/**
5103 * mpi3mr_pel_wait_post - Issue PEL Wait
5104 * @mrioc: Adapter instance reference
5105 * @drv_cmd: Internal command tracker
5106 *
5107 * Issue PEL Wait MPI request through admin queue and return.
5108 *
5109 * Return: Nothing.
5110 */
5111static void mpi3mr_pel_wait_post(struct mpi3mr_ioc *mrioc,
5112	struct mpi3mr_drv_cmd *drv_cmd)
5113{
5114	struct mpi3_pel_req_action_wait pel_wait;
5115
5116	mrioc->pel_abort_requested = false;
5117
5118	memset(&pel_wait, 0, sizeof(pel_wait));
5119	drv_cmd->state = MPI3MR_CMD_PENDING;
5120	drv_cmd->is_waiting = 0;
5121	drv_cmd->callback = mpi3mr_pel_wait_complete;
5122	drv_cmd->ioc_status = 0;
5123	drv_cmd->ioc_loginfo = 0;
5124	pel_wait.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_PEL_WAIT);
5125	pel_wait.function = MPI3_FUNCTION_PERSISTENT_EVENT_LOG;
5126	pel_wait.action = MPI3_PEL_ACTION_WAIT;
5127	pel_wait.starting_sequence_number = cpu_to_le32(mrioc->pel_newest_seqnum);
5128	pel_wait.locale = cpu_to_le16(mrioc->pel_locale);
5129	pel_wait.class = cpu_to_le16(mrioc->pel_class);
5130	pel_wait.wait_time = MPI3_PEL_WAITTIME_INFINITE_WAIT;
5131	dprint_bsg_info(mrioc, "sending pel_wait seqnum(%d), class(%d), locale(0x%08x)\n",
5132	    mrioc->pel_newest_seqnum, mrioc->pel_class, mrioc->pel_locale);
5133
5134	if (mpi3mr_admin_request_post(mrioc, &pel_wait, sizeof(pel_wait), 0)) {
5135		dprint_bsg_err(mrioc,
5136			    "Issuing PELWait: Admin post failed\n");
5137		drv_cmd->state = MPI3MR_CMD_NOTUSED;
5138		drv_cmd->callback = NULL;
5139		drv_cmd->retry_count = 0;
5140		mrioc->pel_enabled = false;
5141	}
5142}
5143
5144/**
5145 * mpi3mr_pel_get_seqnum_post - Issue PEL Get Sequence number
5146 * @mrioc: Adapter instance reference
5147 * @drv_cmd: Internal command tracker
5148 *
5149 * Issue PEL get sequence number MPI request through admin queue
5150 * and return.
5151 *
5152 * Return: 0 on success, non-zero on failure.
5153 */
5154int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc,
5155	struct mpi3mr_drv_cmd *drv_cmd)
5156{
5157	struct mpi3_pel_req_action_get_sequence_numbers pel_getseq_req;
5158	u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
5159	int retval = 0;
5160
5161	memset(&pel_getseq_req, 0, sizeof(pel_getseq_req));
5162	mrioc->pel_cmds.state = MPI3MR_CMD_PENDING;
5163	mrioc->pel_cmds.is_waiting = 0;
5164	mrioc->pel_cmds.ioc_status = 0;
5165	mrioc->pel_cmds.ioc_loginfo = 0;
5166	mrioc->pel_cmds.callback = mpi3mr_pel_get_seqnum_complete;
5167	pel_getseq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_PEL_WAIT);
5168	pel_getseq_req.function = MPI3_FUNCTION_PERSISTENT_EVENT_LOG;
5169	pel_getseq_req.action = MPI3_PEL_ACTION_GET_SEQNUM;
5170	mpi3mr_add_sg_single(&pel_getseq_req.sgl, sgl_flags,
5171	    mrioc->pel_seqnum_sz, mrioc->pel_seqnum_dma);
5172
5173	retval = mpi3mr_admin_request_post(mrioc, &pel_getseq_req,
5174			sizeof(pel_getseq_req), 0);
5175	if (retval) {
5176		if (drv_cmd) {
5177			drv_cmd->state = MPI3MR_CMD_NOTUSED;
5178			drv_cmd->callback = NULL;
5179			drv_cmd->retry_count = 0;
5180		}
5181		mrioc->pel_enabled = false;
5182	}
5183
5184	return retval;
5185}
5186
5187/**
5188 * mpi3mr_pel_wait_complete - PELWait Completion callback
5189 * @mrioc: Adapter instance reference
5190 * @drv_cmd: Internal command tracker
5191 *
5192 * This is a callback handler for the PELWait request and
5193 * firmware completes a PELWait request when it is aborted or a
5194 * new PEL entry is available. This sends AEN to the application
5195 * and if the PELwait completion is not due to PELAbort then
5196 * this will send a request for new PEL Sequence number
5197 *
5198 * Return: Nothing.
5199 */
5200static void mpi3mr_pel_wait_complete(struct mpi3mr_ioc *mrioc,
5201	struct mpi3mr_drv_cmd *drv_cmd)
5202{
5203	struct mpi3_pel_reply *pel_reply = NULL;
5204	u16 ioc_status, pe_log_status;
5205	bool do_retry = false;
5206
5207	if (drv_cmd->state & MPI3MR_CMD_RESET)
5208		goto cleanup_drv_cmd;
5209
5210	ioc_status = drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
5211	if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5212		ioc_err(mrioc, "%s: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
5213			__func__, ioc_status, drv_cmd->ioc_loginfo);
5214		dprint_bsg_err(mrioc,
5215		    "pel_wait: failed with ioc_status(0x%04x), log_info(0x%08x)\n",
5216		    ioc_status, drv_cmd->ioc_loginfo);
5217		do_retry = true;
5218	}
5219
5220	if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID)
5221		pel_reply = (struct mpi3_pel_reply *)drv_cmd->reply;
5222
5223	if (!pel_reply) {
5224		dprint_bsg_err(mrioc,
5225		    "pel_wait: failed due to no reply\n");
5226		goto out_failed;
5227	}
5228
5229	pe_log_status = le16_to_cpu(pel_reply->pe_log_status);
5230	if ((pe_log_status != MPI3_PEL_STATUS_SUCCESS) &&
5231	    (pe_log_status != MPI3_PEL_STATUS_ABORTED)) {
5232		ioc_err(mrioc, "%s: Failed pe_log_status(0x%04x)\n",
5233			__func__, pe_log_status);
5234		dprint_bsg_err(mrioc,
5235		    "pel_wait: failed due to pel_log_status(0x%04x)\n",
5236		    pe_log_status);
5237		do_retry = true;
5238	}
5239
5240	if (do_retry) {
5241		if (drv_cmd->retry_count < MPI3MR_PEL_RETRY_COUNT) {
5242			drv_cmd->retry_count++;
5243			dprint_bsg_err(mrioc, "pel_wait: retrying(%d)\n",
5244			    drv_cmd->retry_count);
5245			mpi3mr_pel_wait_post(mrioc, drv_cmd);
5246			return;
5247		}
5248		dprint_bsg_err(mrioc,
5249		    "pel_wait: failed after all retries(%d)\n",
5250		    drv_cmd->retry_count);
5251		goto out_failed;
5252	}
5253	atomic64_inc(&event_counter);
5254	if (!mrioc->pel_abort_requested) {
5255		mrioc->pel_cmds.retry_count = 0;
5256		mpi3mr_pel_get_seqnum_post(mrioc, &mrioc->pel_cmds);
5257	}
5258
5259	return;
5260out_failed:
5261	mrioc->pel_enabled = false;
5262cleanup_drv_cmd:
5263	drv_cmd->state = MPI3MR_CMD_NOTUSED;
5264	drv_cmd->callback = NULL;
5265	drv_cmd->retry_count = 0;
5266}
5267
5268/**
5269 * mpi3mr_pel_get_seqnum_complete - PELGetSeqNum Completion callback
5270 * @mrioc: Adapter instance reference
5271 * @drv_cmd: Internal command tracker
5272 *
5273 * This is a callback handler for the PEL get sequence number
5274 * request and a new PEL wait request will be issued to the
5275 * firmware from this
5276 *
5277 * Return: Nothing.
5278 */
5279void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc,
5280	struct mpi3mr_drv_cmd *drv_cmd)
5281{
5282	struct mpi3_pel_reply *pel_reply = NULL;
5283	struct mpi3_pel_seq *pel_seqnum_virt;
5284	u16 ioc_status;
5285	bool do_retry = false;
5286
5287	pel_seqnum_virt = (struct mpi3_pel_seq *)mrioc->pel_seqnum_virt;
5288
5289	if (drv_cmd->state & MPI3MR_CMD_RESET)
5290		goto cleanup_drv_cmd;
5291
5292	ioc_status = drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
5293	if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5294		dprint_bsg_err(mrioc,
5295		    "pel_get_seqnum: failed with ioc_status(0x%04x), log_info(0x%08x)\n",
5296		    ioc_status, drv_cmd->ioc_loginfo);
5297		do_retry = true;
5298	}
5299
5300	if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID)
5301		pel_reply = (struct mpi3_pel_reply *)drv_cmd->reply;
5302	if (!pel_reply) {
5303		dprint_bsg_err(mrioc,
5304		    "pel_get_seqnum: failed due to no reply\n");
5305		goto out_failed;
5306	}
5307
5308	if (le16_to_cpu(pel_reply->pe_log_status) != MPI3_PEL_STATUS_SUCCESS) {
5309		dprint_bsg_err(mrioc,
5310		    "pel_get_seqnum: failed due to pel_log_status(0x%04x)\n",
5311		    le16_to_cpu(pel_reply->pe_log_status));
5312		do_retry = true;
5313	}
5314
5315	if (do_retry) {
5316		if (drv_cmd->retry_count < MPI3MR_PEL_RETRY_COUNT) {
5317			drv_cmd->retry_count++;
5318			dprint_bsg_err(mrioc,
5319			    "pel_get_seqnum: retrying(%d)\n",
5320			    drv_cmd->retry_count);
5321			mpi3mr_pel_get_seqnum_post(mrioc, drv_cmd);
5322			return;
5323		}
5324
5325		dprint_bsg_err(mrioc,
5326		    "pel_get_seqnum: failed after all retries(%d)\n",
5327		    drv_cmd->retry_count);
5328		goto out_failed;
5329	}
5330	mrioc->pel_newest_seqnum = le32_to_cpu(pel_seqnum_virt->newest) + 1;
5331	drv_cmd->retry_count = 0;
5332	mpi3mr_pel_wait_post(mrioc, drv_cmd);
5333
5334	return;
5335out_failed:
5336	mrioc->pel_enabled = false;
5337cleanup_drv_cmd:
5338	drv_cmd->state = MPI3MR_CMD_NOTUSED;
5339	drv_cmd->callback = NULL;
5340	drv_cmd->retry_count = 0;
5341}
5342
5343/**
5344 * mpi3mr_check_op_admin_proc -
5345 * @mrioc: Adapter instance reference
5346 *
5347 * Check if any of the operation reply queues
5348 * or the admin reply queue are currently in use.
5349 * If any queue is in use, this function waits for
5350 * a maximum of 10 seconds for them to become available.
5351 *
5352 * Return: 0 on success, non-zero on failure.
5353 */
5354static int mpi3mr_check_op_admin_proc(struct mpi3mr_ioc *mrioc)
5355{
5356
5357	u16 timeout = 10 * 10;
5358	u16 elapsed_time = 0;
5359	bool op_admin_in_use = false;
5360
5361	do {
5362		op_admin_in_use = false;
5363
5364		/* Check admin_reply queue first to exit early */
5365		if (atomic_read(&mrioc->admin_reply_q_in_use) == 1)
5366			op_admin_in_use = true;
5367		else {
5368			/* Check op_reply queues */
5369			int i;
5370
5371			for (i = 0; i < mrioc->num_queues; i++) {
5372				if (atomic_read(&mrioc->op_reply_qinfo[i].in_use) == 1) {
5373					op_admin_in_use = true;
5374					break;
5375				}
5376			}
5377		}
5378
5379		if (!op_admin_in_use)
5380			break;
5381
5382		msleep(100);
5383
5384	} while (++elapsed_time < timeout);
5385
5386	if (op_admin_in_use)
5387		return 1;
5388
5389	return 0;
5390}
5391
5392/**
5393 * mpi3mr_soft_reset_handler - Reset the controller
5394 * @mrioc: Adapter instance reference
5395 * @reset_reason: Reset reason code
5396 * @snapdump: Flag to generate snapdump in firmware or not
5397 *
5398 * This is an handler for recovering controller by issuing soft
5399 * reset are diag fault reset.  This is a blocking function and
5400 * when one reset is executed if any other resets they will be
5401 * blocked. All BSG requests will be blocked during the reset. If
5402 * controller reset is successful then the controller will be
5403 * reinitalized, otherwise the controller will be marked as not
5404 * recoverable
5405 *
5406 * In snapdump bit is set, the controller is issued with diag
5407 * fault reset so that the firmware can create a snap dump and
5408 * post that the firmware will result in F000 fault and the
5409 * driver will issue soft reset to recover from that.
5410 *
5411 * Return: 0 on success, non-zero on failure.
5412 */
5413int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc,
5414	u16 reset_reason, u8 snapdump)
5415{
5416	int retval = 0, i;
5417	unsigned long flags;
5418	u32 host_diagnostic, timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
5419	union mpi3mr_trigger_data trigger_data;
5420
5421	/* Block the reset handler until diag save in progress*/
5422	dprint_reset(mrioc,
5423	    "soft_reset_handler: check and block on diagsave_timeout(%d)\n",
5424	    mrioc->diagsave_timeout);
5425	while (mrioc->diagsave_timeout)
5426		ssleep(1);
5427	/*
5428	 * Block new resets until the currently executing one is finished and
5429	 * return the status of the existing reset for all blocked resets
5430	 */
5431	dprint_reset(mrioc, "soft_reset_handler: acquiring reset_mutex\n");
5432	if (!mutex_trylock(&mrioc->reset_mutex)) {
5433		ioc_info(mrioc,
5434		    "controller reset triggered by %s is blocked due to another reset in progress\n",
5435		    mpi3mr_reset_rc_name(reset_reason));
5436		do {
5437			ssleep(1);
5438		} while (mrioc->reset_in_progress == 1);
5439		ioc_info(mrioc,
5440		    "returning previous reset result(%d) for the reset triggered by %s\n",
5441		    mrioc->prev_reset_result,
5442		    mpi3mr_reset_rc_name(reset_reason));
5443		return mrioc->prev_reset_result;
5444	}
5445	ioc_info(mrioc, "controller reset is triggered by %s\n",
5446	    mpi3mr_reset_rc_name(reset_reason));
5447
5448	mrioc->device_refresh_on = 0;
5449	scsi_block_requests(mrioc->shost);
5450	mrioc->reset_in_progress = 1;
5451	mrioc->stop_bsgs = 1;
5452	mrioc->prev_reset_result = -1;
5453	memset(&trigger_data, 0, sizeof(trigger_data));
5454
5455	if ((!snapdump) && (reset_reason != MPI3MR_RESET_FROM_FAULT_WATCH) &&
5456	    (reset_reason != MPI3MR_RESET_FROM_FIRMWARE) &&
5457	    (reset_reason != MPI3MR_RESET_FROM_CIACTIV_FAULT)) {
5458		mpi3mr_set_trigger_data_in_all_hdb(mrioc,
5459		    MPI3MR_HDB_TRIGGER_TYPE_SOFT_RESET, NULL, 0);
5460		dprint_reset(mrioc,
5461		    "soft_reset_handler: releasing host diagnostic buffers\n");
5462		mpi3mr_release_diag_bufs(mrioc, 0);
5463		for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
5464			mrioc->event_masks[i] = -1;
5465
5466		dprint_reset(mrioc, "soft_reset_handler: masking events\n");
5467		mpi3mr_issue_event_notification(mrioc);
5468	}
5469
5470	mpi3mr_wait_for_host_io(mrioc, MPI3MR_RESET_HOST_IOWAIT_TIMEOUT);
5471
5472	mpi3mr_ioc_disable_intr(mrioc);
5473	mrioc->io_admin_reset_sync = 1;
5474
5475	if (snapdump) {
5476		mpi3mr_set_diagsave(mrioc);
5477		retval = mpi3mr_issue_reset(mrioc,
5478		    MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason);
5479		if (!retval) {
5480			trigger_data.fault = (readl(&mrioc->sysif_regs->fault) &
5481				      MPI3_SYSIF_FAULT_CODE_MASK);
5482			do {
5483				host_diagnostic =
5484				    readl(&mrioc->sysif_regs->host_diagnostic);
5485				if (!(host_diagnostic &
5486				    MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
5487					break;
5488				msleep(100);
5489			} while (--timeout);
5490			mpi3mr_set_trigger_data_in_all_hdb(mrioc,
5491			    MPI3MR_HDB_TRIGGER_TYPE_FAULT, &trigger_data, 0);
5492		}
5493	}
5494
5495	retval = mpi3mr_issue_reset(mrioc,
5496	    MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, reset_reason);
5497	if (retval) {
5498		ioc_err(mrioc, "Failed to issue soft reset to the ioc\n");
5499		goto out;
5500	}
5501
5502	retval = mpi3mr_check_op_admin_proc(mrioc);
5503	if (retval) {
5504		ioc_err(mrioc, "Soft reset failed due to an Admin or I/O queue polling\n"
5505				"thread still processing replies even after a 10 second\n"
5506				"timeout. Marking the controller as unrecoverable!\n");
5507
5508		goto out;
5509	}
5510
5511	if (mrioc->num_io_throttle_group !=
5512	    mrioc->facts.max_io_throttle_group) {
5513		ioc_err(mrioc,
5514		    "max io throttle group doesn't match old(%d), new(%d)\n",
5515		    mrioc->num_io_throttle_group,
5516		    mrioc->facts.max_io_throttle_group);
5517		retval = -EPERM;
5518		goto out;
5519	}
5520
5521	mpi3mr_flush_delayed_cmd_lists(mrioc);
5522	mpi3mr_flush_drv_cmds(mrioc);
5523	bitmap_clear(mrioc->devrem_bitmap, 0, MPI3MR_NUM_DEVRMCMD);
5524	bitmap_clear(mrioc->removepend_bitmap, 0,
5525		     mrioc->dev_handle_bitmap_bits);
5526	bitmap_clear(mrioc->evtack_cmds_bitmap, 0, MPI3MR_NUM_EVTACKCMD);
5527	mpi3mr_flush_host_io(mrioc);
5528	mpi3mr_cleanup_fwevt_list(mrioc);
5529	mpi3mr_invalidate_devhandles(mrioc);
5530	mpi3mr_free_enclosure_list(mrioc);
5531
5532	if (mrioc->prepare_for_reset) {
5533		mrioc->prepare_for_reset = 0;
5534		mrioc->prepare_for_reset_timeout_counter = 0;
5535	}
5536	mpi3mr_memset_buffers(mrioc);
5537	mpi3mr_release_diag_bufs(mrioc, 1);
5538	mrioc->fw_release_trigger_active = false;
5539	mrioc->trace_release_trigger_active = false;
5540	mrioc->snapdump_trigger_active = false;
5541	mpi3mr_set_trigger_data_in_all_hdb(mrioc,
5542	    MPI3MR_HDB_TRIGGER_TYPE_SOFT_RESET, NULL, 0);
5543
5544	dprint_reset(mrioc,
5545	    "soft_reset_handler: reinitializing the controller\n");
5546	retval = mpi3mr_reinit_ioc(mrioc, 0);
5547	if (retval) {
5548		pr_err(IOCNAME "reinit after soft reset failed: reason %d\n",
5549		    mrioc->name, reset_reason);
5550		goto out;
5551	}
5552	ssleep(MPI3MR_RESET_TOPOLOGY_SETTLE_TIME);
5553
5554out:
5555	if (!retval) {
5556		mrioc->diagsave_timeout = 0;
5557		mrioc->reset_in_progress = 0;
5558		scsi_unblock_requests(mrioc->shost);
5559		mrioc->pel_abort_requested = 0;
5560		if (mrioc->pel_enabled) {
5561			mrioc->pel_cmds.retry_count = 0;
5562			mpi3mr_pel_wait_post(mrioc, &mrioc->pel_cmds);
5563		}
5564
5565		mrioc->device_refresh_on = 0;
5566
5567		mrioc->ts_update_counter = 0;
5568		spin_lock_irqsave(&mrioc->watchdog_lock, flags);
5569		if (mrioc->watchdog_work_q)
5570			queue_delayed_work(mrioc->watchdog_work_q,
5571			    &mrioc->watchdog_work,
5572			    msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
5573		spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
5574		mrioc->stop_bsgs = 0;
5575		if (mrioc->pel_enabled)
5576			atomic64_inc(&event_counter);
5577	} else {
5578		mpi3mr_issue_reset(mrioc,
5579		    MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason);
5580		mrioc->device_refresh_on = 0;
5581		mrioc->unrecoverable = 1;
5582		mrioc->reset_in_progress = 0;
5583		scsi_unblock_requests(mrioc->shost);
5584		mrioc->stop_bsgs = 0;
5585		retval = -1;
5586		mpi3mr_flush_cmds_for_unrecovered_controller(mrioc);
5587	}
5588	mrioc->prev_reset_result = retval;
5589	mutex_unlock(&mrioc->reset_mutex);
5590	ioc_info(mrioc, "controller reset is %s\n",
5591	    ((retval == 0) ? "successful" : "failed"));
5592	return retval;
5593}
5594
5595/**
5596 * mpi3mr_post_cfg_req - Issue config requests and wait
5597 * @mrioc: Adapter instance reference
5598 * @cfg_req: Configuration request
5599 * @timeout: Timeout in seconds
5600 * @ioc_status: Pointer to return ioc status
5601 *
5602 * A generic function for posting MPI3 configuration request to
5603 * the firmware. This blocks for the completion of request for
5604 * timeout seconds and if the request times out this function
5605 * faults the controller with proper reason code.
5606 *
5607 * On successful completion of the request this function returns
5608 * appropriate ioc status from the firmware back to the caller.
5609 *
5610 * Return: 0 on success, non-zero on failure.
5611 */
5612static int mpi3mr_post_cfg_req(struct mpi3mr_ioc *mrioc,
5613	struct mpi3_config_request *cfg_req, int timeout, u16 *ioc_status)
5614{
5615	int retval = 0;
5616
5617	mutex_lock(&mrioc->cfg_cmds.mutex);
5618	if (mrioc->cfg_cmds.state & MPI3MR_CMD_PENDING) {
5619		retval = -1;
5620		ioc_err(mrioc, "sending config request failed due to command in use\n");
5621		mutex_unlock(&mrioc->cfg_cmds.mutex);
5622		goto out;
5623	}
5624	mrioc->cfg_cmds.state = MPI3MR_CMD_PENDING;
5625	mrioc->cfg_cmds.is_waiting = 1;
5626	mrioc->cfg_cmds.callback = NULL;
5627	mrioc->cfg_cmds.ioc_status = 0;
5628	mrioc->cfg_cmds.ioc_loginfo = 0;
5629
5630	cfg_req->host_tag = cpu_to_le16(MPI3MR_HOSTTAG_CFG_CMDS);
5631	cfg_req->function = MPI3_FUNCTION_CONFIG;
5632
5633	init_completion(&mrioc->cfg_cmds.done);
5634	dprint_cfg_info(mrioc, "posting config request\n");
5635	if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5636		dprint_dump(cfg_req, sizeof(struct mpi3_config_request),
5637		    "mpi3_cfg_req");
5638	retval = mpi3mr_admin_request_post(mrioc, cfg_req, sizeof(*cfg_req), 1);
5639	if (retval) {
5640		ioc_err(mrioc, "posting config request failed\n");
5641		goto out_unlock;
5642	}
5643	wait_for_completion_timeout(&mrioc->cfg_cmds.done, (timeout * HZ));
5644	if (!(mrioc->cfg_cmds.state & MPI3MR_CMD_COMPLETE)) {
5645		mpi3mr_check_rh_fault_ioc(mrioc,
5646		    MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT);
5647		ioc_err(mrioc, "config request timed out\n");
5648		retval = -1;
5649		goto out_unlock;
5650	}
5651	*ioc_status = mrioc->cfg_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
5652	if ((*ioc_status) != MPI3_IOCSTATUS_SUCCESS)
5653		dprint_cfg_err(mrioc,
5654		    "cfg_page request returned with ioc_status(0x%04x), log_info(0x%08x)\n",
5655		    *ioc_status, mrioc->cfg_cmds.ioc_loginfo);
5656
5657out_unlock:
5658	mrioc->cfg_cmds.state = MPI3MR_CMD_NOTUSED;
5659	mutex_unlock(&mrioc->cfg_cmds.mutex);
5660
5661out:
5662	return retval;
5663}
5664
5665/**
5666 * mpi3mr_process_cfg_req - config page request processor
5667 * @mrioc: Adapter instance reference
5668 * @cfg_req: Configuration request
5669 * @cfg_hdr: Configuration page header
5670 * @timeout: Timeout in seconds
5671 * @ioc_status: Pointer to return ioc status
5672 * @cfg_buf: Memory pointer to copy config page or header
5673 * @cfg_buf_sz: Size of the memory to get config page or header
5674 *
5675 * This is handler for config page read, write and config page
5676 * header read operations.
5677 *
5678 * This function expects the cfg_req to be populated with page
5679 * type, page number, action for the header read and with page
5680 * address for all other operations.
5681 *
5682 * The cfg_hdr can be passed as null for reading required header
5683 * details for read/write pages the cfg_hdr should point valid
5684 * configuration page header.
5685 *
5686 * This allocates dmaable memory based on the size of the config
5687 * buffer and set the SGE of the cfg_req.
5688 *
5689 * For write actions, the config page data has to be passed in
5690 * the cfg_buf and size of the data has to be mentioned in the
5691 * cfg_buf_sz.
5692 *
5693 * For read/header actions, on successful completion of the
5694 * request with successful ioc_status the data will be copied
5695 * into the cfg_buf limited to a minimum of actual page size and
5696 * cfg_buf_sz
5697 *
5698 *
5699 * Return: 0 on success, non-zero on failure.
5700 */
5701static int mpi3mr_process_cfg_req(struct mpi3mr_ioc *mrioc,
5702	struct mpi3_config_request *cfg_req,
5703	struct mpi3_config_page_header *cfg_hdr, int timeout, u16 *ioc_status,
5704	void *cfg_buf, u32 cfg_buf_sz)
5705{
5706	struct dma_memory_desc mem_desc;
5707	int retval = -1;
5708	u8 invalid_action = 0;
5709	u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
5710
5711	memset(&mem_desc, 0, sizeof(struct dma_memory_desc));
5712
5713	if (cfg_req->action == MPI3_CONFIG_ACTION_PAGE_HEADER)
5714		mem_desc.size = sizeof(struct mpi3_config_page_header);
5715	else {
5716		if (!cfg_hdr) {
5717			ioc_err(mrioc, "null config header passed for config action(%d), page_type(0x%02x), page_num(%d)\n",
5718			    cfg_req->action, cfg_req->page_type,
5719			    cfg_req->page_number);
5720			goto out;
5721		}
5722		switch (cfg_hdr->page_attribute & MPI3_CONFIG_PAGEATTR_MASK) {
5723		case MPI3_CONFIG_PAGEATTR_READ_ONLY:
5724			if (cfg_req->action
5725			    != MPI3_CONFIG_ACTION_READ_CURRENT)
5726				invalid_action = 1;
5727			break;
5728		case MPI3_CONFIG_PAGEATTR_CHANGEABLE:
5729			if ((cfg_req->action ==
5730			     MPI3_CONFIG_ACTION_READ_PERSISTENT) ||
5731			    (cfg_req->action ==
5732			     MPI3_CONFIG_ACTION_WRITE_PERSISTENT))
5733				invalid_action = 1;
5734			break;
5735		case MPI3_CONFIG_PAGEATTR_PERSISTENT:
5736		default:
5737			break;
5738		}
5739		if (invalid_action) {
5740			ioc_err(mrioc,
5741			    "config action(%d) is not allowed for page_type(0x%02x), page_num(%d) with page_attribute(0x%02x)\n",
5742			    cfg_req->action, cfg_req->page_type,
5743			    cfg_req->page_number, cfg_hdr->page_attribute);
5744			goto out;
5745		}
5746		mem_desc.size = le16_to_cpu(cfg_hdr->page_length) * 4;
5747		cfg_req->page_length = cfg_hdr->page_length;
5748		cfg_req->page_version = cfg_hdr->page_version;
5749	}
5750
5751	mem_desc.addr = dma_alloc_coherent(&mrioc->pdev->dev,
5752		mem_desc.size, &mem_desc.dma_addr, GFP_KERNEL);
5753
5754	if (!mem_desc.addr)
5755		return retval;
5756
5757	mpi3mr_add_sg_single(&cfg_req->sgl, sgl_flags, mem_desc.size,
5758	    mem_desc.dma_addr);
5759
5760	if ((cfg_req->action == MPI3_CONFIG_ACTION_WRITE_PERSISTENT) ||
5761	    (cfg_req->action == MPI3_CONFIG_ACTION_WRITE_CURRENT)) {
5762		memcpy(mem_desc.addr, cfg_buf, min_t(u16, mem_desc.size,
5763		    cfg_buf_sz));
5764		dprint_cfg_info(mrioc, "config buffer to be written\n");
5765		if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5766			dprint_dump(mem_desc.addr, mem_desc.size, "cfg_buf");
5767	}
5768
5769	if (mpi3mr_post_cfg_req(mrioc, cfg_req, timeout, ioc_status))
5770		goto out;
5771
5772	retval = 0;
5773	if ((*ioc_status == MPI3_IOCSTATUS_SUCCESS) &&
5774	    (cfg_req->action != MPI3_CONFIG_ACTION_WRITE_PERSISTENT) &&
5775	    (cfg_req->action != MPI3_CONFIG_ACTION_WRITE_CURRENT)) {
5776		memcpy(cfg_buf, mem_desc.addr, min_t(u16, mem_desc.size,
5777		    cfg_buf_sz));
5778		dprint_cfg_info(mrioc, "config buffer read\n");
5779		if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5780			dprint_dump(mem_desc.addr, mem_desc.size, "cfg_buf");
5781	}
5782
5783out:
5784	if (mem_desc.addr) {
5785		dma_free_coherent(&mrioc->pdev->dev, mem_desc.size,
5786			mem_desc.addr, mem_desc.dma_addr);
5787		mem_desc.addr = NULL;
5788	}
5789
5790	return retval;
5791}
5792
5793/**
5794 * mpi3mr_cfg_get_dev_pg0 - Read current device page0
5795 * @mrioc: Adapter instance reference
5796 * @ioc_status: Pointer to return ioc status
5797 * @dev_pg0: Pointer to return device page 0
5798 * @pg_sz: Size of the memory allocated to the page pointer
5799 * @form: The form to be used for addressing the page
5800 * @form_spec: Form specific information like device handle
5801 *
5802 * This is handler for config page read for a specific device
5803 * page0. The ioc_status has the controller returned ioc_status.
5804 * This routine doesn't check ioc_status to decide whether the
5805 * page read is success or not and it is the callers
5806 * responsibility.
5807 *
5808 * Return: 0 on success, non-zero on failure.
5809 */
5810int mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5811	struct mpi3_device_page0 *dev_pg0, u16 pg_sz, u32 form, u32 form_spec)
5812{
5813	struct mpi3_config_page_header cfg_hdr;
5814	struct mpi3_config_request cfg_req;
5815	u32 page_address;
5816
5817	memset(dev_pg0, 0, pg_sz);
5818	memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5819	memset(&cfg_req, 0, sizeof(cfg_req));
5820
5821	cfg_req.function = MPI3_FUNCTION_CONFIG;
5822	cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5823	cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DEVICE;
5824	cfg_req.page_number = 0;
5825	cfg_req.page_address = 0;
5826
5827	if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5828	    MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5829		ioc_err(mrioc, "device page0 header read failed\n");
5830		goto out_failed;
5831	}
5832	if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5833		ioc_err(mrioc, "device page0 header read failed with ioc_status(0x%04x)\n",
5834		    *ioc_status);
5835		goto out_failed;
5836	}
5837	cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5838	page_address = ((form & MPI3_DEVICE_PGAD_FORM_MASK) |
5839	    (form_spec & MPI3_DEVICE_PGAD_HANDLE_MASK));
5840	cfg_req.page_address = cpu_to_le32(page_address);
5841	if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5842	    MPI3MR_INTADMCMD_TIMEOUT, ioc_status, dev_pg0, pg_sz)) {
5843		ioc_err(mrioc, "device page0 read failed\n");
5844		goto out_failed;
5845	}
5846	return 0;
5847out_failed:
5848	return -1;
5849}
5850
5851
5852/**
5853 * mpi3mr_cfg_get_sas_phy_pg0 - Read current SAS Phy page0
5854 * @mrioc: Adapter instance reference
5855 * @ioc_status: Pointer to return ioc status
5856 * @phy_pg0: Pointer to return SAS Phy page 0
5857 * @pg_sz: Size of the memory allocated to the page pointer
5858 * @form: The form to be used for addressing the page
5859 * @form_spec: Form specific information like phy number
5860 *
5861 * This is handler for config page read for a specific SAS Phy
5862 * page0. The ioc_status has the controller returned ioc_status.
5863 * This routine doesn't check ioc_status to decide whether the
5864 * page read is success or not and it is the callers
5865 * responsibility.
5866 *
5867 * Return: 0 on success, non-zero on failure.
5868 */
5869int mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5870	struct mpi3_sas_phy_page0 *phy_pg0, u16 pg_sz, u32 form,
5871	u32 form_spec)
5872{
5873	struct mpi3_config_page_header cfg_hdr;
5874	struct mpi3_config_request cfg_req;
5875	u32 page_address;
5876
5877	memset(phy_pg0, 0, pg_sz);
5878	memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5879	memset(&cfg_req, 0, sizeof(cfg_req));
5880
5881	cfg_req.function = MPI3_FUNCTION_CONFIG;
5882	cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5883	cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_PHY;
5884	cfg_req.page_number = 0;
5885	cfg_req.page_address = 0;
5886
5887	if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5888	    MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5889		ioc_err(mrioc, "sas phy page0 header read failed\n");
5890		goto out_failed;
5891	}
5892	if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5893		ioc_err(mrioc, "sas phy page0 header read failed with ioc_status(0x%04x)\n",
5894		    *ioc_status);
5895		goto out_failed;
5896	}
5897	cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5898	page_address = ((form & MPI3_SAS_PHY_PGAD_FORM_MASK) |
5899	    (form_spec & MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK));
5900	cfg_req.page_address = cpu_to_le32(page_address);
5901	if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5902	    MPI3MR_INTADMCMD_TIMEOUT, ioc_status, phy_pg0, pg_sz)) {
5903		ioc_err(mrioc, "sas phy page0 read failed\n");
5904		goto out_failed;
5905	}
5906	return 0;
5907out_failed:
5908	return -1;
5909}
5910
5911/**
5912 * mpi3mr_cfg_get_sas_phy_pg1 - Read current SAS Phy page1
5913 * @mrioc: Adapter instance reference
5914 * @ioc_status: Pointer to return ioc status
5915 * @phy_pg1: Pointer to return SAS Phy page 1
5916 * @pg_sz: Size of the memory allocated to the page pointer
5917 * @form: The form to be used for addressing the page
5918 * @form_spec: Form specific information like phy number
5919 *
5920 * This is handler for config page read for a specific SAS Phy
5921 * page1. The ioc_status has the controller returned ioc_status.
5922 * This routine doesn't check ioc_status to decide whether the
5923 * page read is success or not and it is the callers
5924 * responsibility.
5925 *
5926 * Return: 0 on success, non-zero on failure.
5927 */
5928int mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5929	struct mpi3_sas_phy_page1 *phy_pg1, u16 pg_sz, u32 form,
5930	u32 form_spec)
5931{
5932	struct mpi3_config_page_header cfg_hdr;
5933	struct mpi3_config_request cfg_req;
5934	u32 page_address;
5935
5936	memset(phy_pg1, 0, pg_sz);
5937	memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5938	memset(&cfg_req, 0, sizeof(cfg_req));
5939
5940	cfg_req.function = MPI3_FUNCTION_CONFIG;
5941	cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5942	cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_PHY;
5943	cfg_req.page_number = 1;
5944	cfg_req.page_address = 0;
5945
5946	if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5947	    MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5948		ioc_err(mrioc, "sas phy page1 header read failed\n");
5949		goto out_failed;
5950	}
5951	if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5952		ioc_err(mrioc, "sas phy page1 header read failed with ioc_status(0x%04x)\n",
5953		    *ioc_status);
5954		goto out_failed;
5955	}
5956	cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5957	page_address = ((form & MPI3_SAS_PHY_PGAD_FORM_MASK) |
5958	    (form_spec & MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK));
5959	cfg_req.page_address = cpu_to_le32(page_address);
5960	if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5961	    MPI3MR_INTADMCMD_TIMEOUT, ioc_status, phy_pg1, pg_sz)) {
5962		ioc_err(mrioc, "sas phy page1 read failed\n");
5963		goto out_failed;
5964	}
5965	return 0;
5966out_failed:
5967	return -1;
5968}
5969
5970
5971/**
5972 * mpi3mr_cfg_get_sas_exp_pg0 - Read current SAS Expander page0
5973 * @mrioc: Adapter instance reference
5974 * @ioc_status: Pointer to return ioc status
5975 * @exp_pg0: Pointer to return SAS Expander page 0
5976 * @pg_sz: Size of the memory allocated to the page pointer
5977 * @form: The form to be used for addressing the page
5978 * @form_spec: Form specific information like device handle
5979 *
5980 * This is handler for config page read for a specific SAS
5981 * Expander page0. The ioc_status has the controller returned
5982 * ioc_status. This routine doesn't check ioc_status to decide
5983 * whether the page read is success or not and it is the callers
5984 * responsibility.
5985 *
5986 * Return: 0 on success, non-zero on failure.
5987 */
5988int mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5989	struct mpi3_sas_expander_page0 *exp_pg0, u16 pg_sz, u32 form,
5990	u32 form_spec)
5991{
5992	struct mpi3_config_page_header cfg_hdr;
5993	struct mpi3_config_request cfg_req;
5994	u32 page_address;
5995
5996	memset(exp_pg0, 0, pg_sz);
5997	memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5998	memset(&cfg_req, 0, sizeof(cfg_req));
5999
6000	cfg_req.function = MPI3_FUNCTION_CONFIG;
6001	cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
6002	cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_EXPANDER;
6003	cfg_req.page_number = 0;
6004	cfg_req.page_address = 0;
6005
6006	if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
6007	    MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
6008		ioc_err(mrioc, "expander page0 header read failed\n");
6009		goto out_failed;
6010	}
6011	if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6012		ioc_err(mrioc, "expander page0 header read failed with ioc_status(0x%04x)\n",
6013		    *ioc_status);
6014		goto out_failed;
6015	}
6016	cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
6017	page_address = ((form & MPI3_SAS_EXPAND_PGAD_FORM_MASK) |
6018	    (form_spec & (MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK |
6019	    MPI3_SAS_EXPAND_PGAD_HANDLE_MASK)));
6020	cfg_req.page_address = cpu_to_le32(page_address);
6021	if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6022	    MPI3MR_INTADMCMD_TIMEOUT, ioc_status, exp_pg0, pg_sz)) {
6023		ioc_err(mrioc, "expander page0 read failed\n");
6024		goto out_failed;
6025	}
6026	return 0;
6027out_failed:
6028	return -1;
6029}
6030
6031/**
6032 * mpi3mr_cfg_get_sas_exp_pg1 - Read current SAS Expander page1
6033 * @mrioc: Adapter instance reference
6034 * @ioc_status: Pointer to return ioc status
6035 * @exp_pg1: Pointer to return SAS Expander page 1
6036 * @pg_sz: Size of the memory allocated to the page pointer
6037 * @form: The form to be used for addressing the page
6038 * @form_spec: Form specific information like phy number
6039 *
6040 * This is handler for config page read for a specific SAS
6041 * Expander page1. The ioc_status has the controller returned
6042 * ioc_status. This routine doesn't check ioc_status to decide
6043 * whether the page read is success or not and it is the callers
6044 * responsibility.
6045 *
6046 * Return: 0 on success, non-zero on failure.
6047 */
6048int mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
6049	struct mpi3_sas_expander_page1 *exp_pg1, u16 pg_sz, u32 form,
6050	u32 form_spec)
6051{
6052	struct mpi3_config_page_header cfg_hdr;
6053	struct mpi3_config_request cfg_req;
6054	u32 page_address;
6055
6056	memset(exp_pg1, 0, pg_sz);
6057	memset(&cfg_hdr, 0, sizeof(cfg_hdr));
6058	memset(&cfg_req, 0, sizeof(cfg_req));
6059
6060	cfg_req.function = MPI3_FUNCTION_CONFIG;
6061	cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
6062	cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_EXPANDER;
6063	cfg_req.page_number = 1;
6064	cfg_req.page_address = 0;
6065
6066	if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
6067	    MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
6068		ioc_err(mrioc, "expander page1 header read failed\n");
6069		goto out_failed;
6070	}
6071	if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6072		ioc_err(mrioc, "expander page1 header read failed with ioc_status(0x%04x)\n",
6073		    *ioc_status);
6074		goto out_failed;
6075	}
6076	cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
6077	page_address = ((form & MPI3_SAS_EXPAND_PGAD_FORM_MASK) |
6078	    (form_spec & (MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK |
6079	    MPI3_SAS_EXPAND_PGAD_HANDLE_MASK)));
6080	cfg_req.page_address = cpu_to_le32(page_address);
6081	if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6082	    MPI3MR_INTADMCMD_TIMEOUT, ioc_status, exp_pg1, pg_sz)) {
6083		ioc_err(mrioc, "expander page1 read failed\n");
6084		goto out_failed;
6085	}
6086	return 0;
6087out_failed:
6088	return -1;
6089}
6090
6091/**
6092 * mpi3mr_cfg_get_enclosure_pg0 - Read current Enclosure page0
6093 * @mrioc: Adapter instance reference
6094 * @ioc_status: Pointer to return ioc status
6095 * @encl_pg0: Pointer to return Enclosure page 0
6096 * @pg_sz: Size of the memory allocated to the page pointer
6097 * @form: The form to be used for addressing the page
6098 * @form_spec: Form specific information like device handle
6099 *
6100 * This is handler for config page read for a specific Enclosure
6101 * page0. The ioc_status has the controller returned ioc_status.
6102 * This routine doesn't check ioc_status to decide whether the
6103 * page read is success or not and it is the callers
6104 * responsibility.
6105 *
6106 * Return: 0 on success, non-zero on failure.
6107 */
6108int mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
6109	struct mpi3_enclosure_page0 *encl_pg0, u16 pg_sz, u32 form,
6110	u32 form_spec)
6111{
6112	struct mpi3_config_page_header cfg_hdr;
6113	struct mpi3_config_request cfg_req;
6114	u32 page_address;
6115
6116	memset(encl_pg0, 0, pg_sz);
6117	memset(&cfg_hdr, 0, sizeof(cfg_hdr));
6118	memset(&cfg_req, 0, sizeof(cfg_req));
6119
6120	cfg_req.function = MPI3_FUNCTION_CONFIG;
6121	cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
6122	cfg_req.page_type = MPI3_CONFIG_PAGETYPE_ENCLOSURE;
6123	cfg_req.page_number = 0;
6124	cfg_req.page_address = 0;
6125
6126	if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
6127	    MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
6128		ioc_err(mrioc, "enclosure page0 header read failed\n");
6129		goto out_failed;
6130	}
6131	if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6132		ioc_err(mrioc, "enclosure page0 header read failed with ioc_status(0x%04x)\n",
6133		    *ioc_status);
6134		goto out_failed;
6135	}
6136	cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
6137	page_address = ((form & MPI3_ENCLOS_PGAD_FORM_MASK) |
6138	    (form_spec & MPI3_ENCLOS_PGAD_HANDLE_MASK));
6139	cfg_req.page_address = cpu_to_le32(page_address);
6140	if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6141	    MPI3MR_INTADMCMD_TIMEOUT, ioc_status, encl_pg0, pg_sz)) {
6142		ioc_err(mrioc, "enclosure page0 read failed\n");
6143		goto out_failed;
6144	}
6145	return 0;
6146out_failed:
6147	return -1;
6148}
6149
6150
6151/**
6152 * mpi3mr_cfg_get_sas_io_unit_pg0 - Read current SASIOUnit page0
6153 * @mrioc: Adapter instance reference
6154 * @sas_io_unit_pg0: Pointer to return SAS IO Unit page 0
6155 * @pg_sz: Size of the memory allocated to the page pointer
6156 *
6157 * This is handler for config page read for the SAS IO Unit
6158 * page0. This routine checks ioc_status to decide whether the
6159 * page read is success or not.
6160 *
6161 * Return: 0 on success, non-zero on failure.
6162 */
6163int mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc *mrioc,
6164	struct mpi3_sas_io_unit_page0 *sas_io_unit_pg0, u16 pg_sz)
6165{
6166	struct mpi3_config_page_header cfg_hdr;
6167	struct mpi3_config_request cfg_req;
6168	u16 ioc_status = 0;
6169
6170	memset(sas_io_unit_pg0, 0, pg_sz);
6171	memset(&cfg_hdr, 0, sizeof(cfg_hdr));
6172	memset(&cfg_req, 0, sizeof(cfg_req));
6173
6174	cfg_req.function = MPI3_FUNCTION_CONFIG;
6175	cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
6176	cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
6177	cfg_req.page_number = 0;
6178	cfg_req.page_address = 0;
6179
6180	if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
6181	    MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
6182		ioc_err(mrioc, "sas io unit page0 header read failed\n");
6183		goto out_failed;
6184	}
6185	if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6186		ioc_err(mrioc, "sas io unit page0 header read failed with ioc_status(0x%04x)\n",
6187		    ioc_status);
6188		goto out_failed;
6189	}
6190	cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
6191
6192	if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6193	    MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg0, pg_sz)) {
6194		ioc_err(mrioc, "sas io unit page0 read failed\n");
6195		goto out_failed;
6196	}
6197	if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6198		ioc_err(mrioc, "sas io unit page0 read failed with ioc_status(0x%04x)\n",
6199		    ioc_status);
6200		goto out_failed;
6201	}
6202	return 0;
6203out_failed:
6204	return -1;
6205}
6206
6207/**
6208 * mpi3mr_cfg_get_sas_io_unit_pg1 - Read current SASIOUnit page1
6209 * @mrioc: Adapter instance reference
6210 * @sas_io_unit_pg1: Pointer to return SAS IO Unit page 1
6211 * @pg_sz: Size of the memory allocated to the page pointer
6212 *
6213 * This is handler for config page read for the SAS IO Unit
6214 * page1. This routine checks ioc_status to decide whether the
6215 * page read is success or not.
6216 *
6217 * Return: 0 on success, non-zero on failure.
6218 */
6219int mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
6220	struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz)
6221{
6222	struct mpi3_config_page_header cfg_hdr;
6223	struct mpi3_config_request cfg_req;
6224	u16 ioc_status = 0;
6225
6226	memset(sas_io_unit_pg1, 0, pg_sz);
6227	memset(&cfg_hdr, 0, sizeof(cfg_hdr));
6228	memset(&cfg_req, 0, sizeof(cfg_req));
6229
6230	cfg_req.function = MPI3_FUNCTION_CONFIG;
6231	cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
6232	cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
6233	cfg_req.page_number = 1;
6234	cfg_req.page_address = 0;
6235
6236	if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
6237	    MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
6238		ioc_err(mrioc, "sas io unit page1 header read failed\n");
6239		goto out_failed;
6240	}
6241	if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6242		ioc_err(mrioc, "sas io unit page1 header read failed with ioc_status(0x%04x)\n",
6243		    ioc_status);
6244		goto out_failed;
6245	}
6246	cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
6247
6248	if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6249	    MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
6250		ioc_err(mrioc, "sas io unit page1 read failed\n");
6251		goto out_failed;
6252	}
6253	if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6254		ioc_err(mrioc, "sas io unit page1 read failed with ioc_status(0x%04x)\n",
6255		    ioc_status);
6256		goto out_failed;
6257	}
6258	return 0;
6259out_failed:
6260	return -1;
6261}
6262
6263/**
6264 * mpi3mr_cfg_set_sas_io_unit_pg1 - Write SASIOUnit page1
6265 * @mrioc: Adapter instance reference
6266 * @sas_io_unit_pg1: Pointer to the SAS IO Unit page 1 to write
6267 * @pg_sz: Size of the memory allocated to the page pointer
6268 *
6269 * This is handler for config page write for the SAS IO Unit
6270 * page1. This routine checks ioc_status to decide whether the
6271 * page read is success or not. This will modify both current
6272 * and persistent page.
6273 *
6274 * Return: 0 on success, non-zero on failure.
6275 */
6276int mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
6277	struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz)
6278{
6279	struct mpi3_config_page_header cfg_hdr;
6280	struct mpi3_config_request cfg_req;
6281	u16 ioc_status = 0;
6282
6283	memset(&cfg_hdr, 0, sizeof(cfg_hdr));
6284	memset(&cfg_req, 0, sizeof(cfg_req));
6285
6286	cfg_req.function = MPI3_FUNCTION_CONFIG;
6287	cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
6288	cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
6289	cfg_req.page_number = 1;
6290	cfg_req.page_address = 0;
6291
6292	if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
6293	    MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
6294		ioc_err(mrioc, "sas io unit page1 header read failed\n");
6295		goto out_failed;
6296	}
6297	if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6298		ioc_err(mrioc, "sas io unit page1 header read failed with ioc_status(0x%04x)\n",
6299		    ioc_status);
6300		goto out_failed;
6301	}
6302	cfg_req.action = MPI3_CONFIG_ACTION_WRITE_CURRENT;
6303
6304	if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6305	    MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
6306		ioc_err(mrioc, "sas io unit page1 write current failed\n");
6307		goto out_failed;
6308	}
6309	if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6310		ioc_err(mrioc, "sas io unit page1 write current failed with ioc_status(0x%04x)\n",
6311		    ioc_status);
6312		goto out_failed;
6313	}
6314
6315	cfg_req.action = MPI3_CONFIG_ACTION_WRITE_PERSISTENT;
6316
6317	if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6318	    MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
6319		ioc_err(mrioc, "sas io unit page1 write persistent failed\n");
6320		goto out_failed;
6321	}
6322	if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6323		ioc_err(mrioc, "sas io unit page1 write persistent failed with ioc_status(0x%04x)\n",
6324		    ioc_status);
6325		goto out_failed;
6326	}
6327	return 0;
6328out_failed:
6329	return -1;
6330}
6331
6332/**
6333 * mpi3mr_cfg_get_driver_pg1 - Read current Driver page1
6334 * @mrioc: Adapter instance reference
6335 * @driver_pg1: Pointer to return Driver page 1
6336 * @pg_sz: Size of the memory allocated to the page pointer
6337 *
6338 * This is handler for config page read for the Driver page1.
6339 * This routine checks ioc_status to decide whether the page
6340 * read is success or not.
6341 *
6342 * Return: 0 on success, non-zero on failure.
6343 */
6344int mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc *mrioc,
6345	struct mpi3_driver_page1 *driver_pg1, u16 pg_sz)
6346{
6347	struct mpi3_config_page_header cfg_hdr;
6348	struct mpi3_config_request cfg_req;
6349	u16 ioc_status = 0;
6350
6351	memset(driver_pg1, 0, pg_sz);
6352	memset(&cfg_hdr, 0, sizeof(cfg_hdr));
6353	memset(&cfg_req, 0, sizeof(cfg_req));
6354
6355	cfg_req.function = MPI3_FUNCTION_CONFIG;
6356	cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
6357	cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DRIVER;
6358	cfg_req.page_number = 1;
6359	cfg_req.page_address = 0;
6360
6361	if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
6362	    MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
6363		ioc_err(mrioc, "driver page1 header read failed\n");
6364		goto out_failed;
6365	}
6366	if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6367		ioc_err(mrioc, "driver page1 header read failed with ioc_status(0x%04x)\n",
6368		    ioc_status);
6369		goto out_failed;
6370	}
6371	cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
6372
6373	if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6374	    MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, driver_pg1, pg_sz)) {
6375		ioc_err(mrioc, "driver page1 read failed\n");
6376		goto out_failed;
6377	}
6378	if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6379		ioc_err(mrioc, "driver page1 read failed with ioc_status(0x%04x)\n",
6380		    ioc_status);
6381		goto out_failed;
6382	}
6383	return 0;
6384out_failed:
6385	return -1;
6386}
6387
6388/**
6389 * mpi3mr_cfg_get_driver_pg2 - Read current driver page2
6390 * @mrioc: Adapter instance reference
6391 * @driver_pg2: Pointer to return driver page 2
6392 * @pg_sz: Size of the memory allocated to the page pointer
6393 * @page_action: Page action
6394 *
6395 * This is handler for config page read for the driver page2.
6396 * This routine checks ioc_status to decide whether the page
6397 * read is success or not.
6398 *
6399 * Return: 0 on success, non-zero on failure.
6400 */
6401int mpi3mr_cfg_get_driver_pg2(struct mpi3mr_ioc *mrioc,
6402	struct mpi3_driver_page2 *driver_pg2, u16 pg_sz, u8 page_action)
6403{
6404	struct mpi3_config_page_header cfg_hdr;
6405	struct mpi3_config_request cfg_req;
6406	u16 ioc_status = 0;
6407
6408	memset(driver_pg2, 0, pg_sz);
6409	memset(&cfg_hdr, 0, sizeof(cfg_hdr));
6410	memset(&cfg_req, 0, sizeof(cfg_req));
6411
6412	cfg_req.function = MPI3_FUNCTION_CONFIG;
6413	cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
6414	cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DRIVER;
6415	cfg_req.page_number = 2;
6416	cfg_req.page_address = 0;
6417	cfg_req.page_version = MPI3_DRIVER2_PAGEVERSION;
6418
6419	if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
6420	    MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
6421		ioc_err(mrioc, "driver page2 header read failed\n");
6422		goto out_failed;
6423	}
6424	if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6425		ioc_err(mrioc, "driver page2 header read failed with\n"
6426			       "ioc_status(0x%04x)\n",
6427		    ioc_status);
6428		goto out_failed;
6429	}
6430	cfg_req.action = page_action;
6431
6432	if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6433	    MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, driver_pg2, pg_sz)) {
6434		ioc_err(mrioc, "driver page2 read failed\n");
6435		goto out_failed;
6436	}
6437	if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6438		ioc_err(mrioc, "driver page2 read failed with\n"
6439			       "ioc_status(0x%04x)\n",
6440		    ioc_status);
6441		goto out_failed;
6442	}
6443	return 0;
6444out_failed:
6445	return -1;
6446}
6447