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mpi30_transport.h
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linux-6.19.14/drivers/scsi/mpi3mr/mpi/mpi30_transport.h
1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * Copyright 2016-2023 Broadcom Inc. All rights reserved. 4 */ 5#ifndef MPI30_TRANSPORT_H 6#define MPI30_TRANSPORT_H 1 7struct mpi3_version_struct { 8 u8 dev; 9 u8 unit; 10 u8 minor; 11 u8 major; 12}; 13 14union mpi3_version_union { 15 struct mpi3_version_struct mpi3_version; 16 __le32 word; 17}; 18 19#define MPI3_VERSION_MAJOR (3) 20#define MPI3_VERSION_MINOR (0) 21#define MPI3_VERSION_UNIT (37) 22#define MPI3_VERSION_DEV (0) 23#define MPI3_DEVHANDLE_INVALID (0xffff) 24struct mpi3_sysif_oper_queue_indexes { 25 __le16 producer_index; 26 __le16 reserved02; 27 __le16 consumer_index; 28 __le16 reserved06; 29}; 30 31struct mpi3_sysif_registers { 32 __le64 ioc_information; 33 union mpi3_version_union version; 34 __le32 reserved0c[2]; 35 __le32 ioc_configuration; 36 __le32 reserved18; 37 __le32 ioc_status; 38 __le32 reserved20; 39 __le32 admin_queue_num_entries; 40 __le64 admin_request_queue_address; 41 __le64 admin_reply_queue_address; 42 __le32 reserved38[2]; 43 __le32 coalesce_control; 44 __le32 reserved44[1007]; 45 __le16 admin_request_queue_pi; 46 __le16 reserved1002; 47 __le16 admin_reply_queue_ci; 48 __le16 reserved1006; 49 struct mpi3_sysif_oper_queue_indexes oper_queue_indexes[383]; 50 __le32 reserved1c00; 51 __le32 write_sequence; 52 __le32 host_diagnostic; 53 __le32 reserved1c0c; 54 __le32 fault; 55 __le32 fault_info[3]; 56 __le32 reserved1c20[4]; 57 __le64 hcb_address; 58 __le32 hcb_size; 59 __le32 reserved1c3c; 60 __le32 reply_free_host_index; 61 __le32 sense_buffer_free_host_index; 62 __le32 reserved1c48[2]; 63 __le64 diag_rw_data; 64 __le64 diag_rw_address; 65 __le16 diag_rw_control; 66 __le16 diag_rw_status; 67 __le32 reserved1c64[35]; 68 __le32 scratchpad[4]; 69 __le32 reserved1d00[192]; 70 __le32 device_assigned_registers[2048]; 71}; 72 73#define MPI3_SYSIF_IOC_INFO_LOW_OFFSET (0x00000000) 74#define MPI3_SYSIF_IOC_INFO_HIGH_OFFSET (0x00000004) 75#define MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK (0xff000000) 76#define MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT (24) 77#define MPI3_SYSIF_IOC_INFO_LOW_HCB_DISABLED (0x00000001) 78#define MPI3_SYSIF_IOC_CONFIG_OFFSET (0x00000014) 79#define MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ (0x00f00000) 80#define MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ_SHIFT (20) 81#define MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ (0x000f0000) 82#define MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ_SHIFT (16) 83#define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_SHIFT (14) 84#define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_MASK (0x0000c000) 85#define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NO (0x00000000) 86#define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL (0x00004000) 87#define MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN_SEND_REQ (0x00002000) 88#define MPI3_SYSIF_IOC_CONFIG_DIAG_SAVE (0x00000010) 89#define MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC (0x00000001) 90#define MPI3_SYSIF_IOC_STATUS_OFFSET (0x0000001c) 91#define MPI3_SYSIF_IOC_STATUS_RESET_HISTORY (0x00000010) 92#define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK (0x0000000c) 93#define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_SHIFT (0x00000002) 94#define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_NONE (0x00000000) 95#define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS (0x00000004) 96#define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_COMPLETE (0x00000008) 97#define MPI3_SYSIF_IOC_STATUS_FAULT (0x00000002) 98#define MPI3_SYSIF_IOC_STATUS_READY (0x00000001) 99#define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_OFFSET (0x00000024) 100#define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REQ_MASK (0x0fff) 101#define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REQ_SHIFT (0) 102#define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REPLY_OFFSET (0x00000026) 103#define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REPLY_MASK (0x0fff0000) 104#define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REPLY_SHIFT (16) 105#define MPI3_SYSIF_ADMIN_REQ_Q_ADDR_LOW_OFFSET (0x00000028) 106#define MPI3_SYSIF_ADMIN_REQ_Q_ADDR_HIGH_OFFSET (0x0000002c) 107#define MPI3_SYSIF_ADMIN_REPLY_Q_ADDR_LOW_OFFSET (0x00000030) 108#define MPI3_SYSIF_ADMIN_REPLY_Q_ADDR_HIGH_OFFSET (0x00000034) 109#define MPI3_SYSIF_COALESCE_CONTROL_OFFSET (0x00000040) 110#define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_MASK (0xc0000000) 111#define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_SHIFT (30) 112#define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_NO_CHANGE (0x00000000) 113#define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_DISABLE (0x40000000) 114#define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_ENABLE (0xc0000000) 115#define MPI3_SYSIF_COALESCE_CONTROL_VALID (0x20000000) 116#define MPI3_SYSIF_COALESCE_CONTROL_MSIX_IDX_MASK (0x01ff0000) 117#define MPI3_SYSIF_COALESCE_CONTROL_MSIX_IDX_SHIFT (16) 118#define MPI3_SYSIF_COALESCE_CONTROL_TIMEOUT_MASK (0x0000ff00) 119#define MPI3_SYSIF_COALESCE_CONTROL_TIMEOUT_SHIFT (8) 120#define MPI3_SYSIF_COALESCE_CONTROL_DEPTH_MASK (0x000000ff) 121#define MPI3_SYSIF_COALESCE_CONTROL_DEPTH_SHIFT (0) 122#define MPI3_SYSIF_ADMIN_REQ_Q_PI_OFFSET (0x00001000) 123#define MPI3_SYSIF_ADMIN_REPLY_Q_CI_OFFSET (0x00001004) 124#define MPI3_SYSIF_OPER_REQ_Q_PI_OFFSET (0x00001008) 125#define MPI3_SYSIF_OPER_REQ_Q_N_PI_OFFSET(N) (MPI3_SYSIF_OPER_REQ_Q_PI_OFFSET + (((N) - 1) * 8)) 126#define MPI3_SYSIF_OPER_REPLY_Q_CI_OFFSET (0x0000100c) 127#define MPI3_SYSIF_OPER_REPLY_Q_N_CI_OFFSET(N) (MPI3_SYSIF_OPER_REPLY_Q_CI_OFFSET + (((N) - 1) * 8)) 128#define MPI3_SYSIF_WRITE_SEQUENCE_OFFSET (0x00001c04) 129#define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_MASK (0x0000000f) 130#define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_SHIFT (0) 131#define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH (0x0) 132#define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_1ST (0xf) 133#define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND (0x4) 134#define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_3RD (0xb) 135#define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_4TH (0x2) 136#define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_5TH (0x7) 137#define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_6TH (0xd) 138#define MPI3_SYSIF_HOST_DIAG_OFFSET (0x00001c08) 139#define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_MASK (0x00000700) 140#define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SHIFT (8) 141#define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_NO_RESET (0x00000000) 142#define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET (0x00000100) 143#define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_HOST_CONTROL_BOOT_RESET (0x00000200) 144#define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_COMPLETE_RESET (0x00000300) 145#define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT (0x00000700) 146#define MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS (0x00000080) 147#define MPI3_SYSIF_HOST_DIAG_SECURE_BOOT (0x00000040) 148#define MPI3_SYSIF_HOST_DIAG_CLEAR_INVALID_FW_IMAGE (0x00000020) 149#define MPI3_SYSIF_HOST_DIAG_INVALID_FW_IMAGE (0x00000010) 150#define MPI3_SYSIF_HOST_DIAG_HCBENABLE (0x00000008) 151#define MPI3_SYSIF_HOST_DIAG_HCBMODE (0x00000004) 152#define MPI3_SYSIF_HOST_DIAG_DIAG_RW_ENABLE (0x00000002) 153#define MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE (0x00000001) 154#define MPI3_SYSIF_FAULT_OFFSET (0x00001c10) 155#define MPI3_SYSIF_FAULT_FUNC_AREA_MASK (0xff000000) 156#define MPI3_SYSIF_FAULT_FUNC_AREA_SHIFT (24) 157#define MPI3_SYSIF_FAULT_FUNC_AREA_MPI_DEFINED (0x00000000) 158#define MPI3_SYSIF_FAULT_CODE_MASK (0x0000ffff) 159#define MPI3_SYSIF_FAULT_CODE_SHIFT (0) 160#define MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET (0x0000f000) 161#define MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET (0x0000f001) 162#define MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS (0x0000f002) 163#define MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED (0x0000f003) 164#define MPI3_SYSIF_FAULT_CODE_SOFT_RESET_NEEDED (0x0000f004) 165#define MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED (0x0000f005) 166#define MPI3_SYSIF_FAULT_CODE_TEMP_THRESHOLD_EXCEEDED (0x0000f006) 167#define MPI3_SYSIF_FAULT_CODE_INSUFFICIENT_PCI_SLOT_POWER (0x0000f007) 168#define MPI3_SYSIF_FAULT_INFO0_OFFSET (0x00001c14) 169#define MPI3_SYSIF_FAULT_INFO1_OFFSET (0x00001c18) 170#define MPI3_SYSIF_FAULT_INFO2_OFFSET (0x00001c1c) 171#define MPI3_SYSIF_HCB_ADDRESS_LOW_OFFSET (0x00001c30) 172#define MPI3_SYSIF_HCB_ADDRESS_HIGH_OFFSET (0x00001c34) 173#define MPI3_SYSIF_HCB_SIZE_OFFSET (0x00001c38) 174#define MPI3_SYSIF_HCB_SIZE_SIZE_MASK (0xfffff000) 175#define MPI3_SYSIF_HCB_SIZE_SIZE_SHIFT (12) 176#define MPI3_SYSIF_HCB_SIZE_HCDW_ENABLE (0x00000001) 177#define MPI3_SYSIF_REPLY_FREE_HOST_INDEX_OFFSET (0x00001c40) 178#define MPI3_SYSIF_SENSE_BUF_FREE_HOST_INDEX_OFFSET (0x00001c44) 179#define MPI3_SYSIF_DIAG_RW_DATA_LOW_OFFSET (0x00001c50) 180#define MPI3_SYSIF_DIAG_RW_DATA_HIGH_OFFSET (0x00001c54) 181#define MPI3_SYSIF_DIAG_RW_ADDRESS_LOW_OFFSET (0x00001c58) 182#define MPI3_SYSIF_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00001c5c) 183#define MPI3_SYSIF_DIAG_RW_CONTROL_OFFSET (0x00001c60) 184#define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_MASK (0x00000030) 185#define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_SHIFT (4) 186#define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_1BYTE (0x00000000) 187#define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_2BYTES (0x00000010) 188#define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_4BYTES (0x00000020) 189#define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_8BYTES (0x00000030) 190#define MPI3_SYSIF_DIAG_RW_CONTROL_RESET (0x00000004) 191#define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_MASK (0x00000002) 192#define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_SHIFT (1) 193#define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_READ (0x00000000) 194#define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_WRITE (0x00000002) 195#define MPI3_SYSIF_DIAG_RW_CONTROL_START (0x00000001) 196#define MPI3_SYSIF_DIAG_RW_STATUS_OFFSET (0x00001c62) 197#define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_MASK (0x0000000e) 198#define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_SHIFT (1) 199#define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_SUCCESS (0x00000000) 200#define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_INV_ADDR (0x00000002) 201#define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_ACC_ERR (0x00000004) 202#define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_PAR_ERR (0x00000006) 203#define MPI3_SYSIF_DIAG_RW_STATUS_BUSY (0x00000001) 204#define MPI3_SYSIF_SCRATCHPAD0_OFFSET (0x00001cf0) 205#define MPI3_SYSIF_SCRATCHPAD1_OFFSET (0x00001cf4) 206#define MPI3_SYSIF_SCRATCHPAD2_OFFSET (0x00001cf8) 207#define MPI3_SYSIF_SCRATCHPAD3_OFFSET (0x00001cfc) 208#define MPI3_SYSIF_DEVICE_ASSIGNED_REGS_OFFSET (0x00002000) 209#define MPI3_SYSIF_DIAG_SAVE_TIMEOUT (60) 210struct mpi3_default_reply_descriptor { 211 __le32 descriptor_type_dependent1[2]; 212 __le16 request_queue_ci; 213 __le16 request_queue_id; 214 __le16 descriptor_type_dependent2; 215 __le16 reply_flags; 216}; 217 218#define MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK (0x0001) 219#define MPI3_REPLY_DESCRIPT_FLAGS_PHASE_SHIFT (0) 220#define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK (0xf000) 221#define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SHIFT (12) 222#define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY (0x0000) 223#define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS (0x1000) 224#define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_TARGET_COMMAND_BUFFER (0x2000) 225#define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS (0x3000) 226#define MPI3_REPLY_DESCRIPT_REQUEST_QUEUE_ID_INVALID (0xffff) 227struct mpi3_address_reply_descriptor { 228 __le64 reply_frame_address; 229 __le16 request_queue_ci; 230 __le16 request_queue_id; 231 __le16 reserved0c; 232 __le16 reply_flags; 233}; 234 235struct mpi3_success_reply_descriptor { 236 __le32 reserved00[2]; 237 __le16 request_queue_ci; 238 __le16 request_queue_id; 239 __le16 host_tag; 240 __le16 reply_flags; 241}; 242 243struct mpi3_target_command_buffer_reply_descriptor { 244 __le32 reserved00; 245 __le16 initiator_dev_handle; 246 u8 phy_num; 247 u8 reserved07; 248 __le16 request_queue_ci; 249 __le16 request_queue_id; 250 __le16 io_index; 251 __le16 reply_flags; 252}; 253 254struct mpi3_status_reply_descriptor { 255 __le16 ioc_status; 256 __le16 reserved02; 257 __le32 ioc_log_info; 258 __le16 request_queue_ci; 259 __le16 request_queue_id; 260 __le16 host_tag; 261 __le16 reply_flags; 262}; 263 264#define MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL (0x8000) 265#define MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK (0x7fff) 266#define MPI3_REPLY_DESCRIPT_STATUS_IOCLOGINFO_TYPE_MASK (0xf0000000) 267#define MPI3_REPLY_DESCRIPT_STATUS_IOCLOGINFO_TYPE_NO_INFO (0x00000000) 268#define MPI3_REPLY_DESCRIPT_STATUS_IOCLOGINFO_TYPE_SAS (0x30000000) 269#define MPI3_REPLY_DESCRIPT_STATUS_IOCLOGINFO_DATA_MASK (0x0fffffff) 270union mpi3_reply_descriptors_union { 271 struct mpi3_default_reply_descriptor default_reply; 272 struct mpi3_address_reply_descriptor address_reply; 273 struct mpi3_success_reply_descriptor success; 274 struct mpi3_target_command_buffer_reply_descriptor target_command_buffer; 275 struct mpi3_status_reply_descriptor status; 276 __le32 words[4]; 277}; 278 279struct mpi3_sge_common { 280 __le64 address; 281 __le32 length; 282 u8 reserved0c[3]; 283 u8 flags; 284}; 285 286struct mpi3_sge_bit_bucket { 287 __le64 reserved00; 288 __le32 length; 289 u8 reserved0c[3]; 290 u8 flags; 291}; 292 293struct mpi3_sge_extended_eedp { 294 u8 user_data_size; 295 u8 reserved01; 296 __le16 eedp_flags; 297 __le32 secondary_reference_tag; 298 __le16 secondary_application_tag; 299 __le16 application_tag_translation_mask; 300 __le16 reserved0c; 301 u8 extended_operation; 302 u8 flags; 303}; 304 305union mpi3_sge_union { 306 struct mpi3_sge_common simple; 307 struct mpi3_sge_common chain; 308 struct mpi3_sge_common last_chain; 309 struct mpi3_sge_bit_bucket bit_bucket; 310 struct mpi3_sge_extended_eedp eedp; 311 __le32 words[4]; 312}; 313 314#define MPI3_SGE_FLAGS_ELEMENT_TYPE_MASK (0xf0) 315#define MPI3_SGE_FLAGS_ELEMENT_TYPE_SHIFT (4) 316#define MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE (0x00) 317#define MPI3_SGE_FLAGS_ELEMENT_TYPE_BIT_BUCKET (0x10) 318#define MPI3_SGE_FLAGS_ELEMENT_TYPE_CHAIN (0x20) 319#define MPI3_SGE_FLAGS_ELEMENT_TYPE_LAST_CHAIN (0x30) 320#define MPI3_SGE_FLAGS_ELEMENT_TYPE_EXTENDED (0xf0) 321#define MPI3_SGE_FLAGS_END_OF_LIST (0x08) 322#define MPI3_SGE_FLAGS_END_OF_BUFFER (0x04) 323#define MPI3_SGE_FLAGS_DLAS_MASK (0x03) 324#define MPI3_SGE_FLAGS_DLAS_SHIFT (0) 325#define MPI3_SGE_FLAGS_DLAS_SYSTEM (0x00) 326#define MPI3_SGE_FLAGS_DLAS_IOC_UDP (0x01) 327#define MPI3_SGE_FLAGS_DLAS_IOC_CTL (0x02) 328#define MPI3_SGE_EXT_OPER_EEDP (0x00) 329#define MPI3_EEDPFLAGS_INCR_PRI_REF_TAG (0x8000) 330#define MPI3_EEDPFLAGS_INCR_SEC_REF_TAG (0x4000) 331#define MPI3_EEDPFLAGS_INCR_PRI_APP_TAG (0x2000) 332#define MPI3_EEDPFLAGS_INCR_SEC_APP_TAG (0x1000) 333#define MPI3_EEDPFLAGS_ESC_PASSTHROUGH (0x0800) 334#define MPI3_EEDPFLAGS_CHK_REF_TAG (0x0400) 335#define MPI3_EEDPFLAGS_CHK_APP_TAG (0x0200) 336#define MPI3_EEDPFLAGS_CHK_GUARD (0x0100) 337#define MPI3_EEDPFLAGS_ESC_MODE_MASK (0x00c0) 338#define MPI3_EEDPFLAGS_ESC_MODE_SHIFT (6) 339#define MPI3_EEDPFLAGS_ESC_MODE_DO_NOT_DISABLE (0x0040) 340#define MPI3_EEDPFLAGS_ESC_MODE_APPTAG_DISABLE (0x0080) 341#define MPI3_EEDPFLAGS_ESC_MODE_APPTAG_REFTAG_DISABLE (0x00c0) 342#define MPI3_EEDPFLAGS_HOST_GUARD_MASK (0x0030) 343#define MPI3_EEDPFLAGS_HOST_GUARD_SHIFT (4) 344#define MPI3_EEDPFLAGS_HOST_GUARD_T10_CRC (0x0000) 345#define MPI3_EEDPFLAGS_HOST_GUARD_IP_CHKSUM (0x0010) 346#define MPI3_EEDPFLAGS_HOST_GUARD_OEM_SPECIFIC (0x0020) 347#define MPI3_EEDPFLAGS_PT_REF_TAG (0x0008) 348#define MPI3_EEDPFLAGS_EEDP_OP_MASK (0x0007) 349#define MPI3_EEDPFLAGS_EEDP_OP_SHIFT (0) 350#define MPI3_EEDPFLAGS_EEDP_OP_CHECK (0x0001) 351#define MPI3_EEDPFLAGS_EEDP_OP_STRIP (0x0002) 352#define MPI3_EEDPFLAGS_EEDP_OP_CHECK_REMOVE (0x0003) 353#define MPI3_EEDPFLAGS_EEDP_OP_INSERT (0x0004) 354#define MPI3_EEDPFLAGS_EEDP_OP_REPLACE (0x0006) 355#define MPI3_EEDPFLAGS_EEDP_OP_CHECK_REGEN (0x0007) 356#define MPI3_EEDP_UDS_512 (0x01) 357#define MPI3_EEDP_UDS_520 (0x02) 358#define MPI3_EEDP_UDS_4080 (0x03) 359#define MPI3_EEDP_UDS_4088 (0x04) 360#define MPI3_EEDP_UDS_4096 (0x05) 361#define MPI3_EEDP_UDS_4104 (0x06) 362#define MPI3_EEDP_UDS_4160 (0x07) 363struct mpi3_request_header { 364 __le16 host_tag; 365 u8 ioc_use_only02; 366 u8 function; 367 __le16 ioc_use_only04; 368 u8 ioc_use_only06; 369 u8 msg_flags; 370 __le16 change_count; 371 __le16 function_dependent; 372}; 373 374struct mpi3_default_reply { 375 __le16 host_tag; 376 u8 ioc_use_only02; 377 u8 function; 378 __le16 ioc_use_only04; 379 u8 ioc_use_only06; 380 u8 msg_flags; 381 __le16 ioc_use_only08; 382 __le16 ioc_status; 383 __le32 ioc_log_info; 384}; 385 386#define MPI3_HOST_TAG_INVALID (0xffff) 387#define MPI3_FUNCTION_IOC_FACTS (0x01) 388#define MPI3_FUNCTION_IOC_INIT (0x02) 389#define MPI3_FUNCTION_PORT_ENABLE (0x03) 390#define MPI3_FUNCTION_EVENT_NOTIFICATION (0x04) 391#define MPI3_FUNCTION_EVENT_ACK (0x05) 392#define MPI3_FUNCTION_CI_DOWNLOAD (0x06) 393#define MPI3_FUNCTION_CI_UPLOAD (0x07) 394#define MPI3_FUNCTION_IO_UNIT_CONTROL (0x08) 395#define MPI3_FUNCTION_PERSISTENT_EVENT_LOG (0x09) 396#define MPI3_FUNCTION_MGMT_PASSTHROUGH (0x0a) 397#define MPI3_FUNCTION_CONFIG (0x10) 398#define MPI3_FUNCTION_SCSI_IO (0x20) 399#define MPI3_FUNCTION_SCSI_TASK_MGMT (0x21) 400#define MPI3_FUNCTION_SMP_PASSTHROUGH (0x22) 401#define MPI3_FUNCTION_NVME_ENCAPSULATED (0x24) 402#define MPI3_FUNCTION_TARGET_ASSIST (0x30) 403#define MPI3_FUNCTION_TARGET_STATUS_SEND (0x31) 404#define MPI3_FUNCTION_TARGET_MODE_ABORT (0x32) 405#define MPI3_FUNCTION_TARGET_CMD_BUF_POST_BASE (0x33) 406#define MPI3_FUNCTION_TARGET_CMD_BUF_POST_LIST (0x34) 407#define MPI3_FUNCTION_CREATE_REQUEST_QUEUE (0x70) 408#define MPI3_FUNCTION_DELETE_REQUEST_QUEUE (0x71) 409#define MPI3_FUNCTION_CREATE_REPLY_QUEUE (0x72) 410#define MPI3_FUNCTION_DELETE_REPLY_QUEUE (0x73) 411#define MPI3_FUNCTION_TOOLBOX (0x80) 412#define MPI3_FUNCTION_DIAG_BUFFER_POST (0x81) 413#define MPI3_FUNCTION_DIAG_BUFFER_MANAGE (0x82) 414#define MPI3_FUNCTION_DIAG_BUFFER_UPLOAD (0x83) 415#define MPI3_FUNCTION_MIN_IOC_USE_ONLY (0xc0) 416#define MPI3_FUNCTION_MAX_IOC_USE_ONLY (0xef) 417#define MPI3_FUNCTION_MIN_PRODUCT_SPECIFIC (0xf0) 418#define MPI3_FUNCTION_MAX_PRODUCT_SPECIFIC (0xff) 419#define MPI3_IOCSTATUS_LOG_INFO_AVAIL_MASK (0x8000) 420#define MPI3_IOCSTATUS_LOG_INFO_AVAILABLE (0x8000) 421#define MPI3_IOCSTATUS_STATUS_MASK (0x7fff) 422#define MPI3_IOCSTATUS_STATUS_SHIFT (0) 423#define MPI3_IOCSTATUS_SUCCESS (0x0000) 424#define MPI3_IOCSTATUS_INVALID_FUNCTION (0x0001) 425#define MPI3_IOCSTATUS_BUSY (0x0002) 426#define MPI3_IOCSTATUS_INVALID_SGL (0x0003) 427#define MPI3_IOCSTATUS_INTERNAL_ERROR (0x0004) 428#define MPI3_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) 429#define MPI3_IOCSTATUS_INVALID_FIELD (0x0007) 430#define MPI3_IOCSTATUS_INVALID_STATE (0x0008) 431#define MPI3_IOCSTATUS_SHUTDOWN_ACTIVE (0x0009) 432#define MPI3_IOCSTATUS_INSUFFICIENT_POWER (0x000a) 433#define MPI3_IOCSTATUS_INVALID_CHANGE_COUNT (0x000b) 434#define MPI3_IOCSTATUS_ALLOWED_CMD_BLOCK (0x000c) 435#define MPI3_IOCSTATUS_SUPERVISOR_ONLY (0x000d) 436#define MPI3_IOCSTATUS_FAILURE (0x001f) 437#define MPI3_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) 438#define MPI3_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) 439#define MPI3_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) 440#define MPI3_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) 441#define MPI3_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) 442#define MPI3_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) 443#define MPI3_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) 444#define MPI3_IOCSTATUS_SCSI_TM_NOT_SUPPORTED (0x0041) 445#define MPI3_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042) 446#define MPI3_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) 447#define MPI3_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) 448#define MPI3_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) 449#define MPI3_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) 450#define MPI3_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) 451#define MPI3_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) 452#define MPI3_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) 453#define MPI3_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004a) 454#define MPI3_IOCSTATUS_SCSI_IOC_TERMINATED (0x004b) 455#define MPI3_IOCSTATUS_SCSI_EXT_TERMINATED (0x004c) 456#define MPI3_IOCSTATUS_EEDP_GUARD_ERROR (0x004d) 457#define MPI3_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004e) 458#define MPI3_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004f) 459#define MPI3_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062) 460#define MPI3_IOCSTATUS_TARGET_ABORTED (0x0063) 461#define MPI3_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) 462#define MPI3_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) 463#define MPI3_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006a) 464#define MPI3_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006d) 465#define MPI3_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006e) 466#define MPI3_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006f) 467#define MPI3_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070) 468#define MPI3_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071) 469#define MPI3_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090) 470#define MPI3_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091) 471#define MPI3_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00a0) 472#define MPI3_IOCSTATUS_CI_UNSUPPORTED (0x00b0) 473#define MPI3_IOCSTATUS_CI_UPDATE_SEQUENCE (0x00b1) 474#define MPI3_IOCSTATUS_CI_VALIDATION_FAILED (0x00b2) 475#define MPI3_IOCSTATUS_CI_KEY_UPDATE_PENDING (0x00b3) 476#define MPI3_IOCSTATUS_CI_KEY_UPDATE_NOT_POSSIBLE (0x00b4) 477#define MPI3_IOCSTATUS_SECURITY_KEY_REQUIRED (0x00c0) 478#define MPI3_IOCSTATUS_SECURITY_VIOLATION (0x00c1) 479#define MPI3_IOCSTATUS_INVALID_QUEUE_ID (0x0f00) 480#define MPI3_IOCSTATUS_INVALID_QUEUE_SIZE (0x0f01) 481#define MPI3_IOCSTATUS_INVALID_MSIX_VECTOR (0x0f02) 482#define MPI3_IOCSTATUS_INVALID_REPLY_QUEUE_ID (0x0f03) 483#define MPI3_IOCSTATUS_INVALID_QUEUE_DELETION (0x0f04) 484#define MPI3_IOCLOGINFO_TYPE_MASK (0xf0000000) 485#define MPI3_IOCLOGINFO_TYPE_SHIFT (28) 486#define MPI3_IOCLOGINFO_TYPE_NONE (0x0) 487#define MPI3_IOCLOGINFO_TYPE_SAS (0x3) 488#define MPI3_IOCLOGINFO_LOG_DATA_MASK (0x0fffffff) 489#define MPI3_IOCLOGINFO_LOG_DATA_SHIFT (0) 490#endif
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