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mpi30_ioc.h
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linux-6.19.14/drivers/scsi/mpi3mr/mpi/mpi30_ioc.h
1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * Copyright 2016-2023 Broadcom Inc. All rights reserved. 4 */ 5#ifndef MPI30_IOC_H 6#define MPI30_IOC_H 1 7struct mpi3_ioc_init_request { 8 __le16 host_tag; 9 u8 ioc_use_only02; 10 u8 function; 11 __le16 ioc_use_only04; 12 u8 ioc_use_only06; 13 u8 msg_flags; 14 __le16 change_count; 15 __le16 reserved0a; 16 union mpi3_version_union mpi_version; 17 __le64 time_stamp; 18 u8 reserved18; 19 u8 who_init; 20 __le16 reserved1a; 21 __le16 reply_free_queue_depth; 22 __le16 reserved1e; 23 __le64 reply_free_queue_address; 24 __le32 reserved28; 25 __le16 sense_buffer_free_queue_depth; 26 __le16 sense_buffer_length; 27 __le64 sense_buffer_free_queue_address; 28 __le64 driver_information_address; 29}; 30#define MPI3_IOCINIT_MSGFLAGS_WRITESAMEDIVERT_SUPPORTED (0x08) 31#define MPI3_IOCINIT_MSGFLAGS_SCSIIOSTATUSREPLY_SUPPORTED (0x04) 32#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_MASK (0x03) 33#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_SHIFT (0) 34#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_NOT_USED (0x00) 35#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_SEPARATED (0x01) 36#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_INLINE (0x02) 37#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_BOTH (0x03) 38#define MPI3_WHOINIT_NOT_INITIALIZED (0x00) 39#define MPI3_WHOINIT_ROM_BIOS (0x02) 40#define MPI3_WHOINIT_HOST_DRIVER (0x03) 41#define MPI3_WHOINIT_MANUFACTURER (0x04) 42 43#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_MASK (0x00000003) 44#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_SHIFT (0) 45#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_NO_GUIDANCE (0x00000000) 46#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_NO_SPECIAL (0x00000001) 47#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_REPORT_AS_HDD (0x00000002) 48#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_REPORT_AS_SSD (0x00000003) 49 50struct mpi3_ioc_facts_request { 51 __le16 host_tag; 52 u8 ioc_use_only02; 53 u8 function; 54 __le16 ioc_use_only04; 55 u8 ioc_use_only06; 56 u8 msg_flags; 57 __le16 change_count; 58 __le16 reserved0a; 59 __le32 reserved0c; 60 union mpi3_sge_union sgl; 61}; 62 63struct mpi3_ioc_facts_data { 64 __le16 ioc_facts_data_length; 65 __le16 reserved02; 66 union mpi3_version_union mpi_version; 67 struct mpi3_comp_image_version fw_version; 68 __le32 ioc_capabilities; 69 u8 ioc_number; 70 u8 who_init; 71 __le16 max_msix_vectors; 72 __le16 max_outstanding_requests; 73 __le16 product_id; 74 __le16 ioc_request_frame_size; 75 __le16 reply_frame_size; 76 __le16 ioc_exceptions; 77 __le16 max_persistent_id; 78 u8 sge_modifier_mask; 79 u8 sge_modifier_value; 80 u8 sge_modifier_shift; 81 u8 protocol_flags; 82 __le16 max_sas_initiators; 83 __le16 max_data_length; 84 __le16 max_sas_expanders; 85 __le16 max_enclosures; 86 __le16 min_dev_handle; 87 __le16 max_dev_handle; 88 __le16 max_pcie_switches; 89 __le16 max_nvme; 90 __le16 reserved38; 91 __le16 max_vds; 92 __le16 max_host_pds; 93 __le16 max_adv_host_pds; 94 __le16 max_raid_pds; 95 __le16 max_posted_cmd_buffers; 96 __le32 flags; 97 __le16 max_operational_request_queues; 98 __le16 max_operational_reply_queues; 99 __le16 shutdown_timeout; 100 __le16 reserved4e; 101 __le32 diag_trace_size; 102 __le32 diag_fw_size; 103 __le32 diag_driver_size; 104 u8 max_host_pd_ns_count; 105 u8 max_adv_host_pd_ns_count; 106 u8 max_raidpd_ns_count; 107 u8 max_devices_per_throttle_group; 108 __le16 io_throttle_data_length; 109 __le16 max_io_throttle_group; 110 __le16 io_throttle_low; 111 __le16 io_throttle_high; 112 __le32 diag_fdl_size; 113 __le32 diag_tty_size; 114}; 115#define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_MASK (0x80000000) 116#define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_SHIFT (31) 117#define MPI3_IOCFACTS_CAPABILITY_SUPERVISOR_IOC (0x00000000) 118#define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_IOC (0x80000000) 119#define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_MASK (0x00000600) 120#define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_SHIFT (9) 121#define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_FIXED_THRESHOLD (0x00000000) 122#define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_OUTSTANDING_IO (0x00000200) 123#define MPI3_IOCFACTS_CAPABILITY_COMPLETE_RESET_SUPPORTED (0x00000100) 124#define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_TRACE_SUPPORTED (0x00000080) 125#define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_FW_SUPPORTED (0x00000040) 126#define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_DRIVER_SUPPORTED (0x00000020) 127#define MPI3_IOCFACTS_CAPABILITY_ADVANCED_HOST_PD_SUPPORTED (0x00000010) 128#define MPI3_IOCFACTS_CAPABILITY_RAID_SUPPORTED (0x00000008) 129#define MPI3_IOCFACTS_CAPABILITY_MULTIPATH_SUPPORTED (0x00000002) 130#define MPI3_IOCFACTS_CAPABILITY_COALESCE_CTRL_SUPPORTED (0x00000001) 131#define MPI3_IOCFACTS_PID_TYPE_MASK (0xf000) 132#define MPI3_IOCFACTS_PID_TYPE_SHIFT (12) 133#define MPI3_IOCFACTS_PID_PRODUCT_MASK (0x0f00) 134#define MPI3_IOCFACTS_PID_PRODUCT_SHIFT (8) 135#define MPI3_IOCFACTS_PID_FAMILY_MASK (0x00ff) 136#define MPI3_IOCFACTS_PID_FAMILY_SHIFT (0) 137#define MPI3_IOCFACTS_EXCEPT_SECURITY_REKEY (0x2000) 138#define MPI3_IOCFACTS_EXCEPT_SAS_DISABLED (0x1000) 139#define MPI3_IOCFACTS_EXCEPT_SAFE_MODE (0x0800) 140#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_MASK (0x0700) 141#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_SHIFT (8) 142#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_NONE (0x0000) 143#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_LOCAL_VIA_MGMT (0x0100) 144#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_EXT_VIA_MGMT (0x0200) 145#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_DRIVE_EXT_VIA_MGMT (0x0300) 146#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_LOCAL_VIA_OOB (0x0400) 147#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_EXT_VIA_OOB (0x0500) 148#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_DRIVE_EXT_VIA_OOB (0x0600) 149#define MPI3_IOCFACTS_EXCEPT_PCIE_DISABLED (0x0080) 150#define MPI3_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE (0x0040) 151#define MPI3_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0020) 152#define MPI3_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0010) 153#define MPI3_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0008) 154#define MPI3_IOCFACTS_EXCEPT_BLOCKING_BOOT_EVENT (0x0004) 155#define MPI3_IOCFACTS_EXCEPT_SECURITY_SELFTEST_FAILURE (0x0002) 156#define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x0001) 157#define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_SHIFT (0) 158#define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_PRIMARY (0x0000) 159#define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_SECONDARY (0x0001) 160#define MPI3_IOCFACTS_PROTOCOL_SAS (0x0010) 161#define MPI3_IOCFACTS_PROTOCOL_SATA (0x0008) 162#define MPI3_IOCFACTS_PROTOCOL_NVME (0x0004) 163#define MPI3_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002) 164#define MPI3_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001) 165#define MPI3_IOCFACTS_MAX_DATA_LENGTH_NOT_REPORTED (0x0000) 166#define MPI3_IOCFACTS_FLAGS_SIGNED_NVDATA_REQUIRED (0x00010000) 167#define MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK (0x0000ff00) 168#define MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT (8) 169#define MPI3_IOCFACTS_FLAGS_MAX_REQ_PER_REPLY_QUEUE_LIMIT (0x00000040) 170#define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK (0x00000030) 171#define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_SHIFT (4) 172#define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_NOT_STARTED (0x00000000) 173#define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_IN_PROGRESS (0x00000010) 174#define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_COMPLETE (0x00000020) 175#define MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK (0x0000000f) 176#define MPI3_IOCFACTS_FLAGS_PERSONALITY_SHIFT (0) 177#define MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA (0x00000000) 178#define MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR (0x00000002) 179#define MPI3_IOCFACTS_IO_THROTTLE_DATA_LENGTH_NOT_REQUIRED (0x0000) 180#define MPI3_IOCFACTS_MAX_IO_THROTTLE_GROUP_NOT_REQUIRED (0x0000) 181#define MPI3_IOCFACTS_DIAGFDLSIZE_NOT_SUPPORTED (0x00000000) 182#define MPI3_IOCFACTS_DIAGTTYSIZE_NOT_SUPPORTED (0x00000000) 183struct mpi3_mgmt_passthrough_request { 184 __le16 host_tag; 185 u8 ioc_use_only02; 186 u8 function; 187 __le16 ioc_use_only04; 188 u8 ioc_use_only06; 189 u8 msg_flags; 190 __le16 change_count; 191 __le16 reserved0a; 192 __le32 reserved0c[5]; 193 union mpi3_sge_union command_sgl; 194 union mpi3_sge_union response_sgl; 195}; 196 197struct mpi3_create_request_queue_request { 198 __le16 host_tag; 199 u8 ioc_use_only02; 200 u8 function; 201 __le16 ioc_use_only04; 202 u8 ioc_use_only06; 203 u8 msg_flags; 204 __le16 change_count; 205 u8 flags; 206 u8 burst; 207 __le16 size; 208 __le16 queue_id; 209 __le16 reply_queue_id; 210 __le16 reserved12; 211 __le32 reserved14; 212 __le64 base_address; 213}; 214 215#define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_MASK (0x80) 216#define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SHIFT (7) 217#define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED (0x80) 218#define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_CONTIGUOUS (0x00) 219#define MPI3_CREATE_REQUEST_QUEUE_SIZE_MINIMUM (2) 220struct mpi3_delete_request_queue_request { 221 __le16 host_tag; 222 u8 ioc_use_only02; 223 u8 function; 224 __le16 ioc_use_only04; 225 u8 ioc_use_only06; 226 u8 msg_flags; 227 __le16 change_count; 228 __le16 queue_id; 229}; 230 231struct mpi3_create_reply_queue_request { 232 __le16 host_tag; 233 u8 ioc_use_only02; 234 u8 function; 235 __le16 ioc_use_only04; 236 u8 ioc_use_only06; 237 u8 msg_flags; 238 __le16 change_count; 239 u8 flags; 240 u8 reserved0b; 241 __le16 size; 242 __le16 queue_id; 243 __le16 msix_index; 244 __le16 reserved12; 245 __le32 reserved14; 246 __le64 base_address; 247}; 248 249#define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_MASK (0x80) 250#define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_SHIFT (7) 251#define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_SEGMENTED (0x80) 252#define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_CONTIGUOUS (0x00) 253#define MPI3_CREATE_REPLY_QUEUE_FLAGS_COALESCE_DISABLE (0x02) 254#define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_MASK (0x01) 255#define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_SHIFT (0) 256#define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_DISABLE (0x00) 257#define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE (0x01) 258#define MPI3_CREATE_REPLY_QUEUE_SIZE_MINIMUM (2) 259struct mpi3_delete_reply_queue_request { 260 __le16 host_tag; 261 u8 ioc_use_only02; 262 u8 function; 263 __le16 ioc_use_only04; 264 u8 ioc_use_only06; 265 u8 msg_flags; 266 __le16 change_count; 267 __le16 queue_id; 268}; 269 270struct mpi3_port_enable_request { 271 __le16 host_tag; 272 u8 ioc_use_only02; 273 u8 function; 274 __le16 ioc_use_only04; 275 u8 ioc_use_only06; 276 u8 msg_flags; 277 __le16 change_count; 278 __le16 reserved0a; 279}; 280 281#define MPI3_EVENT_LOG_DATA (0x01) 282#define MPI3_EVENT_CHANGE (0x02) 283#define MPI3_EVENT_GPIO_INTERRUPT (0x04) 284#define MPI3_EVENT_CABLE_MGMT (0x06) 285#define MPI3_EVENT_DEVICE_ADDED (0x07) 286#define MPI3_EVENT_DEVICE_INFO_CHANGED (0x08) 287#define MPI3_EVENT_PREPARE_FOR_RESET (0x09) 288#define MPI3_EVENT_COMP_IMAGE_ACT_START (0x0a) 289#define MPI3_EVENT_ENCL_DEVICE_ADDED (0x0b) 290#define MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE (0x0c) 291#define MPI3_EVENT_DEVICE_STATUS_CHANGE (0x0d) 292#define MPI3_EVENT_ENERGY_PACK_CHANGE (0x0e) 293#define MPI3_EVENT_SAS_DISCOVERY (0x11) 294#define MPI3_EVENT_SAS_BROADCAST_PRIMITIVE (0x12) 295#define MPI3_EVENT_SAS_NOTIFY_PRIMITIVE (0x13) 296#define MPI3_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x14) 297#define MPI3_EVENT_SAS_INIT_TABLE_OVERFLOW (0x15) 298#define MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x16) 299#define MPI3_EVENT_SAS_PHY_COUNTER (0x18) 300#define MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR (0x19) 301#define MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST (0x20) 302#define MPI3_EVENT_PCIE_ENUMERATION (0x22) 303#define MPI3_EVENT_PCIE_ERROR_THRESHOLD (0x23) 304#define MPI3_EVENT_HARD_RESET_RECEIVED (0x40) 305#define MPI3_EVENT_DIAGNOSTIC_BUFFER_STATUS_CHANGE (0x50) 306#define MPI3_EVENT_MIN_PRODUCT_SPECIFIC (0x60) 307#define MPI3_EVENT_MAX_PRODUCT_SPECIFIC (0x7f) 308#define MPI3_EVENT_NOTIFY_EVENTMASK_WORDS (4) 309struct mpi3_event_notification_request { 310 __le16 host_tag; 311 u8 ioc_use_only02; 312 u8 function; 313 __le16 ioc_use_only04; 314 u8 ioc_use_only06; 315 u8 msg_flags; 316 __le16 change_count; 317 __le16 reserved0a; 318 __le16 sas_broadcast_primitive_masks; 319 __le16 sas_notify_primitive_masks; 320 __le32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS]; 321}; 322 323struct mpi3_event_notification_reply { 324 __le16 host_tag; 325 u8 ioc_use_only02; 326 u8 function; 327 __le16 ioc_use_only04; 328 u8 ioc_use_only06; 329 u8 msg_flags; 330 __le16 ioc_use_only08; 331 __le16 ioc_status; 332 __le32 ioc_log_info; 333 u8 event_data_length; 334 u8 event; 335 __le16 ioc_change_count; 336 __le32 event_context; 337 __le32 event_data[1]; 338}; 339 340#define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_MASK (0x01) 341#define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_SHIFT (0) 342#define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_REQUIRED (0x01) 343#define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_NOT_REQUIRED (0x00) 344#define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_MASK (0x02) 345#define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_SHIFT (1) 346#define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_ORIGINAL (0x00) 347#define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_REPLAY (0x02) 348struct mpi3_event_data_gpio_interrupt { 349 u8 gpio_num; 350 u8 reserved01[3]; 351}; 352struct mpi3_event_data_cable_management { 353 __le32 active_cable_power_requirement; 354 u8 status; 355 u8 receptacle_id; 356 __le16 reserved06; 357}; 358 359#define MPI3_EVENT_CABLE_MGMT_ACT_CABLE_PWR_INVALID (0xffffffff) 360#define MPI3_EVENT_CABLE_MGMT_STATUS_INSUFFICIENT_POWER (0x00) 361#define MPI3_EVENT_CABLE_MGMT_STATUS_PRESENT (0x01) 362#define MPI3_EVENT_CABLE_MGMT_STATUS_DEGRADED (0x02) 363struct mpi3_event_ack_request { 364 __le16 host_tag; 365 u8 ioc_use_only02; 366 u8 function; 367 __le16 ioc_use_only04; 368 u8 ioc_use_only06; 369 u8 msg_flags; 370 __le16 change_count; 371 __le16 reserved0a; 372 u8 event; 373 u8 reserved0d[3]; 374 __le32 event_context; 375}; 376 377struct mpi3_event_data_prepare_for_reset { 378 u8 reason_code; 379 u8 reserved01; 380 __le16 reserved02; 381}; 382 383#define MPI3_EVENT_PREPARE_RESET_RC_START (0x01) 384#define MPI3_EVENT_PREPARE_RESET_RC_ABORT (0x02) 385struct mpi3_event_data_comp_image_activation { 386 __le32 reserved00; 387}; 388 389struct mpi3_event_data_device_status_change { 390 __le16 task_tag; 391 u8 reason_code; 392 u8 io_unit_port; 393 __le16 parent_dev_handle; 394 __le16 dev_handle; 395 __le64 wwid; 396 u8 lun[8]; 397}; 398 399#define MPI3_EVENT_DEV_STAT_RC_MOVED (0x01) 400#define MPI3_EVENT_DEV_STAT_RC_HIDDEN (0x02) 401#define MPI3_EVENT_DEV_STAT_RC_NOT_HIDDEN (0x03) 402#define MPI3_EVENT_DEV_STAT_RC_ASYNC_NOTIFICATION (0x04) 403#define MPI3_EVENT_DEV_STAT_RC_INT_DEVICE_RESET_STRT (0x20) 404#define MPI3_EVENT_DEV_STAT_RC_INT_DEVICE_RESET_CMP (0x21) 405#define MPI3_EVENT_DEV_STAT_RC_INT_TASK_ABORT_STRT (0x22) 406#define MPI3_EVENT_DEV_STAT_RC_INT_TASK_ABORT_CMP (0x23) 407#define MPI3_EVENT_DEV_STAT_RC_INT_IT_NEXUS_RESET_STRT (0x24) 408#define MPI3_EVENT_DEV_STAT_RC_INT_IT_NEXUS_RESET_CMP (0x25) 409#define MPI3_EVENT_DEV_STAT_RC_PCIE_HOT_RESET_FAILED (0x30) 410#define MPI3_EVENT_DEV_STAT_RC_EXPANDER_REDUCED_FUNC_STRT (0x40) 411#define MPI3_EVENT_DEV_STAT_RC_EXPANDER_REDUCED_FUNC_CMP (0x41) 412#define MPI3_EVENT_DEV_STAT_RC_VD_NOT_RESPONDING (0x50) 413struct mpi3_event_data_energy_pack_change { 414 __le32 reserved00; 415 __le16 shutdown_timeout; 416 __le16 reserved06; 417}; 418 419struct mpi3_event_data_sas_discovery { 420 u8 flags; 421 u8 reason_code; 422 u8 io_unit_port; 423 u8 reserved03; 424 __le32 discovery_status; 425}; 426 427#define MPI3_EVENT_SAS_DISC_FLAGS_DEVICE_CHANGE (0x02) 428#define MPI3_EVENT_SAS_DISC_FLAGS_IN_PROGRESS (0x01) 429#define MPI3_EVENT_SAS_DISC_RC_STARTED (0x01) 430#define MPI3_EVENT_SAS_DISC_RC_COMPLETED (0x02) 431#define MPI3_SAS_DISC_STATUS_MAX_ENCLOSURES_EXCEED (0x80000000) 432#define MPI3_SAS_DISC_STATUS_MAX_EXPANDERS_EXCEED (0x40000000) 433#define MPI3_SAS_DISC_STATUS_MAX_DEVICES_EXCEED (0x20000000) 434#define MPI3_SAS_DISC_STATUS_MAX_TOPO_PHYS_EXCEED (0x10000000) 435#define MPI3_SAS_DISC_STATUS_INVALID_CEI (0x00010000) 436#define MPI3_SAS_DISC_STATUS_FECEI_MISMATCH (0x00008000) 437#define MPI3_SAS_DISC_STATUS_MULTIPLE_DEVICES_IN_SLOT (0x00004000) 438#define MPI3_SAS_DISC_STATUS_NECEI_MISMATCH (0x00002000) 439#define MPI3_SAS_DISC_STATUS_TOO_MANY_SLOTS (0x00001000) 440#define MPI3_SAS_DISC_STATUS_EXP_MULTI_SUBTRACTIVE (0x00000800) 441#define MPI3_SAS_DISC_STATUS_MULTI_PORT_DOMAIN (0x00000400) 442#define MPI3_SAS_DISC_STATUS_TABLE_TO_SUBTRACTIVE_LINK (0x00000200) 443#define MPI3_SAS_DISC_STATUS_UNSUPPORTED_DEVICE (0x00000100) 444#define MPI3_SAS_DISC_STATUS_TABLE_LINK (0x00000080) 445#define MPI3_SAS_DISC_STATUS_SUBTRACTIVE_LINK (0x00000040) 446#define MPI3_SAS_DISC_STATUS_SMP_CRC_ERROR (0x00000020) 447#define MPI3_SAS_DISC_STATUS_SMP_FUNCTION_FAILED (0x00000010) 448#define MPI3_SAS_DISC_STATUS_SMP_TIMEOUT (0x00000008) 449#define MPI3_SAS_DISC_STATUS_MULTIPLE_PORTS (0x00000004) 450#define MPI3_SAS_DISC_STATUS_INVALID_SAS_ADDRESS (0x00000002) 451#define MPI3_SAS_DISC_STATUS_LOOP_DETECTED (0x00000001) 452struct mpi3_event_data_sas_broadcast_primitive { 453 u8 phy_num; 454 u8 io_unit_port; 455 u8 port_width; 456 u8 primitive; 457}; 458 459#define MPI3_EVENT_BROADCAST_PRIMITIVE_CHANGE (0x01) 460#define MPI3_EVENT_BROADCAST_PRIMITIVE_SES (0x02) 461#define MPI3_EVENT_BROADCAST_PRIMITIVE_EXPANDER (0x03) 462#define MPI3_EVENT_BROADCAST_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04) 463#define MPI3_EVENT_BROADCAST_PRIMITIVE_RESERVED3 (0x05) 464#define MPI3_EVENT_BROADCAST_PRIMITIVE_RESERVED4 (0x06) 465#define MPI3_EVENT_BROADCAST_PRIMITIVE_CHANGE0_RESERVED (0x07) 466#define MPI3_EVENT_BROADCAST_PRIMITIVE_CHANGE1_RESERVED (0x08) 467struct mpi3_event_data_sas_notify_primitive { 468 u8 phy_num; 469 u8 io_unit_port; 470 u8 reserved02; 471 u8 primitive; 472}; 473 474#define MPI3_EVENT_NOTIFY_PRIMITIVE_ENABLE_SPINUP (0x01) 475#define MPI3_EVENT_NOTIFY_PRIMITIVE_POWER_LOSS_EXPECTED (0x02) 476#define MPI3_EVENT_NOTIFY_PRIMITIVE_RESERVED1 (0x03) 477#define MPI3_EVENT_NOTIFY_PRIMITIVE_RESERVED2 (0x04) 478struct mpi3_event_sas_topo_phy_entry { 479 __le16 attached_dev_handle; 480 u8 link_rate; 481 u8 status; 482}; 483 484#define MPI3_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xf0) 485#define MPI3_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4) 486#define MPI3_EVENT_SAS_TOPO_LR_PREV_MASK (0x0f) 487#define MPI3_EVENT_SAS_TOPO_LR_PREV_SHIFT (0) 488#define MPI3_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00) 489#define MPI3_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01) 490#define MPI3_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02) 491#define MPI3_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03) 492#define MPI3_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04) 493#define MPI3_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05) 494#define MPI3_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06) 495#define MPI3_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0a) 496#define MPI3_EVENT_SAS_TOPO_LR_RATE_12_0 (0x0b) 497#define MPI3_EVENT_SAS_TOPO_LR_RATE_22_5 (0x0c) 498#define MPI3_EVENT_SAS_TOPO_PHY_STATUS_MASK (0xc0) 499#define MPI3_EVENT_SAS_TOPO_PHY_STATUS_SHIFT (6) 500#define MPI3_EVENT_SAS_TOPO_PHY_STATUS_ACCESSIBLE (0x00) 501#define MPI3_EVENT_SAS_TOPO_PHY_STATUS_NO_EXIST (0x40) 502#define MPI3_EVENT_SAS_TOPO_PHY_STATUS_VACANT (0x80) 503#define MPI3_EVENT_SAS_TOPO_PHY_RC_MASK (0x0f) 504#define MPI3_EVENT_SAS_TOPO_PHY_RC_SHIFT (0) 505#define MPI3_EVENT_SAS_TOPO_PHY_RC_TARG_NOT_RESPONDING (0x02) 506#define MPI3_EVENT_SAS_TOPO_PHY_RC_PHY_CHANGED (0x03) 507#define MPI3_EVENT_SAS_TOPO_PHY_RC_NO_CHANGE (0x04) 508#define MPI3_EVENT_SAS_TOPO_PHY_RC_DELAY_NOT_RESPONDING (0x05) 509#define MPI3_EVENT_SAS_TOPO_PHY_RC_RESPONDING (0x06) 510struct mpi3_event_data_sas_topology_change_list { 511 __le16 enclosure_handle; 512 __le16 expander_dev_handle; 513 u8 num_phys; 514 u8 reserved05[3]; 515 u8 num_entries; 516 u8 start_phy_num; 517 u8 exp_status; 518 u8 io_unit_port; 519 struct mpi3_event_sas_topo_phy_entry phy_entry[] __counted_by(num_entries); 520}; 521 522#define MPI3_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00) 523#define MPI3_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02) 524#define MPI3_EVENT_SAS_TOPO_ES_RESPONDING (0x03) 525#define MPI3_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04) 526struct mpi3_event_data_sas_phy_counter { 527 __le64 time_stamp; 528 __le32 reserved08; 529 u8 phy_event_code; 530 u8 phy_num; 531 __le16 reserved0e; 532 __le32 phy_event_info; 533 u8 counter_type; 534 u8 threshold_window; 535 u8 time_units; 536 u8 reserved17; 537 __le32 event_threshold; 538 __le16 threshold_flags; 539 __le16 reserved1e; 540}; 541 542struct mpi3_event_data_sas_device_disc_err { 543 __le16 dev_handle; 544 u8 reason_code; 545 u8 io_unit_port; 546 __le32 reserved04; 547 __le64 sas_address; 548}; 549 550#define MPI3_EVENT_SAS_DISC_ERR_RC_SMP_FAILED (0x01) 551#define MPI3_EVENT_SAS_DISC_ERR_RC_SMP_TIMEOUT (0x02) 552struct mpi3_event_data_pcie_enumeration { 553 u8 flags; 554 u8 reason_code; 555 u8 io_unit_port; 556 u8 reserved03; 557 __le32 enumeration_status; 558}; 559 560#define MPI3_EVENT_PCIE_ENUM_FLAGS_DEVICE_CHANGE (0x02) 561#define MPI3_EVENT_PCIE_ENUM_FLAGS_IN_PROGRESS (0x01) 562#define MPI3_EVENT_PCIE_ENUM_RC_STARTED (0x01) 563#define MPI3_EVENT_PCIE_ENUM_RC_COMPLETED (0x02) 564#define MPI3_EVENT_PCIE_ENUM_ES_MAX_SWITCH_DEPTH_EXCEED (0x80000000) 565#define MPI3_EVENT_PCIE_ENUM_ES_MAX_SWITCHES_EXCEED (0x40000000) 566#define MPI3_EVENT_PCIE_ENUM_ES_MAX_DEVICES_EXCEED (0x20000000) 567#define MPI3_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED (0x10000000) 568struct mpi3_event_pcie_topo_port_entry { 569 __le16 attached_dev_handle; 570 u8 port_status; 571 u8 reserved03; 572 u8 current_port_info; 573 u8 reserved05; 574 u8 previous_port_info; 575 u8 reserved07; 576}; 577 578#define MPI3_EVENT_PCIE_TOPO_PS_NOT_RESPONDING (0x02) 579#define MPI3_EVENT_PCIE_TOPO_PS_PORT_CHANGED (0x03) 580#define MPI3_EVENT_PCIE_TOPO_PS_NO_CHANGE (0x04) 581#define MPI3_EVENT_PCIE_TOPO_PS_DELAY_NOT_RESPONDING (0x05) 582#define MPI3_EVENT_PCIE_TOPO_PS_RESPONDING (0x06) 583#define MPI3_EVENT_PCIE_TOPO_PI_LANES_MASK (0xf0) 584#define MPI3_EVENT_PCIE_TOPO_PI_LANES_SHIFT (4) 585#define MPI3_EVENT_PCIE_TOPO_PI_LANES_UNKNOWN (0x00) 586#define MPI3_EVENT_PCIE_TOPO_PI_LANES_1 (0x10) 587#define MPI3_EVENT_PCIE_TOPO_PI_LANES_2 (0x20) 588#define MPI3_EVENT_PCIE_TOPO_PI_LANES_4 (0x30) 589#define MPI3_EVENT_PCIE_TOPO_PI_LANES_8 (0x40) 590#define MPI3_EVENT_PCIE_TOPO_PI_LANES_16 (0x50) 591#define MPI3_EVENT_PCIE_TOPO_PI_RATE_MASK (0x0f) 592#define MPI3_EVENT_PCIE_TOPO_PI_RATE_SHIFT (0) 593#define MPI3_EVENT_PCIE_TOPO_PI_RATE_UNKNOWN (0x00) 594#define MPI3_EVENT_PCIE_TOPO_PI_RATE_DISABLED (0x01) 595#define MPI3_EVENT_PCIE_TOPO_PI_RATE_2_5 (0x02) 596#define MPI3_EVENT_PCIE_TOPO_PI_RATE_5_0 (0x03) 597#define MPI3_EVENT_PCIE_TOPO_PI_RATE_8_0 (0x04) 598#define MPI3_EVENT_PCIE_TOPO_PI_RATE_16_0 (0x05) 599#define MPI3_EVENT_PCIE_TOPO_PI_RATE_32_0 (0x06) 600struct mpi3_event_data_pcie_topology_change_list { 601 __le16 enclosure_handle; 602 __le16 switch_dev_handle; 603 u8 num_ports; 604 u8 reserved05[3]; 605 u8 num_entries; 606 u8 start_port_num; 607 u8 switch_status; 608 u8 io_unit_port; 609 __le32 reserved0c; 610 struct mpi3_event_pcie_topo_port_entry port_entry[] __counted_by(num_entries); 611}; 612 613#define MPI3_EVENT_PCIE_TOPO_SS_NO_PCIE_SWITCH (0x00) 614#define MPI3_EVENT_PCIE_TOPO_SS_NOT_RESPONDING (0x02) 615#define MPI3_EVENT_PCIE_TOPO_SS_RESPONDING (0x03) 616#define MPI3_EVENT_PCIE_TOPO_SS_DELAY_NOT_RESPONDING (0x04) 617struct mpi3_event_data_pcie_error_threshold { 618 __le64 timestamp; 619 u8 reason_code; 620 u8 port; 621 __le16 switch_dev_handle; 622 u8 error; 623 u8 action; 624 __le16 threshold_count; 625 __le16 attached_dev_handle; 626 __le16 reserved12; 627 __le32 reserved14; 628}; 629 630#define MPI3_EVENT_PCI_ERROR_RC_THRESHOLD_EXCEEDED (0x00) 631#define MPI3_EVENT_PCI_ERROR_RC_ESCALATION (0x01) 632struct mpi3_event_data_sas_init_dev_status_change { 633 u8 reason_code; 634 u8 io_unit_port; 635 __le16 dev_handle; 636 __le32 reserved04; 637 __le64 sas_address; 638}; 639 640#define MPI3_EVENT_SAS_INIT_RC_ADDED (0x01) 641#define MPI3_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02) 642struct mpi3_event_data_sas_init_table_overflow { 643 __le16 max_init; 644 __le16 current_init; 645 __le32 reserved04; 646 __le64 sas_address; 647}; 648 649struct mpi3_event_data_hard_reset_received { 650 u8 reserved00; 651 u8 io_unit_port; 652 __le16 reserved02; 653}; 654 655struct mpi3_event_data_diag_buffer_status_change { 656 u8 type; 657 u8 reason_code; 658 __le16 reserved02; 659 __le32 reserved04; 660}; 661 662#define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_RELEASED (0x01) 663#define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_PAUSED (0x02) 664#define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_RESUMED (0x03) 665#define MPI3_PEL_LOCALE_FLAGS_NON_BLOCKING_BOOT_EVENT (0x0200) 666#define MPI3_PEL_LOCALE_FLAGS_BLOCKING_BOOT_EVENT (0x0100) 667#define MPI3_PEL_LOCALE_FLAGS_PCIE (0x0080) 668#define MPI3_PEL_LOCALE_FLAGS_CONFIGURATION (0x0040) 669#define MPI3_PEL_LOCALE_FLAGS_CONTROLER (0x0020) 670#define MPI3_PEL_LOCALE_FLAGS_SAS (0x0010) 671#define MPI3_PEL_LOCALE_FLAGS_EPACK (0x0008) 672#define MPI3_PEL_LOCALE_FLAGS_ENCLOSURE (0x0004) 673#define MPI3_PEL_LOCALE_FLAGS_PD (0x0002) 674#define MPI3_PEL_LOCALE_FLAGS_VD (0x0001) 675#define MPI3_PEL_CLASS_DEBUG (0x00) 676#define MPI3_PEL_CLASS_PROGRESS (0x01) 677#define MPI3_PEL_CLASS_INFORMATIONAL (0x02) 678#define MPI3_PEL_CLASS_WARNING (0x03) 679#define MPI3_PEL_CLASS_CRITICAL (0x04) 680#define MPI3_PEL_CLASS_FATAL (0x05) 681#define MPI3_PEL_CLASS_FAULT (0x06) 682#define MPI3_PEL_CLEARTYPE_CLEAR (0x00) 683#define MPI3_PEL_WAITTIME_INFINITE_WAIT (0x00) 684#define MPI3_PEL_ACTION_GET_SEQNUM (0x01) 685#define MPI3_PEL_ACTION_MARK_CLEAR (0x02) 686#define MPI3_PEL_ACTION_GET_LOG (0x03) 687#define MPI3_PEL_ACTION_GET_COUNT (0x04) 688#define MPI3_PEL_ACTION_WAIT (0x05) 689#define MPI3_PEL_ACTION_ABORT (0x06) 690#define MPI3_PEL_ACTION_GET_PRINT_STRINGS (0x07) 691#define MPI3_PEL_ACTION_ACKNOWLEDGE (0x08) 692#define MPI3_PEL_STATUS_SUCCESS (0x00) 693#define MPI3_PEL_STATUS_NOT_FOUND (0x01) 694#define MPI3_PEL_STATUS_ABORTED (0x02) 695#define MPI3_PEL_STATUS_NOT_READY (0x03) 696struct mpi3_pel_seq { 697 __le32 newest; 698 __le32 oldest; 699 __le32 clear; 700 __le32 shutdown; 701 __le32 boot; 702 __le32 last_acknowledged; 703}; 704 705struct mpi3_pel_entry { 706 __le64 time_stamp; 707 __le32 sequence_number; 708 __le16 log_code; 709 __le16 arg_type; 710 __le16 locale; 711 u8 class; 712 u8 flags; 713 u8 ext_num; 714 u8 num_exts; 715 u8 arg_data_size; 716 u8 fixed_format_strings_size; 717 __le32 reserved18[2]; 718 __le32 pel_info[24]; 719}; 720 721#define MPI3_PEL_FLAGS_COMPLETE_RESET_NEEDED (0x02) 722#define MPI3_PEL_FLAGS_ACK_NEEDED (0x01) 723struct mpi3_pel_list { 724 __le32 log_count; 725 __le32 reserved04; 726 struct mpi3_pel_entry entry[1]; 727}; 728 729struct mpi3_pel_arg_map { 730 u8 arg_type; 731 u8 length; 732 __le16 start_location; 733}; 734 735#define MPI3_PEL_ARG_MAP_ARG_TYPE_APPEND_STRING (0x00) 736#define MPI3_PEL_ARG_MAP_ARG_TYPE_INTEGER (0x01) 737#define MPI3_PEL_ARG_MAP_ARG_TYPE_STRING (0x02) 738#define MPI3_PEL_ARG_MAP_ARG_TYPE_BIT_FIELD (0x03) 739struct mpi3_pel_print_string { 740 __le16 log_code; 741 __le16 string_length; 742 u8 num_arg_map; 743 u8 reserved05[3]; 744 struct mpi3_pel_arg_map arg_map[1]; 745}; 746 747struct mpi3_pel_print_string_list { 748 __le32 num_print_strings; 749 __le32 residual_bytes_remain; 750 __le32 reserved08[2]; 751 struct mpi3_pel_print_string print_string[1]; 752}; 753 754#ifndef MPI3_PEL_ACTION_SPECIFIC_MAX 755#define MPI3_PEL_ACTION_SPECIFIC_MAX (1) 756#endif 757struct mpi3_pel_request { 758 __le16 host_tag; 759 u8 ioc_use_only02; 760 u8 function; 761 __le16 ioc_use_only04; 762 u8 ioc_use_only06; 763 u8 msg_flags; 764 __le16 change_count; 765 u8 action; 766 u8 reserved0b; 767 __le32 action_specific[MPI3_PEL_ACTION_SPECIFIC_MAX]; 768}; 769 770struct mpi3_pel_req_action_get_sequence_numbers { 771 __le16 host_tag; 772 u8 ioc_use_only02; 773 u8 function; 774 __le16 ioc_use_only04; 775 u8 ioc_use_only06; 776 u8 msg_flags; 777 __le16 change_count; 778 u8 action; 779 u8 reserved0b; 780 __le32 reserved0c[5]; 781 union mpi3_sge_union sgl; 782}; 783 784struct mpi3_pel_req_action_clear_log_marker { 785 __le16 host_tag; 786 u8 ioc_use_only02; 787 u8 function; 788 __le16 ioc_use_only04; 789 u8 ioc_use_only06; 790 u8 msg_flags; 791 __le16 change_count; 792 u8 action; 793 u8 reserved0b; 794 u8 clear_type; 795 u8 reserved0d[3]; 796}; 797 798struct mpi3_pel_req_action_get_log { 799 __le16 host_tag; 800 u8 ioc_use_only02; 801 u8 function; 802 __le16 ioc_use_only04; 803 u8 ioc_use_only06; 804 u8 msg_flags; 805 __le16 change_count; 806 u8 action; 807 u8 reserved0b; 808 __le32 starting_sequence_number; 809 __le16 locale; 810 u8 class; 811 u8 reserved13; 812 __le32 reserved14[3]; 813 union mpi3_sge_union sgl; 814}; 815 816struct mpi3_pel_req_action_get_count { 817 __le16 host_tag; 818 u8 ioc_use_only02; 819 u8 function; 820 __le16 ioc_use_only04; 821 u8 ioc_use_only06; 822 u8 msg_flags; 823 __le16 change_count; 824 u8 action; 825 u8 reserved0b; 826 __le32 starting_sequence_number; 827 __le16 locale; 828 u8 class; 829 u8 reserved13; 830 __le32 reserved14[3]; 831 union mpi3_sge_union sgl; 832}; 833 834struct mpi3_pel_req_action_wait { 835 __le16 host_tag; 836 u8 ioc_use_only02; 837 u8 function; 838 __le16 ioc_use_only04; 839 u8 ioc_use_only06; 840 u8 msg_flags; 841 __le16 change_count; 842 u8 action; 843 u8 reserved0b; 844 __le32 starting_sequence_number; 845 __le16 locale; 846 u8 class; 847 u8 reserved13; 848 __le16 wait_time; 849 __le16 reserved16; 850 __le32 reserved18[2]; 851}; 852 853struct mpi3_pel_req_action_abort { 854 __le16 host_tag; 855 u8 ioc_use_only02; 856 u8 function; 857 __le16 ioc_use_only04; 858 u8 ioc_use_only06; 859 u8 msg_flags; 860 __le16 change_count; 861 u8 action; 862 u8 reserved0b; 863 __le32 reserved0c; 864 __le16 abort_host_tag; 865 __le16 reserved12; 866 __le32 reserved14; 867}; 868 869struct mpi3_pel_req_action_get_print_strings { 870 __le16 host_tag; 871 u8 ioc_use_only02; 872 u8 function; 873 __le16 ioc_use_only04; 874 u8 ioc_use_only06; 875 u8 msg_flags; 876 __le16 change_count; 877 u8 action; 878 u8 reserved0b; 879 __le32 reserved0c; 880 __le16 start_log_code; 881 __le16 reserved12; 882 __le32 reserved14[3]; 883 union mpi3_sge_union sgl; 884}; 885 886struct mpi3_pel_req_action_acknowledge { 887 __le16 host_tag; 888 u8 ioc_use_only02; 889 u8 function; 890 __le16 ioc_use_only04; 891 u8 ioc_use_only06; 892 u8 msg_flags; 893 __le16 change_count; 894 u8 action; 895 u8 reserved0b; 896 __le32 sequence_number; 897 __le32 reserved10; 898}; 899 900#define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_MASK (0x03) 901#define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_SHIFT (0) 902#define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_NO_GUIDANCE (0x00) 903#define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_CONTINUE_OP (0x01) 904#define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_TRANSITION_TO_FAULT (0x02) 905struct mpi3_pel_reply { 906 __le16 host_tag; 907 u8 ioc_use_only02; 908 u8 function; 909 __le16 ioc_use_only04; 910 u8 ioc_use_only06; 911 u8 msg_flags; 912 __le16 ioc_use_only08; 913 __le16 ioc_status; 914 __le32 ioc_log_info; 915 u8 action; 916 u8 reserved11; 917 __le16 reserved12; 918 __le16 pe_log_status; 919 __le16 reserved16; 920 __le32 transfer_length; 921}; 922 923struct mpi3_ci_download_request { 924 __le16 host_tag; 925 u8 ioc_use_only02; 926 u8 function; 927 __le16 ioc_use_only04; 928 u8 ioc_use_only06; 929 u8 msg_flags; 930 __le16 change_count; 931 u8 action; 932 u8 reserved0b; 933 __le32 signature1; 934 __le32 total_image_size; 935 __le32 image_offset; 936 __le32 segment_size; 937 __le32 reserved1c; 938 union mpi3_sge_union sgl; 939}; 940 941#define MPI3_CI_DOWNLOAD_MSGFLAGS_LAST_SEGMENT (0x80) 942#define MPI3_CI_DOWNLOAD_MSGFLAGS_FORCE_FMC_ENABLE (0x40) 943#define MPI3_CI_DOWNLOAD_MSGFLAGS_SIGNED_NVDATA (0x20) 944#define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_MASK (0x03) 945#define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_SHIFT (0) 946#define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_FAST (0x00) 947#define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_MEDIUM (0x01) 948#define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_SLOW (0x02) 949#define MPI3_CI_DOWNLOAD_ACTION_DOWNLOAD (0x01) 950#define MPI3_CI_DOWNLOAD_ACTION_ONLINE_ACTIVATION (0x02) 951#define MPI3_CI_DOWNLOAD_ACTION_OFFLINE_ACTIVATION (0x03) 952#define MPI3_CI_DOWNLOAD_ACTION_GET_STATUS (0x04) 953#define MPI3_CI_DOWNLOAD_ACTION_CANCEL_OFFLINE_ACTIVATION (0x05) 954struct mpi3_ci_download_reply { 955 __le16 host_tag; 956 u8 ioc_use_only02; 957 u8 function; 958 __le16 ioc_use_only04; 959 u8 ioc_use_only06; 960 u8 msg_flags; 961 __le16 ioc_use_only08; 962 __le16 ioc_status; 963 __le32 ioc_log_info; 964 u8 flags; 965 u8 cache_dirty; 966 u8 pending_count; 967 u8 reserved13; 968}; 969 970#define MPI3_CI_DOWNLOAD_FLAGS_DOWNLOAD_IN_PROGRESS (0x80) 971#define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_FAILURE (0x40) 972#define MPI3_CI_DOWNLOAD_FLAGS_OFFLINE_ACTIVATION_REQUIRED (0x20) 973#define MPI3_CI_DOWNLOAD_FLAGS_KEY_UPDATE_PENDING (0x10) 974#define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_MASK (0x0e) 975#define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_SHIFT (1) 976#define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_NOT_NEEDED (0x00) 977#define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_AWAITING (0x02) 978#define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_ONLINE_PENDING (0x04) 979#define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_OFFLINE_PENDING (0x06) 980#define MPI3_CI_DOWNLOAD_FLAGS_COMPATIBLE (0x01) 981struct mpi3_ci_upload_request { 982 __le16 host_tag; 983 u8 ioc_use_only02; 984 u8 function; 985 __le16 ioc_use_only04; 986 u8 ioc_use_only06; 987 u8 msg_flags; 988 __le16 change_count; 989 __le16 reserved0a; 990 __le32 signature1; 991 __le32 reserved10; 992 __le32 image_offset; 993 __le32 segment_size; 994 __le32 reserved1c; 995 union mpi3_sge_union sgl; 996}; 997 998#define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_MASK (0x01) 999#define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_SHIFT (0) 1000#define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_PRIMARY (0x00) 1001#define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_SECONDARY (0x01) 1002#define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_MASK (0x02) 1003#define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_SHIFT (1) 1004#define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_FLASH (0x00) 1005#define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_EXECUTABLE (0x02) 1006#define MPI3_CTRL_OP_FORCE_FULL_DISCOVERY (0x01) 1007#define MPI3_CTRL_OP_LOOKUP_MAPPING (0x02) 1008#define MPI3_CTRL_OP_UPDATE_TIMESTAMP (0x04) 1009#define MPI3_CTRL_OP_GET_TIMESTAMP (0x05) 1010#define MPI3_CTRL_OP_GET_IOC_CHANGE_COUNT (0x06) 1011#define MPI3_CTRL_OP_CHANGE_PROFILE (0x07) 1012#define MPI3_CTRL_OP_REMOVE_DEVICE (0x10) 1013#define MPI3_CTRL_OP_CLOSE_PERSISTENT_CONNECTION (0x11) 1014#define MPI3_CTRL_OP_HIDDEN_ACK (0x12) 1015#define MPI3_CTRL_OP_CLEAR_DEVICE_COUNTERS (0x13) 1016#define MPI3_CTRL_OP_SEND_SAS_PRIMITIVE (0x20) 1017#define MPI3_CTRL_OP_SAS_PHY_CONTROL (0x21) 1018#define MPI3_CTRL_OP_READ_INTERNAL_BUS (0x23) 1019#define MPI3_CTRL_OP_WRITE_INTERNAL_BUS (0x24) 1020#define MPI3_CTRL_OP_PCIE_LINK_CONTROL (0x30) 1021#define MPI3_CTRL_OP_LOOKUP_MAPPING_PARAM8_LOOKUP_METHOD_INDEX (0x00) 1022#define MPI3_CTRL_OP_UPDATE_TIMESTAMP_PARAM64_TIMESTAMP_INDEX (0x00) 1023#define MPI3_CTRL_OP_CHANGE_PROFILE_PARAM8_PROFILE_ID_INDEX (0x00) 1024#define MPI3_CTRL_OP_REMOVE_DEVICE_PARAM16_DEVHANDLE_INDEX (0x00) 1025#define MPI3_CTRL_OP_CLOSE_PERSIST_CONN_PARAM16_DEVHANDLE_INDEX (0x00) 1026#define MPI3_CTRL_OP_HIDDEN_ACK_PARAM16_DEVHANDLE_INDEX (0x00) 1027#define MPI3_CTRL_OP_CLEAR_DEVICE_COUNTERS_PARAM16_DEVHANDLE_INDEX (0x00) 1028#define MPI3_CTRL_OP_SEND_SAS_PRIM_PARAM8_PHY_INDEX (0x00) 1029#define MPI3_CTRL_OP_SEND_SAS_PRIM_PARAM8_PRIMSEQ_INDEX (0x01) 1030#define MPI3_CTRL_OP_SEND_SAS_PRIM_PARAM32_PRIMITIVE_INDEX (0x00) 1031#define MPI3_CTRL_OP_SAS_PHY_CONTROL_PARAM8_ACTION_INDEX (0x00) 1032#define MPI3_CTRL_OP_SAS_PHY_CONTROL_PARAM8_PHY_INDEX (0x01) 1033#define MPI3_CTRL_OP_READ_INTERNAL_BUS_PARAM64_ADDRESS_INDEX (0x00) 1034#define MPI3_CTRL_OP_WRITE_INTERNAL_BUS_PARAM64_ADDRESS_INDEX (0x00) 1035#define MPI3_CTRL_OP_WRITE_INTERNAL_BUS_PARAM32_VALUE_INDEX (0x00) 1036#define MPI3_CTRL_OP_PCIE_LINK_CONTROL_PARAM8_ACTION_INDEX (0x00) 1037#define MPI3_CTRL_OP_PCIE_LINK_CONTROL_PARAM8_LINK_INDEX (0x01) 1038#define MPI3_CTRL_LOOKUP_METHOD_WWID_ADDRESS (0x01) 1039#define MPI3_CTRL_LOOKUP_METHOD_ENCLOSURE_SLOT (0x02) 1040#define MPI3_CTRL_LOOKUP_METHOD_SAS_DEVICE_NAME (0x03) 1041#define MPI3_CTRL_LOOKUP_METHOD_PERSISTENT_ID (0x04) 1042#define MPI3_CTRL_LOOKUP_METHOD_WWIDADDR_PARAM16_DEVH_INDEX (0) 1043#define MPI3_CTRL_LOOKUP_METHOD_WWIDADDR_PARAM64_WWID_INDEX (0) 1044#define MPI3_CTRL_LOOKUP_METHOD_ENCLSLOT_PARAM16_SLOTNUM_INDEX (0) 1045#define MPI3_CTRL_LOOKUP_METHOD_ENCLSLOT_PARAM64_ENCLOSURELID_INDEX (0) 1046#define MPI3_CTRL_LOOKUP_METHOD_SASDEVNAME_PARAM16_DEVH_INDEX (0) 1047#define MPI3_CTRL_LOOKUP_METHOD_SASDEVNAME_PARAM64_DEVNAME_INDEX (0) 1048#define MPI3_CTRL_LOOKUP_METHOD_PERSISTID_PARAM16_DEVH_INDEX (0) 1049#define MPI3_CTRL_LOOKUP_METHOD_PERSISTID_PARAM16_PERSISTENT_ID_INDEX (1) 1050#define MPI3_CTRL_LOOKUP_METHOD_VALUE16_DEVH_INDEX (0) 1051#define MPI3_CTRL_GET_TIMESTAMP_VALUE64_TIMESTAMP_INDEX (0) 1052#define MPI3_CTRL_GET_IOC_CHANGE_COUNT_VALUE16_CHANGECOUNT_INDEX (0) 1053#define MPI3_CTRL_READ_INTERNAL_BUS_VALUE32_VALUE_INDEX (0) 1054#define MPI3_CTRL_PRIMFLAGS_SINGLE (0x01) 1055#define MPI3_CTRL_PRIMFLAGS_TRIPLE (0x03) 1056#define MPI3_CTRL_PRIMFLAGS_REDUNDANT (0x06) 1057#define MPI3_CTRL_ACTION_NOP (0x00) 1058#define MPI3_CTRL_ACTION_LINK_RESET (0x01) 1059#define MPI3_CTRL_ACTION_HARD_RESET (0x02) 1060#define MPI3_CTRL_ACTION_CLEAR_ERROR_LOG (0x05) 1061struct mpi3_iounit_control_request { 1062 __le16 host_tag; 1063 u8 ioc_use_only02; 1064 u8 function; 1065 __le16 ioc_use_only04; 1066 u8 ioc_use_only06; 1067 u8 msg_flags; 1068 __le16 change_count; 1069 u8 reserved0a; 1070 u8 operation; 1071 __le32 reserved0c; 1072 __le64 param64[2]; 1073 __le32 param32[4]; 1074 __le16 param16[4]; 1075 u8 param8[8]; 1076}; 1077 1078struct mpi3_iounit_control_reply { 1079 __le16 host_tag; 1080 u8 ioc_use_only02; 1081 u8 function; 1082 __le16 ioc_use_only04; 1083 u8 ioc_use_only06; 1084 u8 msg_flags; 1085 __le16 ioc_use_only08; 1086 __le16 ioc_status; 1087 __le32 ioc_log_info; 1088 __le64 value64[2]; 1089 __le32 value32[4]; 1090 __le16 value16[4]; 1091 u8 value8[8]; 1092}; 1093#endif
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