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mpi30_cnfg.h
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linux-6.19.14/drivers/scsi/mpi3mr/mpi/mpi30_cnfg.h
1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * Copyright 2017-2023 Broadcom Inc. All rights reserved. 4 */ 5#ifndef MPI30_CNFG_H 6#define MPI30_CNFG_H 1 7#define MPI3_CONFIG_PAGETYPE_IO_UNIT (0x00) 8#define MPI3_CONFIG_PAGETYPE_MANUFACTURING (0x01) 9#define MPI3_CONFIG_PAGETYPE_IOC (0x02) 10#define MPI3_CONFIG_PAGETYPE_DRIVER (0x03) 11#define MPI3_CONFIG_PAGETYPE_SECURITY (0x04) 12#define MPI3_CONFIG_PAGETYPE_ENCLOSURE (0x11) 13#define MPI3_CONFIG_PAGETYPE_DEVICE (0x12) 14#define MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT (0x20) 15#define MPI3_CONFIG_PAGETYPE_SAS_EXPANDER (0x21) 16#define MPI3_CONFIG_PAGETYPE_SAS_PHY (0x23) 17#define MPI3_CONFIG_PAGETYPE_SAS_PORT (0x24) 18#define MPI3_CONFIG_PAGETYPE_PCIE_IO_UNIT (0x30) 19#define MPI3_CONFIG_PAGETYPE_PCIE_SWITCH (0x31) 20#define MPI3_CONFIG_PAGETYPE_PCIE_LINK (0x33) 21#define MPI3_CONFIG_PAGEATTR_MASK (0xf0) 22#define MPI3_CONFIG_PAGEATTR_SHIFT (4) 23#define MPI3_CONFIG_PAGEATTR_READ_ONLY (0x00) 24#define MPI3_CONFIG_PAGEATTR_CHANGEABLE (0x10) 25#define MPI3_CONFIG_PAGEATTR_PERSISTENT (0x20) 26#define MPI3_CONFIG_ACTION_PAGE_HEADER (0x00) 27#define MPI3_CONFIG_ACTION_READ_DEFAULT (0x01) 28#define MPI3_CONFIG_ACTION_READ_CURRENT (0x02) 29#define MPI3_CONFIG_ACTION_WRITE_CURRENT (0x03) 30#define MPI3_CONFIG_ACTION_READ_PERSISTENT (0x04) 31#define MPI3_CONFIG_ACTION_WRITE_PERSISTENT (0x05) 32#define MPI3_DEVICE_PGAD_FORM_MASK (0xf0000000) 33#define MPI3_DEVICE_PGAD_FORM_SHIFT (28) 34#define MPI3_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 35#define MPI3_DEVICE_PGAD_FORM_HANDLE (0x20000000) 36#define MPI3_DEVICE_PGAD_HANDLE_MASK (0x0000ffff) 37#define MPI3_DEVICE_PGAD_HANDLE_SHIFT (0) 38#define MPI3_SAS_EXPAND_PGAD_FORM_MASK (0xf0000000) 39#define MPI3_SAS_EXPAND_PGAD_FORM_SHIFT (28) 40#define MPI3_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 41#define MPI3_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM (0x10000000) 42#define MPI3_SAS_EXPAND_PGAD_FORM_HANDLE (0x20000000) 43#define MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00ff0000) 44#define MPI3_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) 45#define MPI3_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000ffff) 46#define MPI3_SAS_PHY_PGAD_FORM_MASK (0xf0000000) 47#define MPI3_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) 48#define MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000ff) 49#define MPI3_SASPORT_PGAD_FORM_MASK (0xf0000000) 50#define MPI3_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) 51#define MPI3_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) 52#define MPI3_SASPORT_PGAD_PORT_NUMBER_MASK (0x000000ff) 53#define MPI3_ENCLOS_PGAD_FORM_MASK (0xf0000000) 54#define MPI3_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 55#define MPI3_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 56#define MPI3_ENCLOS_PGAD_HANDLE_MASK (0x0000ffff) 57#define MPI3_PCIE_SWITCH_PGAD_FORM_MASK (0xf0000000) 58#define MPI3_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 59#define MPI3_PCIE_SWITCH_PGAD_FORM_HANDLE_PORT_NUM (0x10000000) 60#define MPI3_PCIE_SWITCH_PGAD_FORM_HANDLE (0x20000000) 61#define MPI3_PCIE_SWITCH_PGAD_PORTNUM_MASK (0x00ff0000) 62#define MPI3_PCIE_SWITCH_PGAD_PORTNUM_SHIFT (16) 63#define MPI3_PCIE_SWITCH_PGAD_HANDLE_MASK (0x0000ffff) 64#define MPI3_PCIE_LINK_PGAD_FORM_MASK (0xf0000000) 65#define MPI3_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK (0x00000000) 66#define MPI3_PCIE_LINK_PGAD_FORM_LINK_NUM (0x10000000) 67#define MPI3_PCIE_LINK_PGAD_LINKNUM_MASK (0x000000ff) 68#define MPI3_SECURITY_PGAD_FORM_MASK (0xf0000000) 69#define MPI3_SECURITY_PGAD_FORM_GET_NEXT_SLOT (0x00000000) 70#define MPI3_SECURITY_PGAD_FORM_SLOT_NUM (0x10000000) 71#define MPI3_SECURITY_PGAD_SLOT_GROUP_MASK (0x0000ff00) 72#define MPI3_SECURITY_PGAD_SLOT_GROUP_SHIFT (8) 73#define MPI3_SECURITY_PGAD_SLOT_MASK (0x000000ff) 74#define MPI3_INSTANCE_PGAD_INSTANCE_MASK (0x0000ffff) 75struct mpi3_config_request { 76 __le16 host_tag; 77 u8 ioc_use_only02; 78 u8 function; 79 __le16 ioc_use_only04; 80 u8 ioc_use_only06; 81 u8 msg_flags; 82 __le16 change_count; 83 u8 proxy_ioc_number; 84 u8 reserved0b; 85 u8 page_version; 86 u8 page_number; 87 u8 page_type; 88 u8 action; 89 __le32 page_address; 90 __le16 page_length; 91 __le16 reserved16; 92 __le32 reserved18[2]; 93 union mpi3_sge_union sgl; 94}; 95 96struct mpi3_config_page_header { 97 u8 page_version; 98 u8 reserved01; 99 u8 page_number; 100 u8 page_attribute; 101 __le16 page_length; 102 u8 page_type; 103 u8 reserved07; 104}; 105 106#define MPI3_SAS_NEG_LINK_RATE_LOGICAL_MASK (0xf0) 107#define MPI3_SAS_NEG_LINK_RATE_LOGICAL_SHIFT (4) 108#define MPI3_SAS_NEG_LINK_RATE_PHYSICAL_MASK (0x0f) 109#define MPI3_SAS_NEG_LINK_RATE_PHYSICAL_SHIFT (0) 110#define MPI3_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00) 111#define MPI3_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01) 112#define MPI3_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02) 113#define MPI3_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03) 114#define MPI3_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04) 115#define MPI3_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05) 116#define MPI3_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06) 117#define MPI3_SAS_NEG_LINK_RATE_1_5 (0x08) 118#define MPI3_SAS_NEG_LINK_RATE_3_0 (0x09) 119#define MPI3_SAS_NEG_LINK_RATE_6_0 (0x0a) 120#define MPI3_SAS_NEG_LINK_RATE_12_0 (0x0b) 121#define MPI3_SAS_NEG_LINK_RATE_22_5 (0x0c) 122#define MPI3_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040) 123#define MPI3_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020) 124#define MPI3_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) 125#define MPI3_SAS_APHYINFO_REASON_MASK (0x0000000f) 126#define MPI3_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) 127#define MPI3_SAS_APHYINFO_REASON_POWER_ON (0x00000001) 128#define MPI3_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) 129#define MPI3_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003) 130#define MPI3_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004) 131#define MPI3_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005) 132#define MPI3_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006) 133#define MPI3_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007) 134#define MPI3_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008) 135#define MPI3_SAS_APHYINFO_REASON_EXP_REDUCED_FUNC (0x00000009) 136#define MPI3_SAS_PHYINFO_STATUS_MASK (0xc0000000) 137#define MPI3_SAS_PHYINFO_STATUS_SHIFT (30) 138#define MPI3_SAS_PHYINFO_STATUS_ACCESSIBLE (0x00000000) 139#define MPI3_SAS_PHYINFO_STATUS_NOT_EXIST (0x40000000) 140#define MPI3_SAS_PHYINFO_STATUS_VACANT (0x80000000) 141#define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000) 142#define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_ACTIVE (0x00000000) 143#define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_PARTIAL (0x08000000) 144#define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_SLUMBER (0x10000000) 145#define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_CHANGED_MASK (0x04000000) 146#define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_CHANGED_SHIFT (26) 147#define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT_MASK (0x02000000) 148#define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT_SHIFT (25) 149#define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_MASK (0x01000000) 150#define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_SHIFT (24) 151#define MPI3_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000) 152#define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_WITHIN (0x00200000) 153#define MPI3_SAS_PHYINFO_ZONING_ENABLED (0x00100000) 154#define MPI3_SAS_PHYINFO_REASON_MASK (0x000f0000) 155#define MPI3_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) 156#define MPI3_SAS_PHYINFO_REASON_POWER_ON (0x00010000) 157#define MPI3_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) 158#define MPI3_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000) 159#define MPI3_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000) 160#define MPI3_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000) 161#define MPI3_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000) 162#define MPI3_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000) 163#define MPI3_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000) 164#define MPI3_SAS_PHYINFO_REASON_EXP_REDUCED_FUNC (0x00090000) 165#define MPI3_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 166#define MPI3_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000) 167#define MPI3_SAS_PHYINFO_VIRTUAL_PHY (0x00001000) 168#define MPI3_SAS_PHYINFO_PARTIAL_PATHWAY_TIME_MASK (0x00000f00) 169#define MPI3_SAS_PHYINFO_PARTIAL_PATHWAY_TIME_SHIFT (8) 170#define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_MASK (0x000000f0) 171#define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_DIRECT (0x00000000) 172#define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_SUBTRACTIVE (0x00000010) 173#define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_TABLE (0x00000020) 174#define MPI3_SAS_PRATE_MAX_RATE_MASK (0xf0) 175#define MPI3_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 176#define MPI3_SAS_PRATE_MAX_RATE_1_5 (0x80) 177#define MPI3_SAS_PRATE_MAX_RATE_3_0 (0x90) 178#define MPI3_SAS_PRATE_MAX_RATE_6_0 (0xa0) 179#define MPI3_SAS_PRATE_MAX_RATE_12_0 (0xb0) 180#define MPI3_SAS_PRATE_MAX_RATE_22_5 (0xc0) 181#define MPI3_SAS_PRATE_MIN_RATE_MASK (0x0f) 182#define MPI3_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 183#define MPI3_SAS_PRATE_MIN_RATE_1_5 (0x08) 184#define MPI3_SAS_PRATE_MIN_RATE_3_0 (0x09) 185#define MPI3_SAS_PRATE_MIN_RATE_6_0 (0x0a) 186#define MPI3_SAS_PRATE_MIN_RATE_12_0 (0x0b) 187#define MPI3_SAS_PRATE_MIN_RATE_22_5 (0x0c) 188#define MPI3_SAS_HWRATE_MAX_RATE_MASK (0xf0) 189#define MPI3_SAS_HWRATE_MAX_RATE_1_5 (0x80) 190#define MPI3_SAS_HWRATE_MAX_RATE_3_0 (0x90) 191#define MPI3_SAS_HWRATE_MAX_RATE_6_0 (0xa0) 192#define MPI3_SAS_HWRATE_MAX_RATE_12_0 (0xb0) 193#define MPI3_SAS_HWRATE_MAX_RATE_22_5 (0xc0) 194#define MPI3_SAS_HWRATE_MIN_RATE_MASK (0x0f) 195#define MPI3_SAS_HWRATE_MIN_RATE_1_5 (0x08) 196#define MPI3_SAS_HWRATE_MIN_RATE_3_0 (0x09) 197#define MPI3_SAS_HWRATE_MIN_RATE_6_0 (0x0a) 198#define MPI3_SAS_HWRATE_MIN_RATE_12_0 (0x0b) 199#define MPI3_SAS_HWRATE_MIN_RATE_22_5 (0x0c) 200#define MPI3_SLOT_INVALID (0xffff) 201#define MPI3_SLOT_INDEX_INVALID (0xffff) 202#define MPI3_LINK_CHANGE_COUNT_INVALID (0xffff) 203#define MPI3_RATE_CHANGE_COUNT_INVALID (0xffff) 204#define MPI3_TEMP_SENSOR_LOCATION_INTERNAL (0x0) 205#define MPI3_TEMP_SENSOR_LOCATION_INLET (0x1) 206#define MPI3_TEMP_SENSOR_LOCATION_OUTLET (0x2) 207#define MPI3_TEMP_SENSOR_LOCATION_DRAM (0x3) 208#define MPI3_MFGPAGE_VENDORID_BROADCOM (0x1000) 209#define MPI3_MFGPAGE_DEVID_SAS4116 (0x00a5) 210#define MPI3_MFGPAGE_DEVID_SAS5116_MPI (0x00b3) 211#define MPI3_MFGPAGE_DEVID_SAS5116_NVME (0x00b4) 212#define MPI3_MFGPAGE_DEVID_SAS5116_MPI_MGMT (0x00b5) 213#define MPI3_MFGPAGE_DEVID_SAS5116_NVME_MGMT (0x00b6) 214#define MPI3_MFGPAGE_DEVID_SAS5116_PCIE_SWITCH (0x00b8) 215#define MPI3_MFGPAGE_DEVID_SAS5248_MPI (0x00f0) 216#define MPI3_MFGPAGE_DEVID_SAS5248_MPI_NS (0x00f1) 217#define MPI3_MFGPAGE_DEVID_SAS5248_PCIE_SWITCH (0x00f2) 218struct mpi3_man_page0 { 219 struct mpi3_config_page_header header; 220 u8 chip_revision[8]; 221 u8 chip_name[32]; 222 u8 board_name[32]; 223 u8 board_assembly[32]; 224 u8 board_tracer_number[32]; 225 __le32 board_power; 226 __le32 reserved94; 227 __le32 reserved98; 228 u8 oem; 229 u8 profile_identifier; 230 __le16 flags; 231 u8 board_mfg_day; 232 u8 board_mfg_month; 233 __le16 board_mfg_year; 234 u8 board_rework_day; 235 u8 board_rework_month; 236 __le16 board_rework_year; 237 u8 board_revision[8]; 238 u8 e_pack_fru[16]; 239 u8 product_name[256]; 240}; 241 242#define MPI3_MAN0_PAGEVERSION (0x00) 243#define MPI3_MAN0_FLAGS_SWITCH_PRESENT (0x0002) 244#define MPI3_MAN0_FLAGS_EXPANDER_PRESENT (0x0001) 245#define MPI3_MAN1_VPD_SIZE (512) 246struct mpi3_man_page1 { 247 struct mpi3_config_page_header header; 248 __le32 reserved08[2]; 249 u8 vpd[MPI3_MAN1_VPD_SIZE]; 250}; 251 252#define MPI3_MAN1_PAGEVERSION (0x00) 253struct mpi3_man_page2 { 254 struct mpi3_config_page_header header; 255 u8 flags; 256 u8 reserved09[3]; 257 __le32 reserved0c[3]; 258 u8 oem_board_tracer_number[32]; 259}; 260#define MPI3_MAN2_PAGEVERSION (0x00) 261#define MPI3_MAN2_FLAGS_TRACER_PRESENT (0x01) 262struct mpi3_man5_phy_entry { 263 __le64 ioc_wwid; 264 __le64 device_name; 265 __le64 sata_wwid; 266}; 267 268#ifndef MPI3_MAN5_PHY_MAX 269#define MPI3_MAN5_PHY_MAX (1) 270#endif 271struct mpi3_man_page5 { 272 struct mpi3_config_page_header header; 273 u8 num_phys; 274 u8 reserved09[3]; 275 __le32 reserved0c; 276 struct mpi3_man5_phy_entry phy[MPI3_MAN5_PHY_MAX]; 277}; 278 279#define MPI3_MAN5_PAGEVERSION (0x00) 280struct mpi3_man6_gpio_entry { 281 u8 function_code; 282 u8 function_flags; 283 __le16 flags; 284 u8 param1; 285 u8 param2; 286 __le16 reserved06; 287 __le32 param3; 288}; 289 290#define MPI3_MAN6_GPIO_FUNCTION_GENERIC (0x00) 291#define MPI3_MAN6_GPIO_FUNCTION_ALTERNATE (0x01) 292#define MPI3_MAN6_GPIO_FUNCTION_EXT_INTERRUPT (0x02) 293#define MPI3_MAN6_GPIO_FUNCTION_GLOBAL_ACTIVITY (0x03) 294#define MPI3_MAN6_GPIO_FUNCTION_OVER_TEMPERATURE (0x04) 295#define MPI3_MAN6_GPIO_FUNCTION_PORT_STATUS_GREEN (0x05) 296#define MPI3_MAN6_GPIO_FUNCTION_PORT_STATUS_YELLOW (0x06) 297#define MPI3_MAN6_GPIO_FUNCTION_CABLE_MANAGEMENT (0x07) 298#define MPI3_MAN6_GPIO_FUNCTION_BKPLANE_MGMT_TYPE (0x08) 299#define MPI3_MAN6_GPIO_FUNCTION_ISTWI_RESET (0x0a) 300#define MPI3_MAN6_GPIO_FUNCTION_BACKEND_PCIE_RESET (0x0b) 301#define MPI3_MAN6_GPIO_FUNCTION_GLOBAL_FAULT (0x0c) 302#define MPI3_MAN6_GPIO_FUNCTION_PBLP_STATUS_CHANGE (0x0d) 303#define MPI3_MAN6_GPIO_FUNCTION_EPACK_ONLINE (0x0e) 304#define MPI3_MAN6_GPIO_FUNCTION_EPACK_FAULT (0x0f) 305#define MPI3_MAN6_GPIO_FUNCTION_CTRL_TYPE (0x10) 306#define MPI3_MAN6_GPIO_FUNCTION_LICENSE (0x11) 307#define MPI3_MAN6_GPIO_FUNCTION_REFCLK_CONTROL (0x12) 308#define MPI3_MAN6_GPIO_FUNCTION_BACKEND_PCIE_RESET_CLAMP (0x13) 309#define MPI3_MAN6_GPIO_FUNCTION_AUXILIARY_POWER (0x14) 310#define MPI3_MAN6_GPIO_FUNCTION_RAID_DATA_CACHE_DIRTY (0x15) 311#define MPI3_MAN6_GPIO_FUNCTION_BOARD_FAN_CONTROL (0x16) 312#define MPI3_MAN6_GPIO_FUNCTION_BOARD_FAN_FAULT (0x17) 313#define MPI3_MAN6_GPIO_FUNCTION_POWER_BRAKE (0x18) 314#define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_MASK (0x01) 315#define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_ISTWI (0x00) 316#define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_RECEPTACLEID (0x01) 317#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_MASK (0xf0) 318#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_GENERIC (0x00) 319#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_CABLE_MGMT (0x10) 320#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_ACTIVE_CABLE_OVERCURRENT (0x20) 321#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_ACK_REQUIRED (0x02) 322#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_MASK (0x01) 323#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_EDGE (0x00) 324#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_LEVEL (0x01) 325#define MPI3_MAN6_GPIO_OVER_TEMP_PARAM1_LEVEL_WARNING (0x00) 326#define MPI3_MAN6_GPIO_OVER_TEMP_PARAM1_LEVEL_CRITICAL (0x01) 327#define MPI3_MAN6_GPIO_OVER_TEMP_PARAM1_LEVEL_FATAL (0x02) 328#define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ALL_UP (0x00) 329#define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ONE_OR_MORE_UP (0x01) 330#define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_MODULE_PRESENT (0x00) 331#define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_ACTIVE_CABLE_ENABLE (0x01) 332#define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_CABLE_MGMT_ENABLE (0x02) 333#define MPI3_MAN6_GPIO_LICENSE_PARAM1_TYPE_IBUTTON (0x00) 334#define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_MASK (0x0100) 335#define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_FAST_EDGE (0x0100) 336#define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_SLOW_EDGE (0x0000) 337#define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_MASK (0x00c0) 338#define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_100OHM (0x0000) 339#define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_66OHM (0x0040) 340#define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_50OHM (0x0080) 341#define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_33OHM (0x00c0) 342#define MPI3_MAN6_GPIO_FLAGS_ALT_DATA_SEL_MASK (0x0030) 343#define MPI3_MAN6_GPIO_FLAGS_ALT_DATA_SEL_SHIFT (4) 344#define MPI3_MAN6_GPIO_FLAGS_ACTIVE_HIGH (0x0008) 345#define MPI3_MAN6_GPIO_FLAGS_BI_DIR_ENABLED (0x0004) 346#define MPI3_MAN6_GPIO_FLAGS_DIRECTION_MASK (0x0003) 347#define MPI3_MAN6_GPIO_FLAGS_DIRECTION_INPUT (0x0000) 348#define MPI3_MAN6_GPIO_FLAGS_DIRECTION_OPEN_DRAIN_OUTPUT (0x0001) 349#define MPI3_MAN6_GPIO_FLAGS_DIRECTION_OPEN_SOURCE_OUTPUT (0x0002) 350#define MPI3_MAN6_GPIO_FLAGS_DIRECTION_PUSH_PULL_OUTPUT (0x0003) 351#ifndef MPI3_MAN6_GPIO_MAX 352#define MPI3_MAN6_GPIO_MAX (1) 353#endif 354struct mpi3_man_page6 { 355 struct mpi3_config_page_header header; 356 __le16 flags; 357 __le16 reserved0a; 358 u8 num_gpio; 359 u8 reserved0d[3]; 360 struct mpi3_man6_gpio_entry gpio[MPI3_MAN6_GPIO_MAX]; 361}; 362 363#define MPI3_MAN6_PAGEVERSION (0x00) 364#define MPI3_MAN6_FLAGS_HEARTBEAT_LED_DISABLED (0x0001) 365struct mpi3_man7_receptacle_info { 366 __le32 name[4]; 367 u8 location; 368 u8 connector_type; 369 u8 ped_clk; 370 u8 connector_id; 371 __le32 reserved14; 372}; 373 374#define MPI3_MAN7_LOCATION_UNKNOWN (0x00) 375#define MPI3_MAN7_LOCATION_INTERNAL (0x01) 376#define MPI3_MAN7_LOCATION_EXTERNAL (0x02) 377#define MPI3_MAN7_LOCATION_VIRTUAL (0x03) 378#define MPI3_MAN7_LOCATION_HOST (0x04) 379#define MPI3_MAN7_CONNECTOR_TYPE_NO_INFO (0x00) 380#define MPI3_MAN7_PEDCLK_ROUTING_MASK (0x10) 381#define MPI3_MAN7_PEDCLK_ROUTING_DIRECT (0x00) 382#define MPI3_MAN7_PEDCLK_ROUTING_CLOCK_BUFFER (0x10) 383#define MPI3_MAN7_PEDCLK_ID_MASK (0x0f) 384#ifndef MPI3_MAN7_RECEPTACLE_INFO_MAX 385#define MPI3_MAN7_RECEPTACLE_INFO_MAX (1) 386#endif 387struct mpi3_man_page7 { 388 struct mpi3_config_page_header header; 389 __le32 flags; 390 u8 num_receptacles; 391 u8 reserved0d[3]; 392 __le32 enclosure_name[4]; 393 struct mpi3_man7_receptacle_info receptacle_info[MPI3_MAN7_RECEPTACLE_INFO_MAX]; 394}; 395 396#define MPI3_MAN7_PAGEVERSION (0x00) 397#define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_MASK (0x01) 398#define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_0 (0x00) 399#define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_1 (0x01) 400struct mpi3_man8_phy_info { 401 u8 receptacle_id; 402 u8 connector_lane; 403 __le16 reserved02; 404 __le16 slotx1; 405 __le16 slotx2; 406 __le16 slotx4; 407 __le16 reserved0a; 408 __le32 reserved0c; 409}; 410 411#define MPI3_MAN8_PHY_INFO_RECEPTACLE_ID_NOT_ASSOCIATED (0xff) 412#define MPI3_MAN8_PHY_INFO_CONNECTOR_LANE_NOT_ASSOCIATED (0xff) 413#ifndef MPI3_MAN8_PHY_INFO_MAX 414#define MPI3_MAN8_PHY_INFO_MAX (1) 415#endif 416struct mpi3_man_page8 { 417 struct mpi3_config_page_header header; 418 __le32 reserved08; 419 u8 num_phys; 420 u8 reserved0d[3]; 421 struct mpi3_man8_phy_info phy_info[MPI3_MAN8_PHY_INFO_MAX]; 422}; 423 424#define MPI3_MAN8_PAGEVERSION (0x00) 425struct mpi3_man9_rsrc_entry { 426 __le32 maximum; 427 __le32 decrement; 428 __le32 minimum; 429 __le32 actual; 430}; 431 432enum mpi3_man9_resources { 433 MPI3_MAN9_RSRC_OUTSTANDING_REQS = 0, 434 MPI3_MAN9_RSRC_TARGET_CMDS = 1, 435 MPI3_MAN9_RSRC_RESERVED02 = 2, 436 MPI3_MAN9_RSRC_NVME = 3, 437 MPI3_MAN9_RSRC_INITIATORS = 4, 438 MPI3_MAN9_RSRC_VDS = 5, 439 MPI3_MAN9_RSRC_ENCLOSURES = 6, 440 MPI3_MAN9_RSRC_ENCLOSURE_PHYS = 7, 441 MPI3_MAN9_RSRC_EXPANDERS = 8, 442 MPI3_MAN9_RSRC_PCIE_SWITCHES = 9, 443 MPI3_MAN9_RSRC_RESERVED10 = 10, 444 MPI3_MAN9_RSRC_HOST_PD_DRIVES = 11, 445 MPI3_MAN9_RSRC_ADV_HOST_PD_DRIVES = 12, 446 MPI3_MAN9_RSRC_RAID_PD_DRIVES = 13, 447 MPI3_MAN9_RSRC_DRV_DIAG_BUF = 14, 448 MPI3_MAN9_RSRC_NAMESPACE_COUNT = 15, 449 MPI3_MAN9_RSRC_NUM_RESOURCES 450}; 451 452#define MPI3_MAN9_MIN_OUTSTANDING_REQS (1) 453#define MPI3_MAN9_MAX_OUTSTANDING_REQS (65000) 454#define MPI3_MAN9_MIN_TARGET_CMDS (0) 455#define MPI3_MAN9_MAX_TARGET_CMDS (65535) 456#define MPI3_MAN9_MIN_NVME_TARGETS (0) 457#define MPI3_MAN9_MIN_INITIATORS (0) 458#define MPI3_MAN9_MIN_VDS (0) 459#define MPI3_MAN9_MIN_ENCLOSURES (1) 460#define MPI3_MAN9_MAX_ENCLOSURES (65535) 461#define MPI3_MAN9_MIN_ENCLOSURE_PHYS (0) 462#define MPI3_MAN9_MIN_EXPANDERS (0) 463#define MPI3_MAN9_MAX_EXPANDERS (65535) 464#define MPI3_MAN9_MIN_PCIE_SWITCHES (0) 465#define MPI3_MAN9_MIN_HOST_PD_DRIVES (0) 466#define MPI3_MAN9_ADV_HOST_PD_DRIVES (0) 467#define MPI3_MAN9_RAID_PD_DRIVES (0) 468#define MPI3_MAN9_DRIVER_DIAG_BUFFER (0) 469#define MPI3_MAN9_MIN_NAMESPACE_COUNT (1) 470#define MPI3_MAN9_MIN_EXPANDERS (0) 471#define MPI3_MAN9_MAX_EXPANDERS (65535) 472struct mpi3_man_page9 { 473 struct mpi3_config_page_header header; 474 u8 num_resources; 475 u8 reserved09; 476 __le16 reserved0a; 477 __le32 reserved0c; 478 __le32 reserved10; 479 __le32 reserved14; 480 __le32 reserved18; 481 __le32 reserved1c; 482 struct mpi3_man9_rsrc_entry resource[MPI3_MAN9_RSRC_NUM_RESOURCES]; 483}; 484 485#define MPI3_MAN9_PAGEVERSION (0x00) 486struct mpi3_man10_istwi_ctrlr_entry { 487 __le16 target_address; 488 __le16 flags; 489 u8 scl_low_override; 490 u8 scl_high_override; 491 __le16 reserved06; 492}; 493 494#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_MASK (0x000c) 495#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_100K (0x0000) 496#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_400K (0x0004) 497#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_TARGET_ENABLED (0x0002) 498#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_INITIATOR_ENABLED (0x0001) 499#ifndef MPI3_MAN10_ISTWI_CTRLR_MAX 500#define MPI3_MAN10_ISTWI_CTRLR_MAX (1) 501#endif 502struct mpi3_man_page10 { 503 struct mpi3_config_page_header header; 504 __le32 reserved08; 505 u8 num_istwi_ctrl; 506 u8 reserved0d[3]; 507 struct mpi3_man10_istwi_ctrlr_entry istwi_controller[MPI3_MAN10_ISTWI_CTRLR_MAX]; 508}; 509 510#define MPI3_MAN10_PAGEVERSION (0x00) 511struct mpi3_man11_mux_device_format { 512 u8 max_channel; 513 u8 reserved01[3]; 514 __le32 reserved04; 515}; 516 517struct mpi3_man11_temp_sensor_device_format { 518 u8 type; 519 u8 reserved01[3]; 520 u8 temp_channel[4]; 521}; 522 523#define MPI3_MAN11_TEMP_SENSOR_TYPE_MAX6654 (0x00) 524#define MPI3_MAN11_TEMP_SENSOR_TYPE_EMC1442 (0x01) 525#define MPI3_MAN11_TEMP_SENSOR_TYPE_ADT7476 (0x02) 526#define MPI3_MAN11_TEMP_SENSOR_TYPE_SE97B (0x03) 527#define MPI3_MAN11_TEMP_SENSOR_CHANNEL_LOCATION_MASK (0xe0) 528#define MPI3_MAN11_TEMP_SENSOR_CHANNEL_LOCATION_SHIFT (5) 529#define MPI3_MAN11_TEMP_SENSOR_CHANNEL_ENABLED (0x01) 530struct mpi3_man11_seeprom_device_format { 531 u8 size; 532 u8 page_write_size; 533 __le16 reserved02; 534 __le32 reserved04; 535}; 536 537#define MPI3_MAN11_SEEPROM_SIZE_1KBITS (0x01) 538#define MPI3_MAN11_SEEPROM_SIZE_2KBITS (0x02) 539#define MPI3_MAN11_SEEPROM_SIZE_4KBITS (0x03) 540#define MPI3_MAN11_SEEPROM_SIZE_8KBITS (0x04) 541#define MPI3_MAN11_SEEPROM_SIZE_16KBITS (0x05) 542#define MPI3_MAN11_SEEPROM_SIZE_32KBITS (0x06) 543#define MPI3_MAN11_SEEPROM_SIZE_64KBITS (0x07) 544#define MPI3_MAN11_SEEPROM_SIZE_128KBITS (0x08) 545struct mpi3_man11_ddr_spd_device_format { 546 u8 channel; 547 u8 reserved01[3]; 548 __le32 reserved04; 549}; 550 551struct mpi3_man11_cable_mgmt_device_format { 552 u8 type; 553 u8 receptacle_id; 554 __le16 reserved02; 555 __le32 reserved04; 556}; 557 558#define MPI3_MAN11_CABLE_MGMT_TYPE_SFF_8636 (0x00) 559struct mpi3_man11_bkplane_spec_ubm_format { 560 __le16 flags; 561 __le16 reserved02; 562}; 563 564#define MPI3_MAN11_BKPLANE_UBM_FLAGS_REFCLK_POLICY_ALWAYS_ENABLED (0x0200) 565#define MPI3_MAN11_BKPLANE_UBM_FLAGS_FORCE_POLLING (0x0100) 566#define MPI3_MAN11_BKPLANE_UBM_FLAGS_MAX_FRU_MASK (0x00f0) 567#define MPI3_MAN11_BKPLANE_UBM_FLAGS_MAX_FRU_SHIFT (4) 568#define MPI3_MAN11_BKPLANE_UBM_FLAGS_POLL_INTERVAL_MASK (0x000f) 569#define MPI3_MAN11_BKPLANE_UBM_FLAGS_POLL_INTERVAL_SHIFT (0) 570struct mpi3_man11_bkplane_spec_non_ubm_format { 571 __le16 flags; 572 u8 reserved02; 573 u8 type; 574}; 575 576#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_GROUP_MASK (0xf000) 577#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_GROUP_SHIFT (12) 578#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_REFCLK_POLICY_ALWAYS_ENABLED (0x0200) 579#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_MASK (0x00c0) 580#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_4 (0x0000) 581#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_2 (0x0040) 582#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_1 (0x0080) 583#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_MASK (0x0030) 584#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_GPIO (0x0000) 585#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_REG (0x0010) 586#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_POLL_INTERVAL_MASK (0x000f) 587#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_POLL_INTERVAL_SHIFT (0) 588#define MPI3_MAN11_BKPLANE_NON_UBM_TYPE_VPP (0x00) 589union mpi3_man11_bkplane_spec_format { 590 struct mpi3_man11_bkplane_spec_ubm_format ubm; 591 struct mpi3_man11_bkplane_spec_non_ubm_format non_ubm; 592}; 593 594struct mpi3_man11_bkplane_mgmt_device_format { 595 u8 type; 596 u8 receptacle_id; 597 u8 reset_info; 598 u8 reserved03; 599 union mpi3_man11_bkplane_spec_format backplane_mgmt_specific; 600}; 601 602#define MPI3_MAN11_BKPLANE_MGMT_TYPE_UBM (0x00) 603#define MPI3_MAN11_BKPLANE_MGMT_TYPE_NON_UBM (0x01) 604#define MPI3_MAN11_BACKPLANE_RESETINFO_ASSERT_TIME_MASK (0xf0) 605#define MPI3_MAN11_BACKPLANE_RESETINFO_ASSERT_TIME_SHIFT (4) 606#define MPI3_MAN11_BACKPLANE_RESETINFO_READY_TIME_MASK (0x0f) 607#define MPI3_MAN11_BACKPLANE_RESETINFO_READY_TIME_SHIFT (0) 608struct mpi3_man11_gas_gauge_device_format { 609 u8 type; 610 u8 reserved01[3]; 611 __le32 reserved04; 612}; 613 614#define MPI3_MAN11_GAS_GAUGE_TYPE_STANDARD (0x00) 615struct mpi3_man11_mgmt_ctrlr_device_format { 616 __le32 reserved00; 617 __le32 reserved04; 618}; 619struct mpi3_man11_board_fan_device_format { 620 u8 flags; 621 u8 reserved01; 622 u8 min_fan_speed; 623 u8 max_fan_speed; 624 __le32 reserved04; 625}; 626#define MPI3_MAN11_BOARD_FAN_FLAGS_FAN_CTRLR_TYPE_MASK (0x07) 627#define MPI3_MAN11_BOARD_FAN_FLAGS_FAN_CTRLR_TYPE_AMC6821 (0x00) 628union mpi3_man11_device_specific_format { 629 struct mpi3_man11_mux_device_format mux; 630 struct mpi3_man11_temp_sensor_device_format temp_sensor; 631 struct mpi3_man11_seeprom_device_format seeprom; 632 struct mpi3_man11_ddr_spd_device_format ddr_spd; 633 struct mpi3_man11_cable_mgmt_device_format cable_mgmt; 634 struct mpi3_man11_bkplane_mgmt_device_format bkplane_mgmt; 635 struct mpi3_man11_gas_gauge_device_format gas_gauge; 636 struct mpi3_man11_mgmt_ctrlr_device_format mgmt_controller; 637 struct mpi3_man11_board_fan_device_format board_fan; 638 __le32 words[2]; 639}; 640struct mpi3_man11_istwi_device_format { 641 u8 device_type; 642 u8 controller; 643 u8 reserved02; 644 u8 flags; 645 __le16 device_address; 646 u8 mux_channel; 647 u8 mux_index; 648 union mpi3_man11_device_specific_format device_specific; 649}; 650 651#define MPI3_MAN11_ISTWI_DEVTYPE_MUX (0x00) 652#define MPI3_MAN11_ISTWI_DEVTYPE_TEMP_SENSOR (0x01) 653#define MPI3_MAN11_ISTWI_DEVTYPE_SEEPROM (0x02) 654#define MPI3_MAN11_ISTWI_DEVTYPE_DDR_SPD (0x03) 655#define MPI3_MAN11_ISTWI_DEVTYPE_CABLE_MGMT (0x04) 656#define MPI3_MAN11_ISTWI_DEVTYPE_BACKPLANE_MGMT (0x05) 657#define MPI3_MAN11_ISTWI_DEVTYPE_GAS_GAUGE (0x06) 658#define MPI3_MAN11_ISTWI_DEVTYPE_MGMT_CONTROLLER (0x07) 659#define MPI3_MAN11_ISTWI_DEVTYPE_BOARD_FAN (0x08) 660#define MPI3_MAN11_ISTWI_FLAGS_MUX_PRESENT (0x01) 661#ifndef MPI3_MAN11_ISTWI_DEVICE_MAX 662#define MPI3_MAN11_ISTWI_DEVICE_MAX (1) 663#endif 664struct mpi3_man_page11 { 665 struct mpi3_config_page_header header; 666 __le32 reserved08; 667 u8 num_istwi_dev; 668 u8 reserved0d[3]; 669 struct mpi3_man11_istwi_device_format istwi_device[MPI3_MAN11_ISTWI_DEVICE_MAX]; 670}; 671 672#define MPI3_MAN11_PAGEVERSION (0x00) 673#ifndef MPI3_MAN12_NUM_SGPIO_MAX 674#define MPI3_MAN12_NUM_SGPIO_MAX (1) 675#endif 676struct mpi3_man12_sgpio_info { 677 u8 slot_count; 678 u8 reserved01[3]; 679 __le32 reserved04; 680 u8 phy_order[32]; 681}; 682 683struct mpi3_man_page12 { 684 struct mpi3_config_page_header header; 685 __le32 flags; 686 __le32 s_clock_freq; 687 __le32 activity_modulation; 688 u8 num_sgpio; 689 u8 reserved15[3]; 690 __le32 reserved18; 691 __le32 reserved1c; 692 __le32 pattern[8]; 693 struct mpi3_man12_sgpio_info sgpio_info[MPI3_MAN12_NUM_SGPIO_MAX]; 694}; 695 696#define MPI3_MAN12_PAGEVERSION (0x00) 697#define MPI3_MAN12_FLAGS_ERROR_PRESENCE_ENABLED (0x0400) 698#define MPI3_MAN12_FLAGS_ACTIVITY_INVERT_ENABLED (0x0200) 699#define MPI3_MAN12_FLAGS_GROUP_ID_DISABLED (0x0100) 700#define MPI3_MAN12_FLAGS_SIO_CLK_FILTER_ENABLED (0x0004) 701#define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_MASK (0x0002) 702#define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_PUSH_PULL (0x0000) 703#define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_OPEN_DRAIN (0x0002) 704#define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_MASK (0x0001) 705#define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_PUSH_PULL (0x0000) 706#define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_OPEN_DRAIN (0x0001) 707#define MPI3_MAN12_SIO_CLK_FREQ_MIN (32) 708#define MPI3_MAN12_SIO_CLK_FREQ_MAX (100000) 709#define MPI3_MAN12_ACTIVITY_MODULATION_FORCE_OFF_MASK (0x0000f000) 710#define MPI3_MAN12_ACTIVITY_MODULATION_FORCE_OFF_SHIFT (12) 711#define MPI3_MAN12_ACTIVITY_MODULATION_MAX_ON_MASK (0x00000f00) 712#define MPI3_MAN12_ACTIVITY_MODULATION_MAX_ON_SHIFT (8) 713#define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_OFF_MASK (0x000000f0) 714#define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_OFF_SHIFT (4) 715#define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_ON_MASK (0x0000000f) 716#define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_ON_SHIFT (0) 717#define MPI3_MAN12_PATTERN_RATE_MASK (0xe0000000) 718#define MPI3_MAN12_PATTERN_RATE_2_HZ (0x00000000) 719#define MPI3_MAN12_PATTERN_RATE_4_HZ (0x20000000) 720#define MPI3_MAN12_PATTERN_RATE_8_HZ (0x40000000) 721#define MPI3_MAN12_PATTERN_RATE_16_HZ (0x60000000) 722#define MPI3_MAN12_PATTERN_RATE_10_HZ (0x80000000) 723#define MPI3_MAN12_PATTERN_RATE_20_HZ (0xa0000000) 724#define MPI3_MAN12_PATTERN_RATE_40_HZ (0xc0000000) 725#define MPI3_MAN12_PATTERN_LENGTH_MASK (0x1f000000) 726#define MPI3_MAN12_PATTERN_LENGTH_SHIFT (24) 727#define MPI3_MAN12_PATTERN_BIT_PATTERN_MASK (0x00ffffff) 728#define MPI3_MAN12_PATTERN_BIT_PATTERN_SHIFT (0) 729#ifndef MPI3_MAN13_NUM_TRANSLATION_MAX 730#define MPI3_MAN13_NUM_TRANSLATION_MAX (1) 731#endif 732struct mpi3_man13_translation_info { 733 __le32 slot_status; 734 __le32 mask; 735 u8 activity; 736 u8 locate; 737 u8 error; 738 u8 reserved0b; 739}; 740 741#define MPI3_MAN13_TRANSLATION_SLOTSTATUS_FAULT (0x20000000) 742#define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_OFF (0x10000000) 743#define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_ACTIVITY (0x00800000) 744#define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DO_NOT_REMOVE (0x00400000) 745#define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_MISSING (0x00100000) 746#define MPI3_MAN13_TRANSLATION_SLOTSTATUS_INSERT (0x00080000) 747#define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REMOVAL (0x00040000) 748#define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IDENTIFY (0x00020000) 749#define MPI3_MAN13_TRANSLATION_SLOTSTATUS_OK (0x00008000) 750#define MPI3_MAN13_TRANSLATION_SLOTSTATUS_RESERVED_DEVICE (0x00004000) 751#define MPI3_MAN13_TRANSLATION_SLOTSTATUS_HOT_SPARE (0x00002000) 752#define MPI3_MAN13_TRANSLATION_SLOTSTATUS_CONSISTENCY_CHECK (0x00001000) 753#define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IN_CRITICAL_ARRAY (0x00000800) 754#define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IN_FAILED_ARRAY (0x00000400) 755#define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REBUILD_REMAP (0x00000200) 756#define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REBUILD_REMAP_ABORT (0x00000100) 757#define MPI3_MAN13_TRANSLATION_SLOTSTATUS_PREDICTED_FAILURE (0x00000040) 758#define MPI3_MAN13_BLINK_PATTERN_FORCE_OFF (0x00) 759#define MPI3_MAN13_BLINK_PATTERN_FORCE_ON (0x01) 760#define MPI3_MAN13_BLINK_PATTERN_PATTERN_0 (0x02) 761#define MPI3_MAN13_BLINK_PATTERN_PATTERN_1 (0x03) 762#define MPI3_MAN13_BLINK_PATTERN_PATTERN_2 (0x04) 763#define MPI3_MAN13_BLINK_PATTERN_PATTERN_3 (0x05) 764#define MPI3_MAN13_BLINK_PATTERN_PATTERN_4 (0x06) 765#define MPI3_MAN13_BLINK_PATTERN_PATTERN_5 (0x07) 766#define MPI3_MAN13_BLINK_PATTERN_PATTERN_6 (0x08) 767#define MPI3_MAN13_BLINK_PATTERN_PATTERN_7 (0x09) 768#define MPI3_MAN13_BLINK_PATTERN_ACTIVITY (0x0a) 769#define MPI3_MAN13_BLINK_PATTERN_ACTIVITY_TRAIL (0x0b) 770struct mpi3_man_page13 { 771 struct mpi3_config_page_header header; 772 u8 num_trans; 773 u8 reserved09[3]; 774 __le32 reserved0c; 775 struct mpi3_man13_translation_info translation[MPI3_MAN13_NUM_TRANSLATION_MAX]; 776}; 777 778#define MPI3_MAN13_PAGEVERSION (0x00) 779struct mpi3_man_page14 { 780 struct mpi3_config_page_header header; 781 __le32 reserved08; 782 u8 num_slot_groups; 783 u8 num_slots; 784 __le16 max_cert_chain_length; 785 __le32 sealed_slots; 786 __le32 populated_slots; 787 __le32 mgmt_pt_updatable_slots; 788}; 789#define MPI3_MAN14_PAGEVERSION (0x00) 790#define MPI3_MAN14_NUMSLOTS_MAX (32) 791#ifndef MPI3_MAN15_VERSION_RECORD_MAX 792#define MPI3_MAN15_VERSION_RECORD_MAX 1 793#endif 794struct mpi3_man15_version_record { 795 __le16 spdm_version; 796 __le16 reserved02; 797}; 798 799struct mpi3_man_page15 { 800 struct mpi3_config_page_header header; 801 u8 num_version_records; 802 u8 reserved09[3]; 803 __le32 reserved0c; 804 struct mpi3_man15_version_record version_record[MPI3_MAN15_VERSION_RECORD_MAX]; 805}; 806 807#define MPI3_MAN15_PAGEVERSION (0x00) 808#ifndef MPI3_MAN16_CERT_ALGO_MAX 809#define MPI3_MAN16_CERT_ALGO_MAX 1 810#endif 811struct mpi3_man16_certificate_algorithm { 812 u8 slot_group; 813 u8 reserved01[3]; 814 __le32 base_asym_algo; 815 __le32 base_hash_algo; 816 __le32 reserved0c[3]; 817}; 818 819struct mpi3_man_page16 { 820 struct mpi3_config_page_header header; 821 __le32 reserved08; 822 u8 num_cert_algos; 823 u8 reserved0d[3]; 824 struct mpi3_man16_certificate_algorithm certificate_algorithm[MPI3_MAN16_CERT_ALGO_MAX]; 825}; 826 827#define MPI3_MAN16_PAGEVERSION (0x00) 828#ifndef MPI3_MAN17_HASH_ALGORITHM_MAX 829#define MPI3_MAN17_HASH_ALGORITHM_MAX 1 830#endif 831struct mpi3_man17_hash_algorithm { 832 u8 meas_specification; 833 u8 reserved01[3]; 834 __le32 measurement_hash_algo; 835 __le32 reserved08[2]; 836}; 837 838struct mpi3_man_page17 { 839 struct mpi3_config_page_header header; 840 __le32 reserved08; 841 u8 num_hash_algos; 842 u8 reserved0d[3]; 843 struct mpi3_man17_hash_algorithm hash_algorithm[MPI3_MAN17_HASH_ALGORITHM_MAX]; 844}; 845 846#define MPI3_MAN17_PAGEVERSION (0x00) 847struct mpi3_man_page20 { 848 struct mpi3_config_page_header header; 849 __le32 reserved08; 850 __le32 nonpremium_features; 851 u8 allowed_personalities; 852 u8 reserved11[3]; 853}; 854 855#define MPI3_MAN20_PAGEVERSION (0x00) 856#define MPI3_MAN20_ALLOWEDPERSON_RAID_MASK (0x02) 857#define MPI3_MAN20_ALLOWEDPERSON_RAID_ALLOWED (0x02) 858#define MPI3_MAN20_ALLOWEDPERSON_RAID_NOT_ALLOWED (0x00) 859#define MPI3_MAN20_ALLOWEDPERSON_EHBA_MASK (0x01) 860#define MPI3_MAN20_ALLOWEDPERSON_EHBA_ALLOWED (0x01) 861#define MPI3_MAN20_ALLOWEDPERSON_EHBA_NOT_ALLOWED (0x00) 862#define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_MASK (0x01) 863#define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_ENABLED (0x00) 864#define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_DISABLED (0x01) 865struct mpi3_man_page21 { 866 struct mpi3_config_page_header header; 867 __le32 reserved08; 868 __le32 flags; 869}; 870 871#define MPI3_MAN21_PAGEVERSION (0x00) 872#define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_MASK (0x00000060) 873#define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_BLOCK (0x00000000) 874#define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_ALLOW (0x00000020) 875#define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_WARN (0x00000040) 876#define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_MASK (0x00000008) 877#define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_ALLOW (0x00000000) 878#define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_PREVENT (0x00000008) 879#define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_MASK (0x00000001) 880#define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_DEFAULT (0x00000000) 881#define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_OEM_SPECIFIC (0x00000001) 882#ifndef MPI3_MAN_PROD_SPECIFIC_MAX 883#define MPI3_MAN_PROD_SPECIFIC_MAX (1) 884#endif 885struct mpi3_man_page_product_specific { 886 struct mpi3_config_page_header header; 887 __le32 product_specific_info[MPI3_MAN_PROD_SPECIFIC_MAX]; 888}; 889 890struct mpi3_io_unit_page0 { 891 struct mpi3_config_page_header header; 892 __le64 unique_value; 893 __le32 nvdata_version_default; 894 __le32 nvdata_version_persistent; 895}; 896 897#define MPI3_IOUNIT0_PAGEVERSION (0x00) 898struct mpi3_io_unit_page1 { 899 struct mpi3_config_page_header header; 900 __le32 flags; 901 u8 dmd_io_delay; 902 u8 dmd_report_pcie; 903 u8 dmd_report_sata; 904 u8 dmd_report_sas; 905}; 906 907#define MPI3_IOUNIT1_PAGEVERSION (0x00) 908#define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_MASK (0x00000030) 909#define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_ENABLE (0x00000000) 910#define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_DISABLE (0x00000010) 911#define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_NO_MODIFY (0x00000020) 912#define MPI3_IOUNIT1_FLAGS_ATA_SECURITY_FREEZE_LOCK (0x00000008) 913#define MPI3_IOUNIT1_FLAGS_WRITE_SAME_BUFFER (0x00000004) 914#define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_MASK (0x00000003) 915#define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_ENABLE (0x00000000) 916#define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_DISABLE (0x00000001) 917#define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_UNCHANGED (0x00000002) 918#define MPI3_IOUNIT1_DMD_REPORT_DELAY_TIME_MASK (0x7f) 919#define MPI3_IOUNIT1_DMD_REPORT_UNIT_16_SEC (0x80) 920#ifndef MPI3_IO_UNIT2_GPIO_VAL_MAX 921#define MPI3_IO_UNIT2_GPIO_VAL_MAX (1) 922#endif 923struct mpi3_io_unit_page2 { 924 struct mpi3_config_page_header header; 925 u8 gpio_count; 926 u8 reserved09[3]; 927 __le16 gpio_val[MPI3_IO_UNIT2_GPIO_VAL_MAX]; 928}; 929 930#define MPI3_IOUNIT2_PAGEVERSION (0x00) 931#define MPI3_IOUNIT2_GPIO_FUNCTION_MASK (0xfffc) 932#define MPI3_IOUNIT2_GPIO_FUNCTION_SHIFT (2) 933#define MPI3_IOUNIT2_GPIO_SETTING_MASK (0x0001) 934#define MPI3_IOUNIT2_GPIO_SETTING_OFF (0x0000) 935#define MPI3_IOUNIT2_GPIO_SETTING_ON (0x0001) 936struct mpi3_io_unit3_sensor { 937 __le16 flags; 938 u8 threshold_margin; 939 u8 reserved03; 940 __le16 threshold[3]; 941 __le16 reserved0a; 942 __le32 reserved0c; 943 __le32 reserved10; 944 __le32 reserved14; 945}; 946 947#define MPI3_IOUNIT3_SENSOR_FLAGS_FATAL_EVENT_ENABLED (0x0010) 948#define MPI3_IOUNIT3_SENSOR_FLAGS_FATAL_ACTION_ENABLED (0x0008) 949#define MPI3_IOUNIT3_SENSOR_FLAGS_CRITICAL_EVENT_ENABLED (0x0004) 950#define MPI3_IOUNIT3_SENSOR_FLAGS_CRITICAL_ACTION_ENABLED (0x0002) 951#define MPI3_IOUNIT3_SENSOR_FLAGS_WARNING_EVENT_ENABLED (0x0001) 952#ifndef MPI3_IO_UNIT3_SENSOR_MAX 953#define MPI3_IO_UNIT3_SENSOR_MAX (1) 954#endif 955struct mpi3_io_unit_page3 { 956 struct mpi3_config_page_header header; 957 __le32 reserved08; 958 u8 num_sensors; 959 u8 nominal_poll_interval; 960 u8 warning_poll_interval; 961 u8 reserved0f; 962 struct mpi3_io_unit3_sensor sensor[MPI3_IO_UNIT3_SENSOR_MAX]; 963}; 964 965#define MPI3_IOUNIT3_PAGEVERSION (0x00) 966struct mpi3_io_unit4_sensor { 967 __le16 current_temperature; 968 __le16 reserved02; 969 u8 flags; 970 u8 reserved05[3]; 971 __le16 istwi_index; 972 u8 channel; 973 u8 reserved0b; 974 __le32 reserved0c; 975}; 976 977#define MPI3_IOUNIT4_SENSOR_FLAGS_LOC_MASK (0xe0) 978#define MPI3_IOUNIT4_SENSOR_FLAGS_LOC_SHIFT (5) 979#define MPI3_IOUNIT4_SENSOR_FLAGS_TEMP_VALID (0x01) 980#define MPI3_IOUNIT4_SENSOR_ISTWI_INDEX_INTERNAL (0xffff) 981#define MPI3_IOUNIT4_SENSOR_CHANNEL_RESERVED (0xff) 982#ifndef MPI3_IO_UNIT4_SENSOR_MAX 983#define MPI3_IO_UNIT4_SENSOR_MAX (1) 984#endif 985struct mpi3_io_unit_page4 { 986 struct mpi3_config_page_header header; 987 __le32 reserved08; 988 u8 num_sensors; 989 u8 reserved0d[3]; 990 struct mpi3_io_unit4_sensor sensor[MPI3_IO_UNIT4_SENSOR_MAX]; 991}; 992 993#define MPI3_IOUNIT4_PAGEVERSION (0x00) 994struct mpi3_io_unit5_spinup_group { 995 u8 max_target_spinup; 996 u8 spinup_delay; 997 u8 spinup_flags; 998 u8 reserved03; 999}; 1000 1001#define MPI3_IOUNIT5_SPINUP_FLAGS_DISABLE (0x01) 1002#ifndef MPI3_IO_UNIT5_PHY_MAX 1003#define MPI3_IO_UNIT5_PHY_MAX (4) 1004#endif 1005struct mpi3_io_unit_page5 { 1006 struct mpi3_config_page_header header; 1007 struct mpi3_io_unit5_spinup_group spinup_group_parameters[4]; 1008 __le32 reserved18; 1009 __le32 reserved1c; 1010 __le16 device_shutdown; 1011 __le16 reserved22; 1012 u8 pcie_device_wait_time; 1013 u8 sata_device_wait_time; 1014 u8 spinup_encl_drive_count; 1015 u8 spinup_encl_delay; 1016 u8 num_phys; 1017 u8 pe_initial_spinup_delay; 1018 u8 topology_stable_time; 1019 u8 flags; 1020 u8 phy[MPI3_IO_UNIT5_PHY_MAX]; 1021}; 1022 1023#define MPI3_IOUNIT5_PAGEVERSION (0x00) 1024#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NO_ACTION (0x00) 1025#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_ATTACHED (0x01) 1026#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_EXPANDER_ATTACHED (0x02) 1027#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SWITCH_ATTACHED (0x02) 1028#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_AND_EXPANDER (0x03) 1029#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_AND_SWITCH (0x03) 1030#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_HDD_MASK (0x0300) 1031#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_HDD_SHIFT (8) 1032#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_HDD_MASK (0x00c0) 1033#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_HDD_SHIFT (6) 1034#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NVME_SSD_MASK (0x0030) 1035#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NVME_SSD_SHIFT (4) 1036#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_SSD_MASK (0x000c) 1037#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_SSD_SHIFT (2) 1038#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_SSD_MASK (0x0003) 1039#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_SSD_SHIFT (0) 1040#define MPI3_IOUNIT5_FLAGS_SATAPUIS_MASK (0x0c) 1041#define MPI3_IOUNIT5_FLAGS_SATAPUIS_NOT_SUPPORTED (0x00) 1042#define MPI3_IOUNIT5_FLAGS_SATAPUIS_OS_CONTROLLED (0x04) 1043#define MPI3_IOUNIT5_FLAGS_SATAPUIS_APP_CONTROLLED (0x08) 1044#define MPI3_IOUNIT5_FLAGS_SATAPUIS_BLOCKED (0x0c) 1045#define MPI3_IOUNIT5_FLAGS_POWER_CAPABLE_SPINUP (0x02) 1046#define MPI3_IOUNIT5_FLAGS_AUTO_PORT_ENABLE (0x01) 1047#define MPI3_IOUNIT5_PHY_SPINUP_GROUP_MASK (0x03) 1048struct mpi3_io_unit_page6 { 1049 struct mpi3_config_page_header header; 1050 __le32 board_power_requirement; 1051 __le32 pci_slot_power_allocation; 1052 u8 flags; 1053 u8 reserved11[3]; 1054}; 1055 1056#define MPI3_IOUNIT6_PAGEVERSION (0x00) 1057#define MPI3_IOUNIT6_FLAGS_ACT_CABLE_PWR_EXC (0x01) 1058#ifndef MPI3_IOUNIT8_DIGEST_MAX 1059#define MPI3_IOUNIT8_DIGEST_MAX (1) 1060#endif 1061union mpi3_iounit8_digest { 1062 __le32 dword[16]; 1063 __le16 word[32]; 1064 u8 byte[64]; 1065}; 1066 1067struct mpi3_io_unit_page8 { 1068 struct mpi3_config_page_header header; 1069 u8 sb_mode; 1070 u8 sb_state; 1071 __le16 reserved0a; 1072 u8 num_slots; 1073 u8 slots_available; 1074 u8 current_key_encryption_algo; 1075 u8 key_digest_hash_algo; 1076 union mpi3_version_union current_svn; 1077 __le32 reserved14; 1078 __le32 current_key[128]; 1079 union mpi3_iounit8_digest digest[MPI3_IOUNIT8_DIGEST_MAX]; 1080}; 1081 1082#define MPI3_IOUNIT8_PAGEVERSION (0x00) 1083#define MPI3_IOUNIT8_SBMODE_SECURE_DEBUG (0x04) 1084#define MPI3_IOUNIT8_SBMODE_HARD_SECURE (0x02) 1085#define MPI3_IOUNIT8_SBMODE_CONFIG_SECURE (0x01) 1086#define MPI3_IOUNIT8_SBSTATE_SVN_UPDATE_PENDING (0x04) 1087#define MPI3_IOUNIT8_SBSTATE_KEY_UPDATE_PENDING (0x02) 1088#define MPI3_IOUNIT8_SBSTATE_SECURE_BOOT_ENABLED (0x01) 1089#define MPI3_IOUNIT8_SBMODE_CURRENT_KEY_IOUNIT17 (0x10) 1090#define MPI3_IOUNIT8_SBMODE_HARD_SECURE_RECERTIFIED (0x08) 1091struct mpi3_io_unit_page9 { 1092 struct mpi3_config_page_header header; 1093 __le32 flags; 1094 __le16 first_device; 1095 __le16 reserved0e; 1096}; 1097 1098#define MPI3_IOUNIT9_PAGEVERSION (0x00) 1099#define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_MASK (0x00000006) 1100#define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_SHIFT (1) 1101#define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_NONE (0x00000000) 1102#define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_RECEPTACLE (0x00000002) 1103#define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_BACKPLANE_TYPE (0x00000004) 1104#define MPI3_IOUNIT9_FLAGS_VDFIRST_ENABLED (0x00000001) 1105#define MPI3_IOUNIT9_FIRSTDEVICE_UNKNOWN (0xffff) 1106#define MPI3_IOUNIT9_FIRSTDEVICE_IN_DRIVER_PAGE_0 (0xfffe) 1107 1108struct mpi3_io_unit_page10 { 1109 struct mpi3_config_page_header header; 1110 u8 flags; 1111 u8 reserved09[3]; 1112 __le32 silicon_id; 1113 u8 fw_version_minor; 1114 u8 fw_version_major; 1115 u8 hw_version_minor; 1116 u8 hw_version_major; 1117 u8 part_number[16]; 1118}; 1119#define MPI3_IOUNIT10_PAGEVERSION (0x00) 1120#define MPI3_IOUNIT10_FLAGS_VALID (0x01) 1121#define MPI3_IOUNIT10_FLAGS_ACTIVEID_MASK (0x02) 1122#define MPI3_IOUNIT10_FLAGS_ACTIVEID_FIRST_REGION (0x00) 1123#define MPI3_IOUNIT10_FLAGS_ACTIVEID_SECOND_REGION (0x02) 1124#define MPI3_IOUNIT10_FLAGS_PBLP_EXPECTED (0x80) 1125#ifndef MPI3_IOUNIT11_PROFILE_MAX 1126#define MPI3_IOUNIT11_PROFILE_MAX (1) 1127#endif 1128struct mpi3_iounit11_profile { 1129 u8 profile_identifier; 1130 u8 reserved01[3]; 1131 __le16 max_vds; 1132 __le16 max_host_pds; 1133 __le16 max_adv_host_pds; 1134 __le16 max_raid_pds; 1135 __le16 max_nvme; 1136 __le16 max_outstanding_requests; 1137 __le16 subsystem_id; 1138 __le16 reserved12; 1139 __le32 reserved14[2]; 1140}; 1141struct mpi3_io_unit_page11 { 1142 struct mpi3_config_page_header header; 1143 __le32 reserved08; 1144 u8 num_profiles; 1145 u8 current_profile_identifier; 1146 __le16 reserved0e; 1147 struct mpi3_iounit11_profile profile[MPI3_IOUNIT11_PROFILE_MAX]; 1148}; 1149#define MPI3_IOUNIT11_PAGEVERSION (0x00) 1150#ifndef MPI3_IOUNIT12_BUCKET_MAX 1151#define MPI3_IOUNIT12_BUCKET_MAX (1) 1152#endif 1153struct mpi3_iounit12_bucket { 1154 u8 coalescing_depth; 1155 u8 coalescing_timeout; 1156 __le16 io_count_low_boundary; 1157 __le32 reserved04; 1158}; 1159struct mpi3_io_unit_page12 { 1160 struct mpi3_config_page_header header; 1161 __le32 flags; 1162 __le32 reserved0c[4]; 1163 u8 num_buckets; 1164 u8 reserved1d[3]; 1165 struct mpi3_iounit12_bucket bucket[MPI3_IOUNIT12_BUCKET_MAX]; 1166}; 1167#define MPI3_IOUNIT12_PAGEVERSION (0x00) 1168#define MPI3_IOUNIT12_FLAGS_NUMPASSES_MASK (0x00000300) 1169#define MPI3_IOUNIT12_FLAGS_NUMPASSES_SHIFT (8) 1170#define MPI3_IOUNIT12_FLAGS_NUMPASSES_8 (0x00000000) 1171#define MPI3_IOUNIT12_FLAGS_NUMPASSES_16 (0x00000100) 1172#define MPI3_IOUNIT12_FLAGS_NUMPASSES_32 (0x00000200) 1173#define MPI3_IOUNIT12_FLAGS_NUMPASSES_64 (0x00000300) 1174#define MPI3_IOUNIT12_FLAGS_PASSPERIOD_MASK (0x00000003) 1175#define MPI3_IOUNIT12_FLAGS_PASSPERIOD_DISABLED (0x00000000) 1176#define MPI3_IOUNIT12_FLAGS_PASSPERIOD_500US (0x00000001) 1177#define MPI3_IOUNIT12_FLAGS_PASSPERIOD_1MS (0x00000002) 1178#define MPI3_IOUNIT12_FLAGS_PASSPERIOD_2MS (0x00000003) 1179#ifndef MPI3_IOUNIT13_FUNC_MAX 1180#define MPI3_IOUNIT13_FUNC_MAX (1) 1181#endif 1182struct mpi3_iounit13_allowed_function { 1183 __le16 sub_function; 1184 u8 function_code; 1185 u8 function_flags; 1186}; 1187#define MPI3_IOUNIT13_FUNCTION_FLAGS_ADMIN_BLOCKED (0x04) 1188#define MPI3_IOUNIT13_FUNCTION_FLAGS_OOB_BLOCKED (0x02) 1189#define MPI3_IOUNIT13_FUNCTION_FLAGS_CHECK_SUBFUNCTION_ENABLED (0x01) 1190struct mpi3_io_unit_page13 { 1191 struct mpi3_config_page_header header; 1192 __le16 flags; 1193 __le16 reserved0a; 1194 u8 num_allowed_functions; 1195 u8 reserved0d[3]; 1196 struct mpi3_iounit13_allowed_function allowed_function[MPI3_IOUNIT13_FUNC_MAX]; 1197}; 1198#define MPI3_IOUNIT13_PAGEVERSION (0x00) 1199#define MPI3_IOUNIT13_FLAGS_ADMIN_BLOCKED (0x0002) 1200#define MPI3_IOUNIT13_FLAGS_OOB_BLOCKED (0x0001) 1201#ifndef MPI3_IOUNIT14_MD_MAX 1202#define MPI3_IOUNIT14_MD_MAX (1) 1203#endif 1204struct mpi3_iounit14_pagemetadata { 1205 u8 page_type; 1206 u8 page_number; 1207 u8 reserved02; 1208 u8 page_flags; 1209}; 1210#define MPI3_IOUNIT14_PAGEMETADATA_PAGEFLAGS_OOBWRITE_ALLOWED (0x02) 1211#define MPI3_IOUNIT14_PAGEMETADATA_PAGEFLAGS_HOSTWRITE_ALLOWED (0x01) 1212struct mpi3_io_unit_page14 { 1213 struct mpi3_config_page_header header; 1214 u8 flags; 1215 u8 reserved09[3]; 1216 u8 num_pages; 1217 u8 reserved0d[3]; 1218 struct mpi3_iounit14_pagemetadata page_metadata[MPI3_IOUNIT14_MD_MAX]; 1219}; 1220#define MPI3_IOUNIT14_PAGEVERSION (0x00) 1221#define MPI3_IOUNIT14_FLAGS_READONLY (0x01) 1222#ifndef MPI3_IOUNIT15_PBD_MAX 1223#define MPI3_IOUNIT15_PBD_MAX (1) 1224#endif 1225struct mpi3_io_unit_page15 { 1226 struct mpi3_config_page_header header; 1227 u8 flags; 1228 u8 reserved09[3]; 1229 __le32 reserved0c; 1230 u8 power_budgeting_capability; 1231 u8 reserved11[3]; 1232 u8 num_power_budget_data; 1233 u8 reserved15[3]; 1234 __le32 power_budget_data[MPI3_IOUNIT15_PBD_MAX]; 1235}; 1236#define MPI3_IOUNIT15_PAGEVERSION (0x00) 1237#define MPI3_IOUNIT15_FLAGS_EPRINIT_INITREQUIRED (0x04) 1238#define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_MASK (0x03) 1239#define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_NOT_SUPPORTED (0x00) 1240#define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_WITHOUT_POWER_BRAKE_GPIO (0x01) 1241#define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_WITH_POWER_BRAKE_GPIO (0x02) 1242#define MPI3_IOUNIT15_NUMPOWERBUDGETDATA_POWER_BUDGETING_DISABLED (0x00) 1243 1244struct mpi3_io_unit_page17 { 1245 struct mpi3_config_page_header header; 1246 u8 num_instances; 1247 u8 instance; 1248 __le16 reserved0a; 1249 __le32 reserved0c[4]; 1250 __le16 key_length; 1251 u8 encryption_algorithm; 1252 u8 reserved1f; 1253 __le32 current_key[]; 1254}; 1255#define MPI3_IOUNIT17_PAGEVERSION (0x00) 1256struct mpi3_io_unit_page18 { 1257 struct mpi3_config_page_header header; 1258 u8 flags; 1259 u8 poll_interval; 1260 __le16 reserved0a; 1261 __le32 reserved0c; 1262}; 1263 1264#define MPI3_IOUNIT18_PAGEVERSION (0x00) 1265#define MPI3_IOUNIT18_FLAGS_DIRECTATTACHED_ENABLE (0x01) 1266#define MPI3_IOUNIT18_POLLINTERVAL_DISABLE (0x00) 1267#ifndef MPI3_IOUNIT19_DEVICE_MAX 1268#define MPI3_IOUNIT19_DEVICE_MAX (1) 1269#endif 1270struct mpi3_iounit19_device { 1271 __le16 temperature; 1272 __le16 dev_handle; 1273 __le16 persistent_id; 1274 __le16 reserved06; 1275}; 1276 1277#define MPI3_IOUNIT19_DEVICE_TEMPERATURE_UNAVAILABLE (0x8000) 1278struct mpi3_io_unit_page19 { 1279 struct mpi3_config_page_header header; 1280 __le16 num_devices; 1281 __le16 reserved0a; 1282 __le32 reserved0c; 1283 struct mpi3_iounit19_device device[MPI3_IOUNIT19_DEVICE_MAX]; 1284}; 1285 1286#define MPI3_IOUNIT19_PAGEVERSION (0x00) 1287struct mpi3_ioc_page0 { 1288 struct mpi3_config_page_header header; 1289 __le32 reserved08; 1290 __le16 vendor_id; 1291 __le16 device_id; 1292 u8 revision_id; 1293 u8 reserved11[3]; 1294 __le32 class_code; 1295 __le16 subsystem_vendor_id; 1296 __le16 subsystem_id; 1297}; 1298 1299#define MPI3_IOC0_PAGEVERSION (0x00) 1300struct mpi3_ioc_page1 { 1301 struct mpi3_config_page_header header; 1302 __le32 coalescing_timeout; 1303 u8 coalescing_depth; 1304 u8 obsolete; 1305 __le16 reserved0e; 1306}; 1307#define MPI3_IOC1_PAGEVERSION (0x00) 1308#ifndef MPI3_IOC2_EVENTMASK_WORDS 1309#define MPI3_IOC2_EVENTMASK_WORDS (4) 1310#endif 1311struct mpi3_ioc_page2 { 1312 struct mpi3_config_page_header header; 1313 __le32 reserved08; 1314 __le16 sas_broadcast_primitive_masks; 1315 __le16 sas_notify_primitive_masks; 1316 __le32 event_masks[MPI3_IOC2_EVENTMASK_WORDS]; 1317}; 1318 1319#define MPI3_IOC2_PAGEVERSION (0x00) 1320#define MPI3_DRIVER_FLAGS_ADMINRAIDPD_BLOCKED (0x0010) 1321#define MPI3_DRIVER_FLAGS_OOBRAIDPD_BLOCKED (0x0008) 1322#define MPI3_DRIVER_FLAGS_OOBRAIDVD_BLOCKED (0x0004) 1323#define MPI3_DRIVER_FLAGS_OOBADVHOSTPD_BLOCKED (0x0002) 1324#define MPI3_DRIVER_FLAGS_OOBHOSTPD_BLOCKED (0x0001) 1325struct mpi3_allowed_cmd_scsi { 1326 __le16 service_action; 1327 u8 operation_code; 1328 u8 command_flags; 1329}; 1330 1331struct mpi3_allowed_cmd_ata { 1332 u8 subcommand; 1333 u8 reserved01; 1334 u8 command; 1335 u8 command_flags; 1336}; 1337 1338struct mpi3_allowed_cmd_nvme { 1339 u8 reserved00; 1340 u8 nvme_cmd_flags; 1341 u8 op_code; 1342 u8 command_flags; 1343}; 1344 1345#define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_MASK (0x80) 1346#define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_IO (0x00) 1347#define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_ADMIN (0x80) 1348#define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_CMDSET_MASK (0x3f) 1349#define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_CMDSET_NVM (0x00) 1350union mpi3_allowed_cmd { 1351 struct mpi3_allowed_cmd_scsi scsi; 1352 struct mpi3_allowed_cmd_ata ata; 1353 struct mpi3_allowed_cmd_nvme nvme; 1354}; 1355 1356#define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_ADMINRAIDPD_BLOCKED (0x20) 1357#define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBRAIDPD_BLOCKED (0x10) 1358#define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBRAIDVD_BLOCKED (0x08) 1359#define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBADVHOSTPD_BLOCKED (0x04) 1360#define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBHOSTPD_BLOCKED (0x02) 1361#define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_CHECKSUBCMD_ENABLED (0x01) 1362#ifndef MPI3_ALLOWED_CMDS_MAX 1363#define MPI3_ALLOWED_CMDS_MAX (1) 1364#endif 1365struct mpi3_driver_page0 { 1366 struct mpi3_config_page_header header; 1367 __le32 bsd_options; 1368 u8 ssu_timeout; 1369 u8 io_timeout; 1370 u8 tur_retries; 1371 u8 tur_interval; 1372 u8 reserved10; 1373 u8 security_key_timeout; 1374 __le16 first_device; 1375 __le32 reserved14; 1376 __le32 reserved18; 1377}; 1378#define MPI3_DRIVER0_PAGEVERSION (0x00) 1379#define MPI3_DRIVER0_BSDOPTS_DEVICEEXPOSURE_DISABLE (0x00000020) 1380#define MPI3_DRIVER0_BSDOPTS_WRITECACHE_DISABLE (0x00000010) 1381#define MPI3_DRIVER0_BSDOPTS_HEADLESS_MODE_ENABLE (0x00000008) 1382#define MPI3_DRIVER0_BSDOPTS_DIS_HII_CONFIG_UTIL (0x00000004) 1383#define MPI3_DRIVER0_BSDOPTS_REGISTRATION_MASK (0x00000003) 1384#define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_AND_DEVS (0x00000000) 1385#define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_ONLY (0x00000001) 1386#define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_AND_INTERNAL_DEVS (0x00000002) 1387#define MPI3_DRIVER0_FIRSTDEVICE_IGNORE1 (0x0000) 1388#define MPI3_DRIVER0_FIRSTDEVICE_IGNORE2 (0xffff) 1389struct mpi3_driver_page1 { 1390 struct mpi3_config_page_header header; 1391 __le32 flags; 1392 u8 time_stamp_update; 1393 u8 reserved0d[3]; 1394 __le16 host_diag_trace_max_size; 1395 __le16 host_diag_trace_min_size; 1396 __le16 host_diag_trace_decrement_size; 1397 __le16 reserved16; 1398 __le16 host_diag_fw_max_size; 1399 __le16 host_diag_fw_min_size; 1400 __le16 host_diag_fw_decrement_size; 1401 __le16 reserved1e; 1402 __le16 host_diag_driver_max_size; 1403 __le16 host_diag_driver_min_size; 1404 __le16 host_diag_driver_decrement_size; 1405 __le16 reserved26; 1406}; 1407 1408#define MPI3_DRIVER1_PAGEVERSION (0x00) 1409#ifndef MPI3_DRIVER2_TRIGGER_MAX 1410#define MPI3_DRIVER2_TRIGGER_MAX (1) 1411#endif 1412struct mpi3_driver2_trigger_event { 1413 u8 type; 1414 u8 flags; 1415 u8 reserved02; 1416 u8 event; 1417 __le32 reserved04[3]; 1418}; 1419 1420struct mpi3_driver2_trigger_scsi_sense { 1421 u8 type; 1422 u8 flags; 1423 __le16 reserved02; 1424 u8 ascq; 1425 u8 asc; 1426 u8 sense_key; 1427 u8 reserved07; 1428 __le32 reserved08[2]; 1429}; 1430 1431#define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_ASCQ_MATCH_ALL (0xff) 1432#define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_ASC_MATCH_ALL (0xff) 1433#define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_SENSE_KEY_MATCH_ALL (0xff) 1434struct mpi3_driver2_trigger_reply { 1435 u8 type; 1436 u8 flags; 1437 __le16 ioc_status; 1438 __le32 ioc_log_info; 1439 __le32 ioc_log_info_mask; 1440 __le32 reserved0c; 1441}; 1442 1443#define MPI3_DRIVER2_TRIGGER_REPLY_IOCSTATUS_MATCH_ALL (0xffff) 1444union mpi3_driver2_trigger_element { 1445 struct mpi3_driver2_trigger_event event; 1446 struct mpi3_driver2_trigger_scsi_sense scsi_sense; 1447 struct mpi3_driver2_trigger_reply reply; 1448}; 1449 1450#define MPI3_DRIVER2_TRIGGER_TYPE_EVENT (0x00) 1451#define MPI3_DRIVER2_TRIGGER_TYPE_SCSI_SENSE (0x01) 1452#define MPI3_DRIVER2_TRIGGER_TYPE_REPLY (0x02) 1453#define MPI3_DRIVER2_TRIGGER_FLAGS_DIAG_TRACE_RELEASE (0x02) 1454#define MPI3_DRIVER2_TRIGGER_FLAGS_DIAG_FW_RELEASE (0x01) 1455struct mpi3_driver_page2 { 1456 struct mpi3_config_page_header header; 1457 __le64 global_trigger; 1458 __le32 reserved10[3]; 1459 u8 num_triggers; 1460 u8 reserved1d[3]; 1461 union mpi3_driver2_trigger_element trigger[MPI3_DRIVER2_TRIGGER_MAX]; 1462}; 1463 1464#define MPI3_DRIVER2_PAGEVERSION (0x00) 1465#define MPI3_DRIVER2_GLOBALTRIGGER_DIAG_TRACE_RELEASE (0x8000000000000000ULL) 1466#define MPI3_DRIVER2_GLOBALTRIGGER_DIAG_FW_RELEASE (0x4000000000000000ULL) 1467#define MPI3_DRIVER2_GLOBALTRIGGER_SNAPDUMP_ENABLED (0x2000000000000000ULL) 1468#define MPI3_DRIVER2_GLOBALTRIGGER_POST_DIAG_TRACE_DISABLED (0x1000000000000000ULL) 1469#define MPI3_DRIVER2_GLOBALTRIGGER_POST_DIAG_FW_DISABLED (0x0800000000000000ULL) 1470#define MPI3_DRIVER2_GLOBALTRIGGER_DEVICE_REMOVAL_ENABLED (0x0000000000000004ULL) 1471#define MPI3_DRIVER2_GLOBALTRIGGER_TASK_MANAGEMENT_ENABLED (0x0000000000000002ULL) 1472struct mpi3_driver_page10 { 1473 struct mpi3_config_page_header header; 1474 __le16 flags; 1475 __le16 reserved0a; 1476 u8 num_allowed_commands; 1477 u8 reserved0d[3]; 1478 union mpi3_allowed_cmd allowed_command[MPI3_ALLOWED_CMDS_MAX]; 1479}; 1480 1481#define MPI3_DRIVER10_PAGEVERSION (0x00) 1482struct mpi3_driver_page20 { 1483 struct mpi3_config_page_header header; 1484 __le16 flags; 1485 __le16 reserved0a; 1486 u8 num_allowed_commands; 1487 u8 reserved0d[3]; 1488 union mpi3_allowed_cmd allowed_command[MPI3_ALLOWED_CMDS_MAX]; 1489}; 1490 1491#define MPI3_DRIVER20_PAGEVERSION (0x00) 1492struct mpi3_driver_page30 { 1493 struct mpi3_config_page_header header; 1494 __le16 flags; 1495 __le16 reserved0a; 1496 u8 num_allowed_commands; 1497 u8 reserved0d[3]; 1498 union mpi3_allowed_cmd allowed_command[MPI3_ALLOWED_CMDS_MAX]; 1499}; 1500 1501#define MPI3_DRIVER30_PAGEVERSION (0x00) 1502union mpi3_security_mac { 1503 __le32 dword[16]; 1504 __le16 word[32]; 1505 u8 byte[64]; 1506}; 1507 1508union mpi3_security_nonce { 1509 __le32 dword[16]; 1510 __le16 word[32]; 1511 u8 byte[64]; 1512}; 1513 1514union mpi3_security_root_digest { 1515 __le32 dword[16]; 1516 __le16 word[32]; 1517 u8 byte[64]; 1518}; 1519 1520union mpi3_security0_cert_chain { 1521 __le32 dword[1024]; 1522 __le16 word[2048]; 1523 u8 byte[4096]; 1524}; 1525 1526struct mpi3_security_page0 { 1527 struct mpi3_config_page_header header; 1528 u8 slot_num_group; 1529 u8 slot_num; 1530 __le16 cert_chain_length; 1531 u8 cert_chain_flags; 1532 u8 reserved0d[3]; 1533 __le32 base_asym_algo; 1534 __le32 base_hash_algo; 1535 __le32 reserved18[4]; 1536 union mpi3_security_mac mac; 1537 union mpi3_security_nonce nonce; 1538 union mpi3_security0_cert_chain certificate_chain; 1539}; 1540 1541#define MPI3_SECURITY0_PAGEVERSION (0x00) 1542#define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_MASK (0x0e) 1543#define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_UNUSED (0x00) 1544#define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_CERBERUS (0x02) 1545#define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_SPDM (0x04) 1546#define MPI3_SECURITY0_CERTCHAIN_FLAGS_SEALED (0x01) 1547#ifndef MPI3_SECURITY1_KEY_RECORD_MAX 1548#define MPI3_SECURITY1_KEY_RECORD_MAX 1 1549#endif 1550#ifndef MPI3_SECURITY1_PAD_MAX 1551#define MPI3_SECURITY1_PAD_MAX 4 1552#endif 1553union mpi3_security1_key_data { 1554 __le32 dword[128]; 1555 __le16 word[256]; 1556 u8 byte[512]; 1557}; 1558 1559struct mpi3_security1_key_record { 1560 u8 flags; 1561 u8 consumer; 1562 __le16 key_data_size; 1563 __le32 additional_key_data; 1564 __le32 reserved08[2]; 1565 union mpi3_security1_key_data key_data; 1566}; 1567 1568#define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_MASK (0x1f) 1569#define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_NOT_VALID (0x00) 1570#define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_HMAC (0x01) 1571#define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_AES (0x02) 1572#define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_ECDSA_PRIVATE (0x03) 1573#define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_ECDSA_PUBLIC (0x04) 1574#define MPI3_SECURITY1_KEY_RECORD_CONSUMER_NOT_VALID (0x00) 1575#define MPI3_SECURITY1_KEY_RECORD_CONSUMER_SAFESTORE (0x01) 1576#define MPI3_SECURITY1_KEY_RECORD_CONSUMER_CERT_CHAIN (0x02) 1577#define MPI3_SECURITY1_KEY_RECORD_CONSUMER_DEVICE_KEY (0x03) 1578#define MPI3_SECURITY1_KEY_RECORD_CONSUMER_CACHE_OFFLOAD (0x04) 1579struct mpi3_security_page1 { 1580 struct mpi3_config_page_header header; 1581 __le32 reserved08[2]; 1582 union mpi3_security_mac mac; 1583 union mpi3_security_nonce nonce; 1584 u8 num_keys; 1585 u8 reserved91[3]; 1586 __le32 reserved94[3]; 1587 struct mpi3_security1_key_record key_record[MPI3_SECURITY1_KEY_RECORD_MAX]; 1588 u8 pad[MPI3_SECURITY1_PAD_MAX]; 1589}; 1590 1591#define MPI3_SECURITY1_PAGEVERSION (0x00) 1592#ifndef MPI3_SECURITY2_TRUSTED_ROOT_MAX 1593#define MPI3_SECURITY2_TRUSTED_ROOT_MAX 1 1594#endif 1595struct mpi3_security2_trusted_root { 1596 u8 level; 1597 u8 hash_algorithm; 1598 __le16 trusted_root_flags; 1599 __le32 reserved04[3]; 1600 union mpi3_security_root_digest root_digest; 1601}; 1602#define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_MASK (0x0006) 1603#define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_SHIFT (1) 1604#define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_HA_FIELD (0x0000) 1605#define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_AKI (0x0002) 1606#define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_USERPROVISIONED_YES (0x0001) 1607struct mpi3_security_page2 { 1608 struct mpi3_config_page_header header; 1609 __le32 reserved08[2]; 1610 union mpi3_security_mac mac; 1611 union mpi3_security_nonce nonce; 1612 __le32 reserved90[3]; 1613 u8 num_roots; 1614 u8 reserved9d[3]; 1615 struct mpi3_security2_trusted_root trusted_root[MPI3_SECURITY2_TRUSTED_ROOT_MAX]; 1616}; 1617#define MPI3_SECURITY2_PAGEVERSION (0x00) 1618struct mpi3_sas_io_unit0_phy_data { 1619 u8 io_unit_port; 1620 u8 port_flags; 1621 u8 phy_flags; 1622 u8 negotiated_link_rate; 1623 __le16 controller_phy_device_info; 1624 __le16 reserved06; 1625 __le16 attached_dev_handle; 1626 __le16 controller_dev_handle; 1627 __le32 discovery_status; 1628 __le32 reserved10; 1629}; 1630 1631struct mpi3_sas_io_unit_page0 { 1632 struct mpi3_config_page_header header; 1633 __le32 reserved08; 1634 u8 num_phys; 1635 u8 init_status; 1636 __le16 reserved0e; 1637 struct mpi3_sas_io_unit0_phy_data phy_data[]; 1638}; 1639 1640#define MPI3_SASIOUNIT0_PAGEVERSION (0x00) 1641#define MPI3_SASIOUNIT0_INITSTATUS_NO_ERRORS (0x00) 1642#define MPI3_SASIOUNIT0_INITSTATUS_NEEDS_INITIALIZATION (0x01) 1643#define MPI3_SASIOUNIT0_INITSTATUS_NO_TARGETS_ALLOCATED (0x02) 1644#define MPI3_SASIOUNIT0_INITSTATUS_BAD_NUM_PHYS (0x04) 1645#define MPI3_SASIOUNIT0_INITSTATUS_UNSUPPORTED_CONFIG (0x05) 1646#define MPI3_SASIOUNIT0_INITSTATUS_HOST_PHYS_ENABLED (0x06) 1647#define MPI3_SASIOUNIT0_INITSTATUS_PRODUCT_SPECIFIC_MIN (0xf0) 1648#define MPI3_SASIOUNIT0_INITSTATUS_PRODUCT_SPECIFIC_MAX (0xff) 1649#define MPI3_SASIOUNIT0_PORTFLAGS_DISC_IN_PROGRESS (0x08) 1650#define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_MASK (0x03) 1651#define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_IOUNIT1 (0x00) 1652#define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_DYNAMIC (0x01) 1653#define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_BACKPLANE (0x02) 1654#define MPI3_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 1655#define MPI3_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 1656#define MPI3_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 1657#define MPI3_SASIOUNIT0_PHYFLAGS_VIRTUAL_PHY (0x02) 1658#define MPI3_SASIOUNIT0_PHYFLAGS_HOST_PHY (0x01) 1659struct mpi3_sas_io_unit1_phy_data { 1660 u8 io_unit_port; 1661 u8 port_flags; 1662 u8 phy_flags; 1663 u8 max_min_link_rate; 1664 __le16 controller_phy_device_info; 1665 __le16 max_target_port_connect_time; 1666 __le32 reserved08; 1667}; 1668 1669struct mpi3_sas_io_unit_page1 { 1670 struct mpi3_config_page_header header; 1671 __le16 control_flags; 1672 __le16 sas_narrow_max_queue_depth; 1673 __le16 additional_control_flags; 1674 __le16 sas_wide_max_queue_depth; 1675 u8 num_phys; 1676 u8 sata_max_q_depth; 1677 __le16 reserved12; 1678 struct mpi3_sas_io_unit1_phy_data phy_data[]; 1679}; 1680 1681#define MPI3_SASIOUNIT1_PAGEVERSION (0x00) 1682#define MPI3_SASIOUNIT1_CONTROL_CONTROLLER_DEVICE_SELF_TEST (0x8000) 1683#define MPI3_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 1684#define MPI3_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 1685#define MPI3_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 1686#define MPI3_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 1687#define MPI3_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 1688#define MPI3_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) 1689#define MPI3_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 1690#define MPI3_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 1691#define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_MASK (0x0001) 1692#define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_DEVICE_NAME (0x0000) 1693#define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_SAS_ADDRESS (0x0001) 1694#define MPI3_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT (0x0100) 1695#define MPI3_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 1696#define MPI3_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 1697#define MPI3_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) 1698#define MPI3_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 1699#define MPI3_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 1700#define MPI3_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 1701#define MPI3_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 1702#define MPI3_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 1703#define MPI3_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 1704#define MPI3_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 1705#define MPI3_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 1706#define MPI3_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 1707#define MPI3_SASIOUNIT1_MMLR_MAX_RATE_MASK (0xf0) 1708#define MPI3_SASIOUNIT1_MMLR_MAX_RATE_SHIFT (4) 1709#define MPI3_SASIOUNIT1_MMLR_MAX_RATE_6_0 (0xa0) 1710#define MPI3_SASIOUNIT1_MMLR_MAX_RATE_12_0 (0xb0) 1711#define MPI3_SASIOUNIT1_MMLR_MAX_RATE_22_5 (0xc0) 1712#define MPI3_SASIOUNIT1_MMLR_MIN_RATE_MASK (0x0f) 1713#define MPI3_SASIOUNIT1_MMLR_MIN_RATE_6_0 (0x0a) 1714#define MPI3_SASIOUNIT1_MMLR_MIN_RATE_12_0 (0x0b) 1715#define MPI3_SASIOUNIT1_MMLR_MIN_RATE_22_5 (0x0c) 1716struct mpi3_sas_io_unit2_phy_pm_settings { 1717 u8 control_flags; 1718 u8 reserved01; 1719 __le16 inactivity_timer_exponent; 1720 u8 sata_partial_timeout; 1721 u8 reserved05; 1722 u8 sata_slumber_timeout; 1723 u8 reserved07; 1724 u8 sas_partial_timeout; 1725 u8 reserved09; 1726 u8 sas_slumber_timeout; 1727 u8 reserved0b; 1728}; 1729 1730#ifndef MPI3_SAS_IO_UNIT2_PHY_MAX 1731#define MPI3_SAS_IO_UNIT2_PHY_MAX (1) 1732#endif 1733struct mpi3_sas_io_unit_page2 { 1734 struct mpi3_config_page_header header; 1735 u8 num_phys; 1736 u8 reserved09[3]; 1737 __le32 reserved0c; 1738 struct mpi3_sas_io_unit2_phy_pm_settings sas_phy_power_management_settings[MPI3_SAS_IO_UNIT2_PHY_MAX]; 1739}; 1740 1741#define MPI3_SASIOUNIT2_PAGEVERSION (0x00) 1742#define MPI3_SASIOUNIT2_CONTROL_SAS_SLUMBER_ENABLE (0x08) 1743#define MPI3_SASIOUNIT2_CONTROL_SAS_PARTIAL_ENABLE (0x04) 1744#define MPI3_SASIOUNIT2_CONTROL_SATA_SLUMBER_ENABLE (0x02) 1745#define MPI3_SASIOUNIT2_CONTROL_SATA_PARTIAL_ENABLE (0x01) 1746#define MPI3_SASIOUNIT2_ITE_SAS_SLUMBER_MASK (0x7000) 1747#define MPI3_SASIOUNIT2_ITE_SAS_SLUMBER_SHIFT (12) 1748#define MPI3_SASIOUNIT2_ITE_SAS_PARTIAL_MASK (0x0700) 1749#define MPI3_SASIOUNIT2_ITE_SAS_PARTIAL_SHIFT (8) 1750#define MPI3_SASIOUNIT2_ITE_SATA_SLUMBER_MASK (0x0070) 1751#define MPI3_SASIOUNIT2_ITE_SATA_SLUMBER_SHIFT (4) 1752#define MPI3_SASIOUNIT2_ITE_SATA_PARTIAL_MASK (0x0007) 1753#define MPI3_SASIOUNIT2_ITE_SATA_PARTIAL_SHIFT (0) 1754#define MPI3_SASIOUNIT2_ITE_EXP_TEN_SECONDS (7) 1755#define MPI3_SASIOUNIT2_ITE_EXP_ONE_SECOND (6) 1756#define MPI3_SASIOUNIT2_ITE_EXP_HUNDRED_MILLISECONDS (5) 1757#define MPI3_SASIOUNIT2_ITE_EXP_TEN_MILLISECONDS (4) 1758#define MPI3_SASIOUNIT2_ITE_EXP_ONE_MILLISECOND (3) 1759#define MPI3_SASIOUNIT2_ITE_EXP_HUNDRED_MICROSECONDS (2) 1760#define MPI3_SASIOUNIT2_ITE_EXP_TEN_MICROSECONDS (1) 1761#define MPI3_SASIOUNIT2_ITE_EXP_ONE_MICROSECOND (0) 1762struct mpi3_sas_io_unit_page3 { 1763 struct mpi3_config_page_header header; 1764 __le32 reserved08; 1765 __le32 power_management_capabilities; 1766}; 1767 1768#define MPI3_SASIOUNIT3_PAGEVERSION (0x00) 1769#define MPI3_SASIOUNIT3_PM_HOST_SAS_SLUMBER_MODE (0x00000800) 1770#define MPI3_SASIOUNIT3_PM_HOST_SAS_PARTIAL_MODE (0x00000400) 1771#define MPI3_SASIOUNIT3_PM_HOST_SATA_SLUMBER_MODE (0x00000200) 1772#define MPI3_SASIOUNIT3_PM_HOST_SATA_PARTIAL_MODE (0x00000100) 1773#define MPI3_SASIOUNIT3_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008) 1774#define MPI3_SASIOUNIT3_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004) 1775#define MPI3_SASIOUNIT3_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002) 1776#define MPI3_SASIOUNIT3_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001) 1777struct mpi3_sas_expander_page0 { 1778 struct mpi3_config_page_header header; 1779 u8 io_unit_port; 1780 u8 report_gen_length; 1781 __le16 enclosure_handle; 1782 __le32 reserved0c; 1783 __le64 sas_address; 1784 __le32 discovery_status; 1785 __le16 dev_handle; 1786 __le16 parent_dev_handle; 1787 __le16 expander_change_count; 1788 __le16 expander_route_indexes; 1789 u8 num_phys; 1790 u8 sas_level; 1791 __le16 flags; 1792 __le16 stp_bus_inactivity_time_limit; 1793 __le16 stp_max_connect_time_limit; 1794 __le16 stp_smp_nexus_loss_time; 1795 __le16 max_num_routed_sas_addresses; 1796 __le64 active_zone_manager_sas_address; 1797 __le16 zone_lock_inactivity_limit; 1798 __le16 reserved3a; 1799 u8 time_to_reduced_func; 1800 u8 initial_time_to_reduced_func; 1801 u8 max_reduced_func_time; 1802 u8 exp_status; 1803}; 1804 1805#define MPI3_SASEXPANDER0_PAGEVERSION (0x00) 1806#define MPI3_SASEXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000) 1807#define MPI3_SASEXPANDER0_FLAGS_ZONE_LOCKED (0x1000) 1808#define MPI3_SASEXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800) 1809#define MPI3_SASEXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400) 1810#define MPI3_SASEXPANDER0_FLAGS_ZONING_SUPPORT (0x0200) 1811#define MPI3_SASEXPANDER0_FLAGS_ENABLED_ZONING (0x0100) 1812#define MPI3_SASEXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080) 1813#define MPI3_SASEXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010) 1814#define MPI3_SASEXPANDER0_FLAGS_OTHERS_CONFIG (0x0004) 1815#define MPI3_SASEXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002) 1816#define MPI3_SASEXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001) 1817#define MPI3_SASEXPANDER0_ES_NOT_RESPONDING (0x02) 1818#define MPI3_SASEXPANDER0_ES_RESPONDING (0x03) 1819#define MPI3_SASEXPANDER0_ES_DELAY_NOT_RESPONDING (0x04) 1820struct mpi3_sas_expander_page1 { 1821 struct mpi3_config_page_header header; 1822 u8 io_unit_port; 1823 u8 reserved09[3]; 1824 u8 num_phys; 1825 u8 phy; 1826 __le16 num_table_entries_programmed; 1827 u8 programmed_link_rate; 1828 u8 hw_link_rate; 1829 __le16 attached_dev_handle; 1830 __le32 phy_info; 1831 __le16 attached_device_info; 1832 __le16 reserved1a; 1833 __le16 expander_dev_handle; 1834 u8 change_count; 1835 u8 negotiated_link_rate; 1836 u8 phy_identifier; 1837 u8 attached_phy_identifier; 1838 u8 reserved22; 1839 u8 discovery_info; 1840 __le32 attached_phy_info; 1841 u8 zone_group; 1842 u8 self_config_status; 1843 __le16 reserved2a; 1844 __le16 slot; 1845 __le16 slot_index; 1846}; 1847 1848#define MPI3_SASEXPANDER1_PAGEVERSION (0x00) 1849#define MPI3_SASEXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 1850#define MPI3_SASEXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 1851#define MPI3_SASEXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 1852#ifndef MPI3_SASEXPANDER2_MAX_NUM_PHYS 1853#define MPI3_SASEXPANDER2_MAX_NUM_PHYS (1) 1854#endif 1855struct mpi3_sasexpander2_phy_element { 1856 u8 link_change_count; 1857 u8 reserved01; 1858 __le16 rate_change_count; 1859 __le32 reserved04; 1860}; 1861 1862struct mpi3_sas_expander_page2 { 1863 struct mpi3_config_page_header header; 1864 u8 num_phys; 1865 u8 reserved09; 1866 __le16 dev_handle; 1867 __le32 reserved0c; 1868 struct mpi3_sasexpander2_phy_element phy[MPI3_SASEXPANDER2_MAX_NUM_PHYS]; 1869}; 1870 1871#define MPI3_SASEXPANDER2_PAGEVERSION (0x00) 1872struct mpi3_sas_port_page0 { 1873 struct mpi3_config_page_header header; 1874 u8 port_number; 1875 u8 reserved09; 1876 u8 port_width; 1877 u8 reserved0b; 1878 u8 zone_group; 1879 u8 reserved0d[3]; 1880 __le64 sas_address; 1881 __le16 device_info; 1882 __le16 reserved1a; 1883 __le32 reserved1c; 1884}; 1885 1886#define MPI3_SASPORT0_PAGEVERSION (0x00) 1887struct mpi3_sas_phy_page0 { 1888 struct mpi3_config_page_header header; 1889 __le16 owner_dev_handle; 1890 __le16 reserved0a; 1891 __le16 attached_dev_handle; 1892 u8 attached_phy_identifier; 1893 u8 reserved0f; 1894 __le32 attached_phy_info; 1895 u8 programmed_link_rate; 1896 u8 hw_link_rate; 1897 u8 change_count; 1898 u8 flags; 1899 __le32 phy_info; 1900 u8 negotiated_link_rate; 1901 u8 reserved1d[3]; 1902 __le16 slot; 1903 __le16 slot_index; 1904}; 1905 1906#define MPI3_SASPHY0_PAGEVERSION (0x00) 1907#define MPI3_SASPHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 1908struct mpi3_sas_phy_page1 { 1909 struct mpi3_config_page_header header; 1910 __le32 reserved08; 1911 __le32 invalid_dword_count; 1912 __le32 running_disparity_error_count; 1913 __le32 loss_dword_synch_count; 1914 __le32 phy_reset_problem_count; 1915}; 1916 1917#define MPI3_SASPHY1_PAGEVERSION (0x00) 1918struct mpi3_sas_phy2_phy_event { 1919 u8 phy_event_code; 1920 u8 reserved01[3]; 1921 __le32 phy_event_info; 1922}; 1923 1924#ifndef MPI3_SAS_PHY2_PHY_EVENT_MAX 1925#define MPI3_SAS_PHY2_PHY_EVENT_MAX (1) 1926#endif 1927struct mpi3_sas_phy_page2 { 1928 struct mpi3_config_page_header header; 1929 __le32 reserved08; 1930 u8 num_phy_events; 1931 u8 reserved0d[3]; 1932 struct mpi3_sas_phy2_phy_event phy_event[MPI3_SAS_PHY2_PHY_EVENT_MAX]; 1933}; 1934 1935#define MPI3_SASPHY2_PAGEVERSION (0x00) 1936struct mpi3_sas_phy3_phy_event_config { 1937 u8 phy_event_code; 1938 u8 reserved01[3]; 1939 u8 counter_type; 1940 u8 threshold_window; 1941 u8 time_units; 1942 u8 reserved07; 1943 __le32 event_threshold; 1944 __le16 threshold_flags; 1945 __le16 reserved0e; 1946}; 1947 1948#define MPI3_SASPHY3_EVENT_CODE_NO_EVENT (0x00) 1949#define MPI3_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01) 1950#define MPI3_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02) 1951#define MPI3_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03) 1952#define MPI3_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04) 1953#define MPI3_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05) 1954#define MPI3_SASPHY3_EVENT_CODE_RX_ERROR (0x06) 1955#define MPI3_SASPHY3_EVENT_CODE_INV_SPL_PACKETS (0x07) 1956#define MPI3_SASPHY3_EVENT_CODE_LOSS_SPL_PACKET_SYNC (0x08) 1957#define MPI3_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20) 1958#define MPI3_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21) 1959#define MPI3_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22) 1960#define MPI3_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23) 1961#define MPI3_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24) 1962#define MPI3_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25) 1963#define MPI3_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26) 1964#define MPI3_SASPHY3_EVENT_CODE_TX_BREAK (0x27) 1965#define MPI3_SASPHY3_EVENT_CODE_RX_BREAK (0x28) 1966#define MPI3_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29) 1967#define MPI3_SASPHY3_EVENT_CODE_CONNECTION (0x2a) 1968#define MPI3_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2b) 1969#define MPI3_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2c) 1970#define MPI3_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2d) 1971#define MPI3_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2e) 1972#define MPI3_SASPHY3_EVENT_CODE_PERSIST_CONN (0x2f) 1973#define MPI3_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40) 1974#define MPI3_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41) 1975#define MPI3_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42) 1976#define MPI3_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43) 1977#define MPI3_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44) 1978#define MPI3_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45) 1979#define MPI3_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50) 1980#define MPI3_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51) 1981#define MPI3_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52) 1982#define MPI3_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60) 1983#define MPI3_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61) 1984#define MPI3_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63) 1985#define MPI3_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xd0) 1986#define MPI3_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xd1) 1987#define MPI3_SASPHY3_EVENT_CODE_RX_AIP (0xd2) 1988#define MPI3_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME (0xd3) 1989#define MPI3_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME (0xd4) 1990#define MPI3_SASPHY3_EVENT_CODE_LCCONN_TIME (0xd5) 1991#define MPI3_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT (0xd6) 1992#define MPI3_SASPHY3_EVENT_CODE_SATA_TX_START (0xd7) 1993#define MPI3_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT (0xd8) 1994#define MPI3_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN (0xd9) 1995#define MPI3_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE (0xda) 1996#define MPI3_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE (0xdb) 1997#define MPI3_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE (0xdc) 1998#define MPI3_SASPHY3_COUNTER_TYPE_WRAPPING (0x00) 1999#define MPI3_SASPHY3_COUNTER_TYPE_SATURATING (0x01) 2000#define MPI3_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02) 2001#define MPI3_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00) 2002#define MPI3_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01) 2003#define MPI3_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02) 2004#define MPI3_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03) 2005#define MPI3_SASPHY3_TFLAGS_PHY_RESET (0x0002) 2006#define MPI3_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001) 2007#ifndef MPI3_SAS_PHY3_PHY_EVENT_MAX 2008#define MPI3_SAS_PHY3_PHY_EVENT_MAX (1) 2009#endif 2010struct mpi3_sas_phy_page3 { 2011 struct mpi3_config_page_header header; 2012 __le32 reserved08; 2013 u8 num_phy_events; 2014 u8 reserved0d[3]; 2015 struct mpi3_sas_phy3_phy_event_config phy_event_config[MPI3_SAS_PHY3_PHY_EVENT_MAX]; 2016}; 2017 2018#define MPI3_SASPHY3_PAGEVERSION (0x00) 2019struct mpi3_sas_phy_page4 { 2020 struct mpi3_config_page_header header; 2021 u8 reserved08[3]; 2022 u8 flags; 2023 u8 initial_frame[28]; 2024}; 2025 2026#define MPI3_SASPHY4_PAGEVERSION (0x00) 2027#define MPI3_SASPHY4_FLAGS_FRAME_VALID (0x02) 2028#define MPI3_SASPHY4_FLAGS_SATA_FRAME (0x01) 2029#define MPI3_PCIE_LINK_RETIMERS_MASK (0x30) 2030#define MPI3_PCIE_LINK_RETIMERS_SHIFT (4) 2031#define MPI3_PCIE_NEG_LINK_RATE_MASK (0x0f) 2032#define MPI3_PCIE_NEG_LINK_RATE_UNKNOWN (0x00) 2033#define MPI3_PCIE_NEG_LINK_RATE_PHY_DISABLED (0x01) 2034#define MPI3_PCIE_NEG_LINK_RATE_2_5 (0x02) 2035#define MPI3_PCIE_NEG_LINK_RATE_5_0 (0x03) 2036#define MPI3_PCIE_NEG_LINK_RATE_8_0 (0x04) 2037#define MPI3_PCIE_NEG_LINK_RATE_16_0 (0x05) 2038#define MPI3_PCIE_NEG_LINK_RATE_32_0 (0x06) 2039#define MPI3_PCIE_ASPM_ENABLE_NONE (0x0) 2040#define MPI3_PCIE_ASPM_ENABLE_L0S (0x1) 2041#define MPI3_PCIE_ASPM_ENABLE_L1 (0x2) 2042#define MPI3_PCIE_ASPM_ENABLE_L0S_L1 (0x3) 2043#define MPI3_PCIE_ASPM_SUPPORT_NONE (0x0) 2044#define MPI3_PCIE_ASPM_SUPPORT_L0S (0x1) 2045#define MPI3_PCIE_ASPM_SUPPORT_L1 (0x2) 2046#define MPI3_PCIE_ASPM_SUPPORT_L0S_L1 (0x3) 2047struct mpi3_pcie_io_unit0_phy_data { 2048 u8 link; 2049 u8 link_flags; 2050 u8 phy_flags; 2051 u8 negotiated_link_rate; 2052 __le16 attached_dev_handle; 2053 __le16 controller_dev_handle; 2054 __le32 enumeration_status; 2055 u8 io_unit_port; 2056 u8 reserved0d[3]; 2057}; 2058 2059#define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_MASK (0x10) 2060#define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_IOUNIT1 (0x00) 2061#define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_BKPLANE (0x10) 2062#define MPI3_PCIEIOUNIT0_LINKFLAGS_ENUM_IN_PROGRESS (0x08) 2063#define MPI3_PCIEIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 2064#define MPI3_PCIEIOUNIT0_PHYFLAGS_HOST_PHY (0x01) 2065#define MPI3_PCIEIOUNIT0_ES_MAX_SWITCH_DEPTH_EXCEEDED (0x80000000) 2066#define MPI3_PCIEIOUNIT0_ES_MAX_SWITCHES_EXCEEDED (0x40000000) 2067#define MPI3_PCIEIOUNIT0_ES_MAX_ENDPOINTS_EXCEEDED (0x20000000) 2068#define MPI3_PCIEIOUNIT0_ES_INSUFFICIENT_RESOURCES (0x10000000) 2069#ifndef MPI3_PCIE_IO_UNIT0_PHY_MAX 2070#define MPI3_PCIE_IO_UNIT0_PHY_MAX (1) 2071#endif 2072struct mpi3_pcie_io_unit_page0 { 2073 struct mpi3_config_page_header header; 2074 __le32 reserved08; 2075 u8 num_phys; 2076 u8 init_status; 2077 u8 aspm; 2078 u8 reserved0f; 2079 struct mpi3_pcie_io_unit0_phy_data phy_data[MPI3_PCIE_IO_UNIT0_PHY_MAX]; 2080}; 2081 2082#define MPI3_PCIEIOUNIT0_PAGEVERSION (0x00) 2083#define MPI3_PCIEIOUNIT0_INITSTATUS_NO_ERRORS (0x00) 2084#define MPI3_PCIEIOUNIT0_INITSTATUS_NEEDS_INITIALIZATION (0x01) 2085#define MPI3_PCIEIOUNIT0_INITSTATUS_NO_TARGETS_ALLOCATED (0x02) 2086#define MPI3_PCIEIOUNIT0_INITSTATUS_RESOURCE_ALLOC_FAILED (0x03) 2087#define MPI3_PCIEIOUNIT0_INITSTATUS_BAD_NUM_PHYS (0x04) 2088#define MPI3_PCIEIOUNIT0_INITSTATUS_UNSUPPORTED_CONFIG (0x05) 2089#define MPI3_PCIEIOUNIT0_INITSTATUS_HOST_PORT_MISMATCH (0x06) 2090#define MPI3_PCIEIOUNIT0_INITSTATUS_PHYS_NOT_CONSECUTIVE (0x07) 2091#define MPI3_PCIEIOUNIT0_INITSTATUS_BAD_CLOCKING_MODE (0x08) 2092#define MPI3_PCIEIOUNIT0_INITSTATUS_PROD_SPEC_START (0xf0) 2093#define MPI3_PCIEIOUNIT0_INITSTATUS_PROD_SPEC_END (0xff) 2094#define MPI3_PCIEIOUNIT0_ASPM_SWITCH_STATES_MASK (0xc0) 2095#define MPI3_PCIEIOUNIT0_ASPM_SWITCH_STATES_SHIFT (6) 2096#define MPI3_PCIEIOUNIT0_ASPM_DIRECT_STATES_MASK (0x30) 2097#define MPI3_PCIEIOUNIT0_ASPM_DIRECT_STATES_SHIFT (4) 2098#define MPI3_PCIEIOUNIT0_ASPM_SWITCH_SUPPORT_MASK (0x0c) 2099#define MPI3_PCIEIOUNIT0_ASPM_SWITCH_SUPPORT_SHIFT (2) 2100#define MPI3_PCIEIOUNIT0_ASPM_DIRECT_SUPPORT_MASK (0x03) 2101#define MPI3_PCIEIOUNIT0_ASPM_DIRECT_SUPPORT_SHIFT (0) 2102struct mpi3_pcie_io_unit1_phy_data { 2103 u8 link; 2104 u8 link_flags; 2105 u8 phy_flags; 2106 u8 max_min_link_rate; 2107 __le32 reserved04; 2108 __le32 reserved08; 2109}; 2110 2111#define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_MASK (0x03) 2112#define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_DIS_SEPARATE_REFCLK (0x00) 2113#define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_EN_SRIS (0x01) 2114#define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_EN_SRNS (0x02) 2115#define MPI3_PCIEIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 2116#define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_MASK (0xf0) 2117#define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_SHIFT (4) 2118#define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_2_5 (0x20) 2119#define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_5_0 (0x30) 2120#define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_8_0 (0x40) 2121#define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_16_0 (0x50) 2122#define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_32_0 (0x60) 2123#ifndef MPI3_PCIE_IO_UNIT1_PHY_MAX 2124#define MPI3_PCIE_IO_UNIT1_PHY_MAX (1) 2125#endif 2126struct mpi3_pcie_io_unit_page1 { 2127 struct mpi3_config_page_header header; 2128 __le32 control_flags; 2129 __le32 reserved0c; 2130 u8 num_phys; 2131 u8 reserved11; 2132 u8 aspm; 2133 u8 reserved13; 2134 struct mpi3_pcie_io_unit1_phy_data phy_data[MPI3_PCIE_IO_UNIT1_PHY_MAX]; 2135}; 2136 2137#define MPI3_PCIEIOUNIT1_PAGEVERSION (0x00) 2138#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_MASK (0xe0000000) 2139#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_NONE (0x00000000) 2140#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_DEASSERT (0x20000000) 2141#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_ASSERT (0x40000000) 2142#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_BACKPLANE_ERROR (0x60000000) 2143#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_MASK (0x1c000000) 2144#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_NONE (0x00000000) 2145#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_DEASSERT (0x04000000) 2146#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_ASSERT (0x08000000) 2147#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_BACKPLANE_ERROR (0x0c000000) 2148#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_OVERRIDE_DISABLE (0x00000080) 2149#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_DISABLE (0x00000040) 2150#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_MASK (0x00000030) 2151#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SHIFT (4) 2152#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRIS_SRNS_DISABLED (0x00000000) 2153#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRIS_ENABLED (0x00000010) 2154#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRNS_ENABLED (0x00000020) 2155#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MASK (0x0000000f) 2156#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_USE_BACKPLANE (0x00000000) 2157#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_2_5 (0x00000002) 2158#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_5_0 (0x00000003) 2159#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_8_0 (0x00000004) 2160#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_16_0 (0x00000005) 2161#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_32_0 (0x00000006) 2162#define MPI3_PCIEIOUNIT1_ASPM_SWITCH_MASK (0x0c) 2163#define MPI3_PCIEIOUNIT1_ASPM_SWITCH_SHIFT (2) 2164#define MPI3_PCIEIOUNIT1_ASPM_DIRECT_MASK (0x03) 2165#define MPI3_PCIEIOUNIT1_ASPM_DIRECT_SHIFT (0) 2166struct mpi3_pcie_io_unit_page2 { 2167 struct mpi3_config_page_header header; 2168 __le16 nvme_max_q_dx1; 2169 __le16 nvme_max_q_dx2; 2170 u8 nvme_abort_to; 2171 u8 reserved0d; 2172 __le16 nvme_max_q_dx4; 2173}; 2174 2175#define MPI3_PCIEIOUNIT2_PAGEVERSION (0x00) 2176#define MPI3_PCIEIOUNIT3_ERROR_RECEIVER_ERROR (0) 2177#define MPI3_PCIEIOUNIT3_ERROR_RECOVERY (1) 2178#define MPI3_PCIEIOUNIT3_ERROR_CORRECTABLE_ERROR_MSG (2) 2179#define MPI3_PCIEIOUNIT3_ERROR_BAD_DLLP (3) 2180#define MPI3_PCIEIOUNIT3_ERROR_BAD_TLP (4) 2181#define MPI3_PCIEIOUNIT3_NUM_ERROR_INDEX (5) 2182struct mpi3_pcie_io_unit3_error { 2183 __le16 threshold_count; 2184 __le16 reserved02; 2185}; 2186 2187struct mpi3_pcie_io_unit_page3 { 2188 struct mpi3_config_page_header header; 2189 u8 threshold_window; 2190 u8 threshold_action; 2191 u8 escalation_count; 2192 u8 escalation_action; 2193 u8 num_errors; 2194 u8 reserved0d[3]; 2195 struct mpi3_pcie_io_unit3_error error[MPI3_PCIEIOUNIT3_NUM_ERROR_INDEX]; 2196}; 2197 2198#define MPI3_PCIEIOUNIT3_PAGEVERSION (0x00) 2199#define MPI3_PCIEIOUNIT3_ACTION_NO_ACTION (0x00) 2200#define MPI3_PCIEIOUNIT3_ACTION_HOT_RESET (0x01) 2201#define MPI3_PCIEIOUNIT3_ACTION_REDUCE_LINK_RATE_ONLY (0x02) 2202#define MPI3_PCIEIOUNIT3_ACTION_REDUCE_LINK_RATE_NO_ACCESS (0x03) 2203struct mpi3_pcie_switch_page0 { 2204 struct mpi3_config_page_header header; 2205 u8 io_unit_port; 2206 u8 switch_status; 2207 u8 reserved0a[2]; 2208 __le16 dev_handle; 2209 __le16 parent_dev_handle; 2210 u8 num_ports; 2211 u8 pcie_level; 2212 __le16 reserved12; 2213 __le32 reserved14; 2214 __le32 reserved18; 2215 __le32 reserved1c; 2216}; 2217 2218#define MPI3_PCIESWITCH0_PAGEVERSION (0x00) 2219#define MPI3_PCIESWITCH0_SS_NOT_RESPONDING (0x02) 2220#define MPI3_PCIESWITCH0_SS_RESPONDING (0x03) 2221#define MPI3_PCIESWITCH0_SS_DELAY_NOT_RESPONDING (0x04) 2222struct mpi3_pcie_switch_page1 { 2223 struct mpi3_config_page_header header; 2224 u8 io_unit_port; 2225 u8 flags; 2226 __le16 reserved0a; 2227 u8 num_ports; 2228 u8 port_num; 2229 __le16 attached_dev_handle; 2230 __le16 switch_dev_handle; 2231 u8 negotiated_port_width; 2232 u8 negotiated_link_rate; 2233 __le16 slot; 2234 __le16 slot_index; 2235 __le32 reserved18; 2236}; 2237 2238#define MPI3_PCIESWITCH1_PAGEVERSION (0x00) 2239#define MPI3_PCIESWITCH1_FLAGS_ASPMSTATE_MASK (0x0c) 2240#define MPI3_PCIESWITCH1_FLAGS_ASPMSTATE_SHIFT (2) 2241#define MPI3_PCIESWITCH1_FLAGS_ASPMSUPPORT_MASK (0x03) 2242#define MPI3_PCIESWITCH1_FLAGS_ASPMSUPPORT_SHIFT (0) 2243#ifndef MPI3_PCIESWITCH2_MAX_NUM_PORTS 2244#define MPI3_PCIESWITCH2_MAX_NUM_PORTS (1) 2245#endif 2246struct mpi3_pcieswitch2_port_element { 2247 __le16 link_change_count; 2248 __le16 rate_change_count; 2249 __le32 reserved04; 2250}; 2251 2252struct mpi3_pcie_switch_page2 { 2253 struct mpi3_config_page_header header; 2254 u8 num_ports; 2255 u8 reserved09; 2256 __le16 dev_handle; 2257 __le32 reserved0c; 2258 struct mpi3_pcieswitch2_port_element port[MPI3_PCIESWITCH2_MAX_NUM_PORTS]; 2259}; 2260 2261#define MPI3_PCIESWITCH2_PAGEVERSION (0x00) 2262struct mpi3_pcie_link_page0 { 2263 struct mpi3_config_page_header header; 2264 u8 link; 2265 u8 reserved09[3]; 2266 __le32 reserved0c; 2267 __le32 receiver_error_count; 2268 __le32 recovery_count; 2269 __le32 corr_error_msg_count; 2270 __le32 non_fatal_error_msg_count; 2271 __le32 fatal_error_msg_count; 2272 __le32 non_fatal_error_count; 2273 __le32 fatal_error_count; 2274 __le32 bad_dllp_count; 2275 __le32 bad_tlp_count; 2276}; 2277 2278#define MPI3_PCIELINK0_PAGEVERSION (0x00) 2279struct mpi3_enclosure_page0 { 2280 struct mpi3_config_page_header header; 2281 __le64 enclosure_logical_id; 2282 __le16 flags; 2283 __le16 enclosure_handle; 2284 __le16 num_slots; 2285 __le16 reserved16; 2286 u8 io_unit_port; 2287 u8 enclosure_level; 2288 __le16 sep_dev_handle; 2289 u8 chassis_slot; 2290 u8 reserved1d[3]; 2291}; 2292 2293#define MPI3_ENCLOSURE0_PAGEVERSION (0x00) 2294#define MPI3_ENCLS0_FLAGS_ENCL_TYPE_MASK (0xc000) 2295#define MPI3_ENCLS0_FLAGS_ENCL_TYPE_VIRTUAL (0x0000) 2296#define MPI3_ENCLS0_FLAGS_ENCL_TYPE_SAS (0x4000) 2297#define MPI3_ENCLS0_FLAGS_ENCL_TYPE_PCIE (0x8000) 2298#define MPI3_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020) 2299#define MPI3_ENCLS0_FLAGS_ENCL_DEV_PRESENT_MASK (0x0010) 2300#define MPI3_ENCLS0_FLAGS_ENCL_DEV_NOT_FOUND (0x0000) 2301#define MPI3_ENCLS0_FLAGS_ENCL_DEV_PRESENT (0x0010) 2302#define MPI3_ENCLS0_FLAGS_MNG_MASK (0x000f) 2303#define MPI3_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 2304#define MPI3_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 2305#define MPI3_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0002) 2306#define MPI3_DEVICE_DEVFORM_SAS_SATA (0x00) 2307#define MPI3_DEVICE_DEVFORM_PCIE (0x01) 2308#define MPI3_DEVICE_DEVFORM_VD (0x02) 2309struct mpi3_device0_sas_sata_format { 2310 __le64 sas_address; 2311 __le16 flags; 2312 __le16 device_info; 2313 u8 phy_num; 2314 u8 attached_phy_identifier; 2315 u8 max_port_connections; 2316 u8 zone_group; 2317}; 2318 2319#define MPI3_DEVICE0_SASSATA_FLAGS_WRITE_SAME_UNMAP_NCQ (0x0400) 2320#define MPI3_DEVICE0_SASSATA_FLAGS_SLUMBER_CAP (0x0200) 2321#define MPI3_DEVICE0_SASSATA_FLAGS_PARTIAL_CAP (0x0100) 2322#define MPI3_DEVICE0_SASSATA_FLAGS_ASYNC_NOTIFY (0x0080) 2323#define MPI3_DEVICE0_SASSATA_FLAGS_SW_PRESERVE (0x0040) 2324#define MPI3_DEVICE0_SASSATA_FLAGS_UNSUPP_DEV (0x0020) 2325#define MPI3_DEVICE0_SASSATA_FLAGS_48BIT_LBA (0x0010) 2326#define MPI3_DEVICE0_SASSATA_FLAGS_SMART_SUPP (0x0008) 2327#define MPI3_DEVICE0_SASSATA_FLAGS_NCQ_SUPP (0x0004) 2328#define MPI3_DEVICE0_SASSATA_FLAGS_FUA_SUPP (0x0002) 2329#define MPI3_DEVICE0_SASSATA_FLAGS_PERSIST_CAP (0x0001) 2330struct mpi3_device0_pcie_format { 2331 u8 supported_link_rates; 2332 u8 max_port_width; 2333 u8 negotiated_port_width; 2334 u8 negotiated_link_rate; 2335 u8 port_num; 2336 u8 controller_reset_to; 2337 __le16 device_info; 2338 __le32 maximum_data_transfer_size; 2339 __le32 capabilities; 2340 __le16 noiob; 2341 u8 nvme_abort_to; 2342 u8 page_size; 2343 __le16 shutdown_latency; 2344 u8 recovery_info; 2345 u8 reserved17; 2346}; 2347 2348#define MPI3_DEVICE0_PCIE_LINK_RATE_32_0_SUPP (0x10) 2349#define MPI3_DEVICE0_PCIE_LINK_RATE_16_0_SUPP (0x08) 2350#define MPI3_DEVICE0_PCIE_LINK_RATE_8_0_SUPP (0x04) 2351#define MPI3_DEVICE0_PCIE_LINK_RATE_5_0_SUPP (0x02) 2352#define MPI3_DEVICE0_PCIE_LINK_RATE_2_5_SUPP (0x01) 2353#define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_MASK (0x0007) 2354#define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NO_DEVICE (0x0000) 2355#define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NVME_DEVICE (0x0001) 2356#define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SWITCH_DEVICE (0x0002) 2357#define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SCSI_DEVICE (0x0003) 2358#define MPI3_DEVICE0_PCIE_DEVICE_INFO_ASPM_MASK (0x0030) 2359#define MPI3_DEVICE0_PCIE_DEVICE_INFO_ASPM_SHIFT (4) 2360#define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_MASK (0x00c0) 2361#define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_SHIFT (6) 2362#define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_0 (0x0000) 2363#define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_1 (0x0040) 2364#define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_2 (0x0080) 2365#define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_3 (0x00c0) 2366#define MPI3_DEVICE0_PCIE_CAP_SGL_EXTRA_LENGTH_SUPPORTED (0x00000020) 2367#define MPI3_DEVICE0_PCIE_CAP_METADATA_SEPARATED (0x00000010) 2368#define MPI3_DEVICE0_PCIE_CAP_SGL_DWORD_ALIGN_REQUIRED (0x00000008) 2369#define MPI3_DEVICE0_PCIE_CAP_SGL_FORMAT_SGL (0x00000004) 2370#define MPI3_DEVICE0_PCIE_CAP_SGL_FORMAT_PRP (0x00000000) 2371#define MPI3_DEVICE0_PCIE_CAP_BIT_BUCKET_SGL_SUPP (0x00000002) 2372#define MPI3_DEVICE0_PCIE_CAP_SGL_SUPP (0x00000001) 2373#define MPI3_DEVICE0_PCIE_CAP_ASPM_MASK (0x000000c0) 2374#define MPI3_DEVICE0_PCIE_CAP_ASPM_SHIFT (6) 2375#define MPI3_DEVICE0_PCIE_RECOVER_METHOD_MASK (0xe0) 2376#define MPI3_DEVICE0_PCIE_RECOVER_METHOD_NS_MGMT (0x00) 2377#define MPI3_DEVICE0_PCIE_RECOVER_METHOD_FORMAT (0x20) 2378#define MPI3_DEVICE0_PCIE_RECOVER_REASON_MASK (0x1f) 2379#define MPI3_DEVICE0_PCIE_RECOVER_REASON_NO_NS (0x00) 2380#define MPI3_DEVICE0_PCIE_RECOVER_REASON_NO_NSID_1 (0x01) 2381#define MPI3_DEVICE0_PCIE_RECOVER_REASON_TOO_MANY_NS (0x02) 2382#define MPI3_DEVICE0_PCIE_RECOVER_REASON_PROTECTION (0x03) 2383#define MPI3_DEVICE0_PCIE_RECOVER_REASON_METADATA_SZ (0x04) 2384#define MPI3_DEVICE0_PCIE_RECOVER_REASON_LBA_DATA_SZ (0x05) 2385struct mpi3_device0_vd_format { 2386 u8 vd_state; 2387 u8 raid_level; 2388 __le16 device_info; 2389 __le16 flags; 2390 __le16 io_throttle_group; 2391 __le16 io_throttle_group_low; 2392 __le16 io_throttle_group_high; 2393 u8 vd_abort_to; 2394 u8 vd_reset_to; 2395 __le16 reserved0e; 2396}; 2397#define MPI3_DEVICE0_VD_STATE_OFFLINE (0x00) 2398#define MPI3_DEVICE0_VD_STATE_PARTIALLY_DEGRADED (0x01) 2399#define MPI3_DEVICE0_VD_STATE_DEGRADED (0x02) 2400#define MPI3_DEVICE0_VD_STATE_OPTIMAL (0x03) 2401#define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_0 (0) 2402#define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_1 (1) 2403#define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_5 (5) 2404#define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_6 (6) 2405#define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_10 (10) 2406#define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_50 (50) 2407#define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_60 (60) 2408#define MPI3_DEVICE0_VD_DEVICE_INFO_HDD (0x0010) 2409#define MPI3_DEVICE0_VD_DEVICE_INFO_SSD (0x0008) 2410#define MPI3_DEVICE0_VD_DEVICE_INFO_NVME (0x0004) 2411#define MPI3_DEVICE0_VD_DEVICE_INFO_SATA (0x0002) 2412#define MPI3_DEVICE0_VD_DEVICE_INFO_SAS (0x0001) 2413#define MPI3_DEVICE0_VD_FLAGS_IO_THROTTLE_GROUP_QD_MASK (0xf000) 2414#define MPI3_DEVICE0_VD_FLAGS_IO_THROTTLE_GROUP_QD_SHIFT (12) 2415#define MPI3_DEVICE0_VD_FLAGS_OSEXPOSURE_MASK (0x0003) 2416#define MPI3_DEVICE0_VD_FLAGS_OSEXPOSURE_HDD (0x0000) 2417#define MPI3_DEVICE0_VD_FLAGS_OSEXPOSURE_SSD (0x0001) 2418#define MPI3_DEVICE0_VD_FLAGS_OSEXPOSURE_NO_GUIDANCE (0x0002) 2419union mpi3_device0_dev_spec_format { 2420 struct mpi3_device0_sas_sata_format sas_sata_format; 2421 struct mpi3_device0_pcie_format pcie_format; 2422 struct mpi3_device0_vd_format vd_format; 2423}; 2424 2425struct mpi3_device_page0 { 2426 struct mpi3_config_page_header header; 2427 __le16 dev_handle; 2428 __le16 parent_dev_handle; 2429 __le16 slot; 2430 __le16 enclosure_handle; 2431 __le64 wwid; 2432 __le16 persistent_id; 2433 u8 io_unit_port; 2434 u8 access_status; 2435 __le16 flags; 2436 __le16 reserved1e; 2437 __le16 slot_index; 2438 __le16 queue_depth; 2439 u8 reserved24[3]; 2440 u8 device_form; 2441 union mpi3_device0_dev_spec_format device_specific; 2442}; 2443 2444#define MPI3_DEVICE0_PAGEVERSION (0x00) 2445#define MPI3_DEVICE0_PARENT_INVALID (0xffff) 2446#define MPI3_DEVICE0_ENCLOSURE_HANDLE_NO_ENCLOSURE (0x0000) 2447#define MPI3_DEVICE0_WWID_INVALID (0xffffffffffffffff) 2448#define MPI3_DEVICE0_PERSISTENTID_INVALID (0xffff) 2449#define MPI3_DEVICE0_IOUNITPORT_INVALID (0xff) 2450#define MPI3_DEVICE0_ASTATUS_NO_ERRORS (0x00) 2451#define MPI3_DEVICE0_ASTATUS_NEEDS_INITIALIZATION (0x01) 2452#define MPI3_DEVICE0_ASTATUS_CAP_UNSUPPORTED (0x02) 2453#define MPI3_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x03) 2454#define MPI3_DEVICE0_ASTATUS_UNAUTHORIZED (0x04) 2455#define MPI3_DEVICE0_ASTATUS_DEVICE_MISSING_DELAY (0x05) 2456#define MPI3_DEVICE0_ASTATUS_PREPARE (0x06) 2457#define MPI3_DEVICE0_ASTATUS_SAFE_MODE (0x07) 2458#define MPI3_DEVICE0_ASTATUS_GENERIC_MAX (0x0f) 2459#define MPI3_DEVICE0_ASTATUS_SAS_UNKNOWN (0x10) 2460#define MPI3_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x11) 2461#define MPI3_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x12) 2462#define MPI3_DEVICE0_ASTATUS_SAS_MAX (0x1f) 2463#define MPI3_DEVICE0_ASTATUS_SIF_UNKNOWN (0x20) 2464#define MPI3_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x21) 2465#define MPI3_DEVICE0_ASTATUS_SIF_DIAG (0x22) 2466#define MPI3_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x23) 2467#define MPI3_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x24) 2468#define MPI3_DEVICE0_ASTATUS_SIF_PIO_SN (0x25) 2469#define MPI3_DEVICE0_ASTATUS_SIF_MDMA_SN (0x26) 2470#define MPI3_DEVICE0_ASTATUS_SIF_UDMA_SN (0x27) 2471#define MPI3_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x28) 2472#define MPI3_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x29) 2473#define MPI3_DEVICE0_ASTATUS_SIF_MAX (0x2f) 2474#define MPI3_DEVICE0_ASTATUS_PCIE_UNKNOWN (0x30) 2475#define MPI3_DEVICE0_ASTATUS_PCIE_MEM_SPACE_ACCESS (0x31) 2476#define MPI3_DEVICE0_ASTATUS_PCIE_UNSUPPORTED (0x32) 2477#define MPI3_DEVICE0_ASTATUS_PCIE_MSIX_REQUIRED (0x33) 2478#define MPI3_DEVICE0_ASTATUS_PCIE_ECRC_REQUIRED (0x34) 2479#define MPI3_DEVICE0_ASTATUS_PCIE_MAX (0x3f) 2480#define MPI3_DEVICE0_ASTATUS_NVME_UNKNOWN (0x40) 2481#define MPI3_DEVICE0_ASTATUS_NVME_READY_TIMEOUT (0x41) 2482#define MPI3_DEVICE0_ASTATUS_NVME_DEVCFG_UNSUPPORTED (0x42) 2483#define MPI3_DEVICE0_ASTATUS_NVME_IDENTIFY_FAILED (0x43) 2484#define MPI3_DEVICE0_ASTATUS_NVME_QCONFIG_FAILED (0x44) 2485#define MPI3_DEVICE0_ASTATUS_NVME_QCREATION_FAILED (0x45) 2486#define MPI3_DEVICE0_ASTATUS_NVME_EVENTCFG_FAILED (0x46) 2487#define MPI3_DEVICE0_ASTATUS_NVME_GET_FEATURE_STAT_FAILED (0x47) 2488#define MPI3_DEVICE0_ASTATUS_NVME_IDLE_TIMEOUT (0x48) 2489#define MPI3_DEVICE0_ASTATUS_NVME_CTRL_FAILURE_STATUS (0x49) 2490#define MPI3_DEVICE0_ASTATUS_NVME_INSUFFICIENT_POWER (0x4a) 2491#define MPI3_DEVICE0_ASTATUS_NVME_DOORBELL_STRIDE (0x4b) 2492#define MPI3_DEVICE0_ASTATUS_NVME_MEM_PAGE_MIN_SIZE (0x4c) 2493#define MPI3_DEVICE0_ASTATUS_NVME_MEMORY_ALLOCATION (0x4d) 2494#define MPI3_DEVICE0_ASTATUS_NVME_COMPLETION_TIME (0x4e) 2495#define MPI3_DEVICE0_ASTATUS_NVME_BAR (0x4f) 2496#define MPI3_DEVICE0_ASTATUS_NVME_NS_DESCRIPTOR (0x50) 2497#define MPI3_DEVICE0_ASTATUS_NVME_INCOMPATIBLE_SETTINGS (0x51) 2498#define MPI3_DEVICE0_ASTATUS_NVME_TOO_MANY_ERRORS (0x52) 2499#define MPI3_DEVICE0_ASTATUS_NVME_MAX (0x5f) 2500#define MPI3_DEVICE0_ASTATUS_VD_UNKNOWN (0x80) 2501#define MPI3_DEVICE0_ASTATUS_VD_MAX (0x8f) 2502#define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_MASK (0xe000) 2503#define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_NO_LIMIT (0x0000) 2504#define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_256_LB (0x2000) 2505#define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_2048_LB (0x4000) 2506#define MPI3_DEVICE0_FLAGS_CONTROLLER_DEV_HANDLE (0x0080) 2507#define MPI3_DEVICE0_FLAGS_IO_THROTTLING_REQUIRED (0x0010) 2508#define MPI3_DEVICE0_FLAGS_HIDDEN (0x0008) 2509#define MPI3_DEVICE0_FLAGS_ATT_METHOD_VIRTUAL (0x0004) 2510#define MPI3_DEVICE0_FLAGS_ATT_METHOD_DIR_ATTACHED (0x0002) 2511#define MPI3_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 2512#define MPI3_DEVICE0_QUEUE_DEPTH_NOT_APPLICABLE (0x0000) 2513struct mpi3_device1_sas_sata_format { 2514 __le32 reserved00; 2515}; 2516struct mpi3_device1_pcie_format { 2517 __le16 vendor_id; 2518 __le16 device_id; 2519 __le16 subsystem_vendor_id; 2520 __le16 subsystem_id; 2521 __le32 reserved08; 2522 u8 revision_id; 2523 u8 reserved0d; 2524 __le16 pci_parameters; 2525}; 2526 2527#define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_128B (0x0) 2528#define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_256B (0x1) 2529#define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_512B (0x2) 2530#define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_1024B (0x3) 2531#define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_2048B (0x4) 2532#define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_4096B (0x5) 2533#define MPI3_DEVICE1_PCIE_PARAMS_MAX_READ_REQ_MASK (0x01c0) 2534#define MPI3_DEVICE1_PCIE_PARAMS_MAX_READ_REQ_SHIFT (6) 2535#define MPI3_DEVICE1_PCIE_PARAMS_CURR_MAX_PAYLOAD_MASK (0x0038) 2536#define MPI3_DEVICE1_PCIE_PARAMS_CURR_MAX_PAYLOAD_SHIFT (3) 2537#define MPI3_DEVICE1_PCIE_PARAMS_SUPP_MAX_PAYLOAD_MASK (0x0007) 2538#define MPI3_DEVICE1_PCIE_PARAMS_SUPP_MAX_PAYLOAD_SHIFT (0) 2539struct mpi3_device1_vd_format { 2540 __le32 reserved00; 2541}; 2542 2543union mpi3_device1_dev_spec_format { 2544 struct mpi3_device1_sas_sata_format sas_sata_format; 2545 struct mpi3_device1_pcie_format pcie_format; 2546 struct mpi3_device1_vd_format vd_format; 2547}; 2548 2549struct mpi3_device_page1 { 2550 struct mpi3_config_page_header header; 2551 __le16 dev_handle; 2552 __le16 reserved0a; 2553 __le16 link_change_count; 2554 __le16 rate_change_count; 2555 __le16 tm_count; 2556 __le16 reserved12; 2557 __le32 reserved14[10]; 2558 u8 reserved3c[3]; 2559 u8 device_form; 2560 union mpi3_device1_dev_spec_format device_specific; 2561}; 2562 2563#define MPI3_DEVICE1_PAGEVERSION (0x00) 2564#define MPI3_DEVICE1_COUNTER_MAX (0xfffe) 2565#define MPI3_DEVICE1_COUNTER_INVALID (0xffff) 2566#endif
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