lpfc_sli4.h

   1/*******************************************************************
   2 * This file is part of the Emulex Linux Device Driver for         *
   3 * Fibre Channel Host Bus Adapters.                                *
   4 * Copyright (C) 2017-2025 Broadcom. All Rights Reserved. The term *
   5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries.     *
   6 * Copyright (C) 2009-2016 Emulex.  All rights reserved.           *
   7 * EMULEX and SLI are trademarks of Emulex.                        *
   8 * www.broadcom.com                                                *
   9 *                                                                 *
  10 * This program is free software; you can redistribute it and/or   *
  11 * modify it under the terms of version 2 of the GNU General       *
  12 * Public License as published by the Free Software Foundation.    *
  13 * This program is distributed in the hope that it will be useful. *
  14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
  15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
  16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
  17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  18 * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
  19 * more details, a copy of which can be found in the file COPYING  *
  20 * included with this package.                                     *
  21 *******************************************************************/
  22
  23#include <linux/irq_poll.h>
  24#include <linux/cpufreq.h>
  25
  26#if defined(CONFIG_DEBUG_FS) && !defined(CONFIG_SCSI_LPFC_DEBUG_FS)
  27#define CONFIG_SCSI_LPFC_DEBUG_FS
  28#endif
  29
  30#define LPFC_ACTIVE_MBOX_WAIT_CNT               100
  31#define LPFC_XRI_EXCH_BUSY_WAIT_TMO		10000
  32#define LPFC_XRI_EXCH_BUSY_WAIT_T1   		10
  33#define LPFC_XRI_EXCH_BUSY_WAIT_T2              30000
  34#define LPFC_RPI_LOW_WATER_MARK			10
  35
  36#define LPFC_UNREG_FCF                          1
  37#define LPFC_SKIP_UNREG_FCF                     0
  38
  39/* Amount of time in seconds for waiting FCF rediscovery to complete */
  40#define LPFC_FCF_REDISCOVER_WAIT_TMO		2000 /* msec */
  41
  42/* Number of SGL entries can be posted in a 4KB nonembedded mbox command */
  43#define LPFC_NEMBED_MBOX_SGL_CNT		254
  44
  45/* Multi-queue arrangement for FCP EQ/CQ/WQ tuples */
  46#define LPFC_HBA_HDWQ_MIN	0
  47#define LPFC_HBA_HDWQ_MAX	256
  48#define LPFC_HBA_HDWQ_DEF	LPFC_HBA_HDWQ_MIN
  49
  50/* irq_chann range, values */
  51#define LPFC_IRQ_CHANN_MIN	0
  52#define LPFC_IRQ_CHANN_MAX	256
  53#define LPFC_IRQ_CHANN_DEF	LPFC_IRQ_CHANN_MIN
  54
  55/* FCP MQ queue count limiting */
  56#define LPFC_FCP_MQ_THRESHOLD_MIN	0
  57#define LPFC_FCP_MQ_THRESHOLD_MAX	256
  58#define LPFC_FCP_MQ_THRESHOLD_DEF	8
  59
  60/*
  61 * Provide the default FCF Record attributes used by the driver
  62 * when nonFIP mode is configured and there is no other default
  63 * FCF Record attributes.
  64 */
  65#define LPFC_FCOE_FCF_DEF_INDEX	0
  66#define LPFC_FCOE_FCF_GET_FIRST	0xFFFF
  67#define LPFC_FCOE_FCF_NEXT_NONE	0xFFFF
  68
  69#define LPFC_FCOE_NULL_VID	0xFFF
  70#define LPFC_FCOE_IGNORE_VID	0xFFFF
  71
  72/* First 3 bytes of default FCF MAC is specified by FC_MAP */
  73#define LPFC_FCOE_FCF_MAC3	0xFF
  74#define LPFC_FCOE_FCF_MAC4	0xFF
  75#define LPFC_FCOE_FCF_MAC5	0xFE
  76#define LPFC_FCOE_FCF_MAP0	0x0E
  77#define LPFC_FCOE_FCF_MAP1	0xFC
  78#define LPFC_FCOE_FCF_MAP2	0x00
  79#define LPFC_FCOE_MAX_RCV_SIZE	0x800
  80#define LPFC_FCOE_FKA_ADV_PER	0
  81#define LPFC_FCOE_FIP_PRIORITY	0x80
  82
  83#define sli4_sid_from_fc_hdr(fc_hdr)  \
  84	((fc_hdr)->fh_s_id[0] << 16 | \
  85	 (fc_hdr)->fh_s_id[1] <<  8 | \
  86	 (fc_hdr)->fh_s_id[2])
  87
  88#define sli4_did_from_fc_hdr(fc_hdr)  \
  89	((fc_hdr)->fh_d_id[0] << 16 | \
  90	 (fc_hdr)->fh_d_id[1] <<  8 | \
  91	 (fc_hdr)->fh_d_id[2])
  92
  93#define sli4_fctl_from_fc_hdr(fc_hdr)  \
  94	((fc_hdr)->fh_f_ctl[0] << 16 | \
  95	 (fc_hdr)->fh_f_ctl[1] <<  8 | \
  96	 (fc_hdr)->fh_f_ctl[2])
  97
  98#define sli4_type_from_fc_hdr(fc_hdr)  \
  99	((fc_hdr)->fh_type)
 100
 101#define LPFC_FW_RESET_MAXIMUM_WAIT_10MS_CNT 12000
 102
 103#define INT_FW_UPGRADE	0
 104#define RUN_FW_UPGRADE	1
 105
 106enum lpfc_sli4_queue_type {
 107	LPFC_EQ,
 108	LPFC_GCQ,
 109	LPFC_MCQ,
 110	LPFC_WCQ,
 111	LPFC_RCQ,
 112	LPFC_MQ,
 113	LPFC_WQ,
 114	LPFC_HRQ,
 115	LPFC_DRQ
 116};
 117
 118/* The queue sub-type defines the functional purpose of the queue */
 119enum lpfc_sli4_queue_subtype {
 120	LPFC_NONE,
 121	LPFC_MBOX,
 122	LPFC_IO,
 123	LPFC_ELS,
 124	LPFC_NVMET,
 125	LPFC_NVME_LS,
 126	LPFC_USOL
 127};
 128
 129/* RQ buffer list */
 130struct lpfc_rqb {
 131	uint16_t entry_count;	  /* Current number of RQ slots */
 132	uint16_t buffer_count;	  /* Current number of buffers posted */
 133	struct list_head rqb_buffer_list;  /* buffers assigned to this HBQ */
 134				  /* Callback for HBQ buffer allocation */
 135	struct rqb_dmabuf *(*rqb_alloc_buffer)(struct lpfc_hba *);
 136				  /* Callback for HBQ buffer free */
 137	void               (*rqb_free_buffer)(struct lpfc_hba *,
 138					       struct rqb_dmabuf *);
 139};
 140
 141enum lpfc_poll_mode {
 142	LPFC_QUEUE_WORK,
 143	LPFC_THREADED_IRQ,
 144};
 145
 146struct lpfc_idle_stat {
 147	u64 prev_idle;
 148	u64 prev_wall;
 149};
 150
 151struct lpfc_queue {
 152	struct list_head list;
 153	struct list_head wq_list;
 154
 155	/*
 156	 * If interrupts are in effect on _all_ the eq's the footprint
 157	 * of polling code is zero (except mode). This memory is chec-
 158	 * ked for every io to see if the io needs to be polled and
 159	 * while completion to check if the eq's needs to be rearmed.
 160	 * Keep in same cacheline as the queue ptr to avoid cpu fetch
 161	 * stalls. Using 1B memory will leave us with 7B hole. Fill
 162	 * it with other frequently used members.
 163	 */
 164	uint16_t last_cpu;	/* most recent cpu */
 165	uint16_t hdwq;
 166	uint8_t	 qe_valid;
 167	uint8_t  mode;	/* interrupt or polling */
 168#define LPFC_EQ_INTERRUPT	0
 169#define LPFC_EQ_POLL		1
 170
 171	struct list_head wqfull_list;
 172	enum lpfc_sli4_queue_type type;
 173	enum lpfc_sli4_queue_subtype subtype;
 174	struct lpfc_hba *phba;
 175	struct list_head child_list;
 176	struct list_head page_list;
 177	struct list_head sgl_list;
 178	struct list_head cpu_list;
 179	uint32_t entry_count;	/* Number of entries to support on the queue */
 180	uint32_t entry_size;	/* Size of each queue entry. */
 181	uint32_t entry_cnt_per_pg;
 182	uint32_t notify_interval; /* Queue Notification Interval
 183				   * For chip->host queues (EQ, CQ, RQ):
 184				   *  specifies the interval (number of
 185				   *  entries) where the doorbell is rung to
 186				   *  notify the chip of entry consumption.
 187				   * For host->chip queues (WQ):
 188				   *  specifies the interval (number of
 189				   *  entries) where consumption CQE is
 190				   *  requested to indicate WQ entries
 191				   *  consumed by the chip.
 192				   * Not used on an MQ.
 193				   */
 194#define LPFC_EQ_NOTIFY_INTRVL	16
 195#define LPFC_CQ_NOTIFY_INTRVL	16
 196#define LPFC_WQ_NOTIFY_INTRVL	16
 197#define LPFC_RQ_NOTIFY_INTRVL	16
 198	uint32_t max_proc_limit; /* Queue Processing Limit
 199				  * For chip->host queues (EQ, CQ):
 200				  *  specifies the maximum number of
 201				  *  entries to be consumed in one
 202				  *  processing iteration sequence. Queue
 203				  *  will be rearmed after each iteration.
 204				  * Not used on an MQ, RQ or WQ.
 205				  */
 206#define LPFC_EQ_MAX_PROC_LIMIT		256
 207#define LPFC_CQ_MIN_PROC_LIMIT		64
 208#define LPFC_CQ_MAX_PROC_LIMIT		LPFC_CQE_EXP_COUNT	// 4096
 209#define LPFC_CQ_DEF_MAX_PROC_LIMIT	LPFC_CQE_DEF_COUNT	// 1024
 210#define LPFC_CQ_MIN_THRESHOLD_TO_POLL	64
 211#define LPFC_CQ_MAX_THRESHOLD_TO_POLL	LPFC_CQ_DEF_MAX_PROC_LIMIT
 212#define LPFC_CQ_DEF_THRESHOLD_TO_POLL	LPFC_CQ_DEF_MAX_PROC_LIMIT
 213	uint32_t queue_claimed; /* indicates queue is being processed */
 214	uint32_t queue_id;	/* Queue ID assigned by the hardware */
 215	uint32_t assoc_qid;     /* Queue ID associated with, for CQ/WQ/MQ */
 216	uint32_t host_index;	/* The host's index for putting or getting */
 217	uint32_t hba_index;	/* The last known hba index for get or put */
 218	uint32_t q_mode;
 219
 220	struct lpfc_sli_ring *pring; /* ptr to io ring associated with q */
 221	struct lpfc_rqb *rqbp;	/* ptr to RQ buffers */
 222
 223	uint16_t page_count;	/* Number of pages allocated for this queue */
 224	uint16_t page_size;	/* size of page allocated for this queue */
 225#define LPFC_EXPANDED_PAGE_SIZE	16384
 226#define LPFC_DEFAULT_PAGE_SIZE	4096
 227	uint16_t chann;		/* Hardware Queue association WQ/CQ */
 228				/* CPU affinity for EQ */
 229#define LPFC_FIND_BY_EQ		0
 230#define LPFC_FIND_BY_HDWQ	1
 231	uint8_t db_format;
 232#define LPFC_DB_RING_FORMAT	0x01
 233#define LPFC_DB_LIST_FORMAT	0x02
 234	uint8_t q_flag;
 235#define HBA_NVMET_WQFULL	0x1 /* We hit WQ Full condition for NVMET */
 236#define HBA_NVMET_CQ_NOTIFY	0x1 /* LPFC_NVMET_CQ_NOTIFY CQEs this EQE */
 237#define HBA_EQ_DELAY_CHK	0x2 /* EQ is a candidate for coalescing */
 238#define LPFC_NVMET_CQ_NOTIFY	4
 239	void __iomem *db_regaddr;
 240	uint16_t dpp_enable;
 241	uint16_t dpp_id;
 242	void __iomem *dpp_regaddr;
 243
 244	/* For q stats */
 245	uint32_t q_cnt_1;
 246	uint32_t q_cnt_2;
 247	uint32_t q_cnt_3;
 248	uint64_t q_cnt_4;
 249/* defines for EQ stats */
 250#define	EQ_max_eqe		q_cnt_1
 251#define	EQ_no_entry		q_cnt_2
 252#define	EQ_cqe_cnt		q_cnt_3
 253#define	EQ_processed		q_cnt_4
 254
 255/* defines for CQ stats */
 256#define	CQ_mbox			q_cnt_1
 257#define	CQ_max_cqe		q_cnt_1
 258#define	CQ_release_wqe		q_cnt_2
 259#define	CQ_xri_aborted		q_cnt_3
 260#define	CQ_wq			q_cnt_4
 261
 262/* defines for WQ stats */
 263#define	WQ_overflow		q_cnt_1
 264#define	WQ_posted		q_cnt_4
 265
 266/* defines for RQ stats */
 267#define	RQ_no_posted_buf	q_cnt_1
 268#define	RQ_no_buf_found		q_cnt_2
 269#define	RQ_buf_posted		q_cnt_3
 270#define	RQ_rcv_buf		q_cnt_4
 271
 272	struct work_struct	irqwork;
 273	struct work_struct	spwork;
 274	struct delayed_work	sched_irqwork;
 275	struct delayed_work	sched_spwork;
 276
 277	uint64_t isr_timestamp;
 278	struct lpfc_queue *assoc_qp;
 279	struct list_head _poll_list;
 280	void **q_pgs;	/* array to index entries per page */
 281
 282	enum lpfc_poll_mode poll_mode;
 283};
 284
 285struct lpfc_sli4_link {
 286	uint32_t speed;
 287	uint8_t duplex;
 288	uint8_t status;
 289	uint8_t type;
 290	uint8_t number;
 291	uint8_t fault;
 292	uint8_t link_status;
 293	uint16_t topology;
 294	uint32_t logical_speed;
 295};
 296
 297struct lpfc_fcf_rec {
 298	uint8_t  fabric_name[8];
 299	uint8_t  switch_name[8];
 300	uint8_t  mac_addr[6];
 301	uint16_t fcf_indx;
 302	uint32_t priority;
 303	uint16_t vlan_id;
 304	uint32_t addr_mode;
 305	uint32_t flag;
 306#define BOOT_ENABLE	0x01
 307#define RECORD_VALID	0x02
 308};
 309
 310struct lpfc_fcf_pri_rec {
 311	uint16_t fcf_index;
 312#define LPFC_FCF_ON_PRI_LIST 0x0001
 313#define LPFC_FCF_FLOGI_FAILED 0x0002
 314	uint16_t flag;
 315	uint32_t priority;
 316};
 317
 318struct lpfc_fcf_pri {
 319	struct list_head list;
 320	struct lpfc_fcf_pri_rec fcf_rec;
 321};
 322
 323/*
 324 * Maximum FCF table index, it is for driver internal book keeping, it
 325 * just needs to be no less than the supported HBA's FCF table size.
 326 */
 327#define LPFC_SLI4_FCF_TBL_INDX_MAX	32
 328
 329struct lpfc_fcf {
 330	uint16_t fcfi;
 331	uint32_t fcf_flag;
 332#define FCF_AVAILABLE	0x01 /* FCF available for discovery */
 333#define FCF_REGISTERED	0x02 /* FCF registered with FW */
 334#define FCF_SCAN_DONE	0x04 /* FCF table scan done */
 335#define FCF_IN_USE	0x08 /* Atleast one discovery completed */
 336#define FCF_INIT_DISC	0x10 /* Initial FCF discovery */
 337#define FCF_DEAD_DISC	0x20 /* FCF DEAD fast FCF failover discovery */
 338#define FCF_ACVL_DISC	0x40 /* All CVL fast FCF failover discovery */
 339#define FCF_DISCOVERY	(FCF_INIT_DISC | FCF_DEAD_DISC | FCF_ACVL_DISC)
 340#define FCF_REDISC_PEND	0x80 /* FCF rediscovery pending */
 341#define FCF_REDISC_EVT	0x100 /* FCF rediscovery event to worker thread */
 342#define FCF_REDISC_FOV	0x200 /* Post FCF rediscovery fast failover */
 343#define FCF_REDISC_PROG (FCF_REDISC_PEND | FCF_REDISC_EVT)
 344	uint16_t fcf_redisc_attempted;
 345	uint32_t addr_mode;
 346	uint32_t eligible_fcf_cnt;
 347	struct lpfc_fcf_rec current_rec;
 348	struct lpfc_fcf_rec failover_rec;
 349	struct list_head fcf_pri_list;
 350	struct lpfc_fcf_pri fcf_pri[LPFC_SLI4_FCF_TBL_INDX_MAX];
 351	uint32_t current_fcf_scan_pri;
 352	struct timer_list redisc_wait;
 353	unsigned long *fcf_rr_bmask; /* Eligible FCF indexes for RR failover */
 354};
 355
 356
 357#define LPFC_REGION23_SIGNATURE "RG23"
 358#define LPFC_REGION23_VERSION	1
 359#define LPFC_REGION23_LAST_REC  0xff
 360#define DRIVER_SPECIFIC_TYPE	0xA2
 361#define LINUX_DRIVER_ID		0x20
 362#define PORT_STE_TYPE		0x1
 363
 364struct lpfc_fip_param_hdr {
 365	uint8_t type;
 366#define FCOE_PARAM_TYPE		0xA0
 367	uint8_t length;
 368#define FCOE_PARAM_LENGTH	2
 369	uint8_t parm_version;
 370#define FIPP_VERSION		0x01
 371	uint8_t parm_flags;
 372#define	lpfc_fip_param_hdr_fipp_mode_SHIFT	6
 373#define	lpfc_fip_param_hdr_fipp_mode_MASK	0x3
 374#define lpfc_fip_param_hdr_fipp_mode_WORD	parm_flags
 375#define	FIPP_MODE_ON				0x1
 376#define	FIPP_MODE_OFF				0x0
 377#define FIPP_VLAN_VALID				0x1
 378};
 379
 380struct lpfc_fcoe_params {
 381	uint8_t fc_map[3];
 382	uint8_t reserved1;
 383	uint16_t vlan_tag;
 384	uint8_t reserved[2];
 385};
 386
 387struct lpfc_fcf_conn_hdr {
 388	uint8_t type;
 389#define FCOE_CONN_TBL_TYPE		0xA1
 390	uint8_t length;   /* words */
 391	uint8_t reserved[2];
 392};
 393
 394struct lpfc_fcf_conn_rec {
 395	uint16_t flags;
 396#define	FCFCNCT_VALID		0x0001
 397#define	FCFCNCT_BOOT		0x0002
 398#define	FCFCNCT_PRIMARY		0x0004   /* if not set, Secondary */
 399#define	FCFCNCT_FBNM_VALID	0x0008
 400#define	FCFCNCT_SWNM_VALID	0x0010
 401#define	FCFCNCT_VLAN_VALID	0x0020
 402#define	FCFCNCT_AM_VALID	0x0040
 403#define	FCFCNCT_AM_PREFERRED	0x0080   /* if not set, AM Required */
 404#define	FCFCNCT_AM_SPMA		0x0100	 /* if not set, FPMA */
 405
 406	uint16_t vlan_tag;
 407	uint8_t fabric_name[8];
 408	uint8_t switch_name[8];
 409};
 410
 411struct lpfc_fcf_conn_entry {
 412	struct list_head list;
 413	struct lpfc_fcf_conn_rec conn_rec;
 414};
 415
 416/*
 417 * Define the host's bootstrap mailbox.  This structure contains
 418 * the member attributes needed to create, use, and destroy the
 419 * bootstrap mailbox region.
 420 *
 421 * The macro definitions for the bmbx data structure are defined
 422 * in lpfc_hw4.h with the register definition.
 423 */
 424struct lpfc_bmbx {
 425	struct lpfc_dmabuf *dmabuf;
 426	struct dma_address dma_address;
 427	void *avirt;
 428	dma_addr_t aphys;
 429	uint32_t bmbx_size;
 430};
 431
 432#define LPFC_EQE_SIZE LPFC_EQE_SIZE_4
 433
 434#define LPFC_EQE_SIZE_4B 	4
 435#define LPFC_EQE_SIZE_16B	16
 436#define LPFC_CQE_SIZE		16
 437#define LPFC_WQE_SIZE		64
 438#define LPFC_WQE128_SIZE	128
 439#define LPFC_MQE_SIZE		256
 440#define LPFC_RQE_SIZE		8
 441
 442#define LPFC_EQE_DEF_COUNT	1024
 443#define LPFC_CQE_DEF_COUNT      1024
 444#define LPFC_CQE_EXP_COUNT      4096
 445#define LPFC_WQE_DEF_COUNT      256
 446#define LPFC_WQE_EXP_COUNT      1024
 447#define LPFC_MQE_DEF_COUNT      16
 448#define LPFC_RQE_DEF_COUNT	512
 449
 450#define LPFC_QUEUE_NOARM	false
 451#define LPFC_QUEUE_REARM	true
 452
 453
 454/*
 455 * SLI4 CT field defines
 456 */
 457#define SLI4_CT_RPI 0
 458#define SLI4_CT_VPI 1
 459#define SLI4_CT_VFI 2
 460#define SLI4_CT_FCFI 3
 461
 462/*
 463 * SLI4 specific data structures
 464 */
 465struct lpfc_max_cfg_param {
 466	uint16_t max_xri;
 467	uint16_t xri_base;
 468	uint16_t xri_used;
 469	uint16_t max_rpi;
 470	uint16_t rpi_base;
 471	uint16_t rpi_used;
 472	uint16_t max_vpi;
 473	uint16_t vpi_base;
 474	uint16_t vpi_used;
 475	uint16_t max_vfi;
 476	uint16_t vfi_base;
 477	uint16_t vfi_used;
 478	uint16_t max_fcfi;
 479	uint16_t fcfi_used;
 480	uint16_t max_eq;
 481	uint16_t max_rq;
 482	uint16_t max_cq;
 483	uint16_t max_wq;
 484};
 485
 486struct lpfc_hba;
 487/* SLI4 HBA multi-fcp queue handler struct */
 488#define LPFC_SLI4_HANDLER_NAME_SZ	16
 489struct lpfc_hba_eq_hdl {
 490	uint32_t idx;
 491	int irq;
 492	char handler_name[LPFC_SLI4_HANDLER_NAME_SZ];
 493	struct lpfc_hba *phba;
 494	struct lpfc_queue *eq;
 495	struct cpumask aff_mask;
 496};
 497
 498#define lpfc_get_eq_hdl(eqidx) (&phba->sli4_hba.hba_eq_hdl[eqidx])
 499#define lpfc_get_aff_mask(eqidx) (&phba->sli4_hba.hba_eq_hdl[eqidx].aff_mask)
 500#define lpfc_get_irq(eqidx) (phba->sli4_hba.hba_eq_hdl[eqidx].irq)
 501
 502/*BB Credit recovery value*/
 503struct lpfc_bbscn_params {
 504	uint32_t word0;
 505#define lpfc_bbscn_min_SHIFT		0
 506#define lpfc_bbscn_min_MASK		0x0000000F
 507#define lpfc_bbscn_min_WORD		word0
 508#define lpfc_bbscn_max_SHIFT		4
 509#define lpfc_bbscn_max_MASK		0x0000000F
 510#define lpfc_bbscn_max_WORD		word0
 511#define lpfc_bbscn_def_SHIFT		8
 512#define lpfc_bbscn_def_MASK		0x0000000F
 513#define lpfc_bbscn_def_WORD		word0
 514};
 515
 516/* Port Capabilities for SLI4 Parameters */
 517struct lpfc_pc_sli4_params {
 518	uint32_t supported;
 519	uint32_t if_type;
 520	uint32_t sli_rev;
 521	uint32_t sli_family;
 522	uint32_t featurelevel_1;
 523	uint32_t featurelevel_2;
 524	uint32_t proto_types;
 525#define LPFC_SLI4_PROTO_FCOE	0x0000001
 526#define LPFC_SLI4_PROTO_FC	0x0000002
 527#define LPFC_SLI4_PROTO_NIC	0x0000004
 528#define LPFC_SLI4_PROTO_ISCSI	0x0000008
 529#define LPFC_SLI4_PROTO_RDMA	0x0000010
 530	uint32_t sge_supp_len;
 531	uint32_t if_page_sz;
 532	uint32_t rq_db_window;
 533	uint32_t loopbk_scope;
 534	uint32_t oas_supported;
 535	uint32_t eq_pages_max;
 536	uint32_t eqe_size;
 537	uint32_t cq_pages_max;
 538	uint32_t cqe_size;
 539	uint32_t mq_pages_max;
 540	uint32_t mqe_size;
 541	uint32_t mq_elem_cnt;
 542	uint32_t wq_pages_max;
 543	uint32_t wqe_size;
 544	uint32_t rq_pages_max;
 545	uint32_t rqe_size;
 546	uint32_t hdr_pages_max;
 547	uint32_t hdr_size;
 548	uint32_t hdr_pp_align;
 549	uint32_t sgl_pages_max;
 550	uint32_t sgl_pp_align;
 551	uint32_t mib_size;
 552	uint16_t mi_ver;
 553#define LPFC_MIB1_SUPPORT	1
 554#define LPFC_MIB2_SUPPORT	2
 555#define LPFC_MIB3_SUPPORT	3
 556	uint16_t mi_value;
 557#define LPFC_DFLT_MIB_VAL	2
 558	uint8_t mi_cap;
 559	uint8_t mib_bde_cnt;
 560	uint8_t cmf;
 561	uint8_t cqv;
 562	uint8_t mqv;
 563	uint8_t wqv;
 564	uint8_t rqv;
 565	uint8_t eqav;
 566	uint8_t cqav;
 567	uint8_t wqsize;
 568	uint8_t bv1s;
 569	uint8_t pls;
 570#define LPFC_WQ_SZ64_SUPPORT	1
 571#define LPFC_WQ_SZ128_SUPPORT	2
 572	uint8_t wqpcnt;
 573	uint8_t nvme;
 574};
 575
 576#define LPFC_CQ_4K_PAGE_SZ	0x1
 577#define LPFC_CQ_16K_PAGE_SZ	0x4
 578#define LPFC_CQ_32K_PAGE_SZ	0x8
 579#define LPFC_WQ_4K_PAGE_SZ	0x1
 580#define LPFC_WQ_16K_PAGE_SZ	0x4
 581#define LPFC_WQ_32K_PAGE_SZ	0x8
 582
 583struct lpfc_iov {
 584	uint32_t pf_number;
 585	uint32_t vf_number;
 586};
 587
 588struct lpfc_sli4_lnk_info {
 589	uint8_t lnk_dv;
 590#define LPFC_LNK_DAT_INVAL	0
 591#define LPFC_LNK_DAT_VAL	1
 592	uint8_t lnk_tp;
 593#define LPFC_LNK_GE		0x0 /* FCoE */
 594#define LPFC_LNK_FC		0x1 /* FC */
 595#define LPFC_LNK_FC_TRUNKED	0x2 /* FC_Trunked */
 596	uint8_t lnk_no;
 597	uint8_t optic_state;
 598};
 599
 600#define LPFC_SLI4_HANDLER_CNT		(LPFC_HBA_IO_CHAN_MAX+ \
 601					 LPFC_FOF_IO_CHAN_NUM)
 602
 603/* Used for tracking CPU mapping attributes */
 604struct lpfc_vector_map_info {
 605	uint16_t	phys_id;
 606	uint16_t	core_id;
 607	uint16_t	eq;
 608	uint16_t	hdwq;
 609	uint16_t	flag;
 610#define LPFC_CPU_MAP_HYPER	0x1
 611#define LPFC_CPU_MAP_UNASSIGN	0x2
 612#define LPFC_CPU_FIRST_IRQ	0x4
 613};
 614#define LPFC_VECTOR_MAP_EMPTY	0xffff
 615
 616#define LPFC_IRQ_EMPTY 0xffffffff
 617
 618/* Multi-XRI pool */
 619#define XRI_BATCH               8
 620
 621struct lpfc_pbl_pool {
 622	struct list_head list;
 623	u32 count;
 624	spinlock_t lock;	/* lock for pbl_pool*/
 625};
 626
 627struct lpfc_pvt_pool {
 628	u32 low_watermark;
 629	u32 high_watermark;
 630
 631	struct list_head list;
 632	u32 count;
 633	spinlock_t lock;	/* lock for pvt_pool */
 634};
 635
 636struct lpfc_multixri_pool {
 637	u32 xri_limit;
 638
 639	/* Starting point when searching a pbl_pool with round-robin method */
 640	u32 rrb_next_hwqid;
 641
 642	/* Used by lpfc_adjust_pvt_pool_count.
 643	 * io_req_count is incremented by 1 during IO submission. The heartbeat
 644	 * handler uses these two variables to determine if pvt_pool is idle or
 645	 * busy.
 646	 */
 647	u32 prev_io_req_count;
 648	u32 io_req_count;
 649
 650	/* statistics */
 651	u32 pbl_empty_count;
 652#ifdef LPFC_MXP_STAT
 653	u32 above_limit_count;
 654	u32 below_limit_count;
 655	u32 local_pbl_hit_count;
 656	u32 other_pbl_hit_count;
 657	u32 stat_max_hwm;
 658
 659#define LPFC_MXP_SNAPSHOT_TAKEN 3 /* snapshot is taken at 3rd heartbeats */
 660	u32 stat_pbl_count;
 661	u32 stat_pvt_count;
 662	u32 stat_busy_count;
 663	u32 stat_snapshot_taken;
 664#endif
 665
 666	/* TODO: Separate pvt_pool into get and put list */
 667	struct lpfc_pbl_pool pbl_pool;   /* Public free XRI pool */
 668	struct lpfc_pvt_pool pvt_pool;   /* Private free XRI pool */
 669};
 670
 671struct lpfc_fc4_ctrl_stat {
 672	u32 input_requests;
 673	u32 output_requests;
 674	u32 control_requests;
 675	u32 io_cmpls;
 676};
 677
 678#ifdef LPFC_HDWQ_LOCK_STAT
 679struct lpfc_lock_stat {
 680	uint32_t alloc_xri_get;
 681	uint32_t alloc_xri_put;
 682	uint32_t free_xri;
 683	uint32_t wq_access;
 684	uint32_t alloc_pvt_pool;
 685	uint32_t mv_from_pvt_pool;
 686	uint32_t mv_to_pub_pool;
 687	uint32_t mv_to_pvt_pool;
 688	uint32_t free_pub_pool;
 689	uint32_t free_pvt_pool;
 690};
 691#endif
 692
 693struct lpfc_eq_intr_info {
 694	struct list_head list;
 695	uint32_t icnt;
 696};
 697
 698/* SLI4 HBA data structure entries */
 699struct lpfc_sli4_hdw_queue {
 700	/* Pointers to the constructed SLI4 queues */
 701	struct lpfc_queue *hba_eq;  /* Event queues for HBA */
 702	struct lpfc_queue *io_cq;   /* Fast-path FCP & NVME compl queue */
 703	struct lpfc_queue *io_wq;   /* Fast-path FCP & NVME work queue */
 704	uint16_t io_cq_map;
 705
 706	/* Keep track of IO buffers for this hardware queue */
 707	spinlock_t io_buf_list_get_lock;  /* Common buf alloc list lock */
 708	struct list_head lpfc_io_buf_list_get;
 709	spinlock_t io_buf_list_put_lock;  /* Common buf free list lock */
 710	struct list_head lpfc_io_buf_list_put;
 711	spinlock_t abts_io_buf_list_lock; /* list of aborted IOs */
 712	struct list_head lpfc_abts_io_buf_list;
 713	uint32_t total_io_bufs;
 714	uint32_t get_io_bufs;
 715	uint32_t put_io_bufs;
 716	uint32_t empty_io_bufs;
 717	uint32_t abts_scsi_io_bufs;
 718	uint32_t abts_nvme_io_bufs;
 719
 720	/* Multi-XRI pool per HWQ */
 721	struct lpfc_multixri_pool *p_multixri_pool;
 722
 723	/* FC-4 Stats counters */
 724	struct lpfc_fc4_ctrl_stat nvme_cstat;
 725	struct lpfc_fc4_ctrl_stat scsi_cstat;
 726#ifdef LPFC_HDWQ_LOCK_STAT
 727	struct lpfc_lock_stat lock_conflict;
 728#endif
 729
 730	/* Per HDWQ pool resources */
 731	struct list_head sgl_list;
 732	struct list_head cmd_rsp_buf_list;
 733
 734	/* Lock for syncing Per HDWQ pool resources */
 735	spinlock_t hdwq_lock;
 736};
 737
 738#ifdef LPFC_HDWQ_LOCK_STAT
 739/* compile time trylock stats */
 740#define lpfc_qp_spin_lock_irqsave(lock, flag, qp, lstat) \
 741	{ \
 742	int only_once = 1; \
 743	while (spin_trylock_irqsave(lock, flag) == 0) { \
 744		if (only_once) { \
 745			only_once = 0; \
 746			qp->lock_conflict.lstat++; \
 747		} \
 748	} \
 749	}
 750#define lpfc_qp_spin_lock(lock, qp, lstat) \
 751	{ \
 752	int only_once = 1; \
 753	while (spin_trylock(lock) == 0) { \
 754		if (only_once) { \
 755			only_once = 0; \
 756			qp->lock_conflict.lstat++; \
 757		} \
 758	} \
 759	}
 760#else
 761#define lpfc_qp_spin_lock_irqsave(lock, flag, qp, lstat) \
 762	spin_lock_irqsave(lock, flag)
 763#define lpfc_qp_spin_lock(lock, qp, lstat) spin_lock(lock)
 764#endif
 765
 766#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
 767struct lpfc_hdwq_stat {
 768	u32 hdwq_no;
 769	u32 rcv_io;
 770	u32 xmt_io;
 771	u32 cmpl_io;
 772};
 773#endif
 774
 775struct lpfc_sli4_hba {
 776	void __iomem *conf_regs_memmap_p; /* Kernel memory mapped address for
 777					   * config space registers
 778					   */
 779	void __iomem *ctrl_regs_memmap_p; /* Kernel memory mapped address for
 780					   * control registers
 781					   */
 782	void __iomem *drbl_regs_memmap_p; /* Kernel memory mapped address for
 783					   * doorbell registers
 784					   */
 785	void __iomem *dpp_regs_memmap_p;  /* Kernel memory mapped address for
 786					   * dpp registers
 787					   */
 788	void __iomem *dpp_regs_memmap_wc_p;/* Kernel memory mapped address for
 789					    * dpp registers with write combining
 790					    */
 791	union {
 792		struct {
 793			/* IF Type 0, BAR 0 PCI cfg space reg mem map */
 794			void __iomem *UERRLOregaddr;
 795			void __iomem *UERRHIregaddr;
 796			void __iomem *UEMASKLOregaddr;
 797			void __iomem *UEMASKHIregaddr;
 798		} if_type0;
 799		struct {
 800			/* IF Type 2, BAR 0 PCI cfg space reg mem map. */
 801			void __iomem *STATUSregaddr;
 802			void __iomem *CTRLregaddr;
 803			void __iomem *ERR1regaddr;
 804#define SLIPORT_ERR1_REG_ERR_CODE_1		0x1
 805#define SLIPORT_ERR1_REG_ERR_CODE_2		0x2
 806			void __iomem *ERR2regaddr;
 807#define SLIPORT_ERR2_REG_FW_RESTART		0x0
 808#define SLIPORT_ERR2_REG_FUNC_PROVISON		0x1
 809#define SLIPORT_ERR2_REG_FORCED_DUMP		0x2
 810#define SLIPORT_ERR2_REG_FAILURE_EQ		0x3
 811#define SLIPORT_ERR2_REG_FAILURE_CQ		0x4
 812#define SLIPORT_ERR2_REG_FAILURE_BUS		0x5
 813#define SLIPORT_ERR2_REG_FAILURE_RQ		0x6
 814			void __iomem *EQDregaddr;
 815		} if_type2;
 816	} u;
 817
 818	/* IF type 0, BAR1 and if type 2, Bar 0 CSR register memory map */
 819	void __iomem *PSMPHRregaddr;
 820
 821	/* Well-known SLI INTF register memory map. */
 822	void __iomem *SLIINTFregaddr;
 823
 824	/* IF type 0, BAR 1 function CSR register memory map */
 825	void __iomem *ISRregaddr;	/* HST_ISR register */
 826	void __iomem *IMRregaddr;	/* HST_IMR register */
 827	void __iomem *ISCRregaddr;	/* HST_ISCR register */
 828	/* IF type 0, BAR 0 and if type 2, BAR 0 doorbell register memory map */
 829	void __iomem *RQDBregaddr;	/* RQ_DOORBELL register */
 830	void __iomem *WQDBregaddr;	/* WQ_DOORBELL register */
 831	void __iomem *CQDBregaddr;	/* CQ_DOORBELL register */
 832	void __iomem *EQDBregaddr;	/* EQ_DOORBELL register */
 833	void __iomem *MQDBregaddr;	/* MQ_DOORBELL register */
 834	void __iomem *BMBXregaddr;	/* BootStrap MBX register */
 835
 836	uint32_t ue_mask_lo;
 837	uint32_t ue_mask_hi;
 838	uint32_t ue_to_sr;
 839	uint32_t ue_to_rp;
 840	struct lpfc_register sli_intf;
 841	struct lpfc_pc_sli4_params pc_sli4_params;
 842	struct lpfc_bbscn_params bbscn_params;
 843	struct lpfc_hba_eq_hdl *hba_eq_hdl; /* HBA per-WQ handle */
 844
 845	void (*sli4_eq_clr_intr)(struct lpfc_queue *q);
 846	void (*sli4_write_eq_db)(struct lpfc_hba *phba, struct lpfc_queue *eq,
 847				uint32_t count, bool arm);
 848	void (*sli4_write_cq_db)(struct lpfc_hba *phba, struct lpfc_queue *cq,
 849				uint32_t count, bool arm);
 850
 851	/* Pointers to the constructed SLI4 queues */
 852	struct lpfc_sli4_hdw_queue *hdwq;
 853	struct list_head lpfc_wq_list;
 854
 855	/* Pointers to the constructed SLI4 queues for NVMET */
 856	struct lpfc_queue **nvmet_cqset; /* Fast-path NVMET CQ Set queues */
 857	struct lpfc_queue **nvmet_mrq_hdr; /* Fast-path NVMET hdr MRQs */
 858	struct lpfc_queue **nvmet_mrq_data; /* Fast-path NVMET data MRQs */
 859
 860	struct lpfc_queue *mbx_cq; /* Slow-path mailbox complete queue */
 861	struct lpfc_queue *els_cq; /* Slow-path ELS response complete queue */
 862	struct lpfc_queue *nvmels_cq; /* NVME LS complete queue */
 863	struct lpfc_queue *mbx_wq; /* Slow-path MBOX work queue */
 864	struct lpfc_queue *els_wq; /* Slow-path ELS work queue */
 865	struct lpfc_queue *nvmels_wq; /* NVME LS work queue */
 866	struct lpfc_queue *hdr_rq; /* Slow-path Header Receive queue */
 867	struct lpfc_queue *dat_rq; /* Slow-path Data Receive queue */
 868
 869	struct lpfc_name wwnn;
 870	struct lpfc_name wwpn;
 871
 872	uint32_t fw_func_mode;	/* FW function protocol mode */
 873
 874	/* Optimized Access Storage specific queues/structures */
 875	uint64_t oas_next_lun;
 876	uint8_t oas_next_tgt_wwpn[8];
 877	uint8_t oas_next_vpt_wwpn[8];
 878
 879	/* Setup information for various queue parameters */
 880	int eq_esize;
 881	int eq_ecount;
 882	int cq_esize;
 883	int cq_ecount;
 884	int wq_esize;
 885	int wq_ecount;
 886	int mq_esize;
 887	int mq_ecount;
 888	int rq_esize;
 889	int rq_ecount;
 890#define LPFC_SP_EQ_MAX_INTR_SEC         10000
 891#define LPFC_FP_EQ_MAX_INTR_SEC         10000
 892
 893	uint32_t intr_enable;
 894	struct lpfc_bmbx bmbx;
 895	struct lpfc_max_cfg_param max_cfg_param;
 896	uint16_t extents_in_use; /* must allocate resource extents. */
 897	uint16_t rpi_hdrs_in_use; /* must post rpi hdrs if set. */
 898	uint16_t next_xri; /* last_xri - max_cfg_param.xri_base = used */
 899	uint16_t next_rpi;
 900	uint16_t io_xri_max;
 901	uint16_t io_xri_cnt;
 902	uint16_t io_xri_start;
 903	uint16_t els_xri_cnt;
 904	uint16_t nvmet_xri_cnt;
 905	uint16_t nvmet_io_wait_cnt;
 906	uint16_t nvmet_io_wait_total;
 907	uint16_t cq_max;
 908	struct lpfc_queue **cq_lookup;
 909	struct list_head lpfc_els_sgl_list;
 910	struct list_head lpfc_abts_els_sgl_list;
 911	spinlock_t abts_io_buf_list_lock; /* list of aborted SCSI IOs */
 912	struct list_head lpfc_abts_io_buf_list;
 913	struct list_head lpfc_nvmet_sgl_list;
 914	spinlock_t abts_nvmet_buf_list_lock; /* list of aborted NVMET IOs */
 915	struct list_head lpfc_abts_nvmet_ctx_list;
 916	spinlock_t t_active_list_lock; /* list of active NVMET IOs */
 917	struct list_head t_active_ctx_list;
 918	struct list_head lpfc_nvmet_io_wait_list;
 919	struct lpfc_nvmet_ctx_info *nvmet_ctx_info;
 920	struct lpfc_sglq **lpfc_sglq_active_list;
 921	struct list_head lpfc_rpi_hdr_list;
 922	unsigned long *rpi_bmask;
 923	uint16_t *rpi_ids;
 924	uint16_t rpi_count;
 925	struct list_head lpfc_rpi_blk_list;
 926	unsigned long *xri_bmask;
 927	uint16_t *xri_ids;
 928	struct list_head lpfc_xri_blk_list;
 929	unsigned long *vfi_bmask;
 930	uint16_t *vfi_ids;
 931	uint16_t vfi_count;
 932	struct list_head lpfc_vfi_blk_list;
 933	struct lpfc_sli4_flags sli4_flags;
 934	struct list_head sp_queue_event;
 935	struct list_head sp_cqe_event_pool;
 936	struct list_head sp_asynce_work_queue;
 937	spinlock_t asynce_list_lock; /* protect sp_asynce_work_queue list */
 938	struct list_head sp_els_xri_aborted_work_queue;
 939	spinlock_t els_xri_abrt_list_lock; /* protect els_xri_aborted list */
 940	struct list_head sp_unsol_work_queue;
 941	struct lpfc_sli4_link link_state;
 942	struct lpfc_sli4_lnk_info lnk_info;
 943	uint32_t pport_name_sta;
 944#define LPFC_SLI4_PPNAME_NON	0
 945#define LPFC_SLI4_PPNAME_GET	1
 946	struct lpfc_iov iov;
 947	spinlock_t sgl_list_lock; /* list of aborted els IOs */
 948	spinlock_t nvmet_io_wait_lock; /* IOs waiting for ctx resources */
 949	uint32_t physical_port;
 950
 951	/* CPU to vector mapping information */
 952	struct lpfc_vector_map_info *cpu_map;
 953	uint16_t num_possible_cpu;
 954	uint16_t num_present_cpu;
 955	struct cpumask irq_aff_mask;
 956	uint16_t curr_disp_cpu;
 957	struct lpfc_eq_intr_info __percpu *eq_info;
 958#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
 959	struct lpfc_hdwq_stat __percpu *c_stat;
 960#endif
 961	struct lpfc_idle_stat *idle_stat;
 962	uint32_t conf_trunk;
 963#define lpfc_conf_trunk_port0_WORD	conf_trunk
 964#define lpfc_conf_trunk_port0_SHIFT	0
 965#define lpfc_conf_trunk_port0_MASK	0x1
 966#define lpfc_conf_trunk_port1_WORD	conf_trunk
 967#define lpfc_conf_trunk_port1_SHIFT	1
 968#define lpfc_conf_trunk_port1_MASK	0x1
 969#define lpfc_conf_trunk_port2_WORD	conf_trunk
 970#define lpfc_conf_trunk_port2_SHIFT	2
 971#define lpfc_conf_trunk_port2_MASK	0x1
 972#define lpfc_conf_trunk_port3_WORD	conf_trunk
 973#define lpfc_conf_trunk_port3_SHIFT	3
 974#define lpfc_conf_trunk_port3_MASK	0x1
 975#define lpfc_conf_trunk_port0_nd_WORD	conf_trunk
 976#define lpfc_conf_trunk_port0_nd_SHIFT	4
 977#define lpfc_conf_trunk_port0_nd_MASK	0x1
 978#define lpfc_conf_trunk_port1_nd_WORD	conf_trunk
 979#define lpfc_conf_trunk_port1_nd_SHIFT	5
 980#define lpfc_conf_trunk_port1_nd_MASK	0x1
 981#define lpfc_conf_trunk_port2_nd_WORD	conf_trunk
 982#define lpfc_conf_trunk_port2_nd_SHIFT	6
 983#define lpfc_conf_trunk_port2_nd_MASK	0x1
 984#define lpfc_conf_trunk_port3_nd_WORD	conf_trunk
 985#define lpfc_conf_trunk_port3_nd_SHIFT	7
 986#define lpfc_conf_trunk_port3_nd_MASK	0x1
 987	uint8_t flash_id;
 988	uint8_t asic_rev;
 989	uint16_t fawwpn_flag;	/* FA-WWPN support state */
 990#define LPFC_FAWWPN_CONFIG	0x1 /* FA-PWWN is configured */
 991#define LPFC_FAWWPN_FABRIC	0x2 /* FA-PWWN success with Fabric */
 992};
 993
 994enum lpfc_sge_type {
 995	GEN_BUFF_TYPE,
 996	SCSI_BUFF_TYPE,
 997	NVMET_BUFF_TYPE
 998};
 999
1000enum lpfc_sgl_state {
1001	SGL_FREED,
1002	SGL_ALLOCATED,
1003	SGL_XRI_ABORTED
1004};
1005
1006struct lpfc_sglq {
1007	/* lpfc_sglqs are used in double linked lists */
1008	struct list_head list;
1009	struct list_head clist;
1010	enum lpfc_sge_type buff_type; /* is this a scsi sgl */
1011	enum lpfc_sgl_state state;
1012	struct lpfc_nodelist *ndlp; /* ndlp associated with IO */
1013	uint16_t iotag;         /* pre-assigned IO tag */
1014	uint16_t sli4_lxritag;  /* logical pre-assigned xri. */
1015	uint16_t sli4_xritag;   /* pre-assigned XRI, (OXID) tag. */
1016	struct sli4_sge *sgl;	/* pre-assigned SGL */
1017	void *virt;		/* virtual address. */
1018	dma_addr_t phys;	/* physical address */
1019};
1020
1021struct lpfc_rpi_hdr {
1022	struct list_head list;
1023	uint32_t len;
1024	struct lpfc_dmabuf *dmabuf;
1025	uint32_t page_count;
1026	uint32_t start_rpi;
1027	uint16_t next_rpi;
1028};
1029
1030struct lpfc_rsrc_blks {
1031	struct list_head list;
1032	uint16_t rsrc_start;
1033	uint16_t rsrc_size;
1034	uint16_t rsrc_used;
1035};
1036
1037struct lpfc_rdp_context {
1038	struct lpfc_nodelist *ndlp;
1039	uint16_t ox_id;
1040	uint16_t rx_id;
1041	READ_LNK_VAR link_stat;
1042	uint8_t page_a0[DMP_SFF_PAGE_A0_SIZE];
1043	uint8_t page_a2[DMP_SFF_PAGE_A2_SIZE];
1044	void (*cmpl)(struct lpfc_hba *, struct lpfc_rdp_context*, int);
1045};
1046
1047struct lpfc_lcb_context {
1048	uint8_t  sub_command;
1049	uint8_t  type;
1050	uint8_t  capability;
1051	uint8_t  frequency;
1052	uint16_t  duration;
1053	uint16_t ox_id;
1054	uint16_t rx_id;
1055	struct lpfc_nodelist *ndlp;
1056};
1057
1058
1059/*
1060 * SLI4 specific function prototypes
1061 */
1062int lpfc_pci_function_reset(struct lpfc_hba *);
1063int lpfc_sli4_pdev_status_reg_wait(struct lpfc_hba *);
1064int lpfc_sli4_hba_setup(struct lpfc_hba *);
1065int lpfc_sli4_config(struct lpfc_hba *, struct lpfcMboxq *, uint8_t,
1066		     uint8_t, uint32_t, bool);
1067void lpfc_sli4_mbox_cmd_free(struct lpfc_hba *, struct lpfcMboxq *);
1068void lpfc_sli4_mbx_sge_set(struct lpfcMboxq *, uint32_t, dma_addr_t, uint32_t);
1069void lpfc_sli4_mbx_sge_get(struct lpfcMboxq *, uint32_t,
1070			   struct lpfc_mbx_sge *);
1071int lpfc_sli4_mbx_read_fcf_rec(struct lpfc_hba *, struct lpfcMboxq *,
1072			       uint16_t);
1073
1074void lpfc_sli4_hba_reset(struct lpfc_hba *);
1075struct lpfc_queue *lpfc_sli4_queue_alloc(struct lpfc_hba *phba,
1076					 uint32_t page_size,
1077					 uint32_t entry_size,
1078					 uint32_t entry_count, int cpu);
1079void lpfc_sli4_queue_free(struct lpfc_queue *);
1080int lpfc_eq_create(struct lpfc_hba *, struct lpfc_queue *, uint32_t);
1081void lpfc_modify_hba_eq_delay(struct lpfc_hba *phba, uint32_t startq,
1082			     uint32_t numq, uint32_t usdelay);
1083int lpfc_cq_create(struct lpfc_hba *, struct lpfc_queue *,
1084			struct lpfc_queue *, uint32_t, uint32_t);
1085int lpfc_cq_create_set(struct lpfc_hba *phba, struct lpfc_queue **cqp,
1086			struct lpfc_sli4_hdw_queue *hdwq, uint32_t type,
1087			uint32_t subtype);
1088int32_t lpfc_mq_create(struct lpfc_hba *, struct lpfc_queue *,
1089		       struct lpfc_queue *, uint32_t);
1090int lpfc_wq_create(struct lpfc_hba *, struct lpfc_queue *,
1091			struct lpfc_queue *, uint32_t);
1092int lpfc_rq_create(struct lpfc_hba *, struct lpfc_queue *,
1093			struct lpfc_queue *, struct lpfc_queue *, uint32_t);
1094int lpfc_mrq_create(struct lpfc_hba *phba, struct lpfc_queue **hrqp,
1095			struct lpfc_queue **drqp, struct lpfc_queue **cqp,
1096			uint32_t subtype);
1097int lpfc_eq_destroy(struct lpfc_hba *, struct lpfc_queue *);
1098int lpfc_cq_destroy(struct lpfc_hba *, struct lpfc_queue *);
1099int lpfc_mq_destroy(struct lpfc_hba *, struct lpfc_queue *);
1100int lpfc_wq_destroy(struct lpfc_hba *, struct lpfc_queue *);
1101int lpfc_rq_destroy(struct lpfc_hba *, struct lpfc_queue *,
1102			 struct lpfc_queue *);
1103int lpfc_sli4_queue_setup(struct lpfc_hba *);
1104void lpfc_sli4_queue_unset(struct lpfc_hba *);
1105int lpfc_sli4_post_sgl(struct lpfc_hba *, dma_addr_t, dma_addr_t, uint16_t);
1106int lpfc_repost_io_sgl_list(struct lpfc_hba *phba);
1107uint16_t lpfc_sli4_next_xritag(struct lpfc_hba *);
1108void lpfc_sli4_free_xri(struct lpfc_hba *, int);
1109int lpfc_sli4_post_async_mbox(struct lpfc_hba *);
1110struct lpfc_cq_event *__lpfc_sli4_cq_event_alloc(struct lpfc_hba *);
1111struct lpfc_cq_event *lpfc_sli4_cq_event_alloc(struct lpfc_hba *);
1112void __lpfc_sli4_cq_event_release(struct lpfc_hba *, struct lpfc_cq_event *);
1113void lpfc_sli4_cq_event_release(struct lpfc_hba *, struct lpfc_cq_event *);
1114int lpfc_sli4_init_rpi_hdrs(struct lpfc_hba *);
1115int lpfc_sli4_post_rpi_hdr(struct lpfc_hba *, struct lpfc_rpi_hdr *);
1116int lpfc_sli4_post_all_rpi_hdrs(struct lpfc_hba *);
1117struct lpfc_rpi_hdr *lpfc_sli4_create_rpi_hdr(struct lpfc_hba *);
1118void lpfc_sli4_remove_rpi_hdrs(struct lpfc_hba *);
1119int lpfc_sli4_alloc_rpi(struct lpfc_hba *);
1120void lpfc_sli4_free_rpi(struct lpfc_hba *, int);
1121void lpfc_sli4_remove_rpis(struct lpfc_hba *);
1122void lpfc_sli4_async_event_proc(struct lpfc_hba *);
1123void lpfc_sli4_fcf_redisc_event_proc(struct lpfc_hba *);
1124int lpfc_sli4_resume_rpi(struct lpfc_nodelist *ndlp,
1125			 void (*cmpl)(struct lpfc_hba *, LPFC_MBOXQ_t *),
1126			 struct lpfc_iocbq *iocbq);
1127void lpfc_sli4_els_xri_abort_event_proc(struct lpfc_hba *phba);
1128void lpfc_sli4_nvme_pci_offline_aborted(struct lpfc_hba *phba,
1129					struct lpfc_io_buf *lpfc_ncmd);
1130void lpfc_sli4_nvme_xri_aborted(struct lpfc_hba *phba,
1131				struct sli4_wcqe_xri_aborted *axri,
1132				struct lpfc_io_buf *lpfc_ncmd);
1133void lpfc_sli4_io_xri_aborted(struct lpfc_hba *phba,
1134			      struct sli4_wcqe_xri_aborted *axri, int idx);
1135void lpfc_sli4_nvmet_xri_aborted(struct lpfc_hba *phba,
1136				 struct sli4_wcqe_xri_aborted *axri);
1137void lpfc_sli4_els_xri_aborted(struct lpfc_hba *,
1138			       struct sli4_wcqe_xri_aborted *);
1139void lpfc_sli4_vport_delete_els_xri_aborted(struct lpfc_vport *);
1140void lpfc_sli4_vport_delete_fcp_xri_aborted(struct lpfc_vport *);
1141int lpfc_sli4_brdreset(struct lpfc_hba *);
1142int lpfc_sli4_add_fcf_record(struct lpfc_hba *, struct fcf_record *);
1143void lpfc_sli_remove_dflt_fcf(struct lpfc_hba *);
1144int lpfc_sli4_get_els_iocb_cnt(struct lpfc_hba *);
1145int lpfc_sli4_get_iocb_cnt(struct lpfc_hba *phba);
1146int lpfc_sli4_init_vpi(struct lpfc_vport *);
1147void lpfc_sli4_eq_clr_intr(struct lpfc_queue *);
1148void lpfc_sli4_write_cq_db(struct lpfc_hba *phba, struct lpfc_queue *q,
1149			   uint32_t count, bool arm);
1150void lpfc_sli4_write_eq_db(struct lpfc_hba *phba, struct lpfc_queue *q,
1151			   uint32_t count, bool arm);
1152void lpfc_sli4_if6_eq_clr_intr(struct lpfc_queue *q);
1153void lpfc_sli4_if6_write_cq_db(struct lpfc_hba *phba, struct lpfc_queue *q,
1154			       uint32_t count, bool arm);
1155void lpfc_sli4_if6_write_eq_db(struct lpfc_hba *phba, struct lpfc_queue *q,
1156			       uint32_t count, bool arm);
1157void lpfc_sli4_fcfi_unreg(struct lpfc_hba *, uint16_t);
1158int lpfc_sli4_fcf_scan_read_fcf_rec(struct lpfc_hba *, uint16_t);
1159int lpfc_sli4_fcf_rr_read_fcf_rec(struct lpfc_hba *, uint16_t);
1160int lpfc_sli4_read_fcf_rec(struct lpfc_hba *, uint16_t);
1161void lpfc_mbx_cmpl_fcf_scan_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *);
1162void lpfc_mbx_cmpl_fcf_rr_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *);
1163void lpfc_mbx_cmpl_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *);
1164int lpfc_sli4_unregister_fcf(struct lpfc_hba *);
1165int lpfc_sli4_post_status_check(struct lpfc_hba *);
1166uint8_t lpfc_sli_config_mbox_subsys_get(struct lpfc_hba *, LPFC_MBOXQ_t *);
1167uint8_t lpfc_sli_config_mbox_opcode_get(struct lpfc_hba *, LPFC_MBOXQ_t *);
1168void lpfc_sli4_ras_dma_free(struct lpfc_hba *phba);
1169struct sli4_hybrid_sgl *lpfc_get_sgl_per_hdwq(struct lpfc_hba *phba,
1170					      struct lpfc_io_buf *buf);
1171struct fcp_cmd_rsp_buf *lpfc_get_cmd_rsp_buf_per_hdwq(struct lpfc_hba *phba,
1172						      struct lpfc_io_buf *buf);
1173int lpfc_put_sgl_per_hdwq(struct lpfc_hba *phba, struct lpfc_io_buf *buf);
1174int lpfc_put_cmd_rsp_buf_per_hdwq(struct lpfc_hba *phba,
1175				  struct lpfc_io_buf *buf);
1176void lpfc_free_sgl_per_hdwq(struct lpfc_hba *phba,
1177			    struct lpfc_sli4_hdw_queue *hdwq);
1178void lpfc_free_cmd_rsp_buf_per_hdwq(struct lpfc_hba *phba,
1179				    struct lpfc_sli4_hdw_queue *hdwq);
1180static inline void *lpfc_sli4_qe(struct lpfc_queue *q, uint16_t idx)
1181{
1182	return q->q_pgs[idx / q->entry_cnt_per_pg] +
1183		(q->entry_size * (idx % q->entry_cnt_per_pg));
1184}
1185
1186/**
1187 * lpfc_sli4_unrecoverable_port - Check ERR and RN bits in portstat_reg
1188 * @portstat_reg: portstat_reg pointer containing portstat_reg contents
1189 *
1190 * Description:
1191 * Use only for SLI4 interface type-2 or later.  If ERR is set && RN is 0, then
1192 * port is deemed unrecoverable.
1193 *
1194 * Returns:
1195 * true		- ERR && !RN
1196 * false	- otherwise
1197 */
1198static inline bool
1199lpfc_sli4_unrecoverable_port(struct lpfc_register *portstat_reg)
1200{
1201	return bf_get(lpfc_sliport_status_err, portstat_reg) &&
1202	       !bf_get(lpfc_sliport_status_rn, portstat_reg);
1203}