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lpfc_hw4.h
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linux-6.19.14/drivers/scsi/lpfc/lpfc_hw4.h
1/******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2017-2025 Broadcom. All Rights Reserved. The term * 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. * 6 * Copyright (C) 2009-2016 Emulex. All rights reserved. * 7 * EMULEX and SLI are trademarks of Emulex. * 8 * www.broadcom.com * 9 * * 10 * This program is free software; you can redistribute it and/or * 11 * modify it under the terms of version 2 of the GNU General * 12 * Public License as published by the Free Software Foundation. * 13 * This program is distributed in the hope that it will be useful. * 14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 18 * TO BE LEGALLY INVALID. See the GNU General Public License for * 19 * more details, a copy of which can be found in the file COPYING * 20 * included with this package. * 21 *******************************************************************/ 22 23#include <uapi/scsi/fc/fc_fs.h> 24#include <uapi/scsi/fc/fc_els.h> 25 26/* Macros to deal with bit fields. Each bit field must have 3 #defines 27 * associated with it (_SHIFT, _MASK, and _WORD). 28 * EG. For a bit field that is in the 7th bit of the "field4" field of a 29 * structure and is 2 bits in size the following #defines must exist: 30 * struct temp { 31 * uint32_t field1; 32 * uint32_t field2; 33 * uint32_t field3; 34 * uint32_t field4; 35 * #define example_bit_field_SHIFT 7 36 * #define example_bit_field_MASK 0x03 37 * #define example_bit_field_WORD field4 38 * uint32_t field5; 39 * }; 40 * Then the macros below may be used to get or set the value of that field. 41 * EG. To get the value of the bit field from the above example: 42 * struct temp t1; 43 * value = bf_get(example_bit_field, &t1); 44 * And then to set that bit field: 45 * bf_set(example_bit_field, &t1, 2); 46 * Or clear that bit field: 47 * bf_set(example_bit_field, &t1, 0); 48 */ 49#define bf_get_be32(name, ptr) \ 50 ((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 51#define bf_get_le32(name, ptr) \ 52 ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 53#define bf_get(name, ptr) \ 54 (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK) 55#define bf_set_le32(name, ptr, value) \ 56 ((ptr)->name##_WORD = cpu_to_le32(((((value) & \ 57 name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \ 58 ~(name##_MASK << name##_SHIFT))))) 59#define bf_set(name, ptr, value) \ 60 ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \ 61 ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT)))) 62 63#define get_wqe_reqtag(x) (((x)->wqe.words[9] >> 0) & 0xFFFF) 64#define get_wqe_tmo(x) (((x)->wqe.words[7] >> 24) & 0x00FF) 65 66#define get_job_ulpword(x, y) ((x)->iocb.un.ulpWord[y]) 67 68#define set_job_ulpstatus(x, y) bf_set(lpfc_wcqe_c_status, &(x)->wcqe_cmpl, y) 69#define set_job_ulpword4(x, y) ((&(x)->wcqe_cmpl)->parameter = y) 70 71struct dma_address { 72 uint32_t addr_lo; 73 uint32_t addr_hi; 74}; 75 76struct lpfc_sli_intf { 77 uint32_t word0; 78#define lpfc_sli_intf_valid_SHIFT 29 79#define lpfc_sli_intf_valid_MASK 0x00000007 80#define lpfc_sli_intf_valid_WORD word0 81#define LPFC_SLI_INTF_VALID 6 82#define lpfc_sli_intf_sli_hint2_SHIFT 24 83#define lpfc_sli_intf_sli_hint2_MASK 0x0000001F 84#define lpfc_sli_intf_sli_hint2_WORD word0 85#define LPFC_SLI_INTF_SLI_HINT2_NONE 0 86#define lpfc_sli_intf_sli_hint1_SHIFT 16 87#define lpfc_sli_intf_sli_hint1_MASK 0x000000FF 88#define lpfc_sli_intf_sli_hint1_WORD word0 89#define LPFC_SLI_INTF_SLI_HINT1_NONE 0 90#define LPFC_SLI_INTF_SLI_HINT1_1 1 91#define LPFC_SLI_INTF_SLI_HINT1_2 2 92#define lpfc_sli_intf_if_type_SHIFT 12 93#define lpfc_sli_intf_if_type_MASK 0x0000000F 94#define lpfc_sli_intf_if_type_WORD word0 95#define LPFC_SLI_INTF_IF_TYPE_0 0 96#define LPFC_SLI_INTF_IF_TYPE_1 1 97#define LPFC_SLI_INTF_IF_TYPE_2 2 98#define LPFC_SLI_INTF_IF_TYPE_6 6 99#define lpfc_sli_intf_sli_family_SHIFT 8 100#define lpfc_sli_intf_sli_family_MASK 0x0000000F 101#define lpfc_sli_intf_sli_family_WORD word0 102#define LPFC_SLI_INTF_FAMILY_BE2 0x0 103#define LPFC_SLI_INTF_FAMILY_BE3 0x1 104#define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa 105#define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb 106#define LPFC_SLI_INTF_FAMILY_G6 0xc 107#define LPFC_SLI_INTF_FAMILY_G7 0xd 108#define LPFC_SLI_INTF_FAMILY_G7P 0xe 109#define lpfc_sli_intf_slirev_SHIFT 4 110#define lpfc_sli_intf_slirev_MASK 0x0000000F 111#define lpfc_sli_intf_slirev_WORD word0 112#define LPFC_SLI_INTF_REV_SLI3 3 113#define LPFC_SLI_INTF_REV_SLI4 4 114#define lpfc_sli_intf_func_type_SHIFT 0 115#define lpfc_sli_intf_func_type_MASK 0x00000001 116#define lpfc_sli_intf_func_type_WORD word0 117#define LPFC_SLI_INTF_IF_TYPE_PHYS 0 118#define LPFC_SLI_INTF_IF_TYPE_VIRT 1 119}; 120 121#define LPFC_SLI4_MBX_EMBED true 122#define LPFC_SLI4_MBX_NEMBED false 123 124#define LPFC_SLI4_MB_WORD_COUNT 64 125#define LPFC_MAX_MQ_PAGE 8 126#define LPFC_MAX_WQ_PAGE_V0 4 127#define LPFC_MAX_WQ_PAGE 8 128#define LPFC_MAX_RQ_PAGE 8 129#define LPFC_MAX_CQ_PAGE 4 130#define LPFC_MAX_EQ_PAGE 8 131 132#define LPFC_VIR_FUNC_MAX 32 /* Maximum number of virtual functions */ 133#define LPFC_PCI_FUNC_MAX 5 /* Maximum number of PCI functions */ 134#define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */ 135 136/* Define SLI4 Alignment requirements. */ 137#define LPFC_ALIGN_16_BYTE 16 138#define LPFC_ALIGN_64_BYTE 64 139#define SLI4_PAGE_SIZE 4096 140 141/* Define SLI4 specific definitions. */ 142#define LPFC_MQ_CQE_BYTE_OFFSET 256 143#define LPFC_MBX_CMD_HDR_LENGTH 16 144#define LPFC_MBX_ERROR_RANGE 0x4000 145#define LPFC_BMBX_BIT1_ADDR_HI 0x2 146#define LPFC_BMBX_BIT1_ADDR_LO 0 147#define LPFC_RPI_HDR_COUNT 64 148#define LPFC_HDR_TEMPLATE_SIZE 4096 149#define LPFC_RPI_ALLOC_ERROR 0xFFFF 150#define LPFC_FCF_RECORD_WD_CNT 132 151#define LPFC_ENTIRE_FCF_DATABASE 0 152#define LPFC_DFLT_FCF_INDEX 0 153 154/* Virtual function numbers */ 155#define LPFC_VF0 0 156#define LPFC_VF1 1 157#define LPFC_VF2 2 158#define LPFC_VF3 3 159#define LPFC_VF4 4 160#define LPFC_VF5 5 161#define LPFC_VF6 6 162#define LPFC_VF7 7 163#define LPFC_VF8 8 164#define LPFC_VF9 9 165#define LPFC_VF10 10 166#define LPFC_VF11 11 167#define LPFC_VF12 12 168#define LPFC_VF13 13 169#define LPFC_VF14 14 170#define LPFC_VF15 15 171#define LPFC_VF16 16 172#define LPFC_VF17 17 173#define LPFC_VF18 18 174#define LPFC_VF19 19 175#define LPFC_VF20 20 176#define LPFC_VF21 21 177#define LPFC_VF22 22 178#define LPFC_VF23 23 179#define LPFC_VF24 24 180#define LPFC_VF25 25 181#define LPFC_VF26 26 182#define LPFC_VF27 27 183#define LPFC_VF28 28 184#define LPFC_VF29 29 185#define LPFC_VF30 30 186#define LPFC_VF31 31 187 188/* PCI function numbers */ 189#define LPFC_PCI_FUNC0 0 190#define LPFC_PCI_FUNC1 1 191#define LPFC_PCI_FUNC2 2 192#define LPFC_PCI_FUNC3 3 193#define LPFC_PCI_FUNC4 4 194 195/* SLI4 interface type-2 PDEV_CTL register */ 196#define LPFC_CTL_PDEV_CTL_OFFSET 0x414 197#define LPFC_CTL_PDEV_CTL_DRST 0x00000001 198#define LPFC_CTL_PDEV_CTL_FRST 0x00000002 199#define LPFC_CTL_PDEV_CTL_DD 0x00000004 200#define LPFC_CTL_PDEV_CTL_LC 0x00000008 201#define LPFC_CTL_PDEV_CTL_FRL_ALL 0x00 202#define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE 0x10 203#define LPFC_CTL_PDEV_CTL_FRL_NIC 0x20 204#define LPFC_CTL_PDEV_CTL_DDL_RAS 0x1000000 205 206#define LPFC_FW_DUMP_REQUEST (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST) 207 208/* Active interrupt test count */ 209#define LPFC_ACT_INTR_CNT 4 210 211/* Algrithmns for scheduling FCP commands to WQs */ 212#define LPFC_FCP_SCHED_BY_HDWQ 0 213#define LPFC_FCP_SCHED_BY_CPU 1 214 215/* Algrithmns for NameServer Query after RSCN */ 216#define LPFC_NS_QUERY_GID_FT 0 217#define LPFC_NS_QUERY_GID_PT 1 218 219/* Delay Multiplier constant */ 220#define LPFC_DMULT_CONST 651042 221#define LPFC_DMULT_MAX 1023 222 223/* Configuration of Interrupts / sec for entire HBA port */ 224#define LPFC_MIN_IMAX 5000 225#define LPFC_MAX_IMAX 5000000 226#define LPFC_DEF_IMAX 0 227 228#define LPFC_MAX_AUTO_EQ_DELAY 120 229#define LPFC_EQ_DELAY_STEP 15 230#define LPFC_EQD_ISR_TRIGGER 20000 231/* 1s intervals */ 232#define LPFC_EQ_DELAY_MSECS 1000 233 234#define LPFC_MIN_CPU_MAP 0 235#define LPFC_MAX_CPU_MAP 1 236#define LPFC_HBA_CPU_MAP 1 237 238/* PORT_CAPABILITIES constants. */ 239#define LPFC_MAX_SUPPORTED_PAGES 8 240 241enum ulp_bde64_word3 { 242 ULP_BDE64_SIZE_MASK = 0xffffff, 243 244 ULP_BDE64_TYPE_SHIFT = 24, 245 ULP_BDE64_TYPE_MASK = (0xff << ULP_BDE64_TYPE_SHIFT), 246 247 /* BDE (Host_resident) */ 248 ULP_BDE64_TYPE_BDE_64 = (0x00 << ULP_BDE64_TYPE_SHIFT), 249 /* Immediate Data BDE */ 250 ULP_BDE64_TYPE_BDE_IMMED = (0x01 << ULP_BDE64_TYPE_SHIFT), 251 /* BDE (Port-resident) */ 252 ULP_BDE64_TYPE_BDE_64P = (0x02 << ULP_BDE64_TYPE_SHIFT), 253 /* Input BDE (Host-resident) */ 254 ULP_BDE64_TYPE_BDE_64I = (0x08 << ULP_BDE64_TYPE_SHIFT), 255 /* Input BDE (Port-resident) */ 256 ULP_BDE64_TYPE_BDE_64IP = (0x0A << ULP_BDE64_TYPE_SHIFT), 257 /* BLP (Host-resident) */ 258 ULP_BDE64_TYPE_BLP_64 = (0x40 << ULP_BDE64_TYPE_SHIFT), 259 /* BLP (Port-resident) */ 260 ULP_BDE64_TYPE_BLP_64P = (0x42 << ULP_BDE64_TYPE_SHIFT), 261}; 262 263struct ulp_bde64_le { 264 __le32 type_size; /* type 31:24, size 23:0 */ 265 __le32 addr_low; 266 __le32 addr_high; 267}; 268 269struct ulp_bde64 { 270 union ULP_BDE_TUS { 271 uint32_t w; 272 struct { 273#ifdef __BIG_ENDIAN_BITFIELD 274 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 275 VALUE !! */ 276 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 277#else /* __LITTLE_ENDIAN_BITFIELD */ 278 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 279 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 280 VALUE !! */ 281#endif 282#define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */ 283#define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */ 284#define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */ 285#define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */ 286#define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */ 287#define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */ 288#define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */ 289 } f; 290 } tus; 291 uint32_t addrLow; 292 uint32_t addrHigh; 293}; 294 295/* Maximun size of immediate data that can fit into a 128 byte WQE */ 296#define LPFC_MAX_BDE_IMM_SIZE 64 297 298struct lpfc_sli4_flags { 299 uint32_t word0; 300#define lpfc_idx_rsrc_rdy_SHIFT 0 301#define lpfc_idx_rsrc_rdy_MASK 0x00000001 302#define lpfc_idx_rsrc_rdy_WORD word0 303#define LPFC_IDX_RSRC_RDY 1 304#define lpfc_rpi_rsrc_rdy_SHIFT 1 305#define lpfc_rpi_rsrc_rdy_MASK 0x00000001 306#define lpfc_rpi_rsrc_rdy_WORD word0 307#define LPFC_RPI_RSRC_RDY 1 308#define lpfc_vpi_rsrc_rdy_SHIFT 2 309#define lpfc_vpi_rsrc_rdy_MASK 0x00000001 310#define lpfc_vpi_rsrc_rdy_WORD word0 311#define LPFC_VPI_RSRC_RDY 1 312#define lpfc_vfi_rsrc_rdy_SHIFT 3 313#define lpfc_vfi_rsrc_rdy_MASK 0x00000001 314#define lpfc_vfi_rsrc_rdy_WORD word0 315#define LPFC_VFI_RSRC_RDY 1 316#define lpfc_ftr_ashdr_SHIFT 4 317#define lpfc_ftr_ashdr_MASK 0x00000001 318#define lpfc_ftr_ashdr_WORD word0 319}; 320 321struct sli4_bls_rsp { 322 uint32_t word0_rsvd; /* Word0 must be reserved */ 323 uint32_t word1; 324#define lpfc_abts_orig_SHIFT 0 325#define lpfc_abts_orig_MASK 0x00000001 326#define lpfc_abts_orig_WORD word1 327#define LPFC_ABTS_UNSOL_RSP 1 328#define LPFC_ABTS_UNSOL_INT 0 329 uint32_t word2; 330#define lpfc_abts_rxid_SHIFT 0 331#define lpfc_abts_rxid_MASK 0x0000FFFF 332#define lpfc_abts_rxid_WORD word2 333#define lpfc_abts_oxid_SHIFT 16 334#define lpfc_abts_oxid_MASK 0x0000FFFF 335#define lpfc_abts_oxid_WORD word2 336 uint32_t word3; 337#define lpfc_vndr_code_SHIFT 0 338#define lpfc_vndr_code_MASK 0x000000FF 339#define lpfc_vndr_code_WORD word3 340#define lpfc_rsn_expln_SHIFT 8 341#define lpfc_rsn_expln_MASK 0x000000FF 342#define lpfc_rsn_expln_WORD word3 343#define lpfc_rsn_code_SHIFT 16 344#define lpfc_rsn_code_MASK 0x000000FF 345#define lpfc_rsn_code_WORD word3 346 347 uint32_t word4; 348 uint32_t word5_rsvd; /* Word5 must be reserved */ 349}; 350 351/* event queue entry structure */ 352struct lpfc_eqe { 353 uint32_t word0; 354#define lpfc_eqe_resource_id_SHIFT 16 355#define lpfc_eqe_resource_id_MASK 0x0000FFFF 356#define lpfc_eqe_resource_id_WORD word0 357#define lpfc_eqe_minor_code_SHIFT 4 358#define lpfc_eqe_minor_code_MASK 0x00000FFF 359#define lpfc_eqe_minor_code_WORD word0 360#define lpfc_eqe_major_code_SHIFT 1 361#define lpfc_eqe_major_code_MASK 0x00000007 362#define lpfc_eqe_major_code_WORD word0 363#define lpfc_eqe_valid_SHIFT 0 364#define lpfc_eqe_valid_MASK 0x00000001 365#define lpfc_eqe_valid_WORD word0 366}; 367 368/* completion queue entry structure (common fields for all cqe types) */ 369struct lpfc_cqe { 370 uint32_t reserved0; 371 uint32_t reserved1; 372 uint32_t reserved2; 373 uint32_t word3; 374#define lpfc_cqe_valid_SHIFT 31 375#define lpfc_cqe_valid_MASK 0x00000001 376#define lpfc_cqe_valid_WORD word3 377#define lpfc_cqe_code_SHIFT 16 378#define lpfc_cqe_code_MASK 0x000000FF 379#define lpfc_cqe_code_WORD word3 380}; 381 382/* Completion Queue Entry Status Codes */ 383#define CQE_STATUS_SUCCESS 0x0 384#define CQE_STATUS_FCP_RSP_FAILURE 0x1 385#define CQE_STATUS_REMOTE_STOP 0x2 386#define CQE_STATUS_LOCAL_REJECT 0x3 387#define CQE_STATUS_NPORT_RJT 0x4 388#define CQE_STATUS_FABRIC_RJT 0x5 389#define CQE_STATUS_NPORT_BSY 0x6 390#define CQE_STATUS_FABRIC_BSY 0x7 391#define CQE_STATUS_INTERMED_RSP 0x8 392#define CQE_STATUS_LS_RJT 0x9 393#define CQE_STATUS_CMD_REJECT 0xb 394#define CQE_STATUS_FCP_TGT_LENCHECK 0xc 395#define CQE_STATUS_NEED_BUFF_ENTRY 0xf 396#define CQE_STATUS_DI_ERROR 0x16 397 398/* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */ 399#define CQE_HW_STATUS_NO_ERR 0x0 400#define CQE_HW_STATUS_UNDERRUN 0x1 401#define CQE_HW_STATUS_OVERRUN 0x2 402 403/* Completion Queue Entry Codes */ 404#define CQE_CODE_COMPL_WQE 0x1 405#define CQE_CODE_RELEASE_WQE 0x2 406#define CQE_CODE_RECEIVE 0x4 407#define CQE_CODE_XRI_ABORTED 0x5 408#define CQE_CODE_RECEIVE_V1 0x9 409#define CQE_CODE_NVME_ERSP 0xd 410 411/* 412 * Define mask value for xri_aborted and wcqe completed CQE extended status. 413 * Currently, extended status is limited to 9 bits (0x0 -> 0x103) . 414 */ 415#define WCQE_PARAM_MASK 0x1FF 416 417/* completion queue entry for wqe completions */ 418struct lpfc_wcqe_complete { 419 uint32_t word0; 420#define lpfc_wcqe_c_request_tag_SHIFT 16 421#define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF 422#define lpfc_wcqe_c_request_tag_WORD word0 423#define lpfc_wcqe_c_status_SHIFT 8 424#define lpfc_wcqe_c_status_MASK 0x000000FF 425#define lpfc_wcqe_c_status_WORD word0 426#define lpfc_wcqe_c_hw_status_SHIFT 0 427#define lpfc_wcqe_c_hw_status_MASK 0x000000FF 428#define lpfc_wcqe_c_hw_status_WORD word0 429#define lpfc_wcqe_c_ersp0_SHIFT 0 430#define lpfc_wcqe_c_ersp0_MASK 0x0000FFFF 431#define lpfc_wcqe_c_ersp0_WORD word0 432 uint32_t total_data_placed; 433#define lpfc_wcqe_c_cmf_cg_SHIFT 31 434#define lpfc_wcqe_c_cmf_cg_MASK 0x00000001 435#define lpfc_wcqe_c_cmf_cg_WORD total_data_placed 436#define lpfc_wcqe_c_cmf_bw_SHIFT 0 437#define lpfc_wcqe_c_cmf_bw_MASK 0x0FFFFFFF 438#define lpfc_wcqe_c_cmf_bw_WORD total_data_placed 439 uint32_t parameter; 440#define lpfc_wcqe_c_bg_edir_SHIFT 5 441#define lpfc_wcqe_c_bg_edir_MASK 0x00000001 442#define lpfc_wcqe_c_bg_edir_WORD parameter 443#define lpfc_wcqe_c_bg_tdpv_SHIFT 3 444#define lpfc_wcqe_c_bg_tdpv_MASK 0x00000001 445#define lpfc_wcqe_c_bg_tdpv_WORD parameter 446#define lpfc_wcqe_c_bg_re_SHIFT 2 447#define lpfc_wcqe_c_bg_re_MASK 0x00000001 448#define lpfc_wcqe_c_bg_re_WORD parameter 449#define lpfc_wcqe_c_bg_ae_SHIFT 1 450#define lpfc_wcqe_c_bg_ae_MASK 0x00000001 451#define lpfc_wcqe_c_bg_ae_WORD parameter 452#define lpfc_wcqe_c_bg_ge_SHIFT 0 453#define lpfc_wcqe_c_bg_ge_MASK 0x00000001 454#define lpfc_wcqe_c_bg_ge_WORD parameter 455 uint32_t word3; 456#define lpfc_wcqe_c_valid_SHIFT lpfc_cqe_valid_SHIFT 457#define lpfc_wcqe_c_valid_MASK lpfc_cqe_valid_MASK 458#define lpfc_wcqe_c_valid_WORD lpfc_cqe_valid_WORD 459#define lpfc_wcqe_c_xb_SHIFT 28 460#define lpfc_wcqe_c_xb_MASK 0x00000001 461#define lpfc_wcqe_c_xb_WORD word3 462#define lpfc_wcqe_c_pv_SHIFT 27 463#define lpfc_wcqe_c_pv_MASK 0x00000001 464#define lpfc_wcqe_c_pv_WORD word3 465#define lpfc_wcqe_c_priority_SHIFT 24 466#define lpfc_wcqe_c_priority_MASK 0x00000007 467#define lpfc_wcqe_c_priority_WORD word3 468#define lpfc_wcqe_c_code_SHIFT lpfc_cqe_code_SHIFT 469#define lpfc_wcqe_c_code_MASK lpfc_cqe_code_MASK 470#define lpfc_wcqe_c_code_WORD lpfc_cqe_code_WORD 471#define lpfc_wcqe_c_sqhead_SHIFT 0 472#define lpfc_wcqe_c_sqhead_MASK 0x0000FFFF 473#define lpfc_wcqe_c_sqhead_WORD word3 474}; 475 476/* completion queue entry for wqe release */ 477struct lpfc_wcqe_release { 478 uint32_t reserved0; 479 uint32_t reserved1; 480 uint32_t word2; 481#define lpfc_wcqe_r_wq_id_SHIFT 16 482#define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF 483#define lpfc_wcqe_r_wq_id_WORD word2 484#define lpfc_wcqe_r_wqe_index_SHIFT 0 485#define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF 486#define lpfc_wcqe_r_wqe_index_WORD word2 487 uint32_t word3; 488#define lpfc_wcqe_r_valid_SHIFT lpfc_cqe_valid_SHIFT 489#define lpfc_wcqe_r_valid_MASK lpfc_cqe_valid_MASK 490#define lpfc_wcqe_r_valid_WORD lpfc_cqe_valid_WORD 491#define lpfc_wcqe_r_code_SHIFT lpfc_cqe_code_SHIFT 492#define lpfc_wcqe_r_code_MASK lpfc_cqe_code_MASK 493#define lpfc_wcqe_r_code_WORD lpfc_cqe_code_WORD 494}; 495 496struct sli4_wcqe_xri_aborted { 497 uint32_t word0; 498#define lpfc_wcqe_xa_status_SHIFT 8 499#define lpfc_wcqe_xa_status_MASK 0x000000FF 500#define lpfc_wcqe_xa_status_WORD word0 501 uint32_t parameter; 502 uint32_t word2; 503#define lpfc_wcqe_xa_remote_xid_SHIFT 16 504#define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF 505#define lpfc_wcqe_xa_remote_xid_WORD word2 506#define lpfc_wcqe_xa_xri_SHIFT 0 507#define lpfc_wcqe_xa_xri_MASK 0x0000FFFF 508#define lpfc_wcqe_xa_xri_WORD word2 509 uint32_t word3; 510#define lpfc_wcqe_xa_valid_SHIFT lpfc_cqe_valid_SHIFT 511#define lpfc_wcqe_xa_valid_MASK lpfc_cqe_valid_MASK 512#define lpfc_wcqe_xa_valid_WORD lpfc_cqe_valid_WORD 513#define lpfc_wcqe_xa_ia_SHIFT 30 514#define lpfc_wcqe_xa_ia_MASK 0x00000001 515#define lpfc_wcqe_xa_ia_WORD word3 516#define CQE_XRI_ABORTED_IA_REMOTE 0 517#define CQE_XRI_ABORTED_IA_LOCAL 1 518#define lpfc_wcqe_xa_br_SHIFT 29 519#define lpfc_wcqe_xa_br_MASK 0x00000001 520#define lpfc_wcqe_xa_br_WORD word3 521#define CQE_XRI_ABORTED_BR_BA_ACC 0 522#define CQE_XRI_ABORTED_BR_BA_RJT 1 523#define lpfc_wcqe_xa_eo_SHIFT 28 524#define lpfc_wcqe_xa_eo_MASK 0x00000001 525#define lpfc_wcqe_xa_eo_WORD word3 526#define CQE_XRI_ABORTED_EO_REMOTE 0 527#define CQE_XRI_ABORTED_EO_LOCAL 1 528#define lpfc_wcqe_xa_code_SHIFT lpfc_cqe_code_SHIFT 529#define lpfc_wcqe_xa_code_MASK lpfc_cqe_code_MASK 530#define lpfc_wcqe_xa_code_WORD lpfc_cqe_code_WORD 531}; 532 533/* completion queue entry structure for rqe completion */ 534struct lpfc_rcqe { 535 uint32_t word0; 536#define lpfc_rcqe_iv_SHIFT 31 537#define lpfc_rcqe_iv_MASK 0x00000001 538#define lpfc_rcqe_iv_WORD word0 539#define lpfc_rcqe_status_SHIFT 8 540#define lpfc_rcqe_status_MASK 0x000000FF 541#define lpfc_rcqe_status_WORD word0 542#define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */ 543#define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */ 544#define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */ 545#define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */ 546#define FC_STATUS_RQ_DMA_FAILURE 0x14 /* DMA failure */ 547 uint32_t word1; 548#define lpfc_rcqe_fcf_id_v1_SHIFT 0 549#define lpfc_rcqe_fcf_id_v1_MASK 0x0000003F 550#define lpfc_rcqe_fcf_id_v1_WORD word1 551 uint32_t word2; 552#define lpfc_rcqe_length_SHIFT 16 553#define lpfc_rcqe_length_MASK 0x0000FFFF 554#define lpfc_rcqe_length_WORD word2 555#define lpfc_rcqe_rq_id_SHIFT 6 556#define lpfc_rcqe_rq_id_MASK 0x000003FF 557#define lpfc_rcqe_rq_id_WORD word2 558#define lpfc_rcqe_fcf_id_SHIFT 0 559#define lpfc_rcqe_fcf_id_MASK 0x0000003F 560#define lpfc_rcqe_fcf_id_WORD word2 561#define lpfc_rcqe_rq_id_v1_SHIFT 0 562#define lpfc_rcqe_rq_id_v1_MASK 0x0000FFFF 563#define lpfc_rcqe_rq_id_v1_WORD word2 564 uint32_t word3; 565#define lpfc_rcqe_valid_SHIFT lpfc_cqe_valid_SHIFT 566#define lpfc_rcqe_valid_MASK lpfc_cqe_valid_MASK 567#define lpfc_rcqe_valid_WORD lpfc_cqe_valid_WORD 568#define lpfc_rcqe_port_SHIFT 30 569#define lpfc_rcqe_port_MASK 0x00000001 570#define lpfc_rcqe_port_WORD word3 571#define lpfc_rcqe_hdr_length_SHIFT 24 572#define lpfc_rcqe_hdr_length_MASK 0x0000001F 573#define lpfc_rcqe_hdr_length_WORD word3 574#define lpfc_rcqe_code_SHIFT lpfc_cqe_code_SHIFT 575#define lpfc_rcqe_code_MASK lpfc_cqe_code_MASK 576#define lpfc_rcqe_code_WORD lpfc_cqe_code_WORD 577#define lpfc_rcqe_eof_SHIFT 8 578#define lpfc_rcqe_eof_MASK 0x000000FF 579#define lpfc_rcqe_eof_WORD word3 580#define FCOE_EOFn 0x41 581#define FCOE_EOFt 0x42 582#define FCOE_EOFni 0x49 583#define FCOE_EOFa 0x50 584#define lpfc_rcqe_sof_SHIFT 0 585#define lpfc_rcqe_sof_MASK 0x000000FF 586#define lpfc_rcqe_sof_WORD word3 587#define FCOE_SOFi2 0x2d 588#define FCOE_SOFi3 0x2e 589#define FCOE_SOFn2 0x35 590#define FCOE_SOFn3 0x36 591}; 592 593struct lpfc_rqe { 594 uint32_t address_hi; 595 uint32_t address_lo; 596}; 597 598/* buffer descriptors */ 599struct lpfc_bde4 { 600 uint32_t addr_hi; 601 uint32_t addr_lo; 602 uint32_t word2; 603#define lpfc_bde4_last_SHIFT 31 604#define lpfc_bde4_last_MASK 0x00000001 605#define lpfc_bde4_last_WORD word2 606#define lpfc_bde4_sge_offset_SHIFT 0 607#define lpfc_bde4_sge_offset_MASK 0x000003FF 608#define lpfc_bde4_sge_offset_WORD word2 609 uint32_t word3; 610#define lpfc_bde4_length_SHIFT 0 611#define lpfc_bde4_length_MASK 0x000000FF 612#define lpfc_bde4_length_WORD word3 613}; 614 615struct lpfc_register { 616 uint32_t word0; 617}; 618 619#define LPFC_PORT_SEM_UE_RECOVERABLE 0xE000 620#define LPFC_PORT_SEM_MASK 0xF000 621/* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */ 622#define LPFC_UERR_STATUS_HI 0x00A4 623#define LPFC_UERR_STATUS_LO 0x00A0 624#define LPFC_UE_MASK_HI 0x00AC 625#define LPFC_UE_MASK_LO 0x00A8 626 627/* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */ 628#define LPFC_SLI_INTF 0x0058 629#define LPFC_SLI_ASIC_VER 0x009C 630 631#define LPFC_CTL_PORT_SEM_OFFSET 0x400 632#define lpfc_port_smphr_perr_SHIFT 31 633#define lpfc_port_smphr_perr_MASK 0x1 634#define lpfc_port_smphr_perr_WORD word0 635#define lpfc_port_smphr_sfi_SHIFT 30 636#define lpfc_port_smphr_sfi_MASK 0x1 637#define lpfc_port_smphr_sfi_WORD word0 638#define lpfc_port_smphr_nip_SHIFT 29 639#define lpfc_port_smphr_nip_MASK 0x1 640#define lpfc_port_smphr_nip_WORD word0 641#define lpfc_port_smphr_ipc_SHIFT 28 642#define lpfc_port_smphr_ipc_MASK 0x1 643#define lpfc_port_smphr_ipc_WORD word0 644#define lpfc_port_smphr_scr1_SHIFT 27 645#define lpfc_port_smphr_scr1_MASK 0x1 646#define lpfc_port_smphr_scr1_WORD word0 647#define lpfc_port_smphr_scr2_SHIFT 26 648#define lpfc_port_smphr_scr2_MASK 0x1 649#define lpfc_port_smphr_scr2_WORD word0 650#define lpfc_port_smphr_host_scratch_SHIFT 16 651#define lpfc_port_smphr_host_scratch_MASK 0xFF 652#define lpfc_port_smphr_host_scratch_WORD word0 653#define lpfc_port_smphr_port_status_SHIFT 0 654#define lpfc_port_smphr_port_status_MASK 0xFFFF 655#define lpfc_port_smphr_port_status_WORD word0 656 657#define LPFC_POST_STAGE_POWER_ON_RESET 0x0000 658#define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001 659#define LPFC_POST_STAGE_HOST_RDY 0x0002 660#define LPFC_POST_STAGE_BE_RESET 0x0003 661#define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100 662#define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101 663#define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200 664#define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201 665#define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300 666#define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301 667#define LPFC_POST_STAGE_DDR_TEST_START 0x0400 668#define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401 669#define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600 670#define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601 671#define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700 672#define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701 673#define LPFC_POST_STAGE_ARMFW_START 0x0800 674#define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900 675#define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901 676#define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00 677#define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01 678#define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00 679#define LPFC_POST_STAGE_SWITCH_LINK 0x0B01 680#define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02 681#define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03 682#define LPFC_POST_STAGE_PARSE_XML 0x0B04 683#define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05 684#define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06 685#define LPFC_POST_STAGE_RC_DONE 0x0B07 686#define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08 687#define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00 688#define LPFC_POST_STAGE_PORT_READY 0xC000 689#define LPFC_POST_STAGE_PORT_UE 0xF000 690 691#define LPFC_CTL_PORT_STA_OFFSET 0x404 692#define lpfc_sliport_status_err_SHIFT 31 693#define lpfc_sliport_status_err_MASK 0x1 694#define lpfc_sliport_status_err_WORD word0 695#define lpfc_sliport_status_end_SHIFT 30 696#define lpfc_sliport_status_end_MASK 0x1 697#define lpfc_sliport_status_end_WORD word0 698#define lpfc_sliport_status_oti_SHIFT 29 699#define lpfc_sliport_status_oti_MASK 0x1 700#define lpfc_sliport_status_oti_WORD word0 701#define lpfc_sliport_status_dip_SHIFT 25 702#define lpfc_sliport_status_dip_MASK 0x1 703#define lpfc_sliport_status_dip_WORD word0 704#define lpfc_sliport_status_rn_SHIFT 24 705#define lpfc_sliport_status_rn_MASK 0x1 706#define lpfc_sliport_status_rn_WORD word0 707#define lpfc_sliport_status_rdy_SHIFT 23 708#define lpfc_sliport_status_rdy_MASK 0x1 709#define lpfc_sliport_status_rdy_WORD word0 710#define lpfc_sliport_status_pldv_SHIFT 0 711#define lpfc_sliport_status_pldv_MASK 0x1 712#define lpfc_sliport_status_pldv_WORD word0 713#define CFG_PLD 0x3C 714#define MAX_IF_TYPE_2_RESETS 6 715 716#define LPFC_CTL_PORT_CTL_OFFSET 0x408 717#define lpfc_sliport_ctrl_end_SHIFT 30 718#define lpfc_sliport_ctrl_end_MASK 0x1 719#define lpfc_sliport_ctrl_end_WORD word0 720#define LPFC_SLIPORT_LITTLE_ENDIAN 0 721#define LPFC_SLIPORT_BIG_ENDIAN 1 722#define lpfc_sliport_ctrl_ip_SHIFT 27 723#define lpfc_sliport_ctrl_ip_MASK 0x1 724#define lpfc_sliport_ctrl_ip_WORD word0 725#define LPFC_SLIPORT_INIT_PORT 1 726 727#define LPFC_CTL_PORT_ER1_OFFSET 0x40C 728#define LPFC_CTL_PORT_ER2_OFFSET 0x410 729 730#define LPFC_CTL_PORT_EQ_DELAY_OFFSET 0x418 731#define lpfc_sliport_eqdelay_delay_SHIFT 16 732#define lpfc_sliport_eqdelay_delay_MASK 0xffff 733#define lpfc_sliport_eqdelay_delay_WORD word0 734#define lpfc_sliport_eqdelay_id_SHIFT 0 735#define lpfc_sliport_eqdelay_id_MASK 0xfff 736#define lpfc_sliport_eqdelay_id_WORD word0 737#define LPFC_SEC_TO_USEC 1000000 738#define LPFC_SEC_TO_MSEC 1000 739#define LPFC_MSECS_TO_SECS(msecs) ((msecs) / 1000) 740 741/* The following Registers apply to SLI4 if_type 0 UCNAs. They typically 742 * reside in BAR 2. 743 */ 744#define LPFC_SLIPORT_IF0_SMPHR 0x00AC 745 746#define LPFC_IMR_MASK_ALL 0xFFFFFFFF 747#define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF 748 749#define LPFC_HST_ISR0 0x0C18 750#define LPFC_HST_ISR1 0x0C1C 751#define LPFC_HST_ISR2 0x0C20 752#define LPFC_HST_ISR3 0x0C24 753#define LPFC_HST_ISR4 0x0C28 754 755#define LPFC_HST_IMR0 0x0C48 756#define LPFC_HST_IMR1 0x0C4C 757#define LPFC_HST_IMR2 0x0C50 758#define LPFC_HST_IMR3 0x0C54 759#define LPFC_HST_IMR4 0x0C58 760 761#define LPFC_HST_ISCR0 0x0C78 762#define LPFC_HST_ISCR1 0x0C7C 763#define LPFC_HST_ISCR2 0x0C80 764#define LPFC_HST_ISCR3 0x0C84 765#define LPFC_HST_ISCR4 0x0C88 766 767#define LPFC_SLI4_INTR0 BIT0 768#define LPFC_SLI4_INTR1 BIT1 769#define LPFC_SLI4_INTR2 BIT2 770#define LPFC_SLI4_INTR3 BIT3 771#define LPFC_SLI4_INTR4 BIT4 772#define LPFC_SLI4_INTR5 BIT5 773#define LPFC_SLI4_INTR6 BIT6 774#define LPFC_SLI4_INTR7 BIT7 775#define LPFC_SLI4_INTR8 BIT8 776#define LPFC_SLI4_INTR9 BIT9 777#define LPFC_SLI4_INTR10 BIT10 778#define LPFC_SLI4_INTR11 BIT11 779#define LPFC_SLI4_INTR12 BIT12 780#define LPFC_SLI4_INTR13 BIT13 781#define LPFC_SLI4_INTR14 BIT14 782#define LPFC_SLI4_INTR15 BIT15 783#define LPFC_SLI4_INTR16 BIT16 784#define LPFC_SLI4_INTR17 BIT17 785#define LPFC_SLI4_INTR18 BIT18 786#define LPFC_SLI4_INTR19 BIT19 787#define LPFC_SLI4_INTR20 BIT20 788#define LPFC_SLI4_INTR21 BIT21 789#define LPFC_SLI4_INTR22 BIT22 790#define LPFC_SLI4_INTR23 BIT23 791#define LPFC_SLI4_INTR24 BIT24 792#define LPFC_SLI4_INTR25 BIT25 793#define LPFC_SLI4_INTR26 BIT26 794#define LPFC_SLI4_INTR27 BIT27 795#define LPFC_SLI4_INTR28 BIT28 796#define LPFC_SLI4_INTR29 BIT29 797#define LPFC_SLI4_INTR30 BIT30 798#define LPFC_SLI4_INTR31 BIT31 799 800/* 801 * The Doorbell registers defined here exist in different BAR 802 * register sets depending on the UCNA Port's reported if_type 803 * value. For UCNA ports running SLI4 and if_type 0, they reside in 804 * BAR4. For UCNA ports running SLI4 and if_type 2, they reside in 805 * BAR0. For FC ports running SLI4 and if_type 6, they reside in 806 * BAR2. The offsets and base address are different, so the driver 807 * has to compute the register addresses accordingly 808 */ 809#define LPFC_ULP0_RQ_DOORBELL 0x00A0 810#define LPFC_ULP1_RQ_DOORBELL 0x00C0 811#define LPFC_IF6_RQ_DOORBELL 0x0080 812#define lpfc_rq_db_list_fm_num_posted_SHIFT 24 813#define lpfc_rq_db_list_fm_num_posted_MASK 0x00FF 814#define lpfc_rq_db_list_fm_num_posted_WORD word0 815#define lpfc_rq_db_list_fm_index_SHIFT 16 816#define lpfc_rq_db_list_fm_index_MASK 0x00FF 817#define lpfc_rq_db_list_fm_index_WORD word0 818#define lpfc_rq_db_list_fm_id_SHIFT 0 819#define lpfc_rq_db_list_fm_id_MASK 0xFFFF 820#define lpfc_rq_db_list_fm_id_WORD word0 821#define lpfc_rq_db_ring_fm_num_posted_SHIFT 16 822#define lpfc_rq_db_ring_fm_num_posted_MASK 0x3FFF 823#define lpfc_rq_db_ring_fm_num_posted_WORD word0 824#define lpfc_rq_db_ring_fm_id_SHIFT 0 825#define lpfc_rq_db_ring_fm_id_MASK 0xFFFF 826#define lpfc_rq_db_ring_fm_id_WORD word0 827 828#define LPFC_ULP0_WQ_DOORBELL 0x0040 829#define LPFC_ULP1_WQ_DOORBELL 0x0060 830#define lpfc_wq_db_list_fm_num_posted_SHIFT 24 831#define lpfc_wq_db_list_fm_num_posted_MASK 0x00FF 832#define lpfc_wq_db_list_fm_num_posted_WORD word0 833#define lpfc_wq_db_list_fm_index_SHIFT 16 834#define lpfc_wq_db_list_fm_index_MASK 0x00FF 835#define lpfc_wq_db_list_fm_index_WORD word0 836#define lpfc_wq_db_list_fm_id_SHIFT 0 837#define lpfc_wq_db_list_fm_id_MASK 0xFFFF 838#define lpfc_wq_db_list_fm_id_WORD word0 839#define lpfc_wq_db_ring_fm_num_posted_SHIFT 16 840#define lpfc_wq_db_ring_fm_num_posted_MASK 0x3FFF 841#define lpfc_wq_db_ring_fm_num_posted_WORD word0 842#define lpfc_wq_db_ring_fm_id_SHIFT 0 843#define lpfc_wq_db_ring_fm_id_MASK 0xFFFF 844#define lpfc_wq_db_ring_fm_id_WORD word0 845 846#define LPFC_IF6_WQ_DOORBELL 0x0040 847#define lpfc_if6_wq_db_list_fm_num_posted_SHIFT 24 848#define lpfc_if6_wq_db_list_fm_num_posted_MASK 0x00FF 849#define lpfc_if6_wq_db_list_fm_num_posted_WORD word0 850#define lpfc_if6_wq_db_list_fm_dpp_SHIFT 23 851#define lpfc_if6_wq_db_list_fm_dpp_MASK 0x0001 852#define lpfc_if6_wq_db_list_fm_dpp_WORD word0 853#define lpfc_if6_wq_db_list_fm_dpp_id_SHIFT 16 854#define lpfc_if6_wq_db_list_fm_dpp_id_MASK 0x001F 855#define lpfc_if6_wq_db_list_fm_dpp_id_WORD word0 856#define lpfc_if6_wq_db_list_fm_id_SHIFT 0 857#define lpfc_if6_wq_db_list_fm_id_MASK 0xFFFF 858#define lpfc_if6_wq_db_list_fm_id_WORD word0 859 860#define LPFC_EQCQ_DOORBELL 0x0120 861#define lpfc_eqcq_doorbell_se_SHIFT 31 862#define lpfc_eqcq_doorbell_se_MASK 0x0001 863#define lpfc_eqcq_doorbell_se_WORD word0 864#define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0 865#define LPFC_EQCQ_SOLICIT_ENABLE_ON 1 866#define lpfc_eqcq_doorbell_arm_SHIFT 29 867#define lpfc_eqcq_doorbell_arm_MASK 0x0001 868#define lpfc_eqcq_doorbell_arm_WORD word0 869#define lpfc_eqcq_doorbell_num_released_SHIFT 16 870#define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF 871#define lpfc_eqcq_doorbell_num_released_WORD word0 872#define lpfc_eqcq_doorbell_qt_SHIFT 10 873#define lpfc_eqcq_doorbell_qt_MASK 0x0001 874#define lpfc_eqcq_doorbell_qt_WORD word0 875#define LPFC_QUEUE_TYPE_COMPLETION 0 876#define LPFC_QUEUE_TYPE_EVENT 1 877#define lpfc_eqcq_doorbell_eqci_SHIFT 9 878#define lpfc_eqcq_doorbell_eqci_MASK 0x0001 879#define lpfc_eqcq_doorbell_eqci_WORD word0 880#define lpfc_eqcq_doorbell_cqid_lo_SHIFT 0 881#define lpfc_eqcq_doorbell_cqid_lo_MASK 0x03FF 882#define lpfc_eqcq_doorbell_cqid_lo_WORD word0 883#define lpfc_eqcq_doorbell_cqid_hi_SHIFT 11 884#define lpfc_eqcq_doorbell_cqid_hi_MASK 0x001F 885#define lpfc_eqcq_doorbell_cqid_hi_WORD word0 886#define lpfc_eqcq_doorbell_eqid_lo_SHIFT 0 887#define lpfc_eqcq_doorbell_eqid_lo_MASK 0x01FF 888#define lpfc_eqcq_doorbell_eqid_lo_WORD word0 889#define lpfc_eqcq_doorbell_eqid_hi_SHIFT 11 890#define lpfc_eqcq_doorbell_eqid_hi_MASK 0x001F 891#define lpfc_eqcq_doorbell_eqid_hi_WORD word0 892#define LPFC_CQID_HI_FIELD_SHIFT 10 893#define LPFC_EQID_HI_FIELD_SHIFT 9 894 895#define LPFC_IF6_CQ_DOORBELL 0x00C0 896#define lpfc_if6_cq_doorbell_se_SHIFT 31 897#define lpfc_if6_cq_doorbell_se_MASK 0x0001 898#define lpfc_if6_cq_doorbell_se_WORD word0 899#define LPFC_IF6_CQ_SOLICIT_ENABLE_OFF 0 900#define LPFC_IF6_CQ_SOLICIT_ENABLE_ON 1 901#define lpfc_if6_cq_doorbell_arm_SHIFT 29 902#define lpfc_if6_cq_doorbell_arm_MASK 0x0001 903#define lpfc_if6_cq_doorbell_arm_WORD word0 904#define lpfc_if6_cq_doorbell_num_released_SHIFT 16 905#define lpfc_if6_cq_doorbell_num_released_MASK 0x1FFF 906#define lpfc_if6_cq_doorbell_num_released_WORD word0 907#define lpfc_if6_cq_doorbell_cqid_SHIFT 0 908#define lpfc_if6_cq_doorbell_cqid_MASK 0xFFFF 909#define lpfc_if6_cq_doorbell_cqid_WORD word0 910 911#define LPFC_IF6_EQ_DOORBELL 0x0120 912#define lpfc_if6_eq_doorbell_io_SHIFT 31 913#define lpfc_if6_eq_doorbell_io_MASK 0x0001 914#define lpfc_if6_eq_doorbell_io_WORD word0 915#define LPFC_IF6_EQ_INTR_OVERRIDE_OFF 0 916#define LPFC_IF6_EQ_INTR_OVERRIDE_ON 1 917#define lpfc_if6_eq_doorbell_arm_SHIFT 29 918#define lpfc_if6_eq_doorbell_arm_MASK 0x0001 919#define lpfc_if6_eq_doorbell_arm_WORD word0 920#define lpfc_if6_eq_doorbell_num_released_SHIFT 16 921#define lpfc_if6_eq_doorbell_num_released_MASK 0x1FFF 922#define lpfc_if6_eq_doorbell_num_released_WORD word0 923#define lpfc_if6_eq_doorbell_eqid_SHIFT 0 924#define lpfc_if6_eq_doorbell_eqid_MASK 0x0FFF 925#define lpfc_if6_eq_doorbell_eqid_WORD word0 926 927#define LPFC_BMBX 0x0160 928#define lpfc_bmbx_addr_SHIFT 2 929#define lpfc_bmbx_addr_MASK 0x3FFFFFFF 930#define lpfc_bmbx_addr_WORD word0 931#define lpfc_bmbx_hi_SHIFT 1 932#define lpfc_bmbx_hi_MASK 0x0001 933#define lpfc_bmbx_hi_WORD word0 934#define lpfc_bmbx_rdy_SHIFT 0 935#define lpfc_bmbx_rdy_MASK 0x0001 936#define lpfc_bmbx_rdy_WORD word0 937 938#define LPFC_MQ_DOORBELL 0x0140 939#define LPFC_IF6_MQ_DOORBELL 0x0160 940#define lpfc_mq_doorbell_num_posted_SHIFT 16 941#define lpfc_mq_doorbell_num_posted_MASK 0x3FFF 942#define lpfc_mq_doorbell_num_posted_WORD word0 943#define lpfc_mq_doorbell_id_SHIFT 0 944#define lpfc_mq_doorbell_id_MASK 0xFFFF 945#define lpfc_mq_doorbell_id_WORD word0 946 947struct lpfc_sli4_cfg_mhdr { 948 uint32_t word1; 949#define lpfc_mbox_hdr_emb_SHIFT 0 950#define lpfc_mbox_hdr_emb_MASK 0x00000001 951#define lpfc_mbox_hdr_emb_WORD word1 952#define lpfc_mbox_hdr_sge_cnt_SHIFT 3 953#define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F 954#define lpfc_mbox_hdr_sge_cnt_WORD word1 955 uint32_t payload_length; 956 uint32_t tag_lo; 957 uint32_t tag_hi; 958 uint32_t reserved5; 959}; 960 961union lpfc_sli4_cfg_shdr { 962 struct { 963 uint32_t word6; 964#define lpfc_mbox_hdr_opcode_SHIFT 0 965#define lpfc_mbox_hdr_opcode_MASK 0x000000FF 966#define lpfc_mbox_hdr_opcode_WORD word6 967#define lpfc_mbox_hdr_subsystem_SHIFT 8 968#define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 969#define lpfc_mbox_hdr_subsystem_WORD word6 970#define lpfc_mbox_hdr_port_number_SHIFT 16 971#define lpfc_mbox_hdr_port_number_MASK 0x000000FF 972#define lpfc_mbox_hdr_port_number_WORD word6 973#define lpfc_mbox_hdr_domain_SHIFT 24 974#define lpfc_mbox_hdr_domain_MASK 0x000000FF 975#define lpfc_mbox_hdr_domain_WORD word6 976 uint32_t timeout; 977 uint32_t request_length; 978 uint32_t word9; 979#define lpfc_mbox_hdr_version_SHIFT 0 980#define lpfc_mbox_hdr_version_MASK 0x000000FF 981#define lpfc_mbox_hdr_version_WORD word9 982#define lpfc_mbox_hdr_pf_num_SHIFT 16 983#define lpfc_mbox_hdr_pf_num_MASK 0x000000FF 984#define lpfc_mbox_hdr_pf_num_WORD word9 985#define lpfc_mbox_hdr_vh_num_SHIFT 24 986#define lpfc_mbox_hdr_vh_num_MASK 0x000000FF 987#define lpfc_mbox_hdr_vh_num_WORD word9 988#define LPFC_Q_CREATE_VERSION_2 2 989#define LPFC_Q_CREATE_VERSION_1 1 990#define LPFC_Q_CREATE_VERSION_0 0 991#define LPFC_OPCODE_VERSION_0 0 992#define LPFC_OPCODE_VERSION_1 1 993 } request; 994 struct { 995 uint32_t word6; 996#define lpfc_mbox_hdr_opcode_SHIFT 0 997#define lpfc_mbox_hdr_opcode_MASK 0x000000FF 998#define lpfc_mbox_hdr_opcode_WORD word6 999#define lpfc_mbox_hdr_subsystem_SHIFT 8 1000#define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 1001#define lpfc_mbox_hdr_subsystem_WORD word6 1002#define lpfc_mbox_hdr_domain_SHIFT 24 1003#define lpfc_mbox_hdr_domain_MASK 0x000000FF 1004#define lpfc_mbox_hdr_domain_WORD word6 1005 uint32_t word7; 1006#define lpfc_mbox_hdr_status_SHIFT 0 1007#define lpfc_mbox_hdr_status_MASK 0x000000FF 1008#define lpfc_mbox_hdr_status_WORD word7 1009#define lpfc_mbox_hdr_add_status_SHIFT 8 1010#define lpfc_mbox_hdr_add_status_MASK 0x000000FF 1011#define lpfc_mbox_hdr_add_status_WORD word7 1012#define LPFC_ADD_STATUS_INCOMPAT_OBJ 0xA2 1013#define lpfc_mbox_hdr_add_status_2_SHIFT 16 1014#define lpfc_mbox_hdr_add_status_2_MASK 0x000000FF 1015#define lpfc_mbox_hdr_add_status_2_WORD word7 1016#define LPFC_ADD_STATUS_2_INCOMPAT_FLASH 0x01 1017#define LPFC_ADD_STATUS_2_INCORRECT_ASIC 0x02 1018 uint32_t response_length; 1019 uint32_t actual_response_length; 1020 } response; 1021}; 1022 1023/* Mailbox Header structures. 1024 * struct mbox_header is defined for first generation SLI4_CFG mailbox 1025 * calls deployed for BE-based ports. 1026 * 1027 * struct sli4_mbox_header is defined for second generation SLI4 1028 * ports that don't deploy the SLI4_CFG mechanism. 1029 */ 1030struct mbox_header { 1031 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 1032 union lpfc_sli4_cfg_shdr cfg_shdr; 1033}; 1034 1035#define LPFC_EXTENT_LOCAL 0 1036#define LPFC_TIMEOUT_DEFAULT 0 1037#define LPFC_EXTENT_VERSION_DEFAULT 0 1038 1039/* Subsystem Definitions */ 1040#define LPFC_MBOX_SUBSYSTEM_NA 0x0 1041#define LPFC_MBOX_SUBSYSTEM_COMMON 0x1 1042#define LPFC_MBOX_SUBSYSTEM_LOWLEVEL 0xB 1043#define LPFC_MBOX_SUBSYSTEM_FCOE 0xC 1044 1045/* Device Specific Definitions */ 1046 1047/* The HOST ENDIAN defines are in Big Endian format. */ 1048#define HOST_ENDIAN_LOW_WORD0 0xFF3412FF 1049#define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF 1050 1051/* Common Opcodes */ 1052#define LPFC_MBOX_OPCODE_NA 0x00 1053#define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C 1054#define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D 1055#define LPFC_MBOX_OPCODE_MQ_CREATE 0x15 1056#define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20 1057#define LPFC_MBOX_OPCODE_NOP 0x21 1058#define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY 0x29 1059#define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35 1060#define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36 1061#define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37 1062#define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A 1063#define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D 1064#define LPFC_MBOX_OPCODE_SET_PHYSICAL_LINK_CONFIG 0x3E 1065#define LPFC_MBOX_OPCODE_SET_BOOT_CONFIG 0x43 1066#define LPFC_MBOX_OPCODE_SET_BEACON_CONFIG 0x45 1067#define LPFC_MBOX_OPCODE_GET_BEACON_CONFIG 0x46 1068#define LPFC_MBOX_OPCODE_GET_PORT_NAME 0x4D 1069#define LPFC_MBOX_OPCODE_MQ_CREATE_EXT 0x5A 1070#define LPFC_MBOX_OPCODE_GET_VPD_DATA 0x5B 1071#define LPFC_MBOX_OPCODE_SET_HOST_DATA 0x5D 1072#define LPFC_MBOX_OPCODE_SEND_ACTIVATION 0x73 1073#define LPFC_MBOX_OPCODE_RESET_LICENSES 0x74 1074#define LPFC_MBOX_OPCODE_REG_CONGESTION_BUF 0x8E 1075#define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO 0x9A 1076#define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT 0x9B 1077#define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT 0x9C 1078#define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT 0x9D 1079#define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG 0xA0 1080#define LPFC_MBOX_OPCODE_GET_PROFILE_CAPACITIES 0xA1 1081#define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG 0xA4 1082#define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG 0xA5 1083#define LPFC_MBOX_OPCODE_GET_PROFILE_LIST 0xA6 1084#define LPFC_MBOX_OPCODE_SET_ACT_PROFILE 0xA8 1085#define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG 0xA9 1086#define LPFC_MBOX_OPCODE_READ_OBJECT 0xAB 1087#define LPFC_MBOX_OPCODE_WRITE_OBJECT 0xAC 1088#define LPFC_MBOX_OPCODE_READ_OBJECT_LIST 0xAD 1089#define LPFC_MBOX_OPCODE_DELETE_OBJECT 0xAE 1090#define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS 0xB5 1091#define LPFC_MBOX_OPCODE_SET_FEATURES 0xBF 1092 1093/* FCoE Opcodes */ 1094#define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01 1095#define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02 1096#define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03 1097#define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04 1098#define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05 1099#define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06 1100#define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08 1101#define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09 1102#define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A 1103#define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B 1104#define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF 0x10 1105#define LPFC_MBOX_OPCODE_FCOE_CQ_CREATE_SET 0x1D 1106#define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS 0x21 1107#define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE 0x22 1108#define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK 0x23 1109#define LPFC_MBOX_OPCODE_FCOE_FC_SET_TRUNK_MODE 0x42 1110 1111/* Low level Opcodes */ 1112#define LPFC_MBOX_OPCODE_SET_DIAG_LOG_OPTION 0x37 1113 1114/* Mailbox command structures */ 1115struct eq_context { 1116 uint32_t word0; 1117#define lpfc_eq_context_size_SHIFT 31 1118#define lpfc_eq_context_size_MASK 0x00000001 1119#define lpfc_eq_context_size_WORD word0 1120#define LPFC_EQE_SIZE_4 0x0 1121#define LPFC_EQE_SIZE_16 0x1 1122#define lpfc_eq_context_valid_SHIFT 29 1123#define lpfc_eq_context_valid_MASK 0x00000001 1124#define lpfc_eq_context_valid_WORD word0 1125#define lpfc_eq_context_autovalid_SHIFT 28 1126#define lpfc_eq_context_autovalid_MASK 0x00000001 1127#define lpfc_eq_context_autovalid_WORD word0 1128 uint32_t word1; 1129#define lpfc_eq_context_count_SHIFT 26 1130#define lpfc_eq_context_count_MASK 0x00000003 1131#define lpfc_eq_context_count_WORD word1 1132#define LPFC_EQ_CNT_256 0x0 1133#define LPFC_EQ_CNT_512 0x1 1134#define LPFC_EQ_CNT_1024 0x2 1135#define LPFC_EQ_CNT_2048 0x3 1136#define LPFC_EQ_CNT_4096 0x4 1137 uint32_t word2; 1138#define lpfc_eq_context_delay_multi_SHIFT 13 1139#define lpfc_eq_context_delay_multi_MASK 0x000003FF 1140#define lpfc_eq_context_delay_multi_WORD word2 1141 uint32_t reserved3; 1142}; 1143 1144struct eq_delay_info { 1145 uint32_t eq_id; 1146 uint32_t phase; 1147 uint32_t delay_multi; 1148}; 1149#define LPFC_MAX_EQ_DELAY_EQID_CNT 8 1150 1151struct sgl_page_pairs { 1152 uint32_t sgl_pg0_addr_lo; 1153 uint32_t sgl_pg0_addr_hi; 1154 uint32_t sgl_pg1_addr_lo; 1155 uint32_t sgl_pg1_addr_hi; 1156}; 1157 1158struct lpfc_mbx_post_sgl_pages { 1159 struct mbox_header header; 1160 uint32_t word0; 1161#define lpfc_post_sgl_pages_xri_SHIFT 0 1162#define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF 1163#define lpfc_post_sgl_pages_xri_WORD word0 1164#define lpfc_post_sgl_pages_xricnt_SHIFT 16 1165#define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF 1166#define lpfc_post_sgl_pages_xricnt_WORD word0 1167 struct sgl_page_pairs sgl_pg_pairs[1]; 1168}; 1169 1170/* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */ 1171struct lpfc_mbx_post_uembed_sgl_page1 { 1172 union lpfc_sli4_cfg_shdr cfg_shdr; 1173 uint32_t word0; 1174 struct sgl_page_pairs sgl_pg_pairs; 1175}; 1176 1177struct lpfc_mbx_sge { 1178 uint32_t pa_lo; 1179 uint32_t pa_hi; 1180 uint32_t length; 1181}; 1182 1183struct lpfc_mbx_host_buf { 1184 uint32_t length; 1185 uint32_t pa_lo; 1186 uint32_t pa_hi; 1187}; 1188 1189struct lpfc_mbx_nembed_cmd { 1190 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 1191#define LPFC_SLI4_MBX_SGE_MAX_PAGES 19 1192 struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 1193}; 1194 1195struct lpfc_mbx_nembed_sge_virt { 1196 void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 1197}; 1198 1199#define LPFC_MBX_OBJECT_NAME_LEN_DW 26 1200struct lpfc_mbx_read_object { /* Version 0 */ 1201 struct mbox_header header; 1202 union { 1203 struct { 1204 uint32_t word0; 1205#define lpfc_mbx_rd_object_rlen_SHIFT 0 1206#define lpfc_mbx_rd_object_rlen_MASK 0x00FFFFFF 1207#define lpfc_mbx_rd_object_rlen_WORD word0 1208 uint32_t rd_object_offset; 1209 __le32 rd_object_name[LPFC_MBX_OBJECT_NAME_LEN_DW]; 1210#define LPFC_OBJ_NAME_SZ 104 /* 26 x sizeof(uint32_t) is 104. */ 1211 uint32_t rd_object_cnt; 1212 struct lpfc_mbx_host_buf rd_object_hbuf[4]; 1213 } request; 1214 struct { 1215 uint32_t rd_object_actual_rlen; 1216 uint32_t word1; 1217#define lpfc_mbx_rd_object_eof_SHIFT 31 1218#define lpfc_mbx_rd_object_eof_MASK 0x1 1219#define lpfc_mbx_rd_object_eof_WORD word1 1220 } response; 1221 } u; 1222}; 1223 1224struct lpfc_mbx_eq_create { 1225 struct mbox_header header; 1226 union { 1227 struct { 1228 uint32_t word0; 1229#define lpfc_mbx_eq_create_num_pages_SHIFT 0 1230#define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF 1231#define lpfc_mbx_eq_create_num_pages_WORD word0 1232 struct eq_context context; 1233 struct dma_address page[LPFC_MAX_EQ_PAGE]; 1234 } request; 1235 struct { 1236 uint32_t word0; 1237#define lpfc_mbx_eq_create_q_id_SHIFT 0 1238#define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF 1239#define lpfc_mbx_eq_create_q_id_WORD word0 1240 } response; 1241 } u; 1242}; 1243 1244struct lpfc_mbx_modify_eq_delay { 1245 struct mbox_header header; 1246 union { 1247 struct { 1248 uint32_t num_eq; 1249 struct eq_delay_info eq[LPFC_MAX_EQ_DELAY_EQID_CNT]; 1250 } request; 1251 struct { 1252 uint32_t word0; 1253 } response; 1254 } u; 1255}; 1256 1257struct lpfc_mbx_eq_destroy { 1258 struct mbox_header header; 1259 union { 1260 struct { 1261 uint32_t word0; 1262#define lpfc_mbx_eq_destroy_q_id_SHIFT 0 1263#define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF 1264#define lpfc_mbx_eq_destroy_q_id_WORD word0 1265 } request; 1266 struct { 1267 uint32_t word0; 1268 } response; 1269 } u; 1270}; 1271 1272struct lpfc_mbx_nop { 1273 struct mbox_header header; 1274 uint32_t context[2]; 1275}; 1276 1277 1278 1279struct lpfc_mbx_set_ras_fwlog { 1280 struct mbox_header header; 1281 union { 1282 struct { 1283 uint32_t word4; 1284#define lpfc_fwlog_enable_SHIFT 0 1285#define lpfc_fwlog_enable_MASK 0x00000001 1286#define lpfc_fwlog_enable_WORD word4 1287#define lpfc_fwlog_loglvl_SHIFT 8 1288#define lpfc_fwlog_loglvl_MASK 0x0000000F 1289#define lpfc_fwlog_loglvl_WORD word4 1290#define lpfc_fwlog_ra_SHIFT 15 1291#define lpfc_fwlog_ra_WORD 0x00000008 1292#define lpfc_fwlog_buffcnt_SHIFT 16 1293#define lpfc_fwlog_buffcnt_MASK 0x000000FF 1294#define lpfc_fwlog_buffcnt_WORD word4 1295#define lpfc_fwlog_buffsz_SHIFT 24 1296#define lpfc_fwlog_buffsz_MASK 0x000000FF 1297#define lpfc_fwlog_buffsz_WORD word4 1298 uint32_t word5; 1299#define lpfc_fwlog_acqe_SHIFT 0 1300#define lpfc_fwlog_acqe_MASK 0x0000FFFF 1301#define lpfc_fwlog_acqe_WORD word5 1302#define lpfc_fwlog_cqid_SHIFT 16 1303#define lpfc_fwlog_cqid_MASK 0x0000FFFF 1304#define lpfc_fwlog_cqid_WORD word5 1305#define LPFC_MAX_FWLOG_PAGE 16 1306 struct dma_address lwpd; 1307 struct dma_address buff_fwlog[LPFC_MAX_FWLOG_PAGE]; 1308 } request; 1309 struct { 1310 uint32_t word0; 1311 } response; 1312 } u; 1313}; 1314 1315 1316struct cq_context { 1317 uint32_t word0; 1318#define lpfc_cq_context_event_SHIFT 31 1319#define lpfc_cq_context_event_MASK 0x00000001 1320#define lpfc_cq_context_event_WORD word0 1321#define lpfc_cq_context_valid_SHIFT 29 1322#define lpfc_cq_context_valid_MASK 0x00000001 1323#define lpfc_cq_context_valid_WORD word0 1324#define lpfc_cq_context_count_SHIFT 27 1325#define lpfc_cq_context_count_MASK 0x00000003 1326#define lpfc_cq_context_count_WORD word0 1327#define LPFC_CQ_CNT_256 0x0 1328#define LPFC_CQ_CNT_512 0x1 1329#define LPFC_CQ_CNT_1024 0x2 1330#define LPFC_CQ_CNT_WORD7 0x3 1331#define lpfc_cq_context_cqe_sz_SHIFT 25 1332#define lpfc_cq_context_cqe_sz_MASK 0x00000003 1333#define lpfc_cq_context_cqe_sz_WORD word0 1334#define lpfc_cq_context_autovalid_SHIFT 15 1335#define lpfc_cq_context_autovalid_MASK 0x00000001 1336#define lpfc_cq_context_autovalid_WORD word0 1337 uint32_t word1; 1338#define lpfc_cq_eq_id_SHIFT 22 /* Version 0 Only */ 1339#define lpfc_cq_eq_id_MASK 0x000000FF 1340#define lpfc_cq_eq_id_WORD word1 1341#define lpfc_cq_eq_id_2_SHIFT 0 /* Version 2 Only */ 1342#define lpfc_cq_eq_id_2_MASK 0x0000FFFF 1343#define lpfc_cq_eq_id_2_WORD word1 1344 uint32_t lpfc_cq_context_count; /* Version 2 Only */ 1345 uint32_t reserved1; 1346}; 1347 1348struct lpfc_mbx_cq_create { 1349 struct mbox_header header; 1350 union { 1351 struct { 1352 uint32_t word0; 1353#define lpfc_mbx_cq_create_page_size_SHIFT 16 /* Version 2 Only */ 1354#define lpfc_mbx_cq_create_page_size_MASK 0x000000FF 1355#define lpfc_mbx_cq_create_page_size_WORD word0 1356#define lpfc_mbx_cq_create_num_pages_SHIFT 0 1357#define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF 1358#define lpfc_mbx_cq_create_num_pages_WORD word0 1359 struct cq_context context; 1360 struct dma_address page[LPFC_MAX_CQ_PAGE]; 1361 } request; 1362 struct { 1363 uint32_t word0; 1364#define lpfc_mbx_cq_create_q_id_SHIFT 0 1365#define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF 1366#define lpfc_mbx_cq_create_q_id_WORD word0 1367 } response; 1368 } u; 1369}; 1370 1371struct lpfc_mbx_cq_create_set { 1372 union lpfc_sli4_cfg_shdr cfg_shdr; 1373 union { 1374 struct { 1375 uint32_t word0; 1376#define lpfc_mbx_cq_create_set_page_size_SHIFT 16 /* Version 2 Only */ 1377#define lpfc_mbx_cq_create_set_page_size_MASK 0x000000FF 1378#define lpfc_mbx_cq_create_set_page_size_WORD word0 1379#define lpfc_mbx_cq_create_set_num_pages_SHIFT 0 1380#define lpfc_mbx_cq_create_set_num_pages_MASK 0x0000FFFF 1381#define lpfc_mbx_cq_create_set_num_pages_WORD word0 1382 uint32_t word1; 1383#define lpfc_mbx_cq_create_set_evt_SHIFT 31 1384#define lpfc_mbx_cq_create_set_evt_MASK 0x00000001 1385#define lpfc_mbx_cq_create_set_evt_WORD word1 1386#define lpfc_mbx_cq_create_set_valid_SHIFT 29 1387#define lpfc_mbx_cq_create_set_valid_MASK 0x00000001 1388#define lpfc_mbx_cq_create_set_valid_WORD word1 1389#define lpfc_mbx_cq_create_set_cqecnt_SHIFT 27 1390#define lpfc_mbx_cq_create_set_cqecnt_MASK 0x00000003 1391#define lpfc_mbx_cq_create_set_cqecnt_WORD word1 1392#define lpfc_mbx_cq_create_set_cqe_size_SHIFT 25 1393#define lpfc_mbx_cq_create_set_cqe_size_MASK 0x00000003 1394#define lpfc_mbx_cq_create_set_cqe_size_WORD word1 1395#define lpfc_mbx_cq_create_set_autovalid_SHIFT 15 1396#define lpfc_mbx_cq_create_set_autovalid_MASK 0x0000001 1397#define lpfc_mbx_cq_create_set_autovalid_WORD word1 1398#define lpfc_mbx_cq_create_set_nodelay_SHIFT 14 1399#define lpfc_mbx_cq_create_set_nodelay_MASK 0x00000001 1400#define lpfc_mbx_cq_create_set_nodelay_WORD word1 1401#define lpfc_mbx_cq_create_set_clswm_SHIFT 12 1402#define lpfc_mbx_cq_create_set_clswm_MASK 0x00000003 1403#define lpfc_mbx_cq_create_set_clswm_WORD word1 1404#define lpfc_mbx_cq_create_set_cqe_cnt_hi_SHIFT 0 1405#define lpfc_mbx_cq_create_set_cqe_cnt_hi_MASK 0x0000001F 1406#define lpfc_mbx_cq_create_set_cqe_cnt_hi_WORD word1 1407 uint32_t word2; 1408#define lpfc_mbx_cq_create_set_arm_SHIFT 31 1409#define lpfc_mbx_cq_create_set_arm_MASK 0x00000001 1410#define lpfc_mbx_cq_create_set_arm_WORD word2 1411#define lpfc_mbx_cq_create_set_cqe_cnt_lo_SHIFT 16 1412#define lpfc_mbx_cq_create_set_cqe_cnt_lo_MASK 0x00007FFF 1413#define lpfc_mbx_cq_create_set_cqe_cnt_lo_WORD word2 1414#define lpfc_mbx_cq_create_set_num_cq_SHIFT 0 1415#define lpfc_mbx_cq_create_set_num_cq_MASK 0x0000FFFF 1416#define lpfc_mbx_cq_create_set_num_cq_WORD word2 1417 uint32_t word3; 1418#define lpfc_mbx_cq_create_set_eq_id1_SHIFT 16 1419#define lpfc_mbx_cq_create_set_eq_id1_MASK 0x0000FFFF 1420#define lpfc_mbx_cq_create_set_eq_id1_WORD word3 1421#define lpfc_mbx_cq_create_set_eq_id0_SHIFT 0 1422#define lpfc_mbx_cq_create_set_eq_id0_MASK 0x0000FFFF 1423#define lpfc_mbx_cq_create_set_eq_id0_WORD word3 1424 uint32_t word4; 1425#define lpfc_mbx_cq_create_set_eq_id3_SHIFT 16 1426#define lpfc_mbx_cq_create_set_eq_id3_MASK 0x0000FFFF 1427#define lpfc_mbx_cq_create_set_eq_id3_WORD word4 1428#define lpfc_mbx_cq_create_set_eq_id2_SHIFT 0 1429#define lpfc_mbx_cq_create_set_eq_id2_MASK 0x0000FFFF 1430#define lpfc_mbx_cq_create_set_eq_id2_WORD word4 1431 uint32_t word5; 1432#define lpfc_mbx_cq_create_set_eq_id5_SHIFT 16 1433#define lpfc_mbx_cq_create_set_eq_id5_MASK 0x0000FFFF 1434#define lpfc_mbx_cq_create_set_eq_id5_WORD word5 1435#define lpfc_mbx_cq_create_set_eq_id4_SHIFT 0 1436#define lpfc_mbx_cq_create_set_eq_id4_MASK 0x0000FFFF 1437#define lpfc_mbx_cq_create_set_eq_id4_WORD word5 1438 uint32_t word6; 1439#define lpfc_mbx_cq_create_set_eq_id7_SHIFT 16 1440#define lpfc_mbx_cq_create_set_eq_id7_MASK 0x0000FFFF 1441#define lpfc_mbx_cq_create_set_eq_id7_WORD word6 1442#define lpfc_mbx_cq_create_set_eq_id6_SHIFT 0 1443#define lpfc_mbx_cq_create_set_eq_id6_MASK 0x0000FFFF 1444#define lpfc_mbx_cq_create_set_eq_id6_WORD word6 1445 uint32_t word7; 1446#define lpfc_mbx_cq_create_set_eq_id9_SHIFT 16 1447#define lpfc_mbx_cq_create_set_eq_id9_MASK 0x0000FFFF 1448#define lpfc_mbx_cq_create_set_eq_id9_WORD word7 1449#define lpfc_mbx_cq_create_set_eq_id8_SHIFT 0 1450#define lpfc_mbx_cq_create_set_eq_id8_MASK 0x0000FFFF 1451#define lpfc_mbx_cq_create_set_eq_id8_WORD word7 1452 uint32_t word8; 1453#define lpfc_mbx_cq_create_set_eq_id11_SHIFT 16 1454#define lpfc_mbx_cq_create_set_eq_id11_MASK 0x0000FFFF 1455#define lpfc_mbx_cq_create_set_eq_id11_WORD word8 1456#define lpfc_mbx_cq_create_set_eq_id10_SHIFT 0 1457#define lpfc_mbx_cq_create_set_eq_id10_MASK 0x0000FFFF 1458#define lpfc_mbx_cq_create_set_eq_id10_WORD word8 1459 uint32_t word9; 1460#define lpfc_mbx_cq_create_set_eq_id13_SHIFT 16 1461#define lpfc_mbx_cq_create_set_eq_id13_MASK 0x0000FFFF 1462#define lpfc_mbx_cq_create_set_eq_id13_WORD word9 1463#define lpfc_mbx_cq_create_set_eq_id12_SHIFT 0 1464#define lpfc_mbx_cq_create_set_eq_id12_MASK 0x0000FFFF 1465#define lpfc_mbx_cq_create_set_eq_id12_WORD word9 1466 uint32_t word10; 1467#define lpfc_mbx_cq_create_set_eq_id15_SHIFT 16 1468#define lpfc_mbx_cq_create_set_eq_id15_MASK 0x0000FFFF 1469#define lpfc_mbx_cq_create_set_eq_id15_WORD word10 1470#define lpfc_mbx_cq_create_set_eq_id14_SHIFT 0 1471#define lpfc_mbx_cq_create_set_eq_id14_MASK 0x0000FFFF 1472#define lpfc_mbx_cq_create_set_eq_id14_WORD word10 1473 struct dma_address page[1]; 1474 } request; 1475 struct { 1476 uint32_t word0; 1477#define lpfc_mbx_cq_create_set_num_alloc_SHIFT 16 1478#define lpfc_mbx_cq_create_set_num_alloc_MASK 0x0000FFFF 1479#define lpfc_mbx_cq_create_set_num_alloc_WORD word0 1480#define lpfc_mbx_cq_create_set_base_id_SHIFT 0 1481#define lpfc_mbx_cq_create_set_base_id_MASK 0x0000FFFF 1482#define lpfc_mbx_cq_create_set_base_id_WORD word0 1483 } response; 1484 } u; 1485}; 1486 1487struct lpfc_mbx_cq_destroy { 1488 struct mbox_header header; 1489 union { 1490 struct { 1491 uint32_t word0; 1492#define lpfc_mbx_cq_destroy_q_id_SHIFT 0 1493#define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF 1494#define lpfc_mbx_cq_destroy_q_id_WORD word0 1495 } request; 1496 struct { 1497 uint32_t word0; 1498 } response; 1499 } u; 1500}; 1501 1502struct wq_context { 1503 uint32_t reserved0; 1504 uint32_t reserved1; 1505 uint32_t reserved2; 1506 uint32_t reserved3; 1507}; 1508 1509struct lpfc_mbx_wq_create { 1510 struct mbox_header header; 1511 union { 1512 struct { /* Version 0 Request */ 1513 uint32_t word0; 1514#define lpfc_mbx_wq_create_num_pages_SHIFT 0 1515#define lpfc_mbx_wq_create_num_pages_MASK 0x000000FF 1516#define lpfc_mbx_wq_create_num_pages_WORD word0 1517#define lpfc_mbx_wq_create_dua_SHIFT 8 1518#define lpfc_mbx_wq_create_dua_MASK 0x00000001 1519#define lpfc_mbx_wq_create_dua_WORD word0 1520#define lpfc_mbx_wq_create_cq_id_SHIFT 16 1521#define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF 1522#define lpfc_mbx_wq_create_cq_id_WORD word0 1523 struct dma_address page[LPFC_MAX_WQ_PAGE_V0]; 1524 uint32_t word9; 1525#define lpfc_mbx_wq_create_bua_SHIFT 0 1526#define lpfc_mbx_wq_create_bua_MASK 0x00000001 1527#define lpfc_mbx_wq_create_bua_WORD word9 1528#define lpfc_mbx_wq_create_ulp_num_SHIFT 8 1529#define lpfc_mbx_wq_create_ulp_num_MASK 0x000000FF 1530#define lpfc_mbx_wq_create_ulp_num_WORD word9 1531 } request; 1532 struct { /* Version 1 Request */ 1533 uint32_t word0; /* Word 0 is the same as in v0 */ 1534 uint32_t word1; 1535#define lpfc_mbx_wq_create_page_size_SHIFT 0 1536#define lpfc_mbx_wq_create_page_size_MASK 0x000000FF 1537#define lpfc_mbx_wq_create_page_size_WORD word1 1538#define LPFC_WQ_PAGE_SIZE_4096 0x1 1539#define lpfc_mbx_wq_create_dpp_req_SHIFT 15 1540#define lpfc_mbx_wq_create_dpp_req_MASK 0x00000001 1541#define lpfc_mbx_wq_create_dpp_req_WORD word1 1542#define lpfc_mbx_wq_create_doe_SHIFT 14 1543#define lpfc_mbx_wq_create_doe_MASK 0x00000001 1544#define lpfc_mbx_wq_create_doe_WORD word1 1545#define lpfc_mbx_wq_create_toe_SHIFT 13 1546#define lpfc_mbx_wq_create_toe_MASK 0x00000001 1547#define lpfc_mbx_wq_create_toe_WORD word1 1548#define lpfc_mbx_wq_create_wqe_size_SHIFT 8 1549#define lpfc_mbx_wq_create_wqe_size_MASK 0x0000000F 1550#define lpfc_mbx_wq_create_wqe_size_WORD word1 1551#define LPFC_WQ_WQE_SIZE_64 0x5 1552#define LPFC_WQ_WQE_SIZE_128 0x6 1553#define lpfc_mbx_wq_create_wqe_count_SHIFT 16 1554#define lpfc_mbx_wq_create_wqe_count_MASK 0x0000FFFF 1555#define lpfc_mbx_wq_create_wqe_count_WORD word1 1556 uint32_t word2; 1557 struct dma_address page[LPFC_MAX_WQ_PAGE-1]; 1558 } request_1; 1559 struct { 1560 uint32_t word0; 1561#define lpfc_mbx_wq_create_q_id_SHIFT 0 1562#define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF 1563#define lpfc_mbx_wq_create_q_id_WORD word0 1564 uint32_t doorbell_offset; 1565 uint32_t word2; 1566#define lpfc_mbx_wq_create_bar_set_SHIFT 0 1567#define lpfc_mbx_wq_create_bar_set_MASK 0x0000FFFF 1568#define lpfc_mbx_wq_create_bar_set_WORD word2 1569#define WQ_PCI_BAR_0_AND_1 0x00 1570#define WQ_PCI_BAR_2_AND_3 0x01 1571#define WQ_PCI_BAR_4_AND_5 0x02 1572#define lpfc_mbx_wq_create_db_format_SHIFT 16 1573#define lpfc_mbx_wq_create_db_format_MASK 0x0000FFFF 1574#define lpfc_mbx_wq_create_db_format_WORD word2 1575 } response; 1576 struct { 1577 uint32_t word0; 1578#define lpfc_mbx_wq_create_dpp_rsp_SHIFT 31 1579#define lpfc_mbx_wq_create_dpp_rsp_MASK 0x00000001 1580#define lpfc_mbx_wq_create_dpp_rsp_WORD word0 1581#define lpfc_mbx_wq_create_v1_q_id_SHIFT 0 1582#define lpfc_mbx_wq_create_v1_q_id_MASK 0x0000FFFF 1583#define lpfc_mbx_wq_create_v1_q_id_WORD word0 1584 uint32_t word1; 1585#define lpfc_mbx_wq_create_v1_bar_set_SHIFT 0 1586#define lpfc_mbx_wq_create_v1_bar_set_MASK 0x0000000F 1587#define lpfc_mbx_wq_create_v1_bar_set_WORD word1 1588 uint32_t doorbell_offset; 1589 uint32_t word3; 1590#define lpfc_mbx_wq_create_dpp_id_SHIFT 16 1591#define lpfc_mbx_wq_create_dpp_id_MASK 0x0000001F 1592#define lpfc_mbx_wq_create_dpp_id_WORD word3 1593#define lpfc_mbx_wq_create_dpp_bar_SHIFT 0 1594#define lpfc_mbx_wq_create_dpp_bar_MASK 0x0000000F 1595#define lpfc_mbx_wq_create_dpp_bar_WORD word3 1596 uint32_t dpp_offset; 1597 } response_1; 1598 } u; 1599}; 1600 1601struct lpfc_mbx_wq_destroy { 1602 struct mbox_header header; 1603 union { 1604 struct { 1605 uint32_t word0; 1606#define lpfc_mbx_wq_destroy_q_id_SHIFT 0 1607#define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF 1608#define lpfc_mbx_wq_destroy_q_id_WORD word0 1609 } request; 1610 struct { 1611 uint32_t word0; 1612 } response; 1613 } u; 1614}; 1615 1616#define LPFC_HDR_BUF_SIZE 128 1617#define LPFC_DATA_BUF_SIZE 2048 1618#define LPFC_NVMET_DATA_BUF_SIZE 128 1619struct rq_context { 1620 uint32_t word0; 1621#define lpfc_rq_context_rqe_count_SHIFT 16 /* Version 0 Only */ 1622#define lpfc_rq_context_rqe_count_MASK 0x0000000F 1623#define lpfc_rq_context_rqe_count_WORD word0 1624#define LPFC_RQ_RING_SIZE_512 9 /* 512 entries */ 1625#define LPFC_RQ_RING_SIZE_1024 10 /* 1024 entries */ 1626#define LPFC_RQ_RING_SIZE_2048 11 /* 2048 entries */ 1627#define LPFC_RQ_RING_SIZE_4096 12 /* 4096 entries */ 1628#define lpfc_rq_context_rqe_count_1_SHIFT 16 /* Version 1-2 Only */ 1629#define lpfc_rq_context_rqe_count_1_MASK 0x0000FFFF 1630#define lpfc_rq_context_rqe_count_1_WORD word0 1631#define lpfc_rq_context_rqe_size_SHIFT 8 /* Version 1-2 Only */ 1632#define lpfc_rq_context_rqe_size_MASK 0x0000000F 1633#define lpfc_rq_context_rqe_size_WORD word0 1634#define LPFC_RQE_SIZE_8 2 1635#define LPFC_RQE_SIZE_16 3 1636#define LPFC_RQE_SIZE_32 4 1637#define LPFC_RQE_SIZE_64 5 1638#define LPFC_RQE_SIZE_128 6 1639#define lpfc_rq_context_page_size_SHIFT 0 /* Version 1 Only */ 1640#define lpfc_rq_context_page_size_MASK 0x000000FF 1641#define lpfc_rq_context_page_size_WORD word0 1642#define LPFC_RQ_PAGE_SIZE_4096 0x1 1643 uint32_t word1; 1644#define lpfc_rq_context_data_size_SHIFT 16 /* Version 2 Only */ 1645#define lpfc_rq_context_data_size_MASK 0x0000FFFF 1646#define lpfc_rq_context_data_size_WORD word1 1647#define lpfc_rq_context_hdr_size_SHIFT 0 /* Version 2 Only */ 1648#define lpfc_rq_context_hdr_size_MASK 0x0000FFFF 1649#define lpfc_rq_context_hdr_size_WORD word1 1650 uint32_t word2; 1651#define lpfc_rq_context_cq_id_SHIFT 16 1652#define lpfc_rq_context_cq_id_MASK 0x0000FFFF 1653#define lpfc_rq_context_cq_id_WORD word2 1654#define lpfc_rq_context_buf_size_SHIFT 0 1655#define lpfc_rq_context_buf_size_MASK 0x0000FFFF 1656#define lpfc_rq_context_buf_size_WORD word2 1657#define lpfc_rq_context_base_cq_SHIFT 0 /* Version 2 Only */ 1658#define lpfc_rq_context_base_cq_MASK 0x0000FFFF 1659#define lpfc_rq_context_base_cq_WORD word2 1660 uint32_t buffer_size; /* Version 1 Only */ 1661}; 1662 1663struct lpfc_mbx_rq_create { 1664 struct mbox_header header; 1665 union { 1666 struct { 1667 uint32_t word0; 1668#define lpfc_mbx_rq_create_num_pages_SHIFT 0 1669#define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1670#define lpfc_mbx_rq_create_num_pages_WORD word0 1671#define lpfc_mbx_rq_create_dua_SHIFT 16 1672#define lpfc_mbx_rq_create_dua_MASK 0x00000001 1673#define lpfc_mbx_rq_create_dua_WORD word0 1674#define lpfc_mbx_rq_create_bqu_SHIFT 17 1675#define lpfc_mbx_rq_create_bqu_MASK 0x00000001 1676#define lpfc_mbx_rq_create_bqu_WORD word0 1677#define lpfc_mbx_rq_create_ulp_num_SHIFT 24 1678#define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF 1679#define lpfc_mbx_rq_create_ulp_num_WORD word0 1680 struct rq_context context; 1681 struct dma_address page[LPFC_MAX_RQ_PAGE]; 1682 } request; 1683 struct { 1684 uint32_t word0; 1685#define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16 1686#define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF 1687#define lpfc_mbx_rq_create_q_cnt_v2_WORD word0 1688#define lpfc_mbx_rq_create_q_id_SHIFT 0 1689#define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1690#define lpfc_mbx_rq_create_q_id_WORD word0 1691 uint32_t doorbell_offset; 1692 uint32_t word2; 1693#define lpfc_mbx_rq_create_bar_set_SHIFT 0 1694#define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF 1695#define lpfc_mbx_rq_create_bar_set_WORD word2 1696#define lpfc_mbx_rq_create_db_format_SHIFT 16 1697#define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF 1698#define lpfc_mbx_rq_create_db_format_WORD word2 1699 } response; 1700 } u; 1701}; 1702 1703struct lpfc_mbx_rq_create_v2 { 1704 union lpfc_sli4_cfg_shdr cfg_shdr; 1705 union { 1706 struct { 1707 uint32_t word0; 1708#define lpfc_mbx_rq_create_num_pages_SHIFT 0 1709#define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1710#define lpfc_mbx_rq_create_num_pages_WORD word0 1711#define lpfc_mbx_rq_create_rq_cnt_SHIFT 16 1712#define lpfc_mbx_rq_create_rq_cnt_MASK 0x000000FF 1713#define lpfc_mbx_rq_create_rq_cnt_WORD word0 1714#define lpfc_mbx_rq_create_dua_SHIFT 16 1715#define lpfc_mbx_rq_create_dua_MASK 0x00000001 1716#define lpfc_mbx_rq_create_dua_WORD word0 1717#define lpfc_mbx_rq_create_bqu_SHIFT 17 1718#define lpfc_mbx_rq_create_bqu_MASK 0x00000001 1719#define lpfc_mbx_rq_create_bqu_WORD word0 1720#define lpfc_mbx_rq_create_ulp_num_SHIFT 24 1721#define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF 1722#define lpfc_mbx_rq_create_ulp_num_WORD word0 1723#define lpfc_mbx_rq_create_dim_SHIFT 29 1724#define lpfc_mbx_rq_create_dim_MASK 0x00000001 1725#define lpfc_mbx_rq_create_dim_WORD word0 1726#define lpfc_mbx_rq_create_dfd_SHIFT 30 1727#define lpfc_mbx_rq_create_dfd_MASK 0x00000001 1728#define lpfc_mbx_rq_create_dfd_WORD word0 1729#define lpfc_mbx_rq_create_dnb_SHIFT 31 1730#define lpfc_mbx_rq_create_dnb_MASK 0x00000001 1731#define lpfc_mbx_rq_create_dnb_WORD word0 1732 struct rq_context context; 1733 struct dma_address page[1]; 1734 } request; 1735 struct { 1736 uint32_t word0; 1737#define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16 1738#define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF 1739#define lpfc_mbx_rq_create_q_cnt_v2_WORD word0 1740#define lpfc_mbx_rq_create_q_id_SHIFT 0 1741#define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1742#define lpfc_mbx_rq_create_q_id_WORD word0 1743 uint32_t doorbell_offset; 1744 uint32_t word2; 1745#define lpfc_mbx_rq_create_bar_set_SHIFT 0 1746#define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF 1747#define lpfc_mbx_rq_create_bar_set_WORD word2 1748#define lpfc_mbx_rq_create_db_format_SHIFT 16 1749#define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF 1750#define lpfc_mbx_rq_create_db_format_WORD word2 1751 } response; 1752 } u; 1753}; 1754 1755struct lpfc_mbx_rq_destroy { 1756 struct mbox_header header; 1757 union { 1758 struct { 1759 uint32_t word0; 1760#define lpfc_mbx_rq_destroy_q_id_SHIFT 0 1761#define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF 1762#define lpfc_mbx_rq_destroy_q_id_WORD word0 1763 } request; 1764 struct { 1765 uint32_t word0; 1766 } response; 1767 } u; 1768}; 1769 1770struct mq_context { 1771 uint32_t word0; 1772#define lpfc_mq_context_cq_id_SHIFT 22 /* Version 0 Only */ 1773#define lpfc_mq_context_cq_id_MASK 0x000003FF 1774#define lpfc_mq_context_cq_id_WORD word0 1775#define lpfc_mq_context_ring_size_SHIFT 16 1776#define lpfc_mq_context_ring_size_MASK 0x0000000F 1777#define lpfc_mq_context_ring_size_WORD word0 1778#define LPFC_MQ_RING_SIZE_16 0x5 1779#define LPFC_MQ_RING_SIZE_32 0x6 1780#define LPFC_MQ_RING_SIZE_64 0x7 1781#define LPFC_MQ_RING_SIZE_128 0x8 1782 uint32_t word1; 1783#define lpfc_mq_context_valid_SHIFT 31 1784#define lpfc_mq_context_valid_MASK 0x00000001 1785#define lpfc_mq_context_valid_WORD word1 1786 uint32_t reserved2; 1787 uint32_t reserved3; 1788}; 1789 1790struct lpfc_mbx_mq_create { 1791 struct mbox_header header; 1792 union { 1793 struct { 1794 uint32_t word0; 1795#define lpfc_mbx_mq_create_num_pages_SHIFT 0 1796#define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF 1797#define lpfc_mbx_mq_create_num_pages_WORD word0 1798 struct mq_context context; 1799 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1800 } request; 1801 struct { 1802 uint32_t word0; 1803#define lpfc_mbx_mq_create_q_id_SHIFT 0 1804#define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1805#define lpfc_mbx_mq_create_q_id_WORD word0 1806 } response; 1807 } u; 1808}; 1809 1810struct lpfc_mbx_mq_create_ext { 1811 struct mbox_header header; 1812 union { 1813 struct { 1814 uint32_t word0; 1815#define lpfc_mbx_mq_create_ext_num_pages_SHIFT 0 1816#define lpfc_mbx_mq_create_ext_num_pages_MASK 0x0000FFFF 1817#define lpfc_mbx_mq_create_ext_num_pages_WORD word0 1818#define lpfc_mbx_mq_create_ext_cq_id_SHIFT 16 /* Version 1 Only */ 1819#define lpfc_mbx_mq_create_ext_cq_id_MASK 0x0000FFFF 1820#define lpfc_mbx_mq_create_ext_cq_id_WORD word0 1821 uint32_t async_evt_bmap; 1822#define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT LPFC_TRAILER_CODE_LINK 1823#define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001 1824#define lpfc_mbx_mq_create_ext_async_evt_link_WORD async_evt_bmap 1825#define LPFC_EVT_CODE_LINK_NO_LINK 0x0 1826#define LPFC_EVT_CODE_LINK_10_MBIT 0x1 1827#define LPFC_EVT_CODE_LINK_100_MBIT 0x2 1828#define LPFC_EVT_CODE_LINK_1_GBIT 0x3 1829#define LPFC_EVT_CODE_LINK_10_GBIT 0x4 1830#define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT LPFC_TRAILER_CODE_FCOE 1831#define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001 1832#define lpfc_mbx_mq_create_ext_async_evt_fip_WORD async_evt_bmap 1833#define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT LPFC_TRAILER_CODE_GRP5 1834#define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001 1835#define lpfc_mbx_mq_create_ext_async_evt_group5_WORD async_evt_bmap 1836#define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT LPFC_TRAILER_CODE_FC 1837#define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001 1838#define lpfc_mbx_mq_create_ext_async_evt_fc_WORD async_evt_bmap 1839#define LPFC_EVT_CODE_FC_NO_LINK 0x0 1840#define LPFC_EVT_CODE_FC_1_GBAUD 0x1 1841#define LPFC_EVT_CODE_FC_2_GBAUD 0x2 1842#define LPFC_EVT_CODE_FC_4_GBAUD 0x4 1843#define LPFC_EVT_CODE_FC_8_GBAUD 0x8 1844#define LPFC_EVT_CODE_FC_10_GBAUD 0xA 1845#define LPFC_EVT_CODE_FC_16_GBAUD 0x10 1846#define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT LPFC_TRAILER_CODE_SLI 1847#define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001 1848#define lpfc_mbx_mq_create_ext_async_evt_sli_WORD async_evt_bmap 1849 struct mq_context context; 1850 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1851 } request; 1852 struct { 1853 uint32_t word0; 1854#define lpfc_mbx_mq_create_q_id_SHIFT 0 1855#define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1856#define lpfc_mbx_mq_create_q_id_WORD word0 1857 } response; 1858 } u; 1859#define LPFC_ASYNC_EVENT_LINK_STATE 0x2 1860#define LPFC_ASYNC_EVENT_FCF_STATE 0x4 1861#define LPFC_ASYNC_EVENT_GROUP5 0x20 1862}; 1863 1864struct lpfc_mbx_mq_destroy { 1865 struct mbox_header header; 1866 union { 1867 struct { 1868 uint32_t word0; 1869#define lpfc_mbx_mq_destroy_q_id_SHIFT 0 1870#define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF 1871#define lpfc_mbx_mq_destroy_q_id_WORD word0 1872 } request; 1873 struct { 1874 uint32_t word0; 1875 } response; 1876 } u; 1877}; 1878 1879/* Start Gen 2 SLI4 Mailbox definitions: */ 1880 1881/* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */ 1882#define LPFC_RSC_TYPE_FCOE_VFI 0x20 1883#define LPFC_RSC_TYPE_FCOE_VPI 0x21 1884#define LPFC_RSC_TYPE_FCOE_RPI 0x22 1885#define LPFC_RSC_TYPE_FCOE_XRI 0x23 1886 1887struct lpfc_mbx_get_rsrc_extent_info { 1888 struct mbox_header header; 1889 union { 1890 struct { 1891 uint32_t word4; 1892#define lpfc_mbx_get_rsrc_extent_info_type_SHIFT 0 1893#define lpfc_mbx_get_rsrc_extent_info_type_MASK 0x0000FFFF 1894#define lpfc_mbx_get_rsrc_extent_info_type_WORD word4 1895 } req; 1896 struct { 1897 uint32_t word4; 1898#define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT 0 1899#define lpfc_mbx_get_rsrc_extent_info_cnt_MASK 0x0000FFFF 1900#define lpfc_mbx_get_rsrc_extent_info_cnt_WORD word4 1901#define lpfc_mbx_get_rsrc_extent_info_size_SHIFT 16 1902#define lpfc_mbx_get_rsrc_extent_info_size_MASK 0x0000FFFF 1903#define lpfc_mbx_get_rsrc_extent_info_size_WORD word4 1904 } rsp; 1905 } u; 1906}; 1907 1908struct lpfc_mbx_query_fw_config { 1909 struct mbox_header header; 1910 struct { 1911 uint32_t config_number; 1912#define LPFC_FC_FCOE 0x00000007 1913 uint32_t asic_revision; 1914 uint32_t physical_port; 1915 uint32_t function_mode; 1916#define LPFC_FC_INI_MODE 0x00000040 1917#define LPFC_FC_TGT_MODE 0x00000080 1918#define LPFC_DUA_MODE 0x00000800 1919 uint32_t oper_mode; 1920 uint32_t rsvd9[2]; 1921 uint32_t wqid_base; 1922 uint32_t wqid_tot; 1923 uint32_t rqid_base; 1924 uint32_t rqid_tot; 1925 uint32_t rsvd15[19]; 1926 uint32_t function_capabilities; 1927 uint32_t cqid_base; 1928 uint32_t cqid_tot; 1929 uint32_t eqid_base; 1930 uint32_t eqid_tot; 1931 uint32_t rsvd39[4]; 1932 } rsp; 1933}; 1934 1935struct lpfc_mbx_set_beacon_config { 1936 struct mbox_header header; 1937 uint32_t word4; 1938#define lpfc_mbx_set_beacon_port_num_SHIFT 0 1939#define lpfc_mbx_set_beacon_port_num_MASK 0x0000003F 1940#define lpfc_mbx_set_beacon_port_num_WORD word4 1941#define lpfc_mbx_set_beacon_port_type_SHIFT 6 1942#define lpfc_mbx_set_beacon_port_type_MASK 0x00000003 1943#define lpfc_mbx_set_beacon_port_type_WORD word4 1944#define lpfc_mbx_set_beacon_state_SHIFT 8 1945#define lpfc_mbx_set_beacon_state_MASK 0x000000FF 1946#define lpfc_mbx_set_beacon_state_WORD word4 1947#define lpfc_mbx_set_beacon_duration_SHIFT 16 1948#define lpfc_mbx_set_beacon_duration_MASK 0x000000FF 1949#define lpfc_mbx_set_beacon_duration_WORD word4 1950 1951/* COMMON_SET_BEACON_CONFIG_V1 */ 1952#define lpfc_mbx_set_beacon_duration_v1_SHIFT 16 1953#define lpfc_mbx_set_beacon_duration_v1_MASK 0x0000FFFF 1954#define lpfc_mbx_set_beacon_duration_v1_WORD word4 1955 uint32_t word5; /* RESERVED */ 1956}; 1957 1958struct lpfc_id_range { 1959 uint32_t word5; 1960#define lpfc_mbx_rsrc_id_word4_0_SHIFT 0 1961#define lpfc_mbx_rsrc_id_word4_0_MASK 0x0000FFFF 1962#define lpfc_mbx_rsrc_id_word4_0_WORD word5 1963#define lpfc_mbx_rsrc_id_word4_1_SHIFT 16 1964#define lpfc_mbx_rsrc_id_word4_1_MASK 0x0000FFFF 1965#define lpfc_mbx_rsrc_id_word4_1_WORD word5 1966}; 1967 1968struct lpfc_mbx_set_link_diag_state { 1969 struct mbox_header header; 1970 union { 1971 struct { 1972 uint32_t word0; 1973#define lpfc_mbx_set_diag_state_diag_SHIFT 0 1974#define lpfc_mbx_set_diag_state_diag_MASK 0x00000001 1975#define lpfc_mbx_set_diag_state_diag_WORD word0 1976#define lpfc_mbx_set_diag_state_diag_bit_valid_SHIFT 2 1977#define lpfc_mbx_set_diag_state_diag_bit_valid_MASK 0x00000001 1978#define lpfc_mbx_set_diag_state_diag_bit_valid_WORD word0 1979#define LPFC_DIAG_STATE_DIAG_BIT_VALID_NO_CHANGE 0 1980#define LPFC_DIAG_STATE_DIAG_BIT_VALID_CHANGE 1 1981#define lpfc_mbx_set_diag_state_link_num_SHIFT 16 1982#define lpfc_mbx_set_diag_state_link_num_MASK 0x0000003F 1983#define lpfc_mbx_set_diag_state_link_num_WORD word0 1984#define lpfc_mbx_set_diag_state_link_type_SHIFT 22 1985#define lpfc_mbx_set_diag_state_link_type_MASK 0x00000003 1986#define lpfc_mbx_set_diag_state_link_type_WORD word0 1987 } req; 1988 struct { 1989 uint32_t word0; 1990 } rsp; 1991 } u; 1992}; 1993 1994struct lpfc_mbx_set_link_diag_loopback { 1995 struct mbox_header header; 1996 union { 1997 struct { 1998 uint32_t word0; 1999#define lpfc_mbx_set_diag_lpbk_type_SHIFT 0 2000#define lpfc_mbx_set_diag_lpbk_type_MASK 0x00000003 2001#define lpfc_mbx_set_diag_lpbk_type_WORD word0 2002#define LPFC_DIAG_LOOPBACK_TYPE_DISABLE 0x0 2003#define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL 0x1 2004#define LPFC_DIAG_LOOPBACK_TYPE_SERDES 0x2 2005#define LPFC_DIAG_LOOPBACK_TYPE_EXTERNAL_TRUNKED 0x3 2006#define lpfc_mbx_set_diag_lpbk_link_num_SHIFT 16 2007#define lpfc_mbx_set_diag_lpbk_link_num_MASK 0x0000003F 2008#define lpfc_mbx_set_diag_lpbk_link_num_WORD word0 2009#define lpfc_mbx_set_diag_lpbk_link_type_SHIFT 22 2010#define lpfc_mbx_set_diag_lpbk_link_type_MASK 0x00000003 2011#define lpfc_mbx_set_diag_lpbk_link_type_WORD word0 2012 } req; 2013 struct { 2014 uint32_t word0; 2015 } rsp; 2016 } u; 2017}; 2018 2019struct lpfc_mbx_run_link_diag_test { 2020 struct mbox_header header; 2021 union { 2022 struct { 2023 uint32_t word0; 2024#define lpfc_mbx_run_diag_test_link_num_SHIFT 16 2025#define lpfc_mbx_run_diag_test_link_num_MASK 0x0000003F 2026#define lpfc_mbx_run_diag_test_link_num_WORD word0 2027#define lpfc_mbx_run_diag_test_link_type_SHIFT 22 2028#define lpfc_mbx_run_diag_test_link_type_MASK 0x00000003 2029#define lpfc_mbx_run_diag_test_link_type_WORD word0 2030 uint32_t word1; 2031#define lpfc_mbx_run_diag_test_test_id_SHIFT 0 2032#define lpfc_mbx_run_diag_test_test_id_MASK 0x0000FFFF 2033#define lpfc_mbx_run_diag_test_test_id_WORD word1 2034#define lpfc_mbx_run_diag_test_loops_SHIFT 16 2035#define lpfc_mbx_run_diag_test_loops_MASK 0x0000FFFF 2036#define lpfc_mbx_run_diag_test_loops_WORD word1 2037 uint32_t word2; 2038#define lpfc_mbx_run_diag_test_test_ver_SHIFT 0 2039#define lpfc_mbx_run_diag_test_test_ver_MASK 0x0000FFFF 2040#define lpfc_mbx_run_diag_test_test_ver_WORD word2 2041#define lpfc_mbx_run_diag_test_err_act_SHIFT 16 2042#define lpfc_mbx_run_diag_test_err_act_MASK 0x000000FF 2043#define lpfc_mbx_run_diag_test_err_act_WORD word2 2044 } req; 2045 struct { 2046 uint32_t word0; 2047 } rsp; 2048 } u; 2049}; 2050 2051/* 2052 * struct lpfc_mbx_alloc_rsrc_extents: 2053 * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires 2054 * 6 words of header + 4 words of shared subcommand header + 2055 * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total. 2056 * 2057 * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes 2058 * for extents payload. 2059 * 2060 * 212/2 (bytes per extent) = 106 extents. 2061 * 106/2 (extents per word) = 53 words. 2062 * lpfc_id_range id is statically size to 53. 2063 * 2064 * This mailbox definition is used for ALLOC or GET_ALLOCATED 2065 * extent ranges. For ALLOC, the type and cnt are required. 2066 * For GET_ALLOCATED, only the type is required. 2067 */ 2068struct lpfc_mbx_alloc_rsrc_extents { 2069 struct mbox_header header; 2070 union { 2071 struct { 2072 uint32_t word4; 2073#define lpfc_mbx_alloc_rsrc_extents_type_SHIFT 0 2074#define lpfc_mbx_alloc_rsrc_extents_type_MASK 0x0000FFFF 2075#define lpfc_mbx_alloc_rsrc_extents_type_WORD word4 2076#define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT 16 2077#define lpfc_mbx_alloc_rsrc_extents_cnt_MASK 0x0000FFFF 2078#define lpfc_mbx_alloc_rsrc_extents_cnt_WORD word4 2079 } req; 2080 struct { 2081 uint32_t word4; 2082#define lpfc_mbx_rsrc_cnt_SHIFT 0 2083#define lpfc_mbx_rsrc_cnt_MASK 0x0000FFFF 2084#define lpfc_mbx_rsrc_cnt_WORD word4 2085 struct lpfc_id_range id[53]; 2086 } rsp; 2087 } u; 2088}; 2089 2090/* 2091 * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this 2092 * structure shares the same SHIFT/MASK/WORD defines provided in the 2093 * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in 2094 * the structures defined above. This non-embedded structure provides for the 2095 * maximum number of extents supported by the port. 2096 */ 2097struct lpfc_mbx_nembed_rsrc_extent { 2098 union lpfc_sli4_cfg_shdr cfg_shdr; 2099 uint32_t word4; 2100 struct lpfc_id_range id; 2101}; 2102 2103struct lpfc_mbx_dealloc_rsrc_extents { 2104 struct mbox_header header; 2105 struct { 2106 uint32_t word4; 2107#define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT 0 2108#define lpfc_mbx_dealloc_rsrc_extents_type_MASK 0x0000FFFF 2109#define lpfc_mbx_dealloc_rsrc_extents_type_WORD word4 2110 } req; 2111 2112}; 2113 2114/* Start SLI4 FCoE specific mbox structures. */ 2115 2116struct lpfc_mbx_post_hdr_tmpl { 2117 struct mbox_header header; 2118 uint32_t word10; 2119#define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0 2120#define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF 2121#define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD word10 2122#define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT 16 2123#define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF 2124#define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD word10 2125 uint32_t rpi_paddr_lo; 2126 uint32_t rpi_paddr_hi; 2127}; 2128 2129struct sli4_sge { /* SLI-4 */ 2130 uint32_t addr_hi; 2131 uint32_t addr_lo; 2132 2133 uint32_t word2; 2134#define lpfc_sli4_sge_offset_SHIFT 0 2135#define lpfc_sli4_sge_offset_MASK 0x07FFFFFF 2136#define lpfc_sli4_sge_offset_WORD word2 2137#define lpfc_sli4_sge_type_SHIFT 27 2138#define lpfc_sli4_sge_type_MASK 0x0000000F 2139#define lpfc_sli4_sge_type_WORD word2 2140#define LPFC_SGE_TYPE_DATA 0x0 2141#define LPFC_SGE_TYPE_DIF 0x4 2142#define LPFC_SGE_TYPE_LSP 0x5 2143#define LPFC_SGE_TYPE_PEDIF 0x6 2144#define LPFC_SGE_TYPE_PESEED 0x7 2145#define LPFC_SGE_TYPE_DISEED 0x8 2146#define LPFC_SGE_TYPE_ENC 0x9 2147#define LPFC_SGE_TYPE_ATM 0xA 2148#define LPFC_SGE_TYPE_SKIP 0xC 2149#define lpfc_sli4_sge_last_SHIFT 31 /* Last SEG in the SGL sets it */ 2150#define lpfc_sli4_sge_last_MASK 0x00000001 2151#define lpfc_sli4_sge_last_WORD word2 2152 uint32_t sge_len; 2153}; 2154 2155struct sli4_sge_le { 2156 __le32 addr_hi; 2157 __le32 addr_lo; 2158 2159 __le32 word2; 2160 __le32 sge_len; 2161}; 2162 2163struct sli4_hybrid_sgl { 2164 struct list_head list_node; 2165 struct sli4_sge *dma_sgl; 2166 dma_addr_t dma_phys_sgl; 2167}; 2168 2169struct fcp_cmd_rsp_buf { 2170 struct list_head list_node; 2171 2172 /* for storing cmd/rsp dma alloc'ed virt_addr */ 2173 struct fcp_cmnd *fcp_cmnd; 2174 struct fcp_rsp *fcp_rsp; 2175 2176 /* for storing this cmd/rsp's dma mapped phys addr from per CPU pool */ 2177 dma_addr_t fcp_cmd_rsp_dma_handle; 2178}; 2179 2180struct sli4_sge_diseed { /* SLI-4 */ 2181 uint32_t ref_tag; 2182 uint32_t ref_tag_tran; 2183 2184 uint32_t word2; 2185#define lpfc_sli4_sge_dif_apptran_SHIFT 0 2186#define lpfc_sli4_sge_dif_apptran_MASK 0x0000FFFF 2187#define lpfc_sli4_sge_dif_apptran_WORD word2 2188#define lpfc_sli4_sge_dif_af_SHIFT 24 2189#define lpfc_sli4_sge_dif_af_MASK 0x00000001 2190#define lpfc_sli4_sge_dif_af_WORD word2 2191#define lpfc_sli4_sge_dif_na_SHIFT 25 2192#define lpfc_sli4_sge_dif_na_MASK 0x00000001 2193#define lpfc_sli4_sge_dif_na_WORD word2 2194#define lpfc_sli4_sge_dif_hi_SHIFT 26 2195#define lpfc_sli4_sge_dif_hi_MASK 0x00000001 2196#define lpfc_sli4_sge_dif_hi_WORD word2 2197#define lpfc_sli4_sge_dif_type_SHIFT 27 2198#define lpfc_sli4_sge_dif_type_MASK 0x0000000F 2199#define lpfc_sli4_sge_dif_type_WORD word2 2200#define lpfc_sli4_sge_dif_last_SHIFT 31 /* Last SEG in the SGL sets it */ 2201#define lpfc_sli4_sge_dif_last_MASK 0x00000001 2202#define lpfc_sli4_sge_dif_last_WORD word2 2203 uint32_t word3; 2204#define lpfc_sli4_sge_dif_apptag_SHIFT 0 2205#define lpfc_sli4_sge_dif_apptag_MASK 0x0000FFFF 2206#define lpfc_sli4_sge_dif_apptag_WORD word3 2207#define lpfc_sli4_sge_dif_bs_SHIFT 16 2208#define lpfc_sli4_sge_dif_bs_MASK 0x00000007 2209#define lpfc_sli4_sge_dif_bs_WORD word3 2210#define lpfc_sli4_sge_dif_ai_SHIFT 19 2211#define lpfc_sli4_sge_dif_ai_MASK 0x00000001 2212#define lpfc_sli4_sge_dif_ai_WORD word3 2213#define lpfc_sli4_sge_dif_me_SHIFT 20 2214#define lpfc_sli4_sge_dif_me_MASK 0x00000001 2215#define lpfc_sli4_sge_dif_me_WORD word3 2216#define lpfc_sli4_sge_dif_re_SHIFT 21 2217#define lpfc_sli4_sge_dif_re_MASK 0x00000001 2218#define lpfc_sli4_sge_dif_re_WORD word3 2219#define lpfc_sli4_sge_dif_ce_SHIFT 22 2220#define lpfc_sli4_sge_dif_ce_MASK 0x00000001 2221#define lpfc_sli4_sge_dif_ce_WORD word3 2222#define lpfc_sli4_sge_dif_nr_SHIFT 23 2223#define lpfc_sli4_sge_dif_nr_MASK 0x00000001 2224#define lpfc_sli4_sge_dif_nr_WORD word3 2225#define lpfc_sli4_sge_dif_oprx_SHIFT 24 2226#define lpfc_sli4_sge_dif_oprx_MASK 0x0000000F 2227#define lpfc_sli4_sge_dif_oprx_WORD word3 2228#define lpfc_sli4_sge_dif_optx_SHIFT 28 2229#define lpfc_sli4_sge_dif_optx_MASK 0x0000000F 2230#define lpfc_sli4_sge_dif_optx_WORD word3 2231/* optx and oprx use BG_OP_IN defines in lpfc_hw.h */ 2232}; 2233 2234struct fcf_record { 2235 uint32_t max_rcv_size; 2236 uint32_t fka_adv_period; 2237 uint32_t fip_priority; 2238 uint32_t word3; 2239#define lpfc_fcf_record_mac_0_SHIFT 0 2240#define lpfc_fcf_record_mac_0_MASK 0x000000FF 2241#define lpfc_fcf_record_mac_0_WORD word3 2242#define lpfc_fcf_record_mac_1_SHIFT 8 2243#define lpfc_fcf_record_mac_1_MASK 0x000000FF 2244#define lpfc_fcf_record_mac_1_WORD word3 2245#define lpfc_fcf_record_mac_2_SHIFT 16 2246#define lpfc_fcf_record_mac_2_MASK 0x000000FF 2247#define lpfc_fcf_record_mac_2_WORD word3 2248#define lpfc_fcf_record_mac_3_SHIFT 24 2249#define lpfc_fcf_record_mac_3_MASK 0x000000FF 2250#define lpfc_fcf_record_mac_3_WORD word3 2251 uint32_t word4; 2252#define lpfc_fcf_record_mac_4_SHIFT 0 2253#define lpfc_fcf_record_mac_4_MASK 0x000000FF 2254#define lpfc_fcf_record_mac_4_WORD word4 2255#define lpfc_fcf_record_mac_5_SHIFT 8 2256#define lpfc_fcf_record_mac_5_MASK 0x000000FF 2257#define lpfc_fcf_record_mac_5_WORD word4 2258#define lpfc_fcf_record_fcf_avail_SHIFT 16 2259#define lpfc_fcf_record_fcf_avail_MASK 0x000000FF 2260#define lpfc_fcf_record_fcf_avail_WORD word4 2261#define lpfc_fcf_record_mac_addr_prov_SHIFT 24 2262#define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF 2263#define lpfc_fcf_record_mac_addr_prov_WORD word4 2264#define LPFC_FCF_FPMA 1 /* Fabric Provided MAC Address */ 2265#define LPFC_FCF_SPMA 2 /* Server Provided MAC Address */ 2266 uint32_t word5; 2267#define lpfc_fcf_record_fab_name_0_SHIFT 0 2268#define lpfc_fcf_record_fab_name_0_MASK 0x000000FF 2269#define lpfc_fcf_record_fab_name_0_WORD word5 2270#define lpfc_fcf_record_fab_name_1_SHIFT 8 2271#define lpfc_fcf_record_fab_name_1_MASK 0x000000FF 2272#define lpfc_fcf_record_fab_name_1_WORD word5 2273#define lpfc_fcf_record_fab_name_2_SHIFT 16 2274#define lpfc_fcf_record_fab_name_2_MASK 0x000000FF 2275#define lpfc_fcf_record_fab_name_2_WORD word5 2276#define lpfc_fcf_record_fab_name_3_SHIFT 24 2277#define lpfc_fcf_record_fab_name_3_MASK 0x000000FF 2278#define lpfc_fcf_record_fab_name_3_WORD word5 2279 uint32_t word6; 2280#define lpfc_fcf_record_fab_name_4_SHIFT 0 2281#define lpfc_fcf_record_fab_name_4_MASK 0x000000FF 2282#define lpfc_fcf_record_fab_name_4_WORD word6 2283#define lpfc_fcf_record_fab_name_5_SHIFT 8 2284#define lpfc_fcf_record_fab_name_5_MASK 0x000000FF 2285#define lpfc_fcf_record_fab_name_5_WORD word6 2286#define lpfc_fcf_record_fab_name_6_SHIFT 16 2287#define lpfc_fcf_record_fab_name_6_MASK 0x000000FF 2288#define lpfc_fcf_record_fab_name_6_WORD word6 2289#define lpfc_fcf_record_fab_name_7_SHIFT 24 2290#define lpfc_fcf_record_fab_name_7_MASK 0x000000FF 2291#define lpfc_fcf_record_fab_name_7_WORD word6 2292 uint32_t word7; 2293#define lpfc_fcf_record_fc_map_0_SHIFT 0 2294#define lpfc_fcf_record_fc_map_0_MASK 0x000000FF 2295#define lpfc_fcf_record_fc_map_0_WORD word7 2296#define lpfc_fcf_record_fc_map_1_SHIFT 8 2297#define lpfc_fcf_record_fc_map_1_MASK 0x000000FF 2298#define lpfc_fcf_record_fc_map_1_WORD word7 2299#define lpfc_fcf_record_fc_map_2_SHIFT 16 2300#define lpfc_fcf_record_fc_map_2_MASK 0x000000FF 2301#define lpfc_fcf_record_fc_map_2_WORD word7 2302#define lpfc_fcf_record_fcf_valid_SHIFT 24 2303#define lpfc_fcf_record_fcf_valid_MASK 0x00000001 2304#define lpfc_fcf_record_fcf_valid_WORD word7 2305#define lpfc_fcf_record_fcf_fc_SHIFT 25 2306#define lpfc_fcf_record_fcf_fc_MASK 0x00000001 2307#define lpfc_fcf_record_fcf_fc_WORD word7 2308#define lpfc_fcf_record_fcf_sol_SHIFT 31 2309#define lpfc_fcf_record_fcf_sol_MASK 0x00000001 2310#define lpfc_fcf_record_fcf_sol_WORD word7 2311 uint32_t word8; 2312#define lpfc_fcf_record_fcf_index_SHIFT 0 2313#define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF 2314#define lpfc_fcf_record_fcf_index_WORD word8 2315#define lpfc_fcf_record_fcf_state_SHIFT 16 2316#define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF 2317#define lpfc_fcf_record_fcf_state_WORD word8 2318 uint8_t vlan_bitmap[512]; 2319 uint32_t word137; 2320#define lpfc_fcf_record_switch_name_0_SHIFT 0 2321#define lpfc_fcf_record_switch_name_0_MASK 0x000000FF 2322#define lpfc_fcf_record_switch_name_0_WORD word137 2323#define lpfc_fcf_record_switch_name_1_SHIFT 8 2324#define lpfc_fcf_record_switch_name_1_MASK 0x000000FF 2325#define lpfc_fcf_record_switch_name_1_WORD word137 2326#define lpfc_fcf_record_switch_name_2_SHIFT 16 2327#define lpfc_fcf_record_switch_name_2_MASK 0x000000FF 2328#define lpfc_fcf_record_switch_name_2_WORD word137 2329#define lpfc_fcf_record_switch_name_3_SHIFT 24 2330#define lpfc_fcf_record_switch_name_3_MASK 0x000000FF 2331#define lpfc_fcf_record_switch_name_3_WORD word137 2332 uint32_t word138; 2333#define lpfc_fcf_record_switch_name_4_SHIFT 0 2334#define lpfc_fcf_record_switch_name_4_MASK 0x000000FF 2335#define lpfc_fcf_record_switch_name_4_WORD word138 2336#define lpfc_fcf_record_switch_name_5_SHIFT 8 2337#define lpfc_fcf_record_switch_name_5_MASK 0x000000FF 2338#define lpfc_fcf_record_switch_name_5_WORD word138 2339#define lpfc_fcf_record_switch_name_6_SHIFT 16 2340#define lpfc_fcf_record_switch_name_6_MASK 0x000000FF 2341#define lpfc_fcf_record_switch_name_6_WORD word138 2342#define lpfc_fcf_record_switch_name_7_SHIFT 24 2343#define lpfc_fcf_record_switch_name_7_MASK 0x000000FF 2344#define lpfc_fcf_record_switch_name_7_WORD word138 2345}; 2346 2347struct lpfc_mbx_read_fcf_tbl { 2348 union lpfc_sli4_cfg_shdr cfg_shdr; 2349 union { 2350 struct { 2351 uint32_t word10; 2352#define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0 2353#define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF 2354#define lpfc_mbx_read_fcf_tbl_indx_WORD word10 2355 } request; 2356 struct { 2357 uint32_t eventag; 2358 } response; 2359 } u; 2360 uint32_t word11; 2361#define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0 2362#define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF 2363#define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD word11 2364}; 2365 2366struct lpfc_mbx_add_fcf_tbl_entry { 2367 union lpfc_sli4_cfg_shdr cfg_shdr; 2368 uint32_t word10; 2369#define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0 2370#define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF 2371#define lpfc_mbx_add_fcf_tbl_fcfi_WORD word10 2372 struct lpfc_mbx_sge fcf_sge; 2373}; 2374 2375struct lpfc_mbx_del_fcf_tbl_entry { 2376 struct mbox_header header; 2377 uint32_t word10; 2378#define lpfc_mbx_del_fcf_tbl_count_SHIFT 0 2379#define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF 2380#define lpfc_mbx_del_fcf_tbl_count_WORD word10 2381#define lpfc_mbx_del_fcf_tbl_index_SHIFT 16 2382#define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF 2383#define lpfc_mbx_del_fcf_tbl_index_WORD word10 2384}; 2385 2386struct lpfc_mbx_redisc_fcf_tbl { 2387 struct mbox_header header; 2388 uint32_t word10; 2389#define lpfc_mbx_redisc_fcf_count_SHIFT 0 2390#define lpfc_mbx_redisc_fcf_count_MASK 0x0000FFFF 2391#define lpfc_mbx_redisc_fcf_count_WORD word10 2392 uint32_t resvd; 2393 uint32_t word12; 2394#define lpfc_mbx_redisc_fcf_index_SHIFT 0 2395#define lpfc_mbx_redisc_fcf_index_MASK 0x0000FFFF 2396#define lpfc_mbx_redisc_fcf_index_WORD word12 2397}; 2398 2399/* Status field for embedded SLI_CONFIG mailbox command */ 2400#define STATUS_SUCCESS 0x0 2401#define STATUS_FAILED 0x1 2402#define STATUS_ILLEGAL_REQUEST 0x2 2403#define STATUS_ILLEGAL_FIELD 0x3 2404#define STATUS_INSUFFICIENT_BUFFER 0x4 2405#define STATUS_UNAUTHORIZED_REQUEST 0x5 2406#define STATUS_FLASHROM_SAVE_FAILED 0x17 2407#define STATUS_FLASHROM_RESTORE_FAILED 0x18 2408#define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a 2409#define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b 2410#define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c 2411#define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d 2412#define STATUS_ASSERT_FAILED 0x1e 2413#define STATUS_INVALID_SESSION 0x1f 2414#define STATUS_INVALID_CONNECTION 0x20 2415#define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21 2416#define STATUS_BTL_NO_FREE_SLOT_PATH 0x24 2417#define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25 2418#define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26 2419#define STATUS_FLASHROM_READ_FAILED 0x27 2420#define STATUS_POLL_IOCTL_TIMEOUT 0x28 2421#define STATUS_ERROR_ACITMAIN 0x2a 2422#define STATUS_REBOOT_REQUIRED 0x2c 2423#define STATUS_FCF_IN_USE 0x3a 2424#define STATUS_FCF_TABLE_EMPTY 0x43 2425 2426/* 2427 * Additional status field for embedded SLI_CONFIG mailbox 2428 * command. 2429 */ 2430#define ADD_STATUS_OPERATION_ALREADY_ACTIVE 0x67 2431#define ADD_STATUS_FW_NOT_SUPPORTED 0xEB 2432#define ADD_STATUS_INVALID_REQUEST 0x4B 2433#define ADD_STATUS_INVALID_OBJECT_NAME 0xA0 2434#define ADD_STATUS_FW_DOWNLOAD_HW_DISABLED 0x58 2435 2436struct lpfc_mbx_sli4_config { 2437 struct mbox_header header; 2438}; 2439 2440struct lpfc_mbx_init_vfi { 2441 uint32_t word1; 2442#define lpfc_init_vfi_vr_SHIFT 31 2443#define lpfc_init_vfi_vr_MASK 0x00000001 2444#define lpfc_init_vfi_vr_WORD word1 2445#define lpfc_init_vfi_vt_SHIFT 30 2446#define lpfc_init_vfi_vt_MASK 0x00000001 2447#define lpfc_init_vfi_vt_WORD word1 2448#define lpfc_init_vfi_vf_SHIFT 29 2449#define lpfc_init_vfi_vf_MASK 0x00000001 2450#define lpfc_init_vfi_vf_WORD word1 2451#define lpfc_init_vfi_vp_SHIFT 28 2452#define lpfc_init_vfi_vp_MASK 0x00000001 2453#define lpfc_init_vfi_vp_WORD word1 2454#define lpfc_init_vfi_vfi_SHIFT 0 2455#define lpfc_init_vfi_vfi_MASK 0x0000FFFF 2456#define lpfc_init_vfi_vfi_WORD word1 2457 uint32_t word2; 2458#define lpfc_init_vfi_vpi_SHIFT 16 2459#define lpfc_init_vfi_vpi_MASK 0x0000FFFF 2460#define lpfc_init_vfi_vpi_WORD word2 2461#define lpfc_init_vfi_fcfi_SHIFT 0 2462#define lpfc_init_vfi_fcfi_MASK 0x0000FFFF 2463#define lpfc_init_vfi_fcfi_WORD word2 2464 uint32_t word3; 2465#define lpfc_init_vfi_pri_SHIFT 13 2466#define lpfc_init_vfi_pri_MASK 0x00000007 2467#define lpfc_init_vfi_pri_WORD word3 2468#define lpfc_init_vfi_vf_id_SHIFT 1 2469#define lpfc_init_vfi_vf_id_MASK 0x00000FFF 2470#define lpfc_init_vfi_vf_id_WORD word3 2471 uint32_t word4; 2472#define lpfc_init_vfi_hop_count_SHIFT 24 2473#define lpfc_init_vfi_hop_count_MASK 0x000000FF 2474#define lpfc_init_vfi_hop_count_WORD word4 2475}; 2476#define MBX_VFI_IN_USE 0x9F02 2477 2478 2479struct lpfc_mbx_reg_vfi { 2480 uint32_t word1; 2481#define lpfc_reg_vfi_upd_SHIFT 29 2482#define lpfc_reg_vfi_upd_MASK 0x00000001 2483#define lpfc_reg_vfi_upd_WORD word1 2484#define lpfc_reg_vfi_vp_SHIFT 28 2485#define lpfc_reg_vfi_vp_MASK 0x00000001 2486#define lpfc_reg_vfi_vp_WORD word1 2487#define lpfc_reg_vfi_vfi_SHIFT 0 2488#define lpfc_reg_vfi_vfi_MASK 0x0000FFFF 2489#define lpfc_reg_vfi_vfi_WORD word1 2490 uint32_t word2; 2491#define lpfc_reg_vfi_vpi_SHIFT 16 2492#define lpfc_reg_vfi_vpi_MASK 0x0000FFFF 2493#define lpfc_reg_vfi_vpi_WORD word2 2494#define lpfc_reg_vfi_fcfi_SHIFT 0 2495#define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF 2496#define lpfc_reg_vfi_fcfi_WORD word2 2497 uint32_t wwn[2]; 2498 struct ulp_bde64 bde; 2499 uint32_t e_d_tov; 2500 uint32_t r_a_tov; 2501 uint32_t word10; 2502#define lpfc_reg_vfi_nport_id_SHIFT 0 2503#define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF 2504#define lpfc_reg_vfi_nport_id_WORD word10 2505#define lpfc_reg_vfi_bbcr_SHIFT 27 2506#define lpfc_reg_vfi_bbcr_MASK 0x00000001 2507#define lpfc_reg_vfi_bbcr_WORD word10 2508#define lpfc_reg_vfi_bbscn_SHIFT 28 2509#define lpfc_reg_vfi_bbscn_MASK 0x0000000F 2510#define lpfc_reg_vfi_bbscn_WORD word10 2511}; 2512 2513struct lpfc_mbx_init_vpi { 2514 uint32_t word1; 2515#define lpfc_init_vpi_vfi_SHIFT 16 2516#define lpfc_init_vpi_vfi_MASK 0x0000FFFF 2517#define lpfc_init_vpi_vfi_WORD word1 2518#define lpfc_init_vpi_vpi_SHIFT 0 2519#define lpfc_init_vpi_vpi_MASK 0x0000FFFF 2520#define lpfc_init_vpi_vpi_WORD word1 2521}; 2522 2523struct lpfc_mbx_read_vpi { 2524 uint32_t word1_rsvd; 2525 uint32_t word2; 2526#define lpfc_mbx_read_vpi_vnportid_SHIFT 0 2527#define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF 2528#define lpfc_mbx_read_vpi_vnportid_WORD word2 2529 uint32_t word3_rsvd; 2530 uint32_t word4; 2531#define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0 2532#define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF 2533#define lpfc_mbx_read_vpi_acq_alpa_WORD word4 2534#define lpfc_mbx_read_vpi_pb_SHIFT 15 2535#define lpfc_mbx_read_vpi_pb_MASK 0x00000001 2536#define lpfc_mbx_read_vpi_pb_WORD word4 2537#define lpfc_mbx_read_vpi_spec_alpa_SHIFT 16 2538#define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF 2539#define lpfc_mbx_read_vpi_spec_alpa_WORD word4 2540#define lpfc_mbx_read_vpi_ns_SHIFT 30 2541#define lpfc_mbx_read_vpi_ns_MASK 0x00000001 2542#define lpfc_mbx_read_vpi_ns_WORD word4 2543#define lpfc_mbx_read_vpi_hl_SHIFT 31 2544#define lpfc_mbx_read_vpi_hl_MASK 0x00000001 2545#define lpfc_mbx_read_vpi_hl_WORD word4 2546 uint32_t word5_rsvd; 2547 uint32_t word6; 2548#define lpfc_mbx_read_vpi_vpi_SHIFT 0 2549#define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF 2550#define lpfc_mbx_read_vpi_vpi_WORD word6 2551 uint32_t word7; 2552#define lpfc_mbx_read_vpi_mac_0_SHIFT 0 2553#define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF 2554#define lpfc_mbx_read_vpi_mac_0_WORD word7 2555#define lpfc_mbx_read_vpi_mac_1_SHIFT 8 2556#define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF 2557#define lpfc_mbx_read_vpi_mac_1_WORD word7 2558#define lpfc_mbx_read_vpi_mac_2_SHIFT 16 2559#define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF 2560#define lpfc_mbx_read_vpi_mac_2_WORD word7 2561#define lpfc_mbx_read_vpi_mac_3_SHIFT 24 2562#define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF 2563#define lpfc_mbx_read_vpi_mac_3_WORD word7 2564 uint32_t word8; 2565#define lpfc_mbx_read_vpi_mac_4_SHIFT 0 2566#define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF 2567#define lpfc_mbx_read_vpi_mac_4_WORD word8 2568#define lpfc_mbx_read_vpi_mac_5_SHIFT 8 2569#define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF 2570#define lpfc_mbx_read_vpi_mac_5_WORD word8 2571#define lpfc_mbx_read_vpi_vlan_tag_SHIFT 16 2572#define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF 2573#define lpfc_mbx_read_vpi_vlan_tag_WORD word8 2574#define lpfc_mbx_read_vpi_vv_SHIFT 28 2575#define lpfc_mbx_read_vpi_vv_MASK 0x0000001 2576#define lpfc_mbx_read_vpi_vv_WORD word8 2577}; 2578 2579struct lpfc_mbx_unreg_vfi { 2580 uint32_t word1_rsvd; 2581 uint32_t word2; 2582#define lpfc_unreg_vfi_vfi_SHIFT 0 2583#define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF 2584#define lpfc_unreg_vfi_vfi_WORD word2 2585}; 2586 2587struct lpfc_mbx_resume_rpi { 2588 uint32_t word1; 2589#define lpfc_resume_rpi_index_SHIFT 0 2590#define lpfc_resume_rpi_index_MASK 0x0000FFFF 2591#define lpfc_resume_rpi_index_WORD word1 2592#define lpfc_resume_rpi_ii_SHIFT 30 2593#define lpfc_resume_rpi_ii_MASK 0x00000003 2594#define lpfc_resume_rpi_ii_WORD word1 2595#define RESUME_INDEX_RPI 0 2596#define RESUME_INDEX_VPI 1 2597#define RESUME_INDEX_VFI 2 2598#define RESUME_INDEX_FCFI 3 2599 uint32_t event_tag; 2600}; 2601 2602#define REG_FCF_INVALID_QID 0xFFFF 2603struct lpfc_mbx_reg_fcfi { 2604 uint32_t word1; 2605#define lpfc_reg_fcfi_info_index_SHIFT 0 2606#define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF 2607#define lpfc_reg_fcfi_info_index_WORD word1 2608#define lpfc_reg_fcfi_fcfi_SHIFT 16 2609#define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF 2610#define lpfc_reg_fcfi_fcfi_WORD word1 2611 uint32_t word2; 2612#define lpfc_reg_fcfi_rq_id1_SHIFT 0 2613#define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF 2614#define lpfc_reg_fcfi_rq_id1_WORD word2 2615#define lpfc_reg_fcfi_rq_id0_SHIFT 16 2616#define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF 2617#define lpfc_reg_fcfi_rq_id0_WORD word2 2618 uint32_t word3; 2619#define lpfc_reg_fcfi_rq_id3_SHIFT 0 2620#define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF 2621#define lpfc_reg_fcfi_rq_id3_WORD word3 2622#define lpfc_reg_fcfi_rq_id2_SHIFT 16 2623#define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF 2624#define lpfc_reg_fcfi_rq_id2_WORD word3 2625 uint32_t word4; 2626#define lpfc_reg_fcfi_type_match0_SHIFT 24 2627#define lpfc_reg_fcfi_type_match0_MASK 0x000000FF 2628#define lpfc_reg_fcfi_type_match0_WORD word4 2629#define lpfc_reg_fcfi_type_mask0_SHIFT 16 2630#define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF 2631#define lpfc_reg_fcfi_type_mask0_WORD word4 2632#define lpfc_reg_fcfi_rctl_match0_SHIFT 8 2633#define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF 2634#define lpfc_reg_fcfi_rctl_match0_WORD word4 2635#define lpfc_reg_fcfi_rctl_mask0_SHIFT 0 2636#define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF 2637#define lpfc_reg_fcfi_rctl_mask0_WORD word4 2638 uint32_t word5; 2639#define lpfc_reg_fcfi_type_match1_SHIFT 24 2640#define lpfc_reg_fcfi_type_match1_MASK 0x000000FF 2641#define lpfc_reg_fcfi_type_match1_WORD word5 2642#define lpfc_reg_fcfi_type_mask1_SHIFT 16 2643#define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF 2644#define lpfc_reg_fcfi_type_mask1_WORD word5 2645#define lpfc_reg_fcfi_rctl_match1_SHIFT 8 2646#define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF 2647#define lpfc_reg_fcfi_rctl_match1_WORD word5 2648#define lpfc_reg_fcfi_rctl_mask1_SHIFT 0 2649#define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF 2650#define lpfc_reg_fcfi_rctl_mask1_WORD word5 2651 uint32_t word6; 2652#define lpfc_reg_fcfi_type_match2_SHIFT 24 2653#define lpfc_reg_fcfi_type_match2_MASK 0x000000FF 2654#define lpfc_reg_fcfi_type_match2_WORD word6 2655#define lpfc_reg_fcfi_type_mask2_SHIFT 16 2656#define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF 2657#define lpfc_reg_fcfi_type_mask2_WORD word6 2658#define lpfc_reg_fcfi_rctl_match2_SHIFT 8 2659#define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF 2660#define lpfc_reg_fcfi_rctl_match2_WORD word6 2661#define lpfc_reg_fcfi_rctl_mask2_SHIFT 0 2662#define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF 2663#define lpfc_reg_fcfi_rctl_mask2_WORD word6 2664 uint32_t word7; 2665#define lpfc_reg_fcfi_type_match3_SHIFT 24 2666#define lpfc_reg_fcfi_type_match3_MASK 0x000000FF 2667#define lpfc_reg_fcfi_type_match3_WORD word7 2668#define lpfc_reg_fcfi_type_mask3_SHIFT 16 2669#define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF 2670#define lpfc_reg_fcfi_type_mask3_WORD word7 2671#define lpfc_reg_fcfi_rctl_match3_SHIFT 8 2672#define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF 2673#define lpfc_reg_fcfi_rctl_match3_WORD word7 2674#define lpfc_reg_fcfi_rctl_mask3_SHIFT 0 2675#define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF 2676#define lpfc_reg_fcfi_rctl_mask3_WORD word7 2677 uint32_t word8; 2678#define lpfc_reg_fcfi_mam_SHIFT 13 2679#define lpfc_reg_fcfi_mam_MASK 0x00000003 2680#define lpfc_reg_fcfi_mam_WORD word8 2681#define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */ 2682#define LPFC_MAM_SPMA 1 /* Server Provided MAC Address */ 2683#define LPFC_MAM_FPMA 2 /* Fabric Provided MAC Address */ 2684#define lpfc_reg_fcfi_vv_SHIFT 12 2685#define lpfc_reg_fcfi_vv_MASK 0x00000001 2686#define lpfc_reg_fcfi_vv_WORD word8 2687#define lpfc_reg_fcfi_vlan_tag_SHIFT 0 2688#define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF 2689#define lpfc_reg_fcfi_vlan_tag_WORD word8 2690}; 2691 2692struct lpfc_mbx_reg_fcfi_mrq { 2693 uint32_t word1; 2694#define lpfc_reg_fcfi_mrq_info_index_SHIFT 0 2695#define lpfc_reg_fcfi_mrq_info_index_MASK 0x0000FFFF 2696#define lpfc_reg_fcfi_mrq_info_index_WORD word1 2697#define lpfc_reg_fcfi_mrq_fcfi_SHIFT 16 2698#define lpfc_reg_fcfi_mrq_fcfi_MASK 0x0000FFFF 2699#define lpfc_reg_fcfi_mrq_fcfi_WORD word1 2700 uint32_t word2; 2701#define lpfc_reg_fcfi_mrq_rq_id1_SHIFT 0 2702#define lpfc_reg_fcfi_mrq_rq_id1_MASK 0x0000FFFF 2703#define lpfc_reg_fcfi_mrq_rq_id1_WORD word2 2704#define lpfc_reg_fcfi_mrq_rq_id0_SHIFT 16 2705#define lpfc_reg_fcfi_mrq_rq_id0_MASK 0x0000FFFF 2706#define lpfc_reg_fcfi_mrq_rq_id0_WORD word2 2707 uint32_t word3; 2708#define lpfc_reg_fcfi_mrq_rq_id3_SHIFT 0 2709#define lpfc_reg_fcfi_mrq_rq_id3_MASK 0x0000FFFF 2710#define lpfc_reg_fcfi_mrq_rq_id3_WORD word3 2711#define lpfc_reg_fcfi_mrq_rq_id2_SHIFT 16 2712#define lpfc_reg_fcfi_mrq_rq_id2_MASK 0x0000FFFF 2713#define lpfc_reg_fcfi_mrq_rq_id2_WORD word3 2714 uint32_t word4; 2715#define lpfc_reg_fcfi_mrq_type_match0_SHIFT 24 2716#define lpfc_reg_fcfi_mrq_type_match0_MASK 0x000000FF 2717#define lpfc_reg_fcfi_mrq_type_match0_WORD word4 2718#define lpfc_reg_fcfi_mrq_type_mask0_SHIFT 16 2719#define lpfc_reg_fcfi_mrq_type_mask0_MASK 0x000000FF 2720#define lpfc_reg_fcfi_mrq_type_mask0_WORD word4 2721#define lpfc_reg_fcfi_mrq_rctl_match0_SHIFT 8 2722#define lpfc_reg_fcfi_mrq_rctl_match0_MASK 0x000000FF 2723#define lpfc_reg_fcfi_mrq_rctl_match0_WORD word4 2724#define lpfc_reg_fcfi_mrq_rctl_mask0_SHIFT 0 2725#define lpfc_reg_fcfi_mrq_rctl_mask0_MASK 0x000000FF 2726#define lpfc_reg_fcfi_mrq_rctl_mask0_WORD word4 2727 uint32_t word5; 2728#define lpfc_reg_fcfi_mrq_type_match1_SHIFT 24 2729#define lpfc_reg_fcfi_mrq_type_match1_MASK 0x000000FF 2730#define lpfc_reg_fcfi_mrq_type_match1_WORD word5 2731#define lpfc_reg_fcfi_mrq_type_mask1_SHIFT 16 2732#define lpfc_reg_fcfi_mrq_type_mask1_MASK 0x000000FF 2733#define lpfc_reg_fcfi_mrq_type_mask1_WORD word5 2734#define lpfc_reg_fcfi_mrq_rctl_match1_SHIFT 8 2735#define lpfc_reg_fcfi_mrq_rctl_match1_MASK 0x000000FF 2736#define lpfc_reg_fcfi_mrq_rctl_match1_WORD word5 2737#define lpfc_reg_fcfi_mrq_rctl_mask1_SHIFT 0 2738#define lpfc_reg_fcfi_mrq_rctl_mask1_MASK 0x000000FF 2739#define lpfc_reg_fcfi_mrq_rctl_mask1_WORD word5 2740 uint32_t word6; 2741#define lpfc_reg_fcfi_mrq_type_match2_SHIFT 24 2742#define lpfc_reg_fcfi_mrq_type_match2_MASK 0x000000FF 2743#define lpfc_reg_fcfi_mrq_type_match2_WORD word6 2744#define lpfc_reg_fcfi_mrq_type_mask2_SHIFT 16 2745#define lpfc_reg_fcfi_mrq_type_mask2_MASK 0x000000FF 2746#define lpfc_reg_fcfi_mrq_type_mask2_WORD word6 2747#define lpfc_reg_fcfi_mrq_rctl_match2_SHIFT 8 2748#define lpfc_reg_fcfi_mrq_rctl_match2_MASK 0x000000FF 2749#define lpfc_reg_fcfi_mrq_rctl_match2_WORD word6 2750#define lpfc_reg_fcfi_mrq_rctl_mask2_SHIFT 0 2751#define lpfc_reg_fcfi_mrq_rctl_mask2_MASK 0x000000FF 2752#define lpfc_reg_fcfi_mrq_rctl_mask2_WORD word6 2753 uint32_t word7; 2754#define lpfc_reg_fcfi_mrq_type_match3_SHIFT 24 2755#define lpfc_reg_fcfi_mrq_type_match3_MASK 0x000000FF 2756#define lpfc_reg_fcfi_mrq_type_match3_WORD word7 2757#define lpfc_reg_fcfi_mrq_type_mask3_SHIFT 16 2758#define lpfc_reg_fcfi_mrq_type_mask3_MASK 0x000000FF 2759#define lpfc_reg_fcfi_mrq_type_mask3_WORD word7 2760#define lpfc_reg_fcfi_mrq_rctl_match3_SHIFT 8 2761#define lpfc_reg_fcfi_mrq_rctl_match3_MASK 0x000000FF 2762#define lpfc_reg_fcfi_mrq_rctl_match3_WORD word7 2763#define lpfc_reg_fcfi_mrq_rctl_mask3_SHIFT 0 2764#define lpfc_reg_fcfi_mrq_rctl_mask3_MASK 0x000000FF 2765#define lpfc_reg_fcfi_mrq_rctl_mask3_WORD word7 2766 uint32_t word8; 2767#define lpfc_reg_fcfi_mrq_ptc7_SHIFT 31 2768#define lpfc_reg_fcfi_mrq_ptc7_MASK 0x00000001 2769#define lpfc_reg_fcfi_mrq_ptc7_WORD word8 2770#define lpfc_reg_fcfi_mrq_ptc6_SHIFT 30 2771#define lpfc_reg_fcfi_mrq_ptc6_MASK 0x00000001 2772#define lpfc_reg_fcfi_mrq_ptc6_WORD word8 2773#define lpfc_reg_fcfi_mrq_ptc5_SHIFT 29 2774#define lpfc_reg_fcfi_mrq_ptc5_MASK 0x00000001 2775#define lpfc_reg_fcfi_mrq_ptc5_WORD word8 2776#define lpfc_reg_fcfi_mrq_ptc4_SHIFT 28 2777#define lpfc_reg_fcfi_mrq_ptc4_MASK 0x00000001 2778#define lpfc_reg_fcfi_mrq_ptc4_WORD word8 2779#define lpfc_reg_fcfi_mrq_ptc3_SHIFT 27 2780#define lpfc_reg_fcfi_mrq_ptc3_MASK 0x00000001 2781#define lpfc_reg_fcfi_mrq_ptc3_WORD word8 2782#define lpfc_reg_fcfi_mrq_ptc2_SHIFT 26 2783#define lpfc_reg_fcfi_mrq_ptc2_MASK 0x00000001 2784#define lpfc_reg_fcfi_mrq_ptc2_WORD word8 2785#define lpfc_reg_fcfi_mrq_ptc1_SHIFT 25 2786#define lpfc_reg_fcfi_mrq_ptc1_MASK 0x00000001 2787#define lpfc_reg_fcfi_mrq_ptc1_WORD word8 2788#define lpfc_reg_fcfi_mrq_ptc0_SHIFT 24 2789#define lpfc_reg_fcfi_mrq_ptc0_MASK 0x00000001 2790#define lpfc_reg_fcfi_mrq_ptc0_WORD word8 2791#define lpfc_reg_fcfi_mrq_pt7_SHIFT 23 2792#define lpfc_reg_fcfi_mrq_pt7_MASK 0x00000001 2793#define lpfc_reg_fcfi_mrq_pt7_WORD word8 2794#define lpfc_reg_fcfi_mrq_pt6_SHIFT 22 2795#define lpfc_reg_fcfi_mrq_pt6_MASK 0x00000001 2796#define lpfc_reg_fcfi_mrq_pt6_WORD word8 2797#define lpfc_reg_fcfi_mrq_pt5_SHIFT 21 2798#define lpfc_reg_fcfi_mrq_pt5_MASK 0x00000001 2799#define lpfc_reg_fcfi_mrq_pt5_WORD word8 2800#define lpfc_reg_fcfi_mrq_pt4_SHIFT 20 2801#define lpfc_reg_fcfi_mrq_pt4_MASK 0x00000001 2802#define lpfc_reg_fcfi_mrq_pt4_WORD word8 2803#define lpfc_reg_fcfi_mrq_pt3_SHIFT 19 2804#define lpfc_reg_fcfi_mrq_pt3_MASK 0x00000001 2805#define lpfc_reg_fcfi_mrq_pt3_WORD word8 2806#define lpfc_reg_fcfi_mrq_pt2_SHIFT 18 2807#define lpfc_reg_fcfi_mrq_pt2_MASK 0x00000001 2808#define lpfc_reg_fcfi_mrq_pt2_WORD word8 2809#define lpfc_reg_fcfi_mrq_pt1_SHIFT 17 2810#define lpfc_reg_fcfi_mrq_pt1_MASK 0x00000001 2811#define lpfc_reg_fcfi_mrq_pt1_WORD word8 2812#define lpfc_reg_fcfi_mrq_pt0_SHIFT 16 2813#define lpfc_reg_fcfi_mrq_pt0_MASK 0x00000001 2814#define lpfc_reg_fcfi_mrq_pt0_WORD word8 2815#define lpfc_reg_fcfi_mrq_xmv_SHIFT 15 2816#define lpfc_reg_fcfi_mrq_xmv_MASK 0x00000001 2817#define lpfc_reg_fcfi_mrq_xmv_WORD word8 2818#define lpfc_reg_fcfi_mrq_mode_SHIFT 13 2819#define lpfc_reg_fcfi_mrq_mode_MASK 0x00000001 2820#define lpfc_reg_fcfi_mrq_mode_WORD word8 2821#define lpfc_reg_fcfi_mrq_vv_SHIFT 12 2822#define lpfc_reg_fcfi_mrq_vv_MASK 0x00000001 2823#define lpfc_reg_fcfi_mrq_vv_WORD word8 2824#define lpfc_reg_fcfi_mrq_vlan_tag_SHIFT 0 2825#define lpfc_reg_fcfi_mrq_vlan_tag_MASK 0x00000FFF 2826#define lpfc_reg_fcfi_mrq_vlan_tag_WORD word8 2827 uint32_t word9; 2828#define lpfc_reg_fcfi_mrq_policy_SHIFT 12 2829#define lpfc_reg_fcfi_mrq_policy_MASK 0x0000000F 2830#define lpfc_reg_fcfi_mrq_policy_WORD word9 2831#define lpfc_reg_fcfi_mrq_filter_SHIFT 8 2832#define lpfc_reg_fcfi_mrq_filter_MASK 0x0000000F 2833#define lpfc_reg_fcfi_mrq_filter_WORD word9 2834#define lpfc_reg_fcfi_mrq_npairs_SHIFT 0 2835#define lpfc_reg_fcfi_mrq_npairs_MASK 0x000000FF 2836#define lpfc_reg_fcfi_mrq_npairs_WORD word9 2837 uint32_t word10; 2838 uint32_t word11; 2839 uint32_t word12; 2840 uint32_t word13; 2841 uint32_t word14; 2842 uint32_t word15; 2843 uint32_t word16; 2844}; 2845 2846struct lpfc_mbx_unreg_fcfi { 2847 uint32_t word1_rsv; 2848 uint32_t word2; 2849#define lpfc_unreg_fcfi_SHIFT 0 2850#define lpfc_unreg_fcfi_MASK 0x0000FFFF 2851#define lpfc_unreg_fcfi_WORD word2 2852}; 2853 2854struct lpfc_mbx_read_rev { 2855 uint32_t word1; 2856#define lpfc_mbx_rd_rev_sli_lvl_SHIFT 16 2857#define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F 2858#define lpfc_mbx_rd_rev_sli_lvl_WORD word1 2859#define lpfc_mbx_rd_rev_fcoe_SHIFT 20 2860#define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001 2861#define lpfc_mbx_rd_rev_fcoe_WORD word1 2862#define lpfc_mbx_rd_rev_cee_ver_SHIFT 21 2863#define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003 2864#define lpfc_mbx_rd_rev_cee_ver_WORD word1 2865#define LPFC_PREDCBX_CEE_MODE 0 2866#define LPFC_DCBX_CEE_MODE 1 2867#define lpfc_mbx_rd_rev_vpd_SHIFT 29 2868#define lpfc_mbx_rd_rev_vpd_MASK 0x00000001 2869#define lpfc_mbx_rd_rev_vpd_WORD word1 2870 uint32_t first_hw_rev; 2871#define LPFC_G7_ASIC_1 0xd 2872 uint32_t second_hw_rev; 2873 uint32_t word4_rsvd; 2874 uint32_t third_hw_rev; 2875 uint32_t word6; 2876#define lpfc_mbx_rd_rev_fcph_low_SHIFT 0 2877#define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF 2878#define lpfc_mbx_rd_rev_fcph_low_WORD word6 2879#define lpfc_mbx_rd_rev_fcph_high_SHIFT 8 2880#define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF 2881#define lpfc_mbx_rd_rev_fcph_high_WORD word6 2882#define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT 16 2883#define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF 2884#define lpfc_mbx_rd_rev_ftr_lvl_low_WORD word6 2885#define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT 24 2886#define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF 2887#define lpfc_mbx_rd_rev_ftr_lvl_high_WORD word6 2888 uint32_t word7_rsvd; 2889 uint32_t fw_id_rev; 2890 uint8_t fw_name[16]; 2891 uint32_t ulp_fw_id_rev; 2892 uint8_t ulp_fw_name[16]; 2893 uint32_t word18_47_rsvd[30]; 2894 uint32_t word48; 2895#define lpfc_mbx_rd_rev_avail_len_SHIFT 0 2896#define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF 2897#define lpfc_mbx_rd_rev_avail_len_WORD word48 2898 uint32_t vpd_paddr_low; 2899 uint32_t vpd_paddr_high; 2900 uint32_t avail_vpd_len; 2901 uint32_t rsvd_52_63[12]; 2902}; 2903 2904struct lpfc_mbx_read_config { 2905 uint32_t word1; 2906#define lpfc_mbx_rd_conf_extnts_inuse_SHIFT 31 2907#define lpfc_mbx_rd_conf_extnts_inuse_MASK 0x00000001 2908#define lpfc_mbx_rd_conf_extnts_inuse_WORD word1 2909#define lpfc_mbx_rd_conf_fawwpn_SHIFT 30 2910#define lpfc_mbx_rd_conf_fawwpn_MASK 0x00000001 2911#define lpfc_mbx_rd_conf_fawwpn_WORD word1 2912#define lpfc_mbx_rd_conf_wcs_SHIFT 28 /* warning signaling */ 2913#define lpfc_mbx_rd_conf_wcs_MASK 0x00000001 2914#define lpfc_mbx_rd_conf_wcs_WORD word1 2915#define lpfc_mbx_rd_conf_acs_SHIFT 27 /* alarm signaling */ 2916#define lpfc_mbx_rd_conf_acs_MASK 0x00000001 2917#define lpfc_mbx_rd_conf_acs_WORD word1 2918 uint32_t word2; 2919#define lpfc_mbx_rd_conf_lnk_numb_SHIFT 0 2920#define lpfc_mbx_rd_conf_lnk_numb_MASK 0x0000003F 2921#define lpfc_mbx_rd_conf_lnk_numb_WORD word2 2922#define lpfc_mbx_rd_conf_lnk_type_SHIFT 6 2923#define lpfc_mbx_rd_conf_lnk_type_MASK 0x00000003 2924#define lpfc_mbx_rd_conf_lnk_type_WORD word2 2925#define LPFC_LNK_TYPE_GE 0 2926#define LPFC_LNK_TYPE_FC 1 2927#define lpfc_mbx_rd_conf_lnk_ldv_SHIFT 8 2928#define lpfc_mbx_rd_conf_lnk_ldv_MASK 0x00000001 2929#define lpfc_mbx_rd_conf_lnk_ldv_WORD word2 2930#define lpfc_mbx_rd_conf_trunk_SHIFT 12 2931#define lpfc_mbx_rd_conf_trunk_MASK 0x0000000F 2932#define lpfc_mbx_rd_conf_trunk_WORD word2 2933#define lpfc_mbx_rd_conf_pt_SHIFT 20 2934#define lpfc_mbx_rd_conf_pt_MASK 0x00000003 2935#define lpfc_mbx_rd_conf_pt_WORD word2 2936#define lpfc_mbx_rd_conf_tf_SHIFT 22 2937#define lpfc_mbx_rd_conf_tf_MASK 0x00000001 2938#define lpfc_mbx_rd_conf_tf_WORD word2 2939#define lpfc_mbx_rd_conf_ptv_SHIFT 23 2940#define lpfc_mbx_rd_conf_ptv_MASK 0x00000001 2941#define lpfc_mbx_rd_conf_ptv_WORD word2 2942#define lpfc_mbx_rd_conf_topology_SHIFT 24 2943#define lpfc_mbx_rd_conf_topology_MASK 0x000000FF 2944#define lpfc_mbx_rd_conf_topology_WORD word2 2945 uint32_t rsvd_3; 2946 uint32_t word4; 2947#define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0 2948#define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF 2949#define lpfc_mbx_rd_conf_e_d_tov_WORD word4 2950 uint32_t rsvd_5; 2951 uint32_t word6; 2952#define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0 2953#define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF 2954#define lpfc_mbx_rd_conf_r_a_tov_WORD word6 2955#define lpfc_mbx_rd_conf_link_speed_SHIFT 16 2956#define lpfc_mbx_rd_conf_link_speed_MASK 0x0000FFFF 2957#define lpfc_mbx_rd_conf_link_speed_WORD word6 2958 uint32_t rsvd_7; 2959 uint32_t word8; 2960#define lpfc_mbx_rd_conf_bbscn_min_SHIFT 0 2961#define lpfc_mbx_rd_conf_bbscn_min_MASK 0x0000000F 2962#define lpfc_mbx_rd_conf_bbscn_min_WORD word8 2963#define lpfc_mbx_rd_conf_bbscn_max_SHIFT 4 2964#define lpfc_mbx_rd_conf_bbscn_max_MASK 0x0000000F 2965#define lpfc_mbx_rd_conf_bbscn_max_WORD word8 2966#define lpfc_mbx_rd_conf_bbscn_def_SHIFT 8 2967#define lpfc_mbx_rd_conf_bbscn_def_MASK 0x0000000F 2968#define lpfc_mbx_rd_conf_bbscn_def_WORD word8 2969 uint32_t word9; 2970#define lpfc_mbx_rd_conf_lmt_SHIFT 0 2971#define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF 2972#define lpfc_mbx_rd_conf_lmt_WORD word9 2973 uint32_t rsvd_10; 2974 uint32_t rsvd_11; 2975 uint32_t word12; 2976#define lpfc_mbx_rd_conf_xri_base_SHIFT 0 2977#define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF 2978#define lpfc_mbx_rd_conf_xri_base_WORD word12 2979#define lpfc_mbx_rd_conf_xri_count_SHIFT 16 2980#define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF 2981#define lpfc_mbx_rd_conf_xri_count_WORD word12 2982 uint32_t word13; 2983#define lpfc_mbx_rd_conf_rpi_base_SHIFT 0 2984#define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF 2985#define lpfc_mbx_rd_conf_rpi_base_WORD word13 2986#define lpfc_mbx_rd_conf_rpi_count_SHIFT 16 2987#define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF 2988#define lpfc_mbx_rd_conf_rpi_count_WORD word13 2989 uint32_t word14; 2990#define lpfc_mbx_rd_conf_vpi_base_SHIFT 0 2991#define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF 2992#define lpfc_mbx_rd_conf_vpi_base_WORD word14 2993#define lpfc_mbx_rd_conf_vpi_count_SHIFT 16 2994#define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF 2995#define lpfc_mbx_rd_conf_vpi_count_WORD word14 2996 uint32_t word15; 2997#define lpfc_mbx_rd_conf_vfi_base_SHIFT 0 2998#define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF 2999#define lpfc_mbx_rd_conf_vfi_base_WORD word15 3000#define lpfc_mbx_rd_conf_vfi_count_SHIFT 16 3001#define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF 3002#define lpfc_mbx_rd_conf_vfi_count_WORD word15 3003 uint32_t word16; 3004#define lpfc_mbx_rd_conf_fcfi_count_SHIFT 16 3005#define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF 3006#define lpfc_mbx_rd_conf_fcfi_count_WORD word16 3007 uint32_t word17; 3008#define lpfc_mbx_rd_conf_rq_count_SHIFT 0 3009#define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF 3010#define lpfc_mbx_rd_conf_rq_count_WORD word17 3011#define lpfc_mbx_rd_conf_eq_count_SHIFT 16 3012#define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF 3013#define lpfc_mbx_rd_conf_eq_count_WORD word17 3014 uint32_t word18; 3015#define lpfc_mbx_rd_conf_wq_count_SHIFT 0 3016#define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF 3017#define lpfc_mbx_rd_conf_wq_count_WORD word18 3018#define lpfc_mbx_rd_conf_cq_count_SHIFT 16 3019#define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF 3020#define lpfc_mbx_rd_conf_cq_count_WORD word18 3021}; 3022 3023struct lpfc_mbx_request_features { 3024 uint32_t word1; 3025#define lpfc_mbx_rq_ftr_qry_SHIFT 0 3026#define lpfc_mbx_rq_ftr_qry_MASK 0x00000001 3027#define lpfc_mbx_rq_ftr_qry_WORD word1 3028 uint32_t word2; 3029#define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0 3030#define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001 3031#define lpfc_mbx_rq_ftr_rq_iaab_WORD word2 3032#define lpfc_mbx_rq_ftr_rq_npiv_SHIFT 1 3033#define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001 3034#define lpfc_mbx_rq_ftr_rq_npiv_WORD word2 3035#define lpfc_mbx_rq_ftr_rq_dif_SHIFT 2 3036#define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001 3037#define lpfc_mbx_rq_ftr_rq_dif_WORD word2 3038#define lpfc_mbx_rq_ftr_rq_vf_SHIFT 3 3039#define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001 3040#define lpfc_mbx_rq_ftr_rq_vf_WORD word2 3041#define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT 4 3042#define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001 3043#define lpfc_mbx_rq_ftr_rq_fcpi_WORD word2 3044#define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT 5 3045#define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001 3046#define lpfc_mbx_rq_ftr_rq_fcpt_WORD word2 3047#define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT 6 3048#define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001 3049#define lpfc_mbx_rq_ftr_rq_fcpc_WORD word2 3050#define lpfc_mbx_rq_ftr_rq_ifip_SHIFT 7 3051#define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001 3052#define lpfc_mbx_rq_ftr_rq_ifip_WORD word2 3053#define lpfc_mbx_rq_ftr_rq_iaar_SHIFT 9 3054#define lpfc_mbx_rq_ftr_rq_iaar_MASK 0x00000001 3055#define lpfc_mbx_rq_ftr_rq_iaar_WORD word2 3056#define lpfc_mbx_rq_ftr_rq_perfh_SHIFT 11 3057#define lpfc_mbx_rq_ftr_rq_perfh_MASK 0x00000001 3058#define lpfc_mbx_rq_ftr_rq_perfh_WORD word2 3059#define lpfc_mbx_rq_ftr_rq_mrqp_SHIFT 16 3060#define lpfc_mbx_rq_ftr_rq_mrqp_MASK 0x00000001 3061#define lpfc_mbx_rq_ftr_rq_mrqp_WORD word2 3062#define lpfc_mbx_rq_ftr_rq_ashdr_SHIFT 17 3063#define lpfc_mbx_rq_ftr_rq_ashdr_MASK 0x00000001 3064#define lpfc_mbx_rq_ftr_rq_ashdr_WORD word2 3065 uint32_t word3; 3066#define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0 3067#define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001 3068#define lpfc_mbx_rq_ftr_rsp_iaab_WORD word3 3069#define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT 1 3070#define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001 3071#define lpfc_mbx_rq_ftr_rsp_npiv_WORD word3 3072#define lpfc_mbx_rq_ftr_rsp_dif_SHIFT 2 3073#define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001 3074#define lpfc_mbx_rq_ftr_rsp_dif_WORD word3 3075#define lpfc_mbx_rq_ftr_rsp_vf_SHIFT 3 3076#define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001 3077#define lpfc_mbx_rq_ftr_rsp_vf_WORD word3 3078#define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT 4 3079#define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001 3080#define lpfc_mbx_rq_ftr_rsp_fcpi_WORD word3 3081#define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT 5 3082#define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001 3083#define lpfc_mbx_rq_ftr_rsp_fcpt_WORD word3 3084#define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT 6 3085#define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001 3086#define lpfc_mbx_rq_ftr_rsp_fcpc_WORD word3 3087#define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT 7 3088#define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001 3089#define lpfc_mbx_rq_ftr_rsp_ifip_WORD word3 3090#define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT 11 3091#define lpfc_mbx_rq_ftr_rsp_perfh_MASK 0x00000001 3092#define lpfc_mbx_rq_ftr_rsp_perfh_WORD word3 3093#define lpfc_mbx_rq_ftr_rsp_mrqp_SHIFT 16 3094#define lpfc_mbx_rq_ftr_rsp_mrqp_MASK 0x00000001 3095#define lpfc_mbx_rq_ftr_rsp_mrqp_WORD word3 3096#define lpfc_mbx_rq_ftr_rsp_ashdr_SHIFT 17 3097#define lpfc_mbx_rq_ftr_rsp_ashdr_MASK 0x00000001 3098#define lpfc_mbx_rq_ftr_rsp_ashdr_WORD word3 3099}; 3100 3101struct lpfc_mbx_memory_dump_type3 { 3102 uint32_t word1; 3103#define lpfc_mbx_memory_dump_type3_type_SHIFT 0 3104#define lpfc_mbx_memory_dump_type3_type_MASK 0x0000000f 3105#define lpfc_mbx_memory_dump_type3_type_WORD word1 3106#define lpfc_mbx_memory_dump_type3_link_SHIFT 24 3107#define lpfc_mbx_memory_dump_type3_link_MASK 0x000000ff 3108#define lpfc_mbx_memory_dump_type3_link_WORD word1 3109 uint32_t word2; 3110#define lpfc_mbx_memory_dump_type3_page_no_SHIFT 0 3111#define lpfc_mbx_memory_dump_type3_page_no_MASK 0x0000ffff 3112#define lpfc_mbx_memory_dump_type3_page_no_WORD word2 3113#define lpfc_mbx_memory_dump_type3_offset_SHIFT 16 3114#define lpfc_mbx_memory_dump_type3_offset_MASK 0x0000ffff 3115#define lpfc_mbx_memory_dump_type3_offset_WORD word2 3116 uint32_t word3; 3117#define lpfc_mbx_memory_dump_type3_length_SHIFT 0 3118#define lpfc_mbx_memory_dump_type3_length_MASK 0x00ffffff 3119#define lpfc_mbx_memory_dump_type3_length_WORD word3 3120 uint32_t addr_lo; 3121 uint32_t addr_hi; 3122 uint32_t return_len; 3123}; 3124 3125#define DMP_PAGE_A0 0xa0 3126#define DMP_PAGE_A2 0xa2 3127#define DMP_SFF_PAGE_A0_SIZE 256 3128#define DMP_SFF_PAGE_A2_SIZE 256 3129 3130#define SFP_WAVELENGTH_LC1310 1310 3131#define SFP_WAVELENGTH_LL1550 1550 3132 3133 3134/* 3135 * * SFF-8472 TABLE 3.4 3136 * */ 3137#define SFF_PG0_CONNECTOR_UNKNOWN 0x00 /* Unknown */ 3138#define SFF_PG0_CONNECTOR_SC 0x01 /* SC */ 3139#define SFF_PG0_CONNECTOR_FC_COPPER1 0x02 /* FC style 1 copper connector */ 3140#define SFF_PG0_CONNECTOR_FC_COPPER2 0x03 /* FC style 2 copper connector */ 3141#define SFF_PG0_CONNECTOR_BNC 0x04 /* BNC / TNC */ 3142#define SFF_PG0_CONNECTOR__FC_COAX 0x05 /* FC coaxial headers */ 3143#define SFF_PG0_CONNECTOR_FIBERJACK 0x06 /* FiberJack */ 3144#define SFF_PG0_CONNECTOR_LC 0x07 /* LC */ 3145#define SFF_PG0_CONNECTOR_MT 0x08 /* MT - RJ */ 3146#define SFF_PG0_CONNECTOR_MU 0x09 /* MU */ 3147#define SFF_PG0_CONNECTOR_SF 0x0A /* SG */ 3148#define SFF_PG0_CONNECTOR_OPTICAL_PIGTAIL 0x0B /* Optical pigtail */ 3149#define SFF_PG0_CONNECTOR_OPTICAL_PARALLEL 0x0C /* MPO Parallel Optic */ 3150#define SFF_PG0_CONNECTOR_HSSDC_II 0x20 /* HSSDC II */ 3151#define SFF_PG0_CONNECTOR_COPPER_PIGTAIL 0x21 /* Copper pigtail */ 3152#define SFF_PG0_CONNECTOR_RJ45 0x22 /* RJ45 */ 3153 3154/* SFF-8472 Table 3.1 Diagnostics: Data Fields Address/Page A0 */ 3155 3156#define SSF_IDENTIFIER 0 3157#define SSF_EXT_IDENTIFIER 1 3158#define SSF_CONNECTOR 2 3159#define SSF_TRANSCEIVER_CODE_B0 3 3160#define SSF_TRANSCEIVER_CODE_B1 4 3161#define SSF_TRANSCEIVER_CODE_B2 5 3162#define SSF_TRANSCEIVER_CODE_B3 6 3163#define SSF_TRANSCEIVER_CODE_B4 7 3164#define SSF_TRANSCEIVER_CODE_B5 8 3165#define SSF_TRANSCEIVER_CODE_B6 9 3166#define SSF_TRANSCEIVER_CODE_B7 10 3167#define SSF_ENCODING 11 3168#define SSF_BR_NOMINAL 12 3169#define SSF_RATE_IDENTIFIER 13 3170#define SSF_LENGTH_9UM_KM 14 3171#define SSF_LENGTH_9UM 15 3172#define SSF_LENGTH_50UM_OM2 16 3173#define SSF_LENGTH_62UM_OM1 17 3174#define SFF_LENGTH_COPPER 18 3175#define SSF_LENGTH_50UM_OM3 19 3176#define SSF_VENDOR_NAME 20 3177#define SSF_TRANSCEIVER2 36 3178#define SSF_VENDOR_OUI 37 3179#define SSF_VENDOR_PN 40 3180#define SSF_VENDOR_REV 56 3181#define SSF_WAVELENGTH_B1 60 3182#define SSF_WAVELENGTH_B0 61 3183#define SSF_CC_BASE 63 3184#define SSF_OPTIONS_B1 64 3185#define SSF_OPTIONS_B0 65 3186#define SSF_BR_MAX 66 3187#define SSF_BR_MIN 67 3188#define SSF_VENDOR_SN 68 3189#define SSF_DATE_CODE 84 3190#define SSF_MONITORING_TYPEDIAGNOSTIC 92 3191#define SSF_ENHANCED_OPTIONS 93 3192#define SFF_8472_COMPLIANCE 94 3193#define SSF_CC_EXT 95 3194#define SSF_A0_VENDOR_SPECIFIC 96 3195 3196/* SFF-8472 Table 3.1a Diagnostics: Data Fields Address/Page A2 */ 3197 3198#define SSF_TEMP_HIGH_ALARM 0 3199#define SSF_TEMP_LOW_ALARM 2 3200#define SSF_TEMP_HIGH_WARNING 4 3201#define SSF_TEMP_LOW_WARNING 6 3202#define SSF_VOLTAGE_HIGH_ALARM 8 3203#define SSF_VOLTAGE_LOW_ALARM 10 3204#define SSF_VOLTAGE_HIGH_WARNING 12 3205#define SSF_VOLTAGE_LOW_WARNING 14 3206#define SSF_BIAS_HIGH_ALARM 16 3207#define SSF_BIAS_LOW_ALARM 18 3208#define SSF_BIAS_HIGH_WARNING 20 3209#define SSF_BIAS_LOW_WARNING 22 3210#define SSF_TXPOWER_HIGH_ALARM 24 3211#define SSF_TXPOWER_LOW_ALARM 26 3212#define SSF_TXPOWER_HIGH_WARNING 28 3213#define SSF_TXPOWER_LOW_WARNING 30 3214#define SSF_RXPOWER_HIGH_ALARM 32 3215#define SSF_RXPOWER_LOW_ALARM 34 3216#define SSF_RXPOWER_HIGH_WARNING 36 3217#define SSF_RXPOWER_LOW_WARNING 38 3218#define SSF_EXT_CAL_CONSTANTS 56 3219#define SSF_CC_DMI 95 3220#define SFF_TEMPERATURE_B1 96 3221#define SFF_TEMPERATURE_B0 97 3222#define SFF_VCC_B1 98 3223#define SFF_VCC_B0 99 3224#define SFF_TX_BIAS_CURRENT_B1 100 3225#define SFF_TX_BIAS_CURRENT_B0 101 3226#define SFF_TXPOWER_B1 102 3227#define SFF_TXPOWER_B0 103 3228#define SFF_RXPOWER_B1 104 3229#define SFF_RXPOWER_B0 105 3230#define SSF_STATUS_CONTROL 110 3231#define SSF_ALARM_FLAGS 112 3232#define SSF_WARNING_FLAGS 116 3233#define SSF_EXT_TATUS_CONTROL_B1 118 3234#define SSF_EXT_TATUS_CONTROL_B0 119 3235#define SSF_A2_VENDOR_SPECIFIC 120 3236#define SSF_USER_EEPROM 128 3237#define SSF_VENDOR_CONTROL 148 3238 3239 3240/* 3241 * Tranceiver codes Fibre Channel SFF-8472 3242 * Table 3.5. 3243 */ 3244 3245struct sff_trasnceiver_codes_byte0 { 3246 uint8_t inifiband:4; 3247 uint8_t teng_ethernet:4; 3248}; 3249 3250struct sff_trasnceiver_codes_byte1 { 3251 uint8_t sonet:6; 3252 uint8_t escon:2; 3253}; 3254 3255struct sff_trasnceiver_codes_byte2 { 3256 uint8_t soNet:8; 3257}; 3258 3259struct sff_trasnceiver_codes_byte3 { 3260 uint8_t ethernet:8; 3261}; 3262 3263struct sff_trasnceiver_codes_byte4 { 3264 uint8_t fc_el_lo:1; 3265 uint8_t fc_lw_laser:1; 3266 uint8_t fc_sw_laser:1; 3267 uint8_t fc_md_distance:1; 3268 uint8_t fc_lg_distance:1; 3269 uint8_t fc_int_distance:1; 3270 uint8_t fc_short_distance:1; 3271 uint8_t fc_vld_distance:1; 3272}; 3273 3274struct sff_trasnceiver_codes_byte5 { 3275 uint8_t reserved1:1; 3276 uint8_t reserved2:1; 3277 uint8_t fc_sfp_active:1; /* Active cable */ 3278 uint8_t fc_sfp_passive:1; /* Passive cable */ 3279 uint8_t fc_lw_laser:1; /* Longwave laser */ 3280 uint8_t fc_sw_laser_sl:1; 3281 uint8_t fc_sw_laser_sn:1; 3282 uint8_t fc_el_hi:1; /* Electrical enclosure high bit */ 3283}; 3284 3285struct sff_trasnceiver_codes_byte6 { 3286 uint8_t fc_tm_sm:1; /* Single Mode */ 3287 uint8_t reserved:1; 3288 uint8_t fc_tm_m6:1; /* Multimode, 62.5um (M6) */ 3289 uint8_t fc_tm_tv:1; /* Video Coax (TV) */ 3290 uint8_t fc_tm_mi:1; /* Miniature Coax (MI) */ 3291 uint8_t fc_tm_tp:1; /* Twisted Pair (TP) */ 3292 uint8_t fc_tm_tw:1; /* Twin Axial Pair */ 3293}; 3294 3295struct sff_trasnceiver_codes_byte7 { 3296 uint8_t fc_sp_100MB:1; /* 100 MB/sec */ 3297 uint8_t speed_chk_ecc:1; 3298 uint8_t fc_sp_200mb:1; /* 200 MB/sec */ 3299 uint8_t fc_sp_3200MB:1; /* 3200 MB/sec */ 3300 uint8_t fc_sp_400MB:1; /* 400 MB/sec */ 3301 uint8_t fc_sp_1600MB:1; /* 1600 MB/sec */ 3302 uint8_t fc_sp_800MB:1; /* 800 MB/sec */ 3303 uint8_t fc_sp_1200MB:1; /* 1200 MB/sec */ 3304}; 3305 3306/* User writable non-volatile memory, SFF-8472 Table 3.20 */ 3307struct user_eeprom { 3308 uint8_t vendor_name[16]; 3309 uint8_t vendor_oui[3]; 3310 uint8_t vendor_pn[816]; 3311 uint8_t vendor_rev[4]; 3312 uint8_t vendor_sn[16]; 3313 uint8_t datecode[6]; 3314 uint8_t lot_code[2]; 3315 uint8_t reserved191[57]; 3316}; 3317 3318#define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \ 3319 &(~((SLI4_PAGE_SIZE)-1))) 3320 3321struct lpfc_sli4_parameters { 3322 uint32_t word0; 3323#define cfg_prot_type_SHIFT 0 3324#define cfg_prot_type_MASK 0x000000FF 3325#define cfg_prot_type_WORD word0 3326 uint32_t word1; 3327#define cfg_ft_SHIFT 0 3328#define cfg_ft_MASK 0x00000001 3329#define cfg_ft_WORD word1 3330#define cfg_sli_rev_SHIFT 4 3331#define cfg_sli_rev_MASK 0x0000000f 3332#define cfg_sli_rev_WORD word1 3333#define cfg_sli_family_SHIFT 8 3334#define cfg_sli_family_MASK 0x0000000f 3335#define cfg_sli_family_WORD word1 3336#define cfg_if_type_SHIFT 12 3337#define cfg_if_type_MASK 0x0000000f 3338#define cfg_if_type_WORD word1 3339#define cfg_sli_hint_1_SHIFT 16 3340#define cfg_sli_hint_1_MASK 0x000000ff 3341#define cfg_sli_hint_1_WORD word1 3342#define cfg_sli_hint_2_SHIFT 24 3343#define cfg_sli_hint_2_MASK 0x0000001f 3344#define cfg_sli_hint_2_WORD word1 3345 uint32_t word2; 3346#define cfg_eqav_SHIFT 31 3347#define cfg_eqav_MASK 0x00000001 3348#define cfg_eqav_WORD word2 3349 uint32_t word3; 3350 uint32_t word4; 3351#define cfg_cqv_SHIFT 14 3352#define cfg_cqv_MASK 0x00000003 3353#define cfg_cqv_WORD word4 3354#define cfg_cqpsize_SHIFT 16 3355#define cfg_cqpsize_MASK 0x000000ff 3356#define cfg_cqpsize_WORD word4 3357#define cfg_cqav_SHIFT 31 3358#define cfg_cqav_MASK 0x00000001 3359#define cfg_cqav_WORD word4 3360 uint32_t word5; 3361 uint32_t word6; 3362#define cfg_mqv_SHIFT 14 3363#define cfg_mqv_MASK 0x00000003 3364#define cfg_mqv_WORD word6 3365 uint32_t word7; 3366 uint32_t word8; 3367#define cfg_wqpcnt_SHIFT 0 3368#define cfg_wqpcnt_MASK 0x0000000f 3369#define cfg_wqpcnt_WORD word8 3370#define cfg_wqsize_SHIFT 8 3371#define cfg_wqsize_MASK 0x0000000f 3372#define cfg_wqsize_WORD word8 3373#define cfg_wqv_SHIFT 14 3374#define cfg_wqv_MASK 0x00000003 3375#define cfg_wqv_WORD word8 3376#define cfg_wqpsize_SHIFT 16 3377#define cfg_wqpsize_MASK 0x000000ff 3378#define cfg_wqpsize_WORD word8 3379 uint32_t word9; 3380 uint32_t word10; 3381#define cfg_rqv_SHIFT 14 3382#define cfg_rqv_MASK 0x00000003 3383#define cfg_rqv_WORD word10 3384 uint32_t word11; 3385#define cfg_rq_db_window_SHIFT 28 3386#define cfg_rq_db_window_MASK 0x0000000f 3387#define cfg_rq_db_window_WORD word11 3388 uint32_t word12; 3389#define cfg_fcoe_SHIFT 0 3390#define cfg_fcoe_MASK 0x00000001 3391#define cfg_fcoe_WORD word12 3392#define cfg_ext_SHIFT 1 3393#define cfg_ext_MASK 0x00000001 3394#define cfg_ext_WORD word12 3395#define cfg_hdrr_SHIFT 2 3396#define cfg_hdrr_MASK 0x00000001 3397#define cfg_hdrr_WORD word12 3398#define cfg_phwq_SHIFT 15 3399#define cfg_phwq_MASK 0x00000001 3400#define cfg_phwq_WORD word12 3401#define cfg_oas_SHIFT 25 3402#define cfg_oas_MASK 0x00000001 3403#define cfg_oas_WORD word12 3404#define cfg_loopbk_scope_SHIFT 28 3405#define cfg_loopbk_scope_MASK 0x0000000f 3406#define cfg_loopbk_scope_WORD word12 3407 uint32_t sge_supp_len; 3408 uint32_t word14; 3409#define cfg_sgl_page_cnt_SHIFT 0 3410#define cfg_sgl_page_cnt_MASK 0x0000000f 3411#define cfg_sgl_page_cnt_WORD word14 3412#define cfg_sgl_page_size_SHIFT 8 3413#define cfg_sgl_page_size_MASK 0x000000ff 3414#define cfg_sgl_page_size_WORD word14 3415#define cfg_sgl_pp_align_SHIFT 16 3416#define cfg_sgl_pp_align_MASK 0x000000ff 3417#define cfg_sgl_pp_align_WORD word14 3418 uint32_t word15; 3419 uint32_t word16; 3420 uint32_t word17; 3421 uint32_t word18; 3422 uint32_t word19; 3423#define cfg_ext_embed_cb_SHIFT 0 3424#define cfg_ext_embed_cb_MASK 0x00000001 3425#define cfg_ext_embed_cb_WORD word19 3426#define cfg_mds_diags_SHIFT 1 3427#define cfg_mds_diags_MASK 0x00000001 3428#define cfg_mds_diags_WORD word19 3429#define cfg_nvme_SHIFT 3 3430#define cfg_nvme_MASK 0x00000001 3431#define cfg_nvme_WORD word19 3432#define cfg_xib_SHIFT 4 3433#define cfg_xib_MASK 0x00000001 3434#define cfg_xib_WORD word19 3435#define cfg_xpsgl_SHIFT 6 3436#define cfg_xpsgl_MASK 0x00000001 3437#define cfg_xpsgl_WORD word19 3438#define cfg_eqdr_SHIFT 8 3439#define cfg_eqdr_MASK 0x00000001 3440#define cfg_eqdr_WORD word19 3441#define cfg_nosr_SHIFT 9 3442#define cfg_nosr_MASK 0x00000001 3443#define cfg_nosr_WORD word19 3444#define cfg_bv1s_SHIFT 10 3445#define cfg_bv1s_MASK 0x00000001 3446#define cfg_bv1s_WORD word19 3447 3448#define cfg_nsler_SHIFT 12 3449#define cfg_nsler_MASK 0x00000001 3450#define cfg_nsler_WORD word19 3451#define cfg_pvl_SHIFT 13 3452#define cfg_pvl_MASK 0x00000001 3453#define cfg_pvl_WORD word19 3454 3455#define cfg_pbde_SHIFT 20 3456#define cfg_pbde_MASK 0x00000001 3457#define cfg_pbde_WORD word19 3458 3459 uint32_t word20; 3460#define cfg_max_tow_xri_SHIFT 0 3461#define cfg_max_tow_xri_MASK 0x0000ffff 3462#define cfg_max_tow_xri_WORD word20 3463 3464 uint32_t word21; 3465#define cfg_mi_ver_SHIFT 0 3466#define cfg_mi_ver_MASK 0x0000ffff 3467#define cfg_mi_ver_WORD word21 3468#define cfg_cmf_SHIFT 24 3469#define cfg_cmf_MASK 0x000000ff 3470#define cfg_cmf_WORD word21 3471 3472 uint32_t mib_size; 3473 uint32_t word23; /* RESERVED */ 3474 3475 uint32_t word24; 3476#define cfg_frag_field_offset_SHIFT 0 3477#define cfg_frag_field_offset_MASK 0x0000ffff 3478#define cfg_frag_field_offset_WORD word24 3479 3480#define cfg_frag_field_size_SHIFT 16 3481#define cfg_frag_field_size_MASK 0x0000ffff 3482#define cfg_frag_field_size_WORD word24 3483 3484 uint32_t word25; 3485#define cfg_sgl_field_offset_SHIFT 0 3486#define cfg_sgl_field_offset_MASK 0x0000ffff 3487#define cfg_sgl_field_offset_WORD word25 3488 3489#define cfg_sgl_field_size_SHIFT 16 3490#define cfg_sgl_field_size_MASK 0x0000ffff 3491#define cfg_sgl_field_size_WORD word25 3492 3493 uint32_t word26; /* Chain SGE initial value LOW */ 3494 uint32_t word27; /* Chain SGE initial value HIGH */ 3495#define LPFC_NODELAY_MAX_IO 32 3496}; 3497 3498#define LPFC_SET_UE_RECOVERY 0x10 3499#define LPFC_SET_MDS_DIAGS 0x12 3500#define LPFC_SET_DUAL_DUMP 0x1e 3501#define LPFC_SET_CGN_SIGNAL 0x1f 3502#define LPFC_SET_ENABLE_MI 0x21 3503#define LPFC_SET_LD_SIGNAL 0x23 3504#define LPFC_SET_ENABLE_CMF 0x24 3505struct lpfc_mbx_set_feature { 3506 struct mbox_header header; 3507 uint32_t feature; 3508 uint32_t param_len; 3509 uint32_t word6; 3510#define lpfc_mbx_set_feature_UER_SHIFT 0 3511#define lpfc_mbx_set_feature_UER_MASK 0x00000001 3512#define lpfc_mbx_set_feature_UER_WORD word6 3513#define lpfc_mbx_set_feature_mds_SHIFT 2 3514#define lpfc_mbx_set_feature_mds_MASK 0x00000001 3515#define lpfc_mbx_set_feature_mds_WORD word6 3516#define lpfc_mbx_set_feature_mds_deep_loopbk_SHIFT 1 3517#define lpfc_mbx_set_feature_mds_deep_loopbk_MASK 0x00000001 3518#define lpfc_mbx_set_feature_mds_deep_loopbk_WORD word6 3519#define lpfc_mbx_set_feature_CGN_warn_freq_SHIFT 0 3520#define lpfc_mbx_set_feature_CGN_warn_freq_MASK 0x0000ffff 3521#define lpfc_mbx_set_feature_CGN_warn_freq_WORD word6 3522#define lpfc_mbx_set_feature_dd_SHIFT 0 3523#define lpfc_mbx_set_feature_dd_MASK 0x00000001 3524#define lpfc_mbx_set_feature_dd_WORD word6 3525#define lpfc_mbx_set_feature_ddquery_SHIFT 1 3526#define lpfc_mbx_set_feature_ddquery_MASK 0x00000001 3527#define lpfc_mbx_set_feature_ddquery_WORD word6 3528#define LPFC_DISABLE_DUAL_DUMP 0 3529#define LPFC_ENABLE_DUAL_DUMP 1 3530#define LPFC_QUERY_OP_DUAL_DUMP 2 3531#define lpfc_mbx_set_feature_cmf_SHIFT 0 3532#define lpfc_mbx_set_feature_cmf_MASK 0x00000001 3533#define lpfc_mbx_set_feature_cmf_WORD word6 3534#define lpfc_mbx_set_feature_lds_qry_SHIFT 0 3535#define lpfc_mbx_set_feature_lds_qry_MASK 0x00000001 3536#define lpfc_mbx_set_feature_lds_qry_WORD word6 3537#define LPFC_QUERY_LDS_OP 1 3538#define lpfc_mbx_set_feature_mi_SHIFT 0 3539#define lpfc_mbx_set_feature_mi_MASK 0x0000ffff 3540#define lpfc_mbx_set_feature_mi_WORD word6 3541#define lpfc_mbx_set_feature_milunq_SHIFT 16 3542#define lpfc_mbx_set_feature_milunq_MASK 0x0000ffff 3543#define lpfc_mbx_set_feature_milunq_WORD word6 3544 u32 word7; 3545#define lpfc_mbx_set_feature_UERP_SHIFT 0 3546#define lpfc_mbx_set_feature_UERP_MASK 0x0000ffff 3547#define lpfc_mbx_set_feature_UERP_WORD word7 3548#define lpfc_mbx_set_feature_UESR_SHIFT 16 3549#define lpfc_mbx_set_feature_UESR_MASK 0x0000ffff 3550#define lpfc_mbx_set_feature_UESR_WORD word7 3551#define lpfc_mbx_set_feature_CGN_alarm_freq_SHIFT 0 3552#define lpfc_mbx_set_feature_CGN_alarm_freq_MASK 0x0000ffff 3553#define lpfc_mbx_set_feature_CGN_alarm_freq_WORD word7 3554 u32 word8; 3555#define lpfc_mbx_set_feature_CGN_acqe_freq_SHIFT 0 3556#define lpfc_mbx_set_feature_CGN_acqe_freq_MASK 0x000000ff 3557#define lpfc_mbx_set_feature_CGN_acqe_freq_WORD word8 3558 u32 word9; 3559 u32 word10; 3560}; 3561 3562 3563#define LPFC_SET_HOST_OS_DRIVER_VERSION 0x2 3564#define LPFC_SET_HOST_DATE_TIME 0x4 3565 3566struct lpfc_mbx_set_host_date_time { 3567 uint32_t word6; 3568#define lpfc_mbx_set_host_month_WORD word6 3569#define lpfc_mbx_set_host_month_SHIFT 16 3570#define lpfc_mbx_set_host_month_MASK 0xFF 3571#define lpfc_mbx_set_host_day_WORD word6 3572#define lpfc_mbx_set_host_day_SHIFT 8 3573#define lpfc_mbx_set_host_day_MASK 0xFF 3574#define lpfc_mbx_set_host_year_WORD word6 3575#define lpfc_mbx_set_host_year_SHIFT 0 3576#define lpfc_mbx_set_host_year_MASK 0xFF 3577 uint32_t word7; 3578#define lpfc_mbx_set_host_hour_WORD word7 3579#define lpfc_mbx_set_host_hour_SHIFT 16 3580#define lpfc_mbx_set_host_hour_MASK 0xFF 3581#define lpfc_mbx_set_host_min_WORD word7 3582#define lpfc_mbx_set_host_min_SHIFT 8 3583#define lpfc_mbx_set_host_min_MASK 0xFF 3584#define lpfc_mbx_set_host_sec_WORD word7 3585#define lpfc_mbx_set_host_sec_SHIFT 0 3586#define lpfc_mbx_set_host_sec_MASK 0xFF 3587}; 3588 3589struct lpfc_mbx_set_host_data { 3590#define LPFC_HOST_OS_DRIVER_VERSION_SIZE 48 3591 struct mbox_header header; 3592 uint32_t param_id; 3593 uint32_t param_len; 3594 union { 3595 uint8_t data[LPFC_HOST_OS_DRIVER_VERSION_SIZE]; 3596 struct lpfc_mbx_set_host_date_time tm; 3597 } un; 3598}; 3599 3600struct lpfc_mbx_set_trunk_mode { 3601 struct mbox_header header; 3602 uint32_t word0; 3603#define lpfc_mbx_set_trunk_mode_WORD word0 3604#define lpfc_mbx_set_trunk_mode_SHIFT 0 3605#define lpfc_mbx_set_trunk_mode_MASK 0xFF 3606 uint32_t word1; 3607 uint32_t word2; 3608}; 3609 3610struct lpfc_mbx_get_sli4_parameters { 3611 struct mbox_header header; 3612 struct lpfc_sli4_parameters sli4_parameters; 3613}; 3614 3615struct lpfc_mbx_reg_congestion_buf { 3616 struct mbox_header header; 3617 uint32_t word0; 3618#define lpfc_mbx_reg_cgn_buf_type_WORD word0 3619#define lpfc_mbx_reg_cgn_buf_type_SHIFT 0 3620#define lpfc_mbx_reg_cgn_buf_type_MASK 0xFF 3621#define lpfc_mbx_reg_cgn_buf_cnt_WORD word0 3622#define lpfc_mbx_reg_cgn_buf_cnt_SHIFT 16 3623#define lpfc_mbx_reg_cgn_buf_cnt_MASK 0xFF 3624 uint32_t word1; 3625 uint32_t length; 3626 uint32_t addr_lo; 3627 uint32_t addr_hi; 3628}; 3629 3630struct lpfc_rscr_desc_generic { 3631#define LPFC_RSRC_DESC_WSIZE 22 3632 uint32_t desc[LPFC_RSRC_DESC_WSIZE]; 3633}; 3634 3635struct lpfc_rsrc_desc_pcie { 3636 uint32_t word0; 3637#define lpfc_rsrc_desc_pcie_type_SHIFT 0 3638#define lpfc_rsrc_desc_pcie_type_MASK 0x000000ff 3639#define lpfc_rsrc_desc_pcie_type_WORD word0 3640#define LPFC_RSRC_DESC_TYPE_PCIE 0x40 3641#define lpfc_rsrc_desc_pcie_length_SHIFT 8 3642#define lpfc_rsrc_desc_pcie_length_MASK 0x000000ff 3643#define lpfc_rsrc_desc_pcie_length_WORD word0 3644 uint32_t word1; 3645#define lpfc_rsrc_desc_pcie_pfnum_SHIFT 0 3646#define lpfc_rsrc_desc_pcie_pfnum_MASK 0x000000ff 3647#define lpfc_rsrc_desc_pcie_pfnum_WORD word1 3648 uint32_t reserved; 3649 uint32_t word3; 3650#define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT 0 3651#define lpfc_rsrc_desc_pcie_sriov_sta_MASK 0x000000ff 3652#define lpfc_rsrc_desc_pcie_sriov_sta_WORD word3 3653#define lpfc_rsrc_desc_pcie_pf_sta_SHIFT 8 3654#define lpfc_rsrc_desc_pcie_pf_sta_MASK 0x000000ff 3655#define lpfc_rsrc_desc_pcie_pf_sta_WORD word3 3656#define lpfc_rsrc_desc_pcie_pf_type_SHIFT 16 3657#define lpfc_rsrc_desc_pcie_pf_type_MASK 0x000000ff 3658#define lpfc_rsrc_desc_pcie_pf_type_WORD word3 3659 uint32_t word4; 3660#define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT 0 3661#define lpfc_rsrc_desc_pcie_nr_virtfn_MASK 0x0000ffff 3662#define lpfc_rsrc_desc_pcie_nr_virtfn_WORD word4 3663}; 3664 3665struct lpfc_rsrc_desc_fcfcoe { 3666 uint32_t word0; 3667#define lpfc_rsrc_desc_fcfcoe_type_SHIFT 0 3668#define lpfc_rsrc_desc_fcfcoe_type_MASK 0x000000ff 3669#define lpfc_rsrc_desc_fcfcoe_type_WORD word0 3670#define LPFC_RSRC_DESC_TYPE_FCFCOE 0x43 3671#define lpfc_rsrc_desc_fcfcoe_length_SHIFT 8 3672#define lpfc_rsrc_desc_fcfcoe_length_MASK 0x000000ff 3673#define lpfc_rsrc_desc_fcfcoe_length_WORD word0 3674#define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD 0 3675#define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH 72 3676#define LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH 88 3677 uint32_t word1; 3678#define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT 0 3679#define lpfc_rsrc_desc_fcfcoe_vfnum_MASK 0x000000ff 3680#define lpfc_rsrc_desc_fcfcoe_vfnum_WORD word1 3681#define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT 16 3682#define lpfc_rsrc_desc_fcfcoe_pfnum_MASK 0x000007ff 3683#define lpfc_rsrc_desc_fcfcoe_pfnum_WORD word1 3684 uint32_t word2; 3685#define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT 0 3686#define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK 0x0000ffff 3687#define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD word2 3688#define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT 16 3689#define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK 0x0000ffff 3690#define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD word2 3691 uint32_t word3; 3692#define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT 0 3693#define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK 0x0000ffff 3694#define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD word3 3695#define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT 16 3696#define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK 0x0000ffff 3697#define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD word3 3698 uint32_t word4; 3699#define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT 0 3700#define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK 0x0000ffff 3701#define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD word4 3702#define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT 16 3703#define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK 0x0000ffff 3704#define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD word4 3705 uint32_t word5; 3706#define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT 0 3707#define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK 0x0000ffff 3708#define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD word5 3709#define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT 16 3710#define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK 0x0000ffff 3711#define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD word5 3712 uint32_t word6; 3713 uint32_t word7; 3714 uint32_t word8; 3715 uint32_t word9; 3716 uint32_t word10; 3717 uint32_t word11; 3718 uint32_t word12; 3719 uint32_t word13; 3720#define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT 0 3721#define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK 0x0000003f 3722#define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD word13 3723#define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT 6 3724#define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK 0x00000003 3725#define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD word13 3726#define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT 8 3727#define lpfc_rsrc_desc_fcfcoe_lmc_MASK 0x00000001 3728#define lpfc_rsrc_desc_fcfcoe_lmc_WORD word13 3729#define lpfc_rsrc_desc_fcfcoe_lld_SHIFT 9 3730#define lpfc_rsrc_desc_fcfcoe_lld_MASK 0x00000001 3731#define lpfc_rsrc_desc_fcfcoe_lld_WORD word13 3732#define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT 16 3733#define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK 0x0000ffff 3734#define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD word13 3735/* extended FC/FCoE Resource Descriptor when length = 88 bytes */ 3736 uint32_t bw_min; 3737 uint32_t bw_max; 3738 uint32_t iops_min; 3739 uint32_t iops_max; 3740 uint32_t reserved[4]; 3741}; 3742 3743struct lpfc_func_cfg { 3744#define LPFC_RSRC_DESC_MAX_NUM 2 3745 uint32_t rsrc_desc_count; 3746 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 3747}; 3748 3749struct lpfc_mbx_get_func_cfg { 3750 struct mbox_header header; 3751#define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 3752#define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 3753#define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 3754 struct lpfc_func_cfg func_cfg; 3755}; 3756 3757struct lpfc_prof_cfg { 3758#define LPFC_RSRC_DESC_MAX_NUM 2 3759 uint32_t rsrc_desc_count; 3760 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 3761}; 3762 3763struct lpfc_mbx_get_prof_cfg { 3764 struct mbox_header header; 3765#define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 3766#define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 3767#define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 3768 union { 3769 struct { 3770 uint32_t word10; 3771#define lpfc_mbx_get_prof_cfg_prof_id_SHIFT 0 3772#define lpfc_mbx_get_prof_cfg_prof_id_MASK 0x000000ff 3773#define lpfc_mbx_get_prof_cfg_prof_id_WORD word10 3774#define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT 8 3775#define lpfc_mbx_get_prof_cfg_prof_tp_MASK 0x00000003 3776#define lpfc_mbx_get_prof_cfg_prof_tp_WORD word10 3777 } request; 3778 struct { 3779 struct lpfc_prof_cfg prof_cfg; 3780 } response; 3781 } u; 3782}; 3783 3784struct lpfc_controller_attribute { 3785 uint32_t version_string[8]; 3786 uint32_t manufacturer_name[8]; 3787 uint32_t rsvd16; 3788 uint32_t word17; 3789#define lpfc_cntl_attr_flash_id_SHIFT 16 3790#define lpfc_cntl_attr_flash_id_MASK 0x000000ff 3791#define lpfc_cntl_attr_flash_id_WORD word17 3792#define lpfc_cntl_attr_boot_enable_SHIFT 24 3793#define lpfc_cntl_attr_boot_enable_MASK 0x00000001 3794#define lpfc_cntl_attr_boot_enable_WORD word17 3795 uint32_t rsvd18[2]; 3796 uint32_t ncsi_ver_str[3]; 3797 uint32_t rsvd23; 3798 uint32_t model_number[8]; 3799 uint32_t description[16]; 3800 uint32_t serial_number[8]; 3801 uint32_t ipl_name[5]; 3802 uint32_t rsvd61[3]; 3803 uint32_t fw_ver_str[8]; 3804 uint32_t bios_ver_str[8]; 3805 uint32_t redboot_ver_str[8]; 3806 uint32_t driver_ver_str[8]; 3807 uint32_t flash_fw_ver_str[8]; 3808 uint32_t functionality; 3809 uint32_t word105; 3810#define lpfc_cntl_attr_asic_rev_SHIFT 16 3811#define lpfc_cntl_attr_asic_rev_MASK 0x000000ff 3812#define lpfc_cntl_attr_asic_rev_WORD word105 3813 uint32_t rsvd106[3]; 3814 uint32_t word109; 3815#define lpfc_cntl_attr_hba_port_cnt_SHIFT 24 3816#define lpfc_cntl_attr_hba_port_cnt_MASK 0x000000ff 3817#define lpfc_cntl_attr_hba_port_cnt_WORD word109 3818 uint32_t rsvd110; 3819 uint32_t word111; 3820#define lpfc_cntl_attr_hba_status_SHIFT 8 3821#define lpfc_cntl_attr_hba_status_MASK 0x000000ff 3822#define lpfc_cntl_attr_hba_status_WORD word111 3823#define lpfc_cntl_attr_lnk_numb_SHIFT 24 3824#define lpfc_cntl_attr_lnk_numb_MASK 0x0000003f 3825#define lpfc_cntl_attr_lnk_numb_WORD word111 3826#define lpfc_cntl_attr_lnk_type_SHIFT 30 3827#define lpfc_cntl_attr_lnk_type_MASK 0x00000003 3828#define lpfc_cntl_attr_lnk_type_WORD word111 3829 uint32_t rsvd112[9]; 3830 uint32_t word121; 3831#define lpfc_cntl_attr_asic_gen_SHIFT 8 3832#define lpfc_cntl_attr_asic_gen_MASK 0x000000ff 3833#define lpfc_cntl_attr_asic_gen_WORD word121 3834 uint32_t rsvd122[3]; 3835 uint32_t word125; 3836#define lpfc_cntl_attr_pci_vendor_id_SHIFT 0 3837#define lpfc_cntl_attr_pci_vendor_id_MASK 0x0000ffff 3838#define lpfc_cntl_attr_pci_vendor_id_WORD word125 3839#define lpfc_cntl_attr_pci_device_id_SHIFT 16 3840#define lpfc_cntl_attr_pci_device_id_MASK 0x0000ffff 3841#define lpfc_cntl_attr_pci_device_id_WORD word125 3842 uint32_t word126; 3843#define lpfc_cntl_attr_pci_subvdr_id_SHIFT 0 3844#define lpfc_cntl_attr_pci_subvdr_id_MASK 0x0000ffff 3845#define lpfc_cntl_attr_pci_subvdr_id_WORD word126 3846#define lpfc_cntl_attr_pci_subsys_id_SHIFT 16 3847#define lpfc_cntl_attr_pci_subsys_id_MASK 0x0000ffff 3848#define lpfc_cntl_attr_pci_subsys_id_WORD word126 3849 uint32_t word127; 3850#define lpfc_cntl_attr_pci_bus_num_SHIFT 0 3851#define lpfc_cntl_attr_pci_bus_num_MASK 0x000000ff 3852#define lpfc_cntl_attr_pci_bus_num_WORD word127 3853#define lpfc_cntl_attr_pci_dev_num_SHIFT 8 3854#define lpfc_cntl_attr_pci_dev_num_MASK 0x000000ff 3855#define lpfc_cntl_attr_pci_dev_num_WORD word127 3856#define lpfc_cntl_attr_pci_fnc_num_SHIFT 16 3857#define lpfc_cntl_attr_pci_fnc_num_MASK 0x000000ff 3858#define lpfc_cntl_attr_pci_fnc_num_WORD word127 3859 uint32_t rsvd128[7]; 3860}; 3861 3862struct lpfc_mbx_get_cntl_attributes { 3863 union lpfc_sli4_cfg_shdr cfg_shdr; 3864 struct lpfc_controller_attribute cntl_attr; 3865}; 3866 3867struct lpfc_mbx_get_port_name { 3868 struct mbox_header header; 3869 union { 3870 struct { 3871 uint32_t word4; 3872#define lpfc_mbx_get_port_name_lnk_type_SHIFT 0 3873#define lpfc_mbx_get_port_name_lnk_type_MASK 0x00000003 3874#define lpfc_mbx_get_port_name_lnk_type_WORD word4 3875 } request; 3876 struct { 3877 uint32_t word4; 3878#define lpfc_mbx_get_port_name_name0_SHIFT 0 3879#define lpfc_mbx_get_port_name_name0_MASK 0x000000FF 3880#define lpfc_mbx_get_port_name_name0_WORD word4 3881#define lpfc_mbx_get_port_name_name1_SHIFT 8 3882#define lpfc_mbx_get_port_name_name1_MASK 0x000000FF 3883#define lpfc_mbx_get_port_name_name1_WORD word4 3884#define lpfc_mbx_get_port_name_name2_SHIFT 16 3885#define lpfc_mbx_get_port_name_name2_MASK 0x000000FF 3886#define lpfc_mbx_get_port_name_name2_WORD word4 3887#define lpfc_mbx_get_port_name_name3_SHIFT 24 3888#define lpfc_mbx_get_port_name_name3_MASK 0x000000FF 3889#define lpfc_mbx_get_port_name_name3_WORD word4 3890#define LPFC_LINK_NUMBER_0 0 3891#define LPFC_LINK_NUMBER_1 1 3892#define LPFC_LINK_NUMBER_2 2 3893#define LPFC_LINK_NUMBER_3 3 3894 } response; 3895 } u; 3896}; 3897 3898/* Mailbox Completion Queue Error Messages */ 3899#define MB_CQE_STATUS_SUCCESS 0x0 3900#define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1 3901#define MB_CQE_STATUS_INVALID_PARAMETER 0x2 3902#define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3 3903#define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4 3904#define MB_CQE_STATUS_DMA_FAILED 0x5 3905 3906 3907#define LPFC_MBX_WR_CONFIG_MAX_BDE 1 3908struct lpfc_mbx_wr_object { 3909 struct mbox_header header; 3910 union { 3911 struct { 3912 uint32_t word4; 3913#define lpfc_wr_object_eof_SHIFT 31 3914#define lpfc_wr_object_eof_MASK 0x00000001 3915#define lpfc_wr_object_eof_WORD word4 3916#define lpfc_wr_object_eas_SHIFT 29 3917#define lpfc_wr_object_eas_MASK 0x00000001 3918#define lpfc_wr_object_eas_WORD word4 3919#define lpfc_wr_object_write_length_SHIFT 0 3920#define lpfc_wr_object_write_length_MASK 0x00FFFFFF 3921#define lpfc_wr_object_write_length_WORD word4 3922 uint32_t write_offset; 3923 uint32_t object_name[LPFC_MBX_OBJECT_NAME_LEN_DW]; 3924 uint32_t bde_count; 3925 struct ulp_bde64 bde[LPFC_MBX_WR_CONFIG_MAX_BDE]; 3926 } request; 3927 struct { 3928 uint32_t actual_write_length; 3929 uint32_t word5; 3930#define lpfc_wr_object_change_status_SHIFT 0 3931#define lpfc_wr_object_change_status_MASK 0x000000FF 3932#define lpfc_wr_object_change_status_WORD word5 3933#define LPFC_CHANGE_STATUS_NO_RESET_NEEDED 0x00 3934#define LPFC_CHANGE_STATUS_PHYS_DEV_RESET 0x01 3935#define LPFC_CHANGE_STATUS_FW_RESET 0x02 3936#define LPFC_CHANGE_STATUS_PORT_MIGRATION 0x04 3937#define LPFC_CHANGE_STATUS_PCI_RESET 0x05 3938#define lpfc_wr_object_csf_SHIFT 8 3939#define lpfc_wr_object_csf_MASK 0x00000001 3940#define lpfc_wr_object_csf_WORD word5 3941 } response; 3942 } u; 3943}; 3944 3945/* mailbox queue entry structure */ 3946struct lpfc_mqe { 3947 uint32_t word0; 3948#define lpfc_mqe_status_SHIFT 16 3949#define lpfc_mqe_status_MASK 0x0000FFFF 3950#define lpfc_mqe_status_WORD word0 3951#define lpfc_mqe_command_SHIFT 8 3952#define lpfc_mqe_command_MASK 0x000000FF 3953#define lpfc_mqe_command_WORD word0 3954 union { 3955 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1]; 3956 /* sli4 mailbox commands */ 3957 struct lpfc_mbx_sli4_config sli4_config; 3958 struct lpfc_mbx_init_vfi init_vfi; 3959 struct lpfc_mbx_reg_vfi reg_vfi; 3960 struct lpfc_mbx_reg_vfi unreg_vfi; 3961 struct lpfc_mbx_init_vpi init_vpi; 3962 struct lpfc_mbx_resume_rpi resume_rpi; 3963 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl; 3964 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry; 3965 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry; 3966 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl; 3967 struct lpfc_mbx_reg_fcfi reg_fcfi; 3968 struct lpfc_mbx_reg_fcfi_mrq reg_fcfi_mrq; 3969 struct lpfc_mbx_unreg_fcfi unreg_fcfi; 3970 struct lpfc_mbx_mq_create mq_create; 3971 struct lpfc_mbx_mq_create_ext mq_create_ext; 3972 struct lpfc_mbx_read_object read_object; 3973 struct lpfc_mbx_eq_create eq_create; 3974 struct lpfc_mbx_modify_eq_delay eq_delay; 3975 struct lpfc_mbx_cq_create cq_create; 3976 struct lpfc_mbx_cq_create_set cq_create_set; 3977 struct lpfc_mbx_wq_create wq_create; 3978 struct lpfc_mbx_rq_create rq_create; 3979 struct lpfc_mbx_rq_create_v2 rq_create_v2; 3980 struct lpfc_mbx_mq_destroy mq_destroy; 3981 struct lpfc_mbx_eq_destroy eq_destroy; 3982 struct lpfc_mbx_cq_destroy cq_destroy; 3983 struct lpfc_mbx_wq_destroy wq_destroy; 3984 struct lpfc_mbx_rq_destroy rq_destroy; 3985 struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info; 3986 struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents; 3987 struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents; 3988 struct lpfc_mbx_post_sgl_pages post_sgl_pages; 3989 struct lpfc_mbx_nembed_cmd nembed_cmd; 3990 struct lpfc_mbx_read_rev read_rev; 3991 struct lpfc_mbx_read_vpi read_vpi; 3992 struct lpfc_mbx_read_config rd_config; 3993 struct lpfc_mbx_request_features req_ftrs; 3994 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl; 3995 struct lpfc_mbx_query_fw_config query_fw_cfg; 3996 struct lpfc_mbx_set_beacon_config beacon_config; 3997 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters; 3998 struct lpfc_mbx_reg_congestion_buf reg_congestion_buf; 3999 struct lpfc_mbx_set_link_diag_state link_diag_state; 4000 struct lpfc_mbx_set_link_diag_loopback link_diag_loopback; 4001 struct lpfc_mbx_run_link_diag_test link_diag_test; 4002 struct lpfc_mbx_get_func_cfg get_func_cfg; 4003 struct lpfc_mbx_get_prof_cfg get_prof_cfg; 4004 struct lpfc_mbx_wr_object wr_object; 4005 struct lpfc_mbx_get_port_name get_port_name; 4006 struct lpfc_mbx_set_feature set_feature; 4007 struct lpfc_mbx_memory_dump_type3 mem_dump_type3; 4008 struct lpfc_mbx_set_host_data set_host_data; 4009 struct lpfc_mbx_set_trunk_mode set_trunk_mode; 4010 struct lpfc_mbx_nop nop; 4011 struct lpfc_mbx_set_ras_fwlog ras_fwlog; 4012 } un; 4013}; 4014 4015struct lpfc_mcqe { 4016 uint32_t word0; 4017#define lpfc_mcqe_status_SHIFT 0 4018#define lpfc_mcqe_status_MASK 0x0000FFFF 4019#define lpfc_mcqe_status_WORD word0 4020#define lpfc_mcqe_ext_status_SHIFT 16 4021#define lpfc_mcqe_ext_status_MASK 0x0000FFFF 4022#define lpfc_mcqe_ext_status_WORD word0 4023 uint32_t mcqe_tag0; 4024 uint32_t mcqe_tag1; 4025 uint32_t trailer; 4026#define lpfc_trailer_valid_SHIFT 31 4027#define lpfc_trailer_valid_MASK 0x00000001 4028#define lpfc_trailer_valid_WORD trailer 4029#define lpfc_trailer_async_SHIFT 30 4030#define lpfc_trailer_async_MASK 0x00000001 4031#define lpfc_trailer_async_WORD trailer 4032#define lpfc_trailer_hpi_SHIFT 29 4033#define lpfc_trailer_hpi_MASK 0x00000001 4034#define lpfc_trailer_hpi_WORD trailer 4035#define lpfc_trailer_completed_SHIFT 28 4036#define lpfc_trailer_completed_MASK 0x00000001 4037#define lpfc_trailer_completed_WORD trailer 4038#define lpfc_trailer_consumed_SHIFT 27 4039#define lpfc_trailer_consumed_MASK 0x00000001 4040#define lpfc_trailer_consumed_WORD trailer 4041#define lpfc_trailer_type_SHIFT 16 4042#define lpfc_trailer_type_MASK 0x000000FF 4043#define lpfc_trailer_type_WORD trailer 4044#define lpfc_trailer_code_SHIFT 8 4045#define lpfc_trailer_code_MASK 0x000000FF 4046#define lpfc_trailer_code_WORD trailer 4047#define LPFC_TRAILER_CODE_LINK 0x1 4048#define LPFC_TRAILER_CODE_FCOE 0x2 4049#define LPFC_TRAILER_CODE_DCBX 0x3 4050#define LPFC_TRAILER_CODE_GRP5 0x5 4051#define LPFC_TRAILER_CODE_FC 0x10 4052#define LPFC_TRAILER_CODE_SLI 0x11 4053}; 4054 4055struct lpfc_acqe_link { 4056 uint32_t word0; 4057#define lpfc_acqe_link_speed_SHIFT 24 4058#define lpfc_acqe_link_speed_MASK 0x000000FF 4059#define lpfc_acqe_link_speed_WORD word0 4060#define LPFC_ASYNC_LINK_SPEED_ZERO 0x0 4061#define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1 4062#define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2 4063#define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3 4064#define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4 4065#define LPFC_ASYNC_LINK_SPEED_20GBPS 0x5 4066#define LPFC_ASYNC_LINK_SPEED_25GBPS 0x6 4067#define LPFC_ASYNC_LINK_SPEED_40GBPS 0x7 4068#define LPFC_ASYNC_LINK_SPEED_100GBPS 0x8 4069#define lpfc_acqe_link_duplex_SHIFT 16 4070#define lpfc_acqe_link_duplex_MASK 0x000000FF 4071#define lpfc_acqe_link_duplex_WORD word0 4072#define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0 4073#define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1 4074#define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2 4075#define lpfc_acqe_link_status_SHIFT 8 4076#define lpfc_acqe_link_status_MASK 0x000000FF 4077#define lpfc_acqe_link_status_WORD word0 4078#define LPFC_ASYNC_LINK_STATUS_DOWN 0x0 4079#define LPFC_ASYNC_LINK_STATUS_UP 0x1 4080#define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2 4081#define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3 4082#define lpfc_acqe_link_type_SHIFT 6 4083#define lpfc_acqe_link_type_MASK 0x00000003 4084#define lpfc_acqe_link_type_WORD word0 4085#define lpfc_acqe_link_number_SHIFT 0 4086#define lpfc_acqe_link_number_MASK 0x0000003F 4087#define lpfc_acqe_link_number_WORD word0 4088 uint32_t word1; 4089#define lpfc_acqe_link_fault_SHIFT 0 4090#define lpfc_acqe_link_fault_MASK 0x000000FF 4091#define lpfc_acqe_link_fault_WORD word1 4092#define LPFC_ASYNC_LINK_FAULT_NONE 0x0 4093#define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1 4094#define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2 4095#define LPFC_ASYNC_LINK_FAULT_LR_LRR 0x3 4096#define lpfc_acqe_logical_link_speed_SHIFT 16 4097#define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF 4098#define lpfc_acqe_logical_link_speed_WORD word1 4099 uint32_t event_tag; 4100 uint32_t trailer; 4101#define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0 4102#define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1 4103}; 4104 4105struct lpfc_acqe_fip { 4106 uint32_t index; 4107 uint32_t word1; 4108#define lpfc_acqe_fip_fcf_count_SHIFT 0 4109#define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF 4110#define lpfc_acqe_fip_fcf_count_WORD word1 4111#define lpfc_acqe_fip_event_type_SHIFT 16 4112#define lpfc_acqe_fip_event_type_MASK 0x0000FFFF 4113#define lpfc_acqe_fip_event_type_WORD word1 4114 uint32_t event_tag; 4115 uint32_t trailer; 4116#define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1 4117#define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2 4118#define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3 4119#define LPFC_FIP_EVENT_TYPE_CVL 0x4 4120#define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5 4121}; 4122 4123struct lpfc_acqe_dcbx { 4124 uint32_t tlv_ttl; 4125 uint32_t reserved; 4126 uint32_t event_tag; 4127 uint32_t trailer; 4128}; 4129 4130struct lpfc_acqe_grp5 { 4131 uint32_t word0; 4132#define lpfc_acqe_grp5_type_SHIFT 6 4133#define lpfc_acqe_grp5_type_MASK 0x00000003 4134#define lpfc_acqe_grp5_type_WORD word0 4135#define lpfc_acqe_grp5_number_SHIFT 0 4136#define lpfc_acqe_grp5_number_MASK 0x0000003F 4137#define lpfc_acqe_grp5_number_WORD word0 4138 uint32_t word1; 4139#define lpfc_acqe_grp5_llink_spd_SHIFT 16 4140#define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF 4141#define lpfc_acqe_grp5_llink_spd_WORD word1 4142 uint32_t event_tag; 4143 uint32_t trailer; 4144}; 4145 4146extern const char *const trunk_errmsg[]; 4147 4148struct lpfc_acqe_fc_la { 4149 uint32_t word0; 4150#define lpfc_acqe_fc_la_speed_SHIFT 24 4151#define lpfc_acqe_fc_la_speed_MASK 0x000000FF 4152#define lpfc_acqe_fc_la_speed_WORD word0 4153#define LPFC_FC_LA_SPEED_UNKNOWN 0x0 4154#define LPFC_FC_LA_SPEED_1G 0x1 4155#define LPFC_FC_LA_SPEED_2G 0x2 4156#define LPFC_FC_LA_SPEED_4G 0x4 4157#define LPFC_FC_LA_SPEED_8G 0x8 4158#define LPFC_FC_LA_SPEED_10G 0xA 4159#define LPFC_FC_LA_SPEED_16G 0x10 4160#define LPFC_FC_LA_SPEED_32G 0x20 4161#define LPFC_FC_LA_SPEED_64G 0x21 4162#define LPFC_FC_LA_SPEED_128G 0x22 4163#define LPFC_FC_LA_SPEED_256G 0x23 4164#define lpfc_acqe_fc_la_topology_SHIFT 16 4165#define lpfc_acqe_fc_la_topology_MASK 0x000000FF 4166#define lpfc_acqe_fc_la_topology_WORD word0 4167#define LPFC_FC_LA_TOP_UNKOWN 0x0 4168#define LPFC_FC_LA_TOP_P2P 0x1 4169#define LPFC_FC_LA_TOP_FCAL 0x2 4170#define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3 4171#define LPFC_FC_LA_TOP_SERDES_LOOP 0x4 4172#define lpfc_acqe_fc_la_att_type_SHIFT 8 4173#define lpfc_acqe_fc_la_att_type_MASK 0x000000FF 4174#define lpfc_acqe_fc_la_att_type_WORD word0 4175#define LPFC_FC_LA_TYPE_LINK_UP 0x1 4176#define LPFC_FC_LA_TYPE_LINK_DOWN 0x2 4177#define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3 4178#define LPFC_FC_LA_TYPE_MDS_LINK_DOWN 0x4 4179#define LPFC_FC_LA_TYPE_MDS_LOOPBACK 0x5 4180#define LPFC_FC_LA_TYPE_UNEXP_WWPN 0x6 4181#define LPFC_FC_LA_TYPE_TRUNKING_EVENT 0x7 4182#define LPFC_FC_LA_TYPE_ACTIVATE_FAIL 0x8 4183#define LPFC_FC_LA_TYPE_LINK_RESET_PRTCL_EVT 0x9 4184#define lpfc_acqe_fc_la_port_type_SHIFT 6 4185#define lpfc_acqe_fc_la_port_type_MASK 0x00000003 4186#define lpfc_acqe_fc_la_port_type_WORD word0 4187#define LPFC_LINK_TYPE_ETHERNET 0x0 4188#define LPFC_LINK_TYPE_FC 0x1 4189#define lpfc_acqe_fc_la_port_number_SHIFT 0 4190#define lpfc_acqe_fc_la_port_number_MASK 0x0000003F 4191#define lpfc_acqe_fc_la_port_number_WORD word0 4192 4193/* Attention Type is 0x07 (Trunking Event) word0 */ 4194#define lpfc_acqe_fc_la_trunk_link_status_port0_SHIFT 16 4195#define lpfc_acqe_fc_la_trunk_link_status_port0_MASK 0x0000001 4196#define lpfc_acqe_fc_la_trunk_link_status_port0_WORD word0 4197#define lpfc_acqe_fc_la_trunk_link_status_port1_SHIFT 17 4198#define lpfc_acqe_fc_la_trunk_link_status_port1_MASK 0x0000001 4199#define lpfc_acqe_fc_la_trunk_link_status_port1_WORD word0 4200#define lpfc_acqe_fc_la_trunk_link_status_port2_SHIFT 18 4201#define lpfc_acqe_fc_la_trunk_link_status_port2_MASK 0x0000001 4202#define lpfc_acqe_fc_la_trunk_link_status_port2_WORD word0 4203#define lpfc_acqe_fc_la_trunk_link_status_port3_SHIFT 19 4204#define lpfc_acqe_fc_la_trunk_link_status_port3_MASK 0x0000001 4205#define lpfc_acqe_fc_la_trunk_link_status_port3_WORD word0 4206#define lpfc_acqe_fc_la_trunk_config_port0_SHIFT 20 4207#define lpfc_acqe_fc_la_trunk_config_port0_MASK 0x0000001 4208#define lpfc_acqe_fc_la_trunk_config_port0_WORD word0 4209#define lpfc_acqe_fc_la_trunk_config_port1_SHIFT 21 4210#define lpfc_acqe_fc_la_trunk_config_port1_MASK 0x0000001 4211#define lpfc_acqe_fc_la_trunk_config_port1_WORD word0 4212#define lpfc_acqe_fc_la_trunk_config_port2_SHIFT 22 4213#define lpfc_acqe_fc_la_trunk_config_port2_MASK 0x0000001 4214#define lpfc_acqe_fc_la_trunk_config_port2_WORD word0 4215#define lpfc_acqe_fc_la_trunk_config_port3_SHIFT 23 4216#define lpfc_acqe_fc_la_trunk_config_port3_MASK 0x0000001 4217#define lpfc_acqe_fc_la_trunk_config_port3_WORD word0 4218 uint32_t word1; 4219#define lpfc_acqe_fc_la_llink_spd_SHIFT 16 4220#define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF 4221#define lpfc_acqe_fc_la_llink_spd_WORD word1 4222#define lpfc_acqe_fc_la_fault_SHIFT 0 4223#define lpfc_acqe_fc_la_fault_MASK 0x000000FF 4224#define lpfc_acqe_fc_la_fault_WORD word1 4225#define lpfc_acqe_fc_la_link_status_SHIFT 8 4226#define lpfc_acqe_fc_la_link_status_MASK 0x0000007F 4227#define lpfc_acqe_fc_la_link_status_WORD word1 4228#define lpfc_acqe_fc_la_trunk_fault_SHIFT 0 4229#define lpfc_acqe_fc_la_trunk_fault_MASK 0x0000000F 4230#define lpfc_acqe_fc_la_trunk_fault_WORD word1 4231#define lpfc_acqe_fc_la_trunk_linkmask_SHIFT 4 4232#define lpfc_acqe_fc_la_trunk_linkmask_MASK 0x000000F 4233#define lpfc_acqe_fc_la_trunk_linkmask_WORD word1 4234#define LPFC_FC_LA_FAULT_NONE 0x0 4235#define LPFC_FC_LA_FAULT_LOCAL 0x1 4236#define LPFC_FC_LA_FAULT_REMOTE 0x2 4237 uint32_t event_tag; 4238 uint32_t trailer; 4239#define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1 4240#define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2 4241}; 4242 4243struct lpfc_acqe_misconfigured_event { 4244 struct { 4245 uint32_t word0; 4246#define lpfc_sli_misconfigured_port0_state_SHIFT 0 4247#define lpfc_sli_misconfigured_port0_state_MASK 0x000000FF 4248#define lpfc_sli_misconfigured_port0_state_WORD word0 4249#define lpfc_sli_misconfigured_port1_state_SHIFT 8 4250#define lpfc_sli_misconfigured_port1_state_MASK 0x000000FF 4251#define lpfc_sli_misconfigured_port1_state_WORD word0 4252#define lpfc_sli_misconfigured_port2_state_SHIFT 16 4253#define lpfc_sli_misconfigured_port2_state_MASK 0x000000FF 4254#define lpfc_sli_misconfigured_port2_state_WORD word0 4255#define lpfc_sli_misconfigured_port3_state_SHIFT 24 4256#define lpfc_sli_misconfigured_port3_state_MASK 0x000000FF 4257#define lpfc_sli_misconfigured_port3_state_WORD word0 4258 uint32_t word1; 4259#define lpfc_sli_misconfigured_port0_op_SHIFT 0 4260#define lpfc_sli_misconfigured_port0_op_MASK 0x00000001 4261#define lpfc_sli_misconfigured_port0_op_WORD word1 4262#define lpfc_sli_misconfigured_port0_severity_SHIFT 1 4263#define lpfc_sli_misconfigured_port0_severity_MASK 0x00000003 4264#define lpfc_sli_misconfigured_port0_severity_WORD word1 4265#define lpfc_sli_misconfigured_port1_op_SHIFT 8 4266#define lpfc_sli_misconfigured_port1_op_MASK 0x00000001 4267#define lpfc_sli_misconfigured_port1_op_WORD word1 4268#define lpfc_sli_misconfigured_port1_severity_SHIFT 9 4269#define lpfc_sli_misconfigured_port1_severity_MASK 0x00000003 4270#define lpfc_sli_misconfigured_port1_severity_WORD word1 4271#define lpfc_sli_misconfigured_port2_op_SHIFT 16 4272#define lpfc_sli_misconfigured_port2_op_MASK 0x00000001 4273#define lpfc_sli_misconfigured_port2_op_WORD word1 4274#define lpfc_sli_misconfigured_port2_severity_SHIFT 17 4275#define lpfc_sli_misconfigured_port2_severity_MASK 0x00000003 4276#define lpfc_sli_misconfigured_port2_severity_WORD word1 4277#define lpfc_sli_misconfigured_port3_op_SHIFT 24 4278#define lpfc_sli_misconfigured_port3_op_MASK 0x00000001 4279#define lpfc_sli_misconfigured_port3_op_WORD word1 4280#define lpfc_sli_misconfigured_port3_severity_SHIFT 25 4281#define lpfc_sli_misconfigured_port3_severity_MASK 0x00000003 4282#define lpfc_sli_misconfigured_port3_severity_WORD word1 4283 } theEvent; 4284#define LPFC_SLI_EVENT_STATUS_VALID 0x00 4285#define LPFC_SLI_EVENT_STATUS_NOT_PRESENT 0x01 4286#define LPFC_SLI_EVENT_STATUS_WRONG_TYPE 0x02 4287#define LPFC_SLI_EVENT_STATUS_UNSUPPORTED 0x03 4288#define LPFC_SLI_EVENT_STATUS_UNQUALIFIED 0x04 4289#define LPFC_SLI_EVENT_STATUS_UNCERTIFIED 0x05 4290}; 4291 4292struct lpfc_acqe_cgn_signal { 4293 u32 word0; 4294#define lpfc_warn_acqe_SHIFT 0 4295#define lpfc_warn_acqe_MASK 0x7FFFFFFF 4296#define lpfc_warn_acqe_WORD word0 4297#define lpfc_imm_acqe_SHIFT 31 4298#define lpfc_imm_acqe_MASK 0x1 4299#define lpfc_imm_acqe_WORD word0 4300 u32 alarm_cnt; 4301 u32 word2; 4302 u32 trailer; 4303}; 4304 4305struct lpfc_acqe_sli { 4306 uint32_t event_data1; 4307 uint32_t event_data2; 4308 uint32_t event_data3; 4309 uint32_t trailer; 4310#define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1 4311#define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2 4312#define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3 4313#define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4 4314#define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5 4315#define LPFC_SLI_EVENT_TYPE_MISCONFIGURED 0x9 4316#define LPFC_SLI_EVENT_TYPE_REMOTE_DPORT 0xA 4317#define LPFC_SLI_EVENT_TYPE_PORT_PARAMS_CHG 0xE 4318#define LPFC_SLI_EVENT_TYPE_MISCONF_FAWWN 0xF 4319#define LPFC_SLI_EVENT_TYPE_EEPROM_FAILURE 0x10 4320#define LPFC_SLI_EVENT_TYPE_CGN_SIGNAL 0x11 4321#define LPFC_SLI_EVENT_TYPE_RD_SIGNAL 0x12 4322#define LPFC_SLI_EVENT_TYPE_RESET_CM_STATS 0x13 4323}; 4324 4325/* 4326 * Define the bootstrap mailbox (bmbx) region used to communicate 4327 * mailbox command between the host and port. The mailbox consists 4328 * of a payload area of 256 bytes and a completion queue of length 4329 * 16 bytes. 4330 */ 4331struct lpfc_bmbx_create { 4332 struct lpfc_mqe mqe; 4333 struct lpfc_mcqe mcqe; 4334}; 4335 4336#define SGL_ALIGN_SZ 64 4337#define SGL_PAGE_SIZE 4096 4338/* align SGL addr on a size boundary - adjust address up */ 4339#define NO_XRI 0xffff 4340 4341struct wqe_common { 4342 uint32_t word6; 4343#define wqe_xri_tag_SHIFT 0 4344#define wqe_xri_tag_MASK 0x0000FFFF 4345#define wqe_xri_tag_WORD word6 4346#define wqe_ctxt_tag_SHIFT 16 4347#define wqe_ctxt_tag_MASK 0x0000FFFF 4348#define wqe_ctxt_tag_WORD word6 4349 uint32_t word7; 4350#define wqe_dif_SHIFT 0 4351#define wqe_dif_MASK 0x00000003 4352#define wqe_dif_WORD word7 4353#define LPFC_WQE_DIF_PASSTHRU 1 4354#define LPFC_WQE_DIF_STRIP 2 4355#define LPFC_WQE_DIF_INSERT 3 4356#define wqe_ct_SHIFT 2 4357#define wqe_ct_MASK 0x00000003 4358#define wqe_ct_WORD word7 4359#define wqe_status_SHIFT 4 4360#define wqe_status_MASK 0x0000000f 4361#define wqe_status_WORD word7 4362#define wqe_cmnd_SHIFT 8 4363#define wqe_cmnd_MASK 0x000000ff 4364#define wqe_cmnd_WORD word7 4365#define wqe_class_SHIFT 16 4366#define wqe_class_MASK 0x00000007 4367#define wqe_class_WORD word7 4368#define wqe_ar_SHIFT 19 4369#define wqe_ar_MASK 0x00000001 4370#define wqe_ar_WORD word7 4371#define wqe_ag_SHIFT wqe_ar_SHIFT 4372#define wqe_ag_MASK wqe_ar_MASK 4373#define wqe_ag_WORD wqe_ar_WORD 4374#define wqe_pu_SHIFT 20 4375#define wqe_pu_MASK 0x00000003 4376#define wqe_pu_WORD word7 4377#define wqe_erp_SHIFT 22 4378#define wqe_erp_MASK 0x00000001 4379#define wqe_erp_WORD word7 4380#define wqe_conf_SHIFT wqe_erp_SHIFT 4381#define wqe_conf_MASK wqe_erp_MASK 4382#define wqe_conf_WORD wqe_erp_WORD 4383#define wqe_lnk_SHIFT 23 4384#define wqe_lnk_MASK 0x00000001 4385#define wqe_lnk_WORD word7 4386#define wqe_tmo_SHIFT 24 4387#define wqe_tmo_MASK 0x000000ff 4388#define wqe_tmo_WORD word7 4389 uint32_t abort_tag; /* word 8 in WQE */ 4390 uint32_t word9; 4391#define wqe_reqtag_SHIFT 0 4392#define wqe_reqtag_MASK 0x0000FFFF 4393#define wqe_reqtag_WORD word9 4394#define wqe_temp_rpi_SHIFT 16 4395#define wqe_temp_rpi_MASK 0x0000FFFF 4396#define wqe_temp_rpi_WORD word9 4397#define wqe_rcvoxid_SHIFT 16 4398#define wqe_rcvoxid_MASK 0x0000FFFF 4399#define wqe_rcvoxid_WORD word9 4400#define wqe_sof_SHIFT 24 4401#define wqe_sof_MASK 0x000000FF 4402#define wqe_sof_WORD word9 4403#define wqe_eof_SHIFT 16 4404#define wqe_eof_MASK 0x000000FF 4405#define wqe_eof_WORD word9 4406 uint32_t word10; 4407#define wqe_ebde_cnt_SHIFT 0 4408#define wqe_ebde_cnt_MASK 0x0000000f 4409#define wqe_ebde_cnt_WORD word10 4410#define wqe_xchg_SHIFT 4 4411#define wqe_xchg_MASK 0x00000001 4412#define wqe_xchg_WORD word10 4413#define LPFC_SCSI_XCHG 0x0 4414#define LPFC_NVME_XCHG 0x1 4415#define wqe_appid_SHIFT 5 4416#define wqe_appid_MASK 0x00000001 4417#define wqe_appid_WORD word10 4418#define wqe_oas_SHIFT 6 4419#define wqe_oas_MASK 0x00000001 4420#define wqe_oas_WORD word10 4421#define wqe_lenloc_SHIFT 7 4422#define wqe_lenloc_MASK 0x00000003 4423#define wqe_lenloc_WORD word10 4424#define LPFC_WQE_LENLOC_NONE 0 4425#define LPFC_WQE_LENLOC_WORD3 1 4426#define LPFC_WQE_LENLOC_WORD12 2 4427#define LPFC_WQE_LENLOC_WORD4 3 4428#define wqe_qosd_SHIFT 9 4429#define wqe_qosd_MASK 0x00000001 4430#define wqe_qosd_WORD word10 4431#define wqe_xbl_SHIFT 11 4432#define wqe_xbl_MASK 0x00000001 4433#define wqe_xbl_WORD word10 4434#define wqe_iod_SHIFT 13 4435#define wqe_iod_MASK 0x00000001 4436#define wqe_iod_WORD word10 4437#define LPFC_WQE_IOD_NONE 0 4438#define LPFC_WQE_IOD_WRITE 0 4439#define LPFC_WQE_IOD_READ 1 4440#define wqe_dbde_SHIFT 14 4441#define wqe_dbde_MASK 0x00000001 4442#define wqe_dbde_WORD word10 4443#define wqe_wqes_SHIFT 15 4444#define wqe_wqes_MASK 0x00000001 4445#define wqe_wqes_WORD word10 4446/* Note that this field overlaps above fields */ 4447#define wqe_wqid_SHIFT 1 4448#define wqe_wqid_MASK 0x00007fff 4449#define wqe_wqid_WORD word10 4450#define wqe_pri_SHIFT 16 4451#define wqe_pri_MASK 0x00000007 4452#define wqe_pri_WORD word10 4453#define wqe_pv_SHIFT 19 4454#define wqe_pv_MASK 0x00000001 4455#define wqe_pv_WORD word10 4456#define wqe_xc_SHIFT 21 4457#define wqe_xc_MASK 0x00000001 4458#define wqe_xc_WORD word10 4459#define wqe_sr_SHIFT 22 4460#define wqe_sr_MASK 0x00000001 4461#define wqe_sr_WORD word10 4462#define wqe_ccpe_SHIFT 23 4463#define wqe_ccpe_MASK 0x00000001 4464#define wqe_ccpe_WORD word10 4465#define wqe_ccp_SHIFT 24 4466#define wqe_ccp_MASK 0x000000ff 4467#define wqe_ccp_WORD word10 4468 uint32_t word11; 4469#define wqe_cmd_type_SHIFT 0 4470#define wqe_cmd_type_MASK 0x0000000f 4471#define wqe_cmd_type_WORD word11 4472#define wqe_els_id_SHIFT 4 4473#define wqe_els_id_MASK 0x00000007 4474#define wqe_els_id_WORD word11 4475#define wqe_irsp_SHIFT 4 4476#define wqe_irsp_MASK 0x00000001 4477#define wqe_irsp_WORD word11 4478#define wqe_pbde_SHIFT 5 4479#define wqe_pbde_MASK 0x00000001 4480#define wqe_pbde_WORD word11 4481#define wqe_sup_SHIFT 6 4482#define wqe_sup_MASK 0x00000001 4483#define wqe_sup_WORD word11 4484#define wqe_ffrq_SHIFT 6 4485#define wqe_ffrq_MASK 0x00000001 4486#define wqe_ffrq_WORD word11 4487#define wqe_wqec_SHIFT 7 4488#define wqe_wqec_MASK 0x00000001 4489#define wqe_wqec_WORD word11 4490#define wqe_irsplen_SHIFT 8 4491#define wqe_irsplen_MASK 0x0000000f 4492#define wqe_irsplen_WORD word11 4493#define wqe_cqid_SHIFT 16 4494#define wqe_cqid_MASK 0x0000ffff 4495#define wqe_cqid_WORD word11 4496#define LPFC_WQE_CQ_ID_DEFAULT 0xffff 4497}; 4498 4499struct wqe_did { 4500 uint32_t word5; 4501#define wqe_els_did_SHIFT 0 4502#define wqe_els_did_MASK 0x00FFFFFF 4503#define wqe_els_did_WORD word5 4504#define wqe_xmit_bls_pt_SHIFT 28 4505#define wqe_xmit_bls_pt_MASK 0x00000003 4506#define wqe_xmit_bls_pt_WORD word5 4507#define wqe_xmit_bls_ar_SHIFT 30 4508#define wqe_xmit_bls_ar_MASK 0x00000001 4509#define wqe_xmit_bls_ar_WORD word5 4510#define wqe_xmit_bls_xo_SHIFT 31 4511#define wqe_xmit_bls_xo_MASK 0x00000001 4512#define wqe_xmit_bls_xo_WORD word5 4513}; 4514 4515struct lpfc_wqe_generic{ 4516 struct ulp_bde64 bde; 4517 uint32_t word3; 4518 uint32_t word4; 4519 uint32_t word5; 4520 struct wqe_common wqe_com; 4521 uint32_t payload[4]; 4522}; 4523 4524enum els_request64_wqe_word11 { 4525 LPFC_ELS_ID_DEFAULT, 4526 LPFC_ELS_ID_LOGO, 4527 LPFC_ELS_ID_FDISC, 4528 LPFC_ELS_ID_FLOGI, 4529 LPFC_ELS_ID_PLOGI, 4530}; 4531 4532struct els_request64_wqe { 4533 struct ulp_bde64 bde; 4534 uint32_t payload_len; 4535 uint32_t word4; 4536#define els_req64_sid_SHIFT 0 4537#define els_req64_sid_MASK 0x00FFFFFF 4538#define els_req64_sid_WORD word4 4539#define els_req64_sp_SHIFT 24 4540#define els_req64_sp_MASK 0x00000001 4541#define els_req64_sp_WORD word4 4542#define els_req64_vf_SHIFT 25 4543#define els_req64_vf_MASK 0x00000001 4544#define els_req64_vf_WORD word4 4545 struct wqe_did wqe_dest; 4546 struct wqe_common wqe_com; /* words 6-11 */ 4547 uint32_t word12; 4548#define els_req64_vfid_SHIFT 1 4549#define els_req64_vfid_MASK 0x00000FFF 4550#define els_req64_vfid_WORD word12 4551#define els_req64_pri_SHIFT 13 4552#define els_req64_pri_MASK 0x00000007 4553#define els_req64_pri_WORD word12 4554 uint32_t word13; 4555#define els_req64_hopcnt_SHIFT 24 4556#define els_req64_hopcnt_MASK 0x000000ff 4557#define els_req64_hopcnt_WORD word13 4558 uint32_t word14; 4559 uint32_t max_response_payload_len; 4560}; 4561 4562struct xmit_els_rsp64_wqe { 4563 struct ulp_bde64 bde; 4564 uint32_t response_payload_len; 4565 uint32_t word4; 4566#define els_rsp64_sid_SHIFT 0 4567#define els_rsp64_sid_MASK 0x00FFFFFF 4568#define els_rsp64_sid_WORD word4 4569#define els_rsp64_sp_SHIFT 24 4570#define els_rsp64_sp_MASK 0x00000001 4571#define els_rsp64_sp_WORD word4 4572 struct wqe_did wqe_dest; 4573 struct wqe_common wqe_com; /* words 6-11 */ 4574 uint32_t word12; 4575#define wqe_rsp_temp_rpi_SHIFT 0 4576#define wqe_rsp_temp_rpi_MASK 0x0000FFFF 4577#define wqe_rsp_temp_rpi_WORD word12 4578 uint32_t rsvd_13_15[3]; 4579}; 4580 4581struct xmit_bls_rsp64_wqe { 4582 uint32_t payload0; 4583/* Payload0 for BA_ACC */ 4584#define xmit_bls_rsp64_acc_seq_id_SHIFT 16 4585#define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff 4586#define xmit_bls_rsp64_acc_seq_id_WORD payload0 4587#define xmit_bls_rsp64_acc_seq_id_vald_SHIFT 24 4588#define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff 4589#define xmit_bls_rsp64_acc_seq_id_vald_WORD payload0 4590/* Payload0 for BA_RJT */ 4591#define xmit_bls_rsp64_rjt_vspec_SHIFT 0 4592#define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff 4593#define xmit_bls_rsp64_rjt_vspec_WORD payload0 4594#define xmit_bls_rsp64_rjt_expc_SHIFT 8 4595#define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff 4596#define xmit_bls_rsp64_rjt_expc_WORD payload0 4597#define xmit_bls_rsp64_rjt_rsnc_SHIFT 16 4598#define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff 4599#define xmit_bls_rsp64_rjt_rsnc_WORD payload0 4600 uint32_t word1; 4601#define xmit_bls_rsp64_rxid_SHIFT 0 4602#define xmit_bls_rsp64_rxid_MASK 0x0000ffff 4603#define xmit_bls_rsp64_rxid_WORD word1 4604#define xmit_bls_rsp64_oxid_SHIFT 16 4605#define xmit_bls_rsp64_oxid_MASK 0x0000ffff 4606#define xmit_bls_rsp64_oxid_WORD word1 4607 uint32_t word2; 4608#define xmit_bls_rsp64_seqcnthi_SHIFT 0 4609#define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff 4610#define xmit_bls_rsp64_seqcnthi_WORD word2 4611#define xmit_bls_rsp64_seqcntlo_SHIFT 16 4612#define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff 4613#define xmit_bls_rsp64_seqcntlo_WORD word2 4614 uint32_t rsrvd3; 4615 uint32_t rsrvd4; 4616 struct wqe_did wqe_dest; 4617 struct wqe_common wqe_com; /* words 6-11 */ 4618 uint32_t word12; 4619#define xmit_bls_rsp64_temprpi_SHIFT 0 4620#define xmit_bls_rsp64_temprpi_MASK 0x0000ffff 4621#define xmit_bls_rsp64_temprpi_WORD word12 4622 uint32_t rsvd_13_15[3]; 4623}; 4624 4625struct wqe_rctl_dfctl { 4626 uint32_t word5; 4627#define wqe_si_SHIFT 2 4628#define wqe_si_MASK 0x000000001 4629#define wqe_si_WORD word5 4630#define wqe_la_SHIFT 3 4631#define wqe_la_MASK 0x000000001 4632#define wqe_la_WORD word5 4633#define wqe_xo_SHIFT 6 4634#define wqe_xo_MASK 0x000000001 4635#define wqe_xo_WORD word5 4636#define wqe_ls_SHIFT 7 4637#define wqe_ls_MASK 0x000000001 4638#define wqe_ls_WORD word5 4639#define wqe_dfctl_SHIFT 8 4640#define wqe_dfctl_MASK 0x0000000ff 4641#define wqe_dfctl_WORD word5 4642#define wqe_type_SHIFT 16 4643#define wqe_type_MASK 0x0000000ff 4644#define wqe_type_WORD word5 4645#define wqe_rctl_SHIFT 24 4646#define wqe_rctl_MASK 0x0000000ff 4647#define wqe_rctl_WORD word5 4648}; 4649 4650struct xmit_seq64_wqe { 4651 struct ulp_bde64 bde; 4652 uint32_t rsvd3; 4653 uint32_t relative_offset; 4654 struct wqe_rctl_dfctl wge_ctl; 4655 struct wqe_common wqe_com; /* words 6-11 */ 4656 uint32_t xmit_len; 4657 uint32_t rsvd_12_15[3]; 4658}; 4659struct xmit_bcast64_wqe { 4660 struct ulp_bde64 bde; 4661 uint32_t seq_payload_len; 4662 uint32_t rsvd4; 4663 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 4664 struct wqe_common wqe_com; /* words 6-11 */ 4665 uint32_t rsvd_12_15[4]; 4666}; 4667 4668struct gen_req64_wqe { 4669 struct ulp_bde64 bde; 4670 uint32_t request_payload_len; 4671 uint32_t relative_offset; 4672 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 4673 struct wqe_common wqe_com; /* words 6-11 */ 4674 uint32_t rsvd_12_14[3]; 4675 uint32_t max_response_payload_len; 4676}; 4677 4678/* Define NVME PRLI request to fabric. NVME is a 4679 * fabric-only protocol. 4680 * Updated to red-lined v1.08 on Sept 16, 2016 4681 */ 4682struct lpfc_nvme_prli { 4683 uint32_t word1; 4684 /* The Response Code is defined in the FCP PRLI lpfc_hw.h */ 4685#define prli_acc_rsp_code_SHIFT 8 4686#define prli_acc_rsp_code_MASK 0x0000000f 4687#define prli_acc_rsp_code_WORD word1 4688#define prli_estabImagePair_SHIFT 13 4689#define prli_estabImagePair_MASK 0x00000001 4690#define prli_estabImagePair_WORD word1 4691#define prli_type_code_ext_SHIFT 16 4692#define prli_type_code_ext_MASK 0x000000ff 4693#define prli_type_code_ext_WORD word1 4694#define prli_type_code_SHIFT 24 4695#define prli_type_code_MASK 0x000000ff 4696#define prli_type_code_WORD word1 4697 uint32_t word_rsvd2; 4698 uint32_t word_rsvd3; 4699 4700 uint32_t word4; 4701#define prli_fba_SHIFT 0 4702#define prli_fba_MASK 0x00000001 4703#define prli_fba_WORD word4 4704#define prli_disc_SHIFT 3 4705#define prli_disc_MASK 0x00000001 4706#define prli_disc_WORD word4 4707#define prli_tgt_SHIFT 4 4708#define prli_tgt_MASK 0x00000001 4709#define prli_tgt_WORD word4 4710#define prli_init_SHIFT 5 4711#define prli_init_MASK 0x00000001 4712#define prli_init_WORD word4 4713#define prli_conf_SHIFT 7 4714#define prli_conf_MASK 0x00000001 4715#define prli_conf_WORD word4 4716#define prli_nsler_SHIFT 8 4717#define prli_nsler_MASK 0x00000001 4718#define prli_nsler_WORD word4 4719 uint32_t word5; 4720#define prli_fb_sz_SHIFT 0 4721#define prli_fb_sz_MASK 0x0000ffff 4722#define prli_fb_sz_WORD word5 4723#define LPFC_NVMET_FB_SZ_MAX 65536 /* Driver target mode only. */ 4724}; 4725 4726struct create_xri_wqe { 4727 uint32_t rsrvd[5]; /* words 0-4 */ 4728 struct wqe_did wqe_dest; /* word 5 */ 4729 struct wqe_common wqe_com; /* words 6-11 */ 4730 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4731}; 4732 4733#define T_REQUEST_TAG 3 4734#define T_XRI_TAG 1 4735 4736struct cmf_sync_wqe { 4737 uint32_t rsrvd[3]; 4738 uint32_t word3; 4739#define cmf_sync_interval_SHIFT 0 4740#define cmf_sync_interval_MASK 0x00000ffff 4741#define cmf_sync_interval_WORD word3 4742#define cmf_sync_afpin_SHIFT 16 4743#define cmf_sync_afpin_MASK 0x000000001 4744#define cmf_sync_afpin_WORD word3 4745#define cmf_sync_asig_SHIFT 17 4746#define cmf_sync_asig_MASK 0x000000001 4747#define cmf_sync_asig_WORD word3 4748#define cmf_sync_op_SHIFT 20 4749#define cmf_sync_op_MASK 0x00000000f 4750#define cmf_sync_op_WORD word3 4751#define cmf_sync_ver_SHIFT 24 4752#define cmf_sync_ver_MASK 0x0000000ff 4753#define cmf_sync_ver_WORD word3 4754#define LPFC_CMF_SYNC_VER 1 4755 uint32_t event_tag; 4756 uint32_t word5; 4757#define cmf_sync_wsigmax_SHIFT 0 4758#define cmf_sync_wsigmax_MASK 0x00000ffff 4759#define cmf_sync_wsigmax_WORD word5 4760#define cmf_sync_wsigcnt_SHIFT 16 4761#define cmf_sync_wsigcnt_MASK 0x00000ffff 4762#define cmf_sync_wsigcnt_WORD word5 4763 uint32_t word6; 4764 uint32_t word7; 4765#define cmf_sync_cmnd_SHIFT 8 4766#define cmf_sync_cmnd_MASK 0x0000000ff 4767#define cmf_sync_cmnd_WORD word7 4768 uint32_t word8; 4769 uint32_t word9; 4770#define cmf_sync_reqtag_SHIFT 0 4771#define cmf_sync_reqtag_MASK 0x00000ffff 4772#define cmf_sync_reqtag_WORD word9 4773#define cmf_sync_wfpinmax_SHIFT 16 4774#define cmf_sync_wfpinmax_MASK 0x0000000ff 4775#define cmf_sync_wfpinmax_WORD word9 4776#define cmf_sync_wfpincnt_SHIFT 24 4777#define cmf_sync_wfpincnt_MASK 0x0000000ff 4778#define cmf_sync_wfpincnt_WORD word9 4779 uint32_t word10; 4780#define cmf_sync_qosd_SHIFT 9 4781#define cmf_sync_qosd_MASK 0x00000001 4782#define cmf_sync_qosd_WORD word10 4783 uint32_t word11; 4784#define cmf_sync_cmd_type_SHIFT 0 4785#define cmf_sync_cmd_type_MASK 0x0000000f 4786#define cmf_sync_cmd_type_WORD word11 4787#define cmf_sync_wqec_SHIFT 7 4788#define cmf_sync_wqec_MASK 0x00000001 4789#define cmf_sync_wqec_WORD word11 4790#define cmf_sync_cqid_SHIFT 16 4791#define cmf_sync_cqid_MASK 0x0000ffff 4792#define cmf_sync_cqid_WORD word11 4793 uint32_t read_bytes; 4794 uint32_t word13; 4795#define cmf_sync_period_SHIFT 24 4796#define cmf_sync_period_MASK 0x000000ff 4797#define cmf_sync_period_WORD word13 4798 uint32_t word14; 4799 uint32_t word15; 4800}; 4801 4802struct abort_cmd_wqe { 4803 uint32_t rsrvd[3]; 4804 uint32_t word3; 4805#define abort_cmd_ia_SHIFT 0 4806#define abort_cmd_ia_MASK 0x000000001 4807#define abort_cmd_ia_WORD word3 4808#define abort_cmd_criteria_SHIFT 8 4809#define abort_cmd_criteria_MASK 0x0000000ff 4810#define abort_cmd_criteria_WORD word3 4811 uint32_t rsrvd4; 4812 uint32_t rsrvd5; 4813 struct wqe_common wqe_com; /* words 6-11 */ 4814 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4815}; 4816 4817struct fcp_iwrite64_wqe { 4818 struct ulp_bde64 bde; 4819 uint32_t word3; 4820#define cmd_buff_len_SHIFT 16 4821#define cmd_buff_len_MASK 0x00000ffff 4822#define cmd_buff_len_WORD word3 4823/* Note: payload_offset_len field depends on ASIC support */ 4824#define payload_offset_len_SHIFT 0 4825#define payload_offset_len_MASK 0x0000ffff 4826#define payload_offset_len_WORD word3 4827 uint32_t total_xfer_len; 4828 uint32_t initial_xfer_len; 4829 struct wqe_common wqe_com; /* words 6-11 */ 4830 uint32_t rsrvd12; 4831 struct ulp_bde64 ph_bde; /* words 13-15 */ 4832}; 4833 4834struct fcp_iread64_wqe { 4835 struct ulp_bde64 bde; 4836 uint32_t word3; 4837#define cmd_buff_len_SHIFT 16 4838#define cmd_buff_len_MASK 0x00000ffff 4839#define cmd_buff_len_WORD word3 4840/* Note: payload_offset_len field depends on ASIC support */ 4841#define payload_offset_len_SHIFT 0 4842#define payload_offset_len_MASK 0x0000ffff 4843#define payload_offset_len_WORD word3 4844 uint32_t total_xfer_len; /* word 4 */ 4845 uint32_t rsrvd5; /* word 5 */ 4846 struct wqe_common wqe_com; /* words 6-11 */ 4847 uint32_t rsrvd12; 4848 struct ulp_bde64 ph_bde; /* words 13-15 */ 4849}; 4850 4851struct fcp_icmnd64_wqe { 4852 struct ulp_bde64 bde; /* words 0-2 */ 4853 uint32_t word3; 4854#define cmd_buff_len_SHIFT 16 4855#define cmd_buff_len_MASK 0x00000ffff 4856#define cmd_buff_len_WORD word3 4857/* Note: payload_offset_len field depends on ASIC support */ 4858#define payload_offset_len_SHIFT 0 4859#define payload_offset_len_MASK 0x0000ffff 4860#define payload_offset_len_WORD word3 4861 uint32_t rsrvd4; /* word 4 */ 4862 uint32_t rsrvd5; /* word 5 */ 4863 struct wqe_common wqe_com; /* words 6-11 */ 4864 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4865}; 4866 4867struct fcp_trsp64_wqe { 4868 struct ulp_bde64 bde; 4869 uint32_t response_len; 4870 uint32_t rsvd_4_5[2]; 4871 struct wqe_common wqe_com; /* words 6-11 */ 4872 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4873}; 4874 4875struct fcp_tsend64_wqe { 4876 struct ulp_bde64 bde; 4877 uint32_t payload_offset_len; 4878 uint32_t relative_offset; 4879 uint32_t reserved; 4880 struct wqe_common wqe_com; /* words 6-11 */ 4881 uint32_t fcp_data_len; /* word 12 */ 4882 uint32_t rsvd_13_15[3]; /* word 13-15 */ 4883}; 4884 4885struct fcp_treceive64_wqe { 4886 struct ulp_bde64 bde; 4887 uint32_t payload_offset_len; 4888 uint32_t relative_offset; 4889 uint32_t reserved; 4890 struct wqe_common wqe_com; /* words 6-11 */ 4891 uint32_t fcp_data_len; /* word 12 */ 4892 uint32_t rsvd_13_15[3]; /* word 13-15 */ 4893}; 4894#define TXRDY_PAYLOAD_LEN 12 4895 4896#define CMD_SEND_FRAME 0xE1 4897 4898struct send_frame_wqe { 4899 struct ulp_bde64 bde; /* words 0-2 */ 4900 uint32_t frame_len; /* word 3 */ 4901 uint32_t fc_hdr_wd0; /* word 4 */ 4902 uint32_t fc_hdr_wd1; /* word 5 */ 4903 struct wqe_common wqe_com; /* words 6-11 */ 4904 uint32_t fc_hdr_wd2; /* word 12 */ 4905 uint32_t fc_hdr_wd3; /* word 13 */ 4906 uint32_t fc_hdr_wd4; /* word 14 */ 4907 uint32_t fc_hdr_wd5; /* word 15 */ 4908}; 4909 4910#define ELS_RDF_REG_TAG_CNT 4 4911struct lpfc_els_rdf_reg_desc { 4912 struct fc_df_desc_fpin_reg_hdr reg_desc; /* descriptor header */ 4913 __be32 desc_tags[ELS_RDF_REG_TAG_CNT]; 4914 /* tags in reg_desc */ 4915}; 4916 4917struct lpfc_els_rdf_req { 4918 struct fc_els_rdf_hdr rdf; /* hdr up to descriptors */ 4919 struct lpfc_els_rdf_reg_desc reg_d1; /* 1st descriptor */ 4920}; 4921 4922struct lpfc_els_rdf_rsp { 4923 struct fc_els_rdf_resp_hdr rdf_resp; /* hdr up to descriptors */ 4924 struct lpfc_els_rdf_reg_desc reg_d1; /* 1st descriptor */ 4925}; 4926 4927union lpfc_wqe { 4928 uint32_t words[16]; 4929 struct lpfc_wqe_generic generic; 4930 struct fcp_icmnd64_wqe fcp_icmd; 4931 struct fcp_iread64_wqe fcp_iread; 4932 struct fcp_iwrite64_wqe fcp_iwrite; 4933 struct abort_cmd_wqe abort_cmd; 4934 struct cmf_sync_wqe cmf_sync; 4935 struct create_xri_wqe create_xri; 4936 struct xmit_bcast64_wqe xmit_bcast64; 4937 struct xmit_seq64_wqe xmit_sequence; 4938 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 4939 struct xmit_els_rsp64_wqe xmit_els_rsp; 4940 struct els_request64_wqe els_req; 4941 struct gen_req64_wqe gen_req; 4942 struct fcp_trsp64_wqe fcp_trsp; 4943 struct fcp_tsend64_wqe fcp_tsend; 4944 struct fcp_treceive64_wqe fcp_treceive; 4945 struct send_frame_wqe send_frame; 4946}; 4947 4948union lpfc_wqe128 { 4949 uint32_t words[32]; 4950 struct lpfc_wqe_generic generic; 4951 struct fcp_icmnd64_wqe fcp_icmd; 4952 struct fcp_iread64_wqe fcp_iread; 4953 struct fcp_iwrite64_wqe fcp_iwrite; 4954 struct abort_cmd_wqe abort_cmd; 4955 struct cmf_sync_wqe cmf_sync; 4956 struct create_xri_wqe create_xri; 4957 struct xmit_bcast64_wqe xmit_bcast64; 4958 struct xmit_seq64_wqe xmit_sequence; 4959 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 4960 struct xmit_els_rsp64_wqe xmit_els_rsp; 4961 struct els_request64_wqe els_req; 4962 struct gen_req64_wqe gen_req; 4963 struct fcp_trsp64_wqe fcp_trsp; 4964 struct fcp_tsend64_wqe fcp_tsend; 4965 struct fcp_treceive64_wqe fcp_treceive; 4966 struct send_frame_wqe send_frame; 4967}; 4968 4969#define MAGIC_NUMBER_G6 0xFEAA0003 4970#define MAGIC_NUMBER_G7 0xFEAA0005 4971#define MAGIC_NUMBER_G7P 0xFEAA0020 4972 4973struct lpfc_grp_hdr { 4974 uint32_t size; 4975 uint32_t magic_number; 4976 uint32_t word2; 4977#define lpfc_grp_hdr_file_type_SHIFT 24 4978#define lpfc_grp_hdr_file_type_MASK 0x000000FF 4979#define lpfc_grp_hdr_file_type_WORD word2 4980#define lpfc_grp_hdr_id_SHIFT 16 4981#define lpfc_grp_hdr_id_MASK 0x000000FF 4982#define lpfc_grp_hdr_id_WORD word2 4983 uint8_t rev_name[128]; 4984 uint8_t date[12]; 4985 uint8_t revision[32]; 4986}; 4987 4988/* Defines for WQE command type */ 4989#define FCP_COMMAND 0x0 4990#define NVME_READ_CMD 0x0 4991#define FCP_COMMAND_DATA_OUT 0x1 4992#define NVME_WRITE_CMD 0x1 4993#define COMMAND_DATA_IN 0x0 4994#define COMMAND_DATA_OUT 0x1 4995#define FCP_COMMAND_TRECEIVE 0x2 4996#define FCP_COMMAND_TRSP 0x3 4997#define FCP_COMMAND_TSEND 0x7 4998#define OTHER_COMMAND 0x8 4999#define CMF_SYNC_COMMAND 0xA 5000#define ELS_COMMAND_NON_FIP 0xC 5001#define ELS_COMMAND_FIP 0xD 5002 5003#define LPFC_NVME_EMBED_CMD 0x0 5004#define LPFC_NVME_EMBED_WRITE 0x1 5005#define LPFC_NVME_EMBED_READ 0x2 5006 5007/* WQE Commands */ 5008#define CMD_ABORT_XRI_WQE 0x0F 5009#define CMD_XMIT_SEQUENCE64_WQE 0x82 5010#define CMD_XMIT_BCAST64_WQE 0x84 5011#define CMD_ELS_REQUEST64_WQE 0x8A 5012#define CMD_XMIT_ELS_RSP64_WQE 0x95 5013#define CMD_XMIT_BLS_RSP64_WQE 0x97 5014#define CMD_FCP_IWRITE64_WQE 0x98 5015#define CMD_FCP_IREAD64_WQE 0x9A 5016#define CMD_FCP_ICMND64_WQE 0x9C 5017#define CMD_FCP_TSEND64_WQE 0x9F 5018#define CMD_FCP_TRECEIVE64_WQE 0xA1 5019#define CMD_FCP_TRSP64_WQE 0xA3 5020#define CMD_GEN_REQUEST64_WQE 0xC2 5021#define CMD_CMF_SYNC_WQE 0xE8 5022 5023#define CMD_WQE_MASK 0xff 5024 5025 5026#define LPFC_FW_DUMP 1 5027#define LPFC_FW_RESET 2 5028#define LPFC_DV_RESET 3 5029 5030/* On some kernels, enum fc_ls_tlv_dtag does not have 5031 * these 2 enums defined, on other kernels it does. 5032 * To get aound this we need to add these 2 defines here. 5033 */ 5034#ifndef ELS_DTAG_LNK_FAULT_CAP 5035#define ELS_DTAG_LNK_FAULT_CAP 0x0001000D 5036#endif 5037#ifndef ELS_DTAG_CG_SIGNAL_CAP 5038#define ELS_DTAG_CG_SIGNAL_CAP 0x0001000F 5039#endif 5040 5041/* 5042 * Initializer useful for decoding FPIN string table. 5043 */ 5044#define FC_FPIN_CONGN_SEVERITY_INIT { \ 5045 { FPIN_CONGN_SEVERITY_WARNING, "Warning" }, \ 5046 { FPIN_CONGN_SEVERITY_ERROR, "Alarm" }, \ 5047} 5048 5049/* Used for logging FPIN messages */ 5050#define LPFC_FPIN_WWPN_LINE_SZ 128 5051#define LPFC_FPIN_WWPN_LINE_CNT 6 5052#define LPFC_FPIN_WWPN_NUM_LINE 6
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