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lpfc_hw.h
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linux-6.19.14/drivers/scsi/lpfc/lpfc_hw.h
1/******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2017-2025 Broadcom. All Rights Reserved. The term * 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. * 6 * Copyright (C) 2004-2016 Emulex. All rights reserved. * 7 * EMULEX and SLI are trademarks of Emulex. * 8 * www.broadcom.com * 9 * * 10 * This program is free software; you can redistribute it and/or * 11 * modify it under the terms of version 2 of the GNU General * 12 * Public License as published by the Free Software Foundation. * 13 * This program is distributed in the hope that it will be useful. * 14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 18 * TO BE LEGALLY INVALID. See the GNU General Public License for * 19 * more details, a copy of which can be found in the file COPYING * 20 * included with this package. * 21 *******************************************************************/ 22 23#define FDMI_DID 0xfffffaU 24#define NameServer_DID 0xfffffcU 25#define Fabric_Cntl_DID 0xfffffdU 26#define Fabric_DID 0xfffffeU 27#define Bcast_DID 0xffffffU 28#define Mask_DID 0xffffffU 29#define CT_DID_MASK 0xffff00U 30#define Fabric_DID_MASK 0xfff000U 31#define WELL_KNOWN_DID_MASK 0xfffff0U 32 33#define PT2PT_LocalID 1 34#define PT2PT_RemoteID 2 35 36#define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */ 37#define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */ 38#define FF_DEF_RATOV 10 /* Default RA_TOV (10s) */ 39#define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */ 40 41#define LPFC_BUF_RING0 64 /* Number of buffers to post to RING 42 0 */ 43 44#define FCELSSIZE 1024 /* maximum ELS transfer size */ 45 46#define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */ 47#define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */ 48#define LPFC_ELS_RING 2 /* ring 2 for ELS commands */ 49 50#define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */ 51#define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */ 52#define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */ 53#define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */ 54#define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */ 55#define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */ 56#define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */ 57#define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */ 58#define SLI2_IOCB_CMD_R3_ENTRIES 0 59#define SLI2_IOCB_RSP_R3_ENTRIES 0 60#define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24 61#define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32 62 63#define SLI2_IOCB_CMD_SIZE 32 64#define SLI2_IOCB_RSP_SIZE 32 65#define SLI3_IOCB_CMD_SIZE 128 66#define SLI3_IOCB_RSP_SIZE 64 67 68#define LPFC_UNREG_ALL_RPIS_VPORT 0xffff 69#define LPFC_UNREG_ALL_DFLT_RPIS 0xffffffff 70 71/* vendor ID used in SCSI netlink calls */ 72#define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX) 73 74#define FW_REV_STR_SIZE 32 75/* Common Transport structures and definitions */ 76 77union CtRevisionId { 78 /* Structure is in Big Endian format */ 79 struct { 80 uint32_t Revision:8; 81 uint32_t InId:24; 82 } bits; 83 uint32_t word; 84}; 85 86union CtCommandResponse { 87 /* Structure is in Big Endian format */ 88 struct { 89 __be16 CmdRsp; 90 __be16 Size; 91 } bits; 92 uint32_t word; 93}; 94 95/* FC4 Feature bits for RFF_ID */ 96#define FC4_FEATURE_TARGET 0x1 97#define FC4_FEATURE_INIT 0x2 98#define FC4_FEATURE_NVME_DISC 0x4 99 100enum rft_word0 { 101 RFT_FCP_REG = (0x1 << 8), 102}; 103 104enum rft_word1 { 105 RFT_NVME_REG = (0x1 << 8), 106}; 107 108enum rft_word3 { 109 RFT_APP_SERV_REG = (0x1 << 0), 110}; 111 112struct lpfc_sli_ct_request { 113 /* Structure is in Big Endian format */ 114 union CtRevisionId RevisionId; 115 uint8_t FsType; 116 uint8_t FsSubType; 117 uint8_t Options; 118 uint8_t Rsrvd1; 119 union CtCommandResponse CommandResponse; 120 uint8_t Rsrvd2; 121 uint8_t ReasonCode; 122 uint8_t Explanation; 123 uint8_t VendorUnique; 124#define LPFC_CT_PREAMBLE 20 /* Size of CTReq + 4 up to here */ 125 126 union { 127 __be32 PortID; 128 struct gid { 129 uint8_t PortType; /* for GID_PT requests */ 130#define GID_PT_N_PORT 1 131 uint8_t DomainScope; 132 uint8_t AreaScope; 133 uint8_t Fc4Type; /* for GID_FT requests */ 134 } gid; 135 struct gid_ff { 136 uint8_t Flags; 137 uint8_t DomainScope; 138 uint8_t AreaScope; 139 uint8_t rsvd1; 140 uint8_t rsvd2; 141 uint8_t rsvd3; 142 uint8_t Fc4FBits; 143 uint8_t Fc4Type; 144 } gid_ff; 145 struct rft { 146 __be32 port_id; /* For RFT_ID requests */ 147 148 __be32 fcp_reg; /* rsvd 31:9, fcp_reg 8, rsvd 7:0 */ 149 __be32 nvme_reg; /* rsvd 31:9, nvme_reg 8, rsvd 7:0 */ 150 __be32 word2; 151 __be32 app_serv_reg; /* rsvd 31:1, app_serv_reg 0 */ 152 __be32 word[4]; 153 } rft; 154 struct rnn { 155 uint32_t PortId; /* For RNN_ID requests */ 156 uint8_t wwnn[8]; 157 } rnn; 158 struct rsnn { /* For RSNN_ID requests */ 159 uint8_t wwnn[8]; 160 uint8_t len; 161 uint8_t symbname[255]; 162 } rsnn; 163 struct da_id { /* For DA_ID requests */ 164 uint32_t port_id; 165 } da_id; 166 struct rspn { /* For RSPN_ID requests */ 167 uint32_t PortId; 168 uint8_t len; 169 uint8_t symbname[255]; 170 } rspn; 171 struct rspni { /* For RSPNI_PNI requests */ 172 __be64 pni; 173 u8 len; 174 u8 symbname[255]; 175 } rspni; 176 struct gff { 177 uint32_t PortId; 178 } gff; 179 struct gff_acc { 180 uint8_t fbits[128]; 181 } gff_acc; 182 struct gft { 183 uint32_t PortId; 184 } gft; 185 struct gft_acc { 186 uint32_t fc4_types[8]; 187 } gft_acc; 188#define FCP_TYPE_FEATURE_OFFSET 7 189 struct rff { 190 uint32_t PortId; 191 uint8_t reserved[2]; 192 uint8_t fbits; 193 uint8_t type_code; /* type=8 for FCP */ 194 } rff; 195 } un; 196}; 197 198#define LPFC_MAX_CT_SIZE (60 * 4096) 199 200#define SLI_CT_REVISION 1 201#define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 202 sizeof(struct gid)) 203#define GIDFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 204 sizeof(struct gid_ff)) 205#define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 206 sizeof(struct gff)) 207#define GFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 208 sizeof(struct gft)) 209#define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 210 sizeof(struct rft)) 211#define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 212 sizeof(struct rff)) 213#define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 214 sizeof(struct rnn)) 215#define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 216 sizeof(struct rsnn)) 217#define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 218 sizeof(struct da_id)) 219#define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 220 sizeof(struct rspn)) 221#define RSPNI_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 222 sizeof(struct rspni)) 223 224/* 225 * FsType Definitions 226 */ 227 228#define SLI_CT_MANAGEMENT_SERVICE 0xFA 229#define SLI_CT_TIME_SERVICE 0xFB 230#define SLI_CT_DIRECTORY_SERVICE 0xFC 231#define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD 232 233/* 234 * Directory Service Subtypes 235 */ 236 237#define SLI_CT_DIRECTORY_NAME_SERVER 0x02 238 239/* 240 * Response Codes 241 */ 242 243#define SLI_CT_RESPONSE_FS_RJT 0x8001 244#define SLI_CT_RESPONSE_FS_ACC 0x8002 245 246/* 247 * Reason Codes 248 */ 249 250#define SLI_CT_NO_ADDITIONAL_EXPL 0x0 251#define SLI_CT_INVALID_COMMAND 0x01 252#define SLI_CT_INVALID_VERSION 0x02 253#define SLI_CT_LOGICAL_ERROR 0x03 254#define SLI_CT_INVALID_IU_SIZE 0x04 255#define SLI_CT_LOGICAL_BUSY 0x05 256#define SLI_CT_PROTOCOL_ERROR 0x07 257#define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09 258#define SLI_CT_REQ_NOT_SUPPORTED 0x0b 259#define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10 260#define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11 261#define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12 262#define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13 263#define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20 264#define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21 265#define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22 266#define SLI_CT_VENDOR_UNIQUE 0xff 267 268/* 269 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations 270 */ 271 272#define SLI_CT_NO_PORT_ID 0x01 273#define SLI_CT_NO_PORT_NAME 0x02 274#define SLI_CT_NO_NODE_NAME 0x03 275#define SLI_CT_NO_CLASS_OF_SERVICE 0x04 276#define SLI_CT_NO_IP_ADDRESS 0x05 277#define SLI_CT_NO_IPA 0x06 278#define SLI_CT_NO_FC4_TYPES 0x07 279#define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08 280#define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09 281#define SLI_CT_NO_PORT_TYPE 0x0A 282#define SLI_CT_ACCESS_DENIED 0x10 283#define SLI_CT_INVALID_PORT_ID 0x11 284#define SLI_CT_DATABASE_EMPTY 0x12 285#define SLI_CT_APP_ID_NOT_AVAILABLE 0x40 286 287/* 288 * Name Server Command Codes 289 */ 290 291#define SLI_CTNS_GA_NXT 0x0100 292#define SLI_CTNS_GPN_ID 0x0112 293#define SLI_CTNS_GNN_ID 0x0113 294#define SLI_CTNS_GCS_ID 0x0114 295#define SLI_CTNS_GFT_ID 0x0117 296#define SLI_CTNS_GSPN_ID 0x0118 297#define SLI_CTNS_GPT_ID 0x011A 298#define SLI_CTNS_GFF_ID 0x011F 299#define SLI_CTNS_GID_PN 0x0121 300#define SLI_CTNS_GID_NN 0x0131 301#define SLI_CTNS_GIP_NN 0x0135 302#define SLI_CTNS_GIPA_NN 0x0136 303#define SLI_CTNS_GSNN_NN 0x0139 304#define SLI_CTNS_GNN_IP 0x0153 305#define SLI_CTNS_GIPA_IP 0x0156 306#define SLI_CTNS_GID_FT 0x0171 307#define SLI_CTNS_GID_FF 0x01F1 308#define SLI_CTNS_GID_PT 0x01A1 309#define SLI_CTNS_RPN_ID 0x0212 310#define SLI_CTNS_RNN_ID 0x0213 311#define SLI_CTNS_RCS_ID 0x0214 312#define SLI_CTNS_RFT_ID 0x0217 313#define SLI_CTNS_RSPN_ID 0x0218 314#define SLI_CTNS_RPT_ID 0x021A 315#define SLI_CTNS_RFF_ID 0x021F 316#define SLI_CTNS_RIP_NN 0x0235 317#define SLI_CTNS_RIPA_NN 0x0236 318#define SLI_CTNS_RSNN_NN 0x0239 319#define SLI_CTNS_RSPNI_PNI 0x0240 320#define SLI_CTNS_DA_ID 0x0300 321 322/* 323 * Port Types 324 */ 325 326#define SLI_CTPT_N_PORT 0x01 327#define SLI_CTPT_NL_PORT 0x02 328#define SLI_CTPT_FNL_PORT 0x03 329#define SLI_CTPT_IP 0x04 330#define SLI_CTPT_FCP 0x08 331#define SLI_CTPT_NVME 0x28 332#define SLI_CTPT_NX_PORT 0x7F 333#define SLI_CTPT_F_PORT 0x81 334#define SLI_CTPT_FL_PORT 0x82 335#define SLI_CTPT_E_PORT 0x84 336 337#define SLI_CT_LAST_ENTRY 0x80000000 338 339/* Fibre Channel Service Parameter definitions */ 340 341#define FC_PH_4_0 6 /* FC-PH version 4.0 */ 342#define FC_PH_4_1 7 /* FC-PH version 4.1 */ 343#define FC_PH_4_2 8 /* FC-PH version 4.2 */ 344#define FC_PH_4_3 9 /* FC-PH version 4.3 */ 345 346#define FC_PH_LOW 8 /* Lowest supported FC-PH version */ 347#define FC_PH_HIGH 9 /* Highest supported FC-PH version */ 348#define FC_PH3 0x20 /* FC-PH-3 version */ 349 350#define FF_FRAME_SIZE 2048 351 352struct lpfc_name { 353 union { 354 struct { 355#ifdef __BIG_ENDIAN_BITFIELD 356 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 357 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 358 8:11 of IEEE ext */ 359#else /* __LITTLE_ENDIAN_BITFIELD */ 360 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 361 8:11 of IEEE ext */ 362 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 363#endif 364 365#define NAME_IEEE 0x1 /* IEEE name - nameType */ 366#define NAME_IEEE_EXT 0x2 /* IEEE extended name */ 367#define NAME_FC_TYPE 0x3 /* FC native name type */ 368#define NAME_IP_TYPE 0x4 /* IP address */ 369#define NAME_CCITT_TYPE 0xC 370#define NAME_CCITT_GR_TYPE 0xE 371 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE 372 extended Lsb */ 373 uint8_t IEEE[6]; /* FC IEEE address */ 374 } s; 375 uint8_t wwn[8]; 376 uint64_t name __packed __aligned(4); 377 __be64 wwn_be __packed __aligned(4); 378 } u; 379}; 380 381struct csp { 382 uint8_t fcphHigh; /* FC Word 0, byte 0 */ 383 uint8_t fcphLow; 384 uint8_t bbCreditMsb; 385 uint8_t bbCreditLsb; /* FC Word 0, byte 3 */ 386 387/* 388 * Word 1 Bit 31 in common service parameter is overloaded. 389 * Word 1 Bit 31 in FLOGI request is multiple NPort request 390 * Word 1 Bit 31 in FLOGI response is clean address bit 391 */ 392#define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */ 393/* 394 * Word 1 Bit 30 in common service parameter is overloaded. 395 * Word 1 Bit 30 in FLOGI request is Virtual Fabrics 396 * Word 1 Bit 30 in PLOGI request is random offset 397 */ 398#define virtual_fabric_support randomOffset /* Word 1, bit 30 */ 399/* 400 * Word 1 Bit 29 in common service parameter is overloaded. 401 * Word 1 Bit 29 in FLOGI response is multiple NPort assignment 402 * Word 1 Bit 29 in FLOGI/PLOGI request is Valid Vendor Version Level 403 */ 404#define valid_vendor_ver_level response_multiple_NPort /* Word 1, bit 29 */ 405#ifdef __BIG_ENDIAN_BITFIELD 406 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */ 407 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 408 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */ 409 uint16_t fPort:1; /* FC Word 1, bit 28 */ 410 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 411 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 412 uint16_t multicast:1; /* FC Word 1, bit 25 */ 413 uint16_t app_hdr_support:1; /* FC Word 1, bit 24 */ 414 415 uint16_t priority_tagging:1; /* FC Word 1, bit 23 */ 416 uint16_t simplex:1; /* FC Word 1, bit 22 */ 417 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 418 uint16_t dhd:1; /* FC Word 1, bit 18 */ 419 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 420 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 421#else /* __LITTLE_ENDIAN_BITFIELD */ 422 uint16_t app_hdr_support:1; /* FC Word 1, bit 24 */ 423 uint16_t multicast:1; /* FC Word 1, bit 25 */ 424 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 425 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 426 uint16_t fPort:1; /* FC Word 1, bit 28 */ 427 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */ 428 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 429 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */ 430 431 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 432 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 433 uint16_t dhd:1; /* FC Word 1, bit 18 */ 434 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 435 uint16_t simplex:1; /* FC Word 1, bit 22 */ 436 uint16_t priority_tagging:1; /* FC Word 1, bit 23 */ 437#endif 438 439 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */ 440 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */ 441 union { 442 struct { 443 uint8_t word2Reserved1; /* FC Word 2 byte 0 */ 444 445 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */ 446 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */ 447 448 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */ 449 } nPort; 450 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */ 451 } w2; 452 453 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */ 454}; 455 456struct class_parms { 457#ifdef __BIG_ENDIAN_BITFIELD 458 uint8_t classValid:1; /* FC Word 0, bit 31 */ 459 uint8_t intermix:1; /* FC Word 0, bit 30 */ 460 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 461 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 462 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 463 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 464#else /* __LITTLE_ENDIAN_BITFIELD */ 465 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 466 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 467 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 468 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 469 uint8_t intermix:1; /* FC Word 0, bit 30 */ 470 uint8_t classValid:1; /* FC Word 0, bit 31 */ 471 472#endif 473 474 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */ 475 476#ifdef __BIG_ENDIAN_BITFIELD 477 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 478 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 479 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 480 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 481 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 482#else /* __LITTLE_ENDIAN_BITFIELD */ 483 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 484 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 485 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 486 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 487 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 488#endif 489 490 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */ 491 492#ifdef __BIG_ENDIAN_BITFIELD 493 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 494 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 495 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 496 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 497 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 498 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 499#else /* __LITTLE_ENDIAN_BITFIELD */ 500 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 501 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 502 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 503 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 504 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 505 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 506#endif 507 508 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */ 509 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */ 510 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */ 511 512 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */ 513 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */ 514 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */ 515 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */ 516 517 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */ 518 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */ 519 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */ 520 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */ 521}; 522 523enum aux_parm_flags { 524 AUX_PARM_PNI_VALID = 0x20, /* FC Word 0, bit 29 */ 525 AUX_PARM_DATA_VALID = 0x40, /* FC Word 0, bit 30 */ 526}; 527 528struct aux_parm { 529 u8 flags; /* FC Word 0, bit 31:24 */ 530 u8 ext_feat[3]; /* FC Word 0, bit 23:0 */ 531 532 __be64 pni; /* FC Word 1 and 2, platform name identifier */ 533 534 __be16 rsvd; /* FC Word 3, bit 31:16 */ 535 __be16 npiv_cnt; /* FC Word 3, bit 15:0 */ 536} __packed; 537 538struct serv_parm { /* Structure is in Big Endian format */ 539 struct csp cmn; 540 struct lpfc_name portName; 541 struct lpfc_name nodeName; 542 struct class_parms cls1; 543 struct class_parms cls2; 544 struct class_parms cls3; 545 struct aux_parm aux; 546 union { 547 uint8_t vendorVersion[16]; 548 struct { 549 uint32_t vid; 550#define LPFC_VV_EMLX_ID 0x454d4c58 /* EMLX */ 551 uint32_t flags; 552#define LPFC_VV_SUPPRESS_RSP 1 553 } vv; 554 } un; 555}; 556 557/* 558 * Virtual Fabric Tagging Header 559 */ 560struct fc_vft_header { 561 uint32_t word0; 562#define fc_vft_hdr_r_ctl_SHIFT 24 563#define fc_vft_hdr_r_ctl_MASK 0xFF 564#define fc_vft_hdr_r_ctl_WORD word0 565#define fc_vft_hdr_ver_SHIFT 22 566#define fc_vft_hdr_ver_MASK 0x3 567#define fc_vft_hdr_ver_WORD word0 568#define fc_vft_hdr_type_SHIFT 18 569#define fc_vft_hdr_type_MASK 0xF 570#define fc_vft_hdr_type_WORD word0 571#define fc_vft_hdr_e_SHIFT 16 572#define fc_vft_hdr_e_MASK 0x1 573#define fc_vft_hdr_e_WORD word0 574#define fc_vft_hdr_priority_SHIFT 13 575#define fc_vft_hdr_priority_MASK 0x7 576#define fc_vft_hdr_priority_WORD word0 577#define fc_vft_hdr_vf_id_SHIFT 1 578#define fc_vft_hdr_vf_id_MASK 0xFFF 579#define fc_vft_hdr_vf_id_WORD word0 580 uint32_t word1; 581#define fc_vft_hdr_hopct_SHIFT 24 582#define fc_vft_hdr_hopct_MASK 0xFF 583#define fc_vft_hdr_hopct_WORD word1 584}; 585 586#include <uapi/scsi/fc/fc_els.h> 587 588/* 589 * Application Header 590 */ 591struct fc_app_header { 592 uint32_t dst_app_id; 593 uint32_t src_app_id; 594#define LOOPBACK_SRC_APPID 0x4321 595 uint32_t word2; 596 uint32_t word3; 597}; 598 599/* 600 * dfctl optional header definition 601 */ 602enum lpfc_fc_dfctl { 603 LPFC_FC_NO_DEVICE_HEADER, 604 LPFC_FC_16B_DEVICE_HEADER, 605 LPFC_FC_32B_DEVICE_HEADER, 606 LPFC_FC_64B_DEVICE_HEADER, 607}; 608 609/* 610 * Extended Link Service LS_COMMAND codes (Payload Word 0) 611 */ 612#ifdef __BIG_ENDIAN_BITFIELD 613#define ELS_CMD_MASK 0xffff0000 614#define ELS_RSP_MASK 0xff000000 615#define ELS_CMD_LS_RJT 0x01000000 616#define ELS_CMD_ACC 0x02000000 617#define ELS_CMD_PLOGI 0x03000000 618#define ELS_CMD_FLOGI 0x04000000 619#define ELS_CMD_LOGO 0x05000000 620#define ELS_CMD_ABTX 0x06000000 621#define ELS_CMD_RCS 0x07000000 622#define ELS_CMD_RES 0x08000000 623#define ELS_CMD_RSS 0x09000000 624#define ELS_CMD_RSI 0x0A000000 625#define ELS_CMD_ESTS 0x0B000000 626#define ELS_CMD_ESTC 0x0C000000 627#define ELS_CMD_ADVC 0x0D000000 628#define ELS_CMD_RTV 0x0E000000 629#define ELS_CMD_RLS 0x0F000000 630#define ELS_CMD_ECHO 0x10000000 631#define ELS_CMD_TEST 0x11000000 632#define ELS_CMD_RRQ 0x12000000 633#define ELS_CMD_REC 0x13000000 634#define ELS_CMD_RDP 0x18000000 635#define ELS_CMD_RDF 0x19000000 636#define ELS_CMD_PRLI 0x20100014 637#define ELS_CMD_NVMEPRLI 0x20140018 638#define ELS_CMD_PRLO 0x21100014 639#define ELS_CMD_PRLO_ACC 0x02100014 640#define ELS_CMD_PDISC 0x50000000 641#define ELS_CMD_FDISC 0x51000000 642#define ELS_CMD_ADISC 0x52000000 643#define ELS_CMD_FARP 0x54000000 644#define ELS_CMD_FARPR 0x55000000 645#define ELS_CMD_RPL 0x57000000 646#define ELS_CMD_FAN 0x60000000 647#define ELS_CMD_RSCN 0x61040000 648#define ELS_CMD_RSCN_XMT 0x61040008 649#define ELS_CMD_SCR 0x62000000 650#define ELS_CMD_RNID 0x78000000 651#define ELS_CMD_LIRR 0x7A000000 652#define ELS_CMD_LCB 0x81000000 653#define ELS_CMD_FPIN 0x16000000 654#define ELS_CMD_EDC 0x17000000 655#define ELS_CMD_QFPA 0xB0000000 656#define ELS_CMD_UVEM 0xB1000000 657#else /* __LITTLE_ENDIAN_BITFIELD */ 658#define ELS_CMD_MASK 0xffff 659#define ELS_RSP_MASK 0xff 660#define ELS_CMD_LS_RJT 0x01 661#define ELS_CMD_ACC 0x02 662#define ELS_CMD_PLOGI 0x03 663#define ELS_CMD_FLOGI 0x04 664#define ELS_CMD_LOGO 0x05 665#define ELS_CMD_ABTX 0x06 666#define ELS_CMD_RCS 0x07 667#define ELS_CMD_RES 0x08 668#define ELS_CMD_RSS 0x09 669#define ELS_CMD_RSI 0x0A 670#define ELS_CMD_ESTS 0x0B 671#define ELS_CMD_ESTC 0x0C 672#define ELS_CMD_ADVC 0x0D 673#define ELS_CMD_RTV 0x0E 674#define ELS_CMD_RLS 0x0F 675#define ELS_CMD_ECHO 0x10 676#define ELS_CMD_TEST 0x11 677#define ELS_CMD_RRQ 0x12 678#define ELS_CMD_REC 0x13 679#define ELS_CMD_RDP 0x18 680#define ELS_CMD_RDF 0x19 681#define ELS_CMD_PRLI 0x14001020 682#define ELS_CMD_NVMEPRLI 0x18001420 683#define ELS_CMD_PRLO 0x14001021 684#define ELS_CMD_PRLO_ACC 0x14001002 685#define ELS_CMD_PDISC 0x50 686#define ELS_CMD_FDISC 0x51 687#define ELS_CMD_ADISC 0x52 688#define ELS_CMD_FARP 0x54 689#define ELS_CMD_FARPR 0x55 690#define ELS_CMD_RPL 0x57 691#define ELS_CMD_FAN 0x60 692#define ELS_CMD_RSCN 0x0461 693#define ELS_CMD_RSCN_XMT 0x08000461 694#define ELS_CMD_SCR 0x62 695#define ELS_CMD_RNID 0x78 696#define ELS_CMD_LIRR 0x7A 697#define ELS_CMD_LCB 0x81 698#define ELS_CMD_FPIN ELS_FPIN 699#define ELS_CMD_EDC ELS_EDC 700#define ELS_CMD_QFPA 0xB0 701#define ELS_CMD_UVEM 0xB1 702#endif 703 704/* 705 * LS_RJT Payload Definition 706 */ 707 708struct ls_rjt { /* Structure is in Big Endian format */ 709 union { 710 __be32 ls_rjt_error_be; 711 uint32_t lsRjtError; 712 struct { 713 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */ 714 715 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */ 716 /* LS_RJT reason codes */ 717#define LSRJT_INVALID_CMD 0x01 718#define LSRJT_LOGICAL_ERR 0x03 719#define LSRJT_LOGICAL_BSY 0x05 720#define LSRJT_PROTOCOL_ERR 0x07 721#define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */ 722#define LSRJT_CMD_UNSUPPORTED 0x0B 723#define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */ 724 725 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */ 726 /* LS_RJT reason explanation */ 727#define LSEXP_NOTHING_MORE 0x00 728#define LSEXP_SPARM_OPTIONS 0x01 729#define LSEXP_SPARM_ICTL 0x03 730#define LSEXP_SPARM_RCTL 0x05 731#define LSEXP_SPARM_RCV_SIZE 0x07 732#define LSEXP_SPARM_CONCUR_SEQ 0x09 733#define LSEXP_SPARM_CREDIT 0x0B 734#define LSEXP_INVALID_PNAME 0x0D 735#define LSEXP_INVALID_NNAME 0x0E 736#define LSEXP_INVALID_CSP 0x0F 737#define LSEXP_INVALID_ASSOC_HDR 0x11 738#define LSEXP_ASSOC_HDR_REQ 0x13 739#define LSEXP_INVALID_O_SID 0x15 740#define LSEXP_INVALID_OX_RX 0x17 741#define LSEXP_CMD_IN_PROGRESS 0x19 742#define LSEXP_PORT_LOGIN_REQ 0x1E 743#define LSEXP_INVALID_NPORT_ID 0x1F 744#define LSEXP_INVALID_SEQ_ID 0x21 745#define LSEXP_INVALID_XCHG 0x23 746#define LSEXP_INACTIVE_XCHG 0x25 747#define LSEXP_RQ_REQUIRED 0x27 748#define LSEXP_OUT_OF_RESOURCE 0x29 749#define LSEXP_CANT_GIVE_DATA 0x2A 750#define LSEXP_REQ_UNSUPPORTED 0x2C 751#define LSEXP_AUTH_REQ 0x48 752#define LSEXP_NO_RSRC_ASSIGN 0x52 753 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */ 754 } b; 755 } un; 756}; 757 758/* 759 * N_Port Login (FLOGO/PLOGO Request) Payload Definition 760 */ 761 762typedef struct _LOGO { /* Structure is in Big Endian format */ 763 union { 764 uint32_t nPortId32; /* Access nPortId as a word */ 765 struct { 766 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */ 767 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */ 768 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */ 769 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */ 770 } b; 771 } un; 772 struct lpfc_name portName; /* N_port name field */ 773} LOGO; 774 775/* 776 * FCP Login (PRLI Request / ACC) Payload Definition 777 */ 778 779#define PRLX_PAGE_LEN 0x10 780#define TPRLO_PAGE_LEN 0x14 781 782typedef struct _PRLI { /* Structure is in Big Endian format */ 783 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */ 784 785#define PRLI_FCP_TYPE 0x08 786#define PRLI_NVME_TYPE 0x28 787 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 788 789#ifdef __BIG_ENDIAN_BITFIELD 790 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 791 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 792 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 793 794 /* ACC = imagePairEstablished */ 795 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 796 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 797#else /* __LITTLE_ENDIAN_BITFIELD */ 798 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 799 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 800 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 801 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 802 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 803 /* ACC = imagePairEstablished */ 804#endif 805 806#define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */ 807#define PRLI_NO_RESOURCES 0x2 808#define PRLI_INIT_INCOMPLETE 0x3 809#define PRLI_NO_SUCH_PA 0x4 810#define PRLI_PREDEF_CONFIG 0x5 811#define PRLI_PARTIAL_SUCCESS 0x6 812#define PRLI_INVALID_PAGE_CNT 0x7 813#define PRLI_INV_SRV_PARM 0x8 814 815 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 816 817 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 818 819 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 820 821 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */ 822 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */ 823 824#ifdef __BIG_ENDIAN_BITFIELD 825 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 826 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 827 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 828 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 829 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 830 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 831 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 832 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 833 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 834 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 835 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 836 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 837 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 838 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 839 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 840 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 841#else /* __LITTLE_ENDIAN_BITFIELD */ 842 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 843 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 844 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 845 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 846 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 847 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 848 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 849 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 850 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 851 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 852 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 853 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 854 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 855 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 856 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 857 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 858#endif 859} PRLI; 860 861/* 862 * FCP Logout (PRLO Request / ACC) Payload Definition 863 */ 864 865typedef struct _PRLO { /* Structure is in Big Endian format */ 866 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */ 867 868#define PRLO_FCP_TYPE 0x08 869 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 870 871#ifdef __BIG_ENDIAN_BITFIELD 872 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 873 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 874 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 875 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 876#else /* __LITTLE_ENDIAN_BITFIELD */ 877 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 878 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 879 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 880 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 881#endif 882 883#define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */ 884#define PRLO_NO_SUCH_IMAGE 0x4 885#define PRLO_INVALID_PAGE_CNT 0x7 886 887 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 888 889 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 890 891 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 892 893 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */ 894} PRLO; 895 896typedef struct _ADISC { /* Structure is in Big Endian format */ 897 uint32_t hardAL_PA; 898 struct lpfc_name portName; 899 struct lpfc_name nodeName; 900 uint32_t DID; 901} ADISC; 902 903typedef struct _FARP { /* Structure is in Big Endian format */ 904 uint32_t Mflags:8; 905 uint32_t Odid:24; 906#define FARP_NO_ACTION 0 /* FARP information enclosed, no 907 action */ 908#define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */ 909#define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */ 910#define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */ 911#define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not 912 supported */ 913#define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not 914 supported */ 915 uint32_t Rflags:8; 916 uint32_t Rdid:24; 917#define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */ 918#define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */ 919 struct lpfc_name OportName; 920 struct lpfc_name OnodeName; 921 struct lpfc_name RportName; 922 struct lpfc_name RnodeName; 923 uint8_t Oipaddr[16]; 924 uint8_t Ripaddr[16]; 925} FARP; 926 927typedef struct _FAN { /* Structure is in Big Endian format */ 928 uint32_t Fdid; 929 struct lpfc_name FportName; 930 struct lpfc_name FnodeName; 931} FAN; 932 933typedef struct _SCR { /* Structure is in Big Endian format */ 934 uint8_t resvd1; 935 uint8_t resvd2; 936 uint8_t resvd3; 937 uint8_t Function; 938#define SCR_FUNC_FABRIC 0x01 939#define SCR_FUNC_NPORT 0x02 940#define SCR_FUNC_FULL 0x03 941#define SCR_CLEAR 0xff 942} SCR; 943 944typedef struct _RNID_TOP_DISC { 945 struct lpfc_name portName; 946 uint8_t resvd[8]; 947 uint32_t unitType; 948#define RNID_HBA 0x7 949#define RNID_HOST 0xa 950#define RNID_DRIVER 0xd 951 uint32_t physPort; 952 uint32_t attachedNodes; 953 uint16_t ipVersion; 954#define RNID_IPV4 0x1 955#define RNID_IPV6 0x2 956 uint16_t UDPport; 957 uint8_t ipAddr[16]; 958 uint16_t resvd1; 959 uint16_t flags; 960#define RNID_TD_SUPPORT 0x1 961#define RNID_LP_VALID 0x2 962} RNID_TOP_DISC; 963 964typedef struct _RNID { /* Structure is in Big Endian format */ 965 uint8_t Format; 966#define RNID_TOPOLOGY_DISC 0xdf 967 uint8_t CommonLen; 968 uint8_t resvd1; 969 uint8_t SpecificLen; 970 struct lpfc_name portName; 971 struct lpfc_name nodeName; 972 union { 973 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */ 974 } un; 975} RNID; 976 977struct RLS { /* Structure is in Big Endian format */ 978 uint32_t rls; 979#define rls_rsvd_SHIFT 24 980#define rls_rsvd_MASK 0x000000ff 981#define rls_rsvd_WORD rls 982#define rls_did_SHIFT 0 983#define rls_did_MASK 0x00ffffff 984#define rls_did_WORD rls 985}; 986 987struct RLS_RSP { /* Structure is in Big Endian format */ 988 uint32_t linkFailureCnt; 989 uint32_t lossSyncCnt; 990 uint32_t lossSignalCnt; 991 uint32_t primSeqErrCnt; 992 uint32_t invalidXmitWord; 993 uint32_t crcCnt; 994}; 995 996struct RRQ { /* Structure is in Big Endian format */ 997 uint32_t rrq; 998#define rrq_rsvd_SHIFT 24 999#define rrq_rsvd_MASK 0x000000ff 1000#define rrq_rsvd_WORD rrq 1001#define rrq_did_SHIFT 0 1002#define rrq_did_MASK 0x00ffffff 1003#define rrq_did_WORD rrq 1004 uint32_t rrq_exchg; 1005#define rrq_oxid_SHIFT 16 1006#define rrq_oxid_MASK 0xffff 1007#define rrq_oxid_WORD rrq_exchg 1008#define rrq_rxid_SHIFT 0 1009#define rrq_rxid_MASK 0xffff 1010#define rrq_rxid_WORD rrq_exchg 1011}; 1012 1013#define LPFC_MAX_VFN_PER_PFN 255 /* Maximum VFs allowed per ARI */ 1014#define LPFC_DEF_VFN_PER_PFN 0 /* Default VFs due to platform limitation*/ 1015 1016struct RTV_RSP { /* Structure is in Big Endian format */ 1017 uint32_t ratov; 1018 uint32_t edtov; 1019 uint32_t qtov; 1020#define qtov_rsvd0_SHIFT 28 1021#define qtov_rsvd0_MASK 0x0000000f 1022#define qtov_rsvd0_WORD qtov /* reserved */ 1023#define qtov_edtovres_SHIFT 27 1024#define qtov_edtovres_MASK 0x00000001 1025#define qtov_edtovres_WORD qtov /* E_D_TOV Resolution */ 1026#define qtov__rsvd1_SHIFT 19 1027#define qtov_rsvd1_MASK 0x0000003f 1028#define qtov_rsvd1_WORD qtov /* reserved */ 1029#define qtov_rttov_SHIFT 18 1030#define qtov_rttov_MASK 0x00000001 1031#define qtov_rttov_WORD qtov /* R_T_TOV value */ 1032#define qtov_rsvd2_SHIFT 0 1033#define qtov_rsvd2_MASK 0x0003ffff 1034#define qtov_rsvd2_WORD qtov /* reserved */ 1035}; 1036 1037 1038typedef struct _RPL { /* Structure is in Big Endian format */ 1039 uint32_t maxsize; 1040 uint32_t index; 1041} RPL; 1042 1043typedef struct _PORT_NUM_BLK { 1044 uint32_t portNum; 1045 uint32_t portID; 1046 struct lpfc_name portName; 1047} PORT_NUM_BLK; 1048 1049typedef struct _RPL_RSP { /* Structure is in Big Endian format */ 1050 uint32_t listLen; 1051 uint32_t index; 1052 PORT_NUM_BLK port_num_blk; 1053} RPL_RSP; 1054 1055/* This is used for RSCN command */ 1056typedef struct _D_ID { /* Structure is in Big Endian format */ 1057 union { 1058 uint32_t word; 1059 struct { 1060#ifdef __BIG_ENDIAN_BITFIELD 1061 uint8_t resv; 1062 uint8_t domain; 1063 uint8_t area; 1064 uint8_t id; 1065#else /* __LITTLE_ENDIAN_BITFIELD */ 1066 uint8_t id; 1067 uint8_t area; 1068 uint8_t domain; 1069 uint8_t resv; 1070#endif 1071 } b; 1072 } un; 1073} D_ID; 1074 1075#define RSCN_ADDRESS_FORMAT_PORT 0x0 1076#define RSCN_ADDRESS_FORMAT_AREA 0x1 1077#define RSCN_ADDRESS_FORMAT_DOMAIN 0x2 1078#define RSCN_ADDRESS_FORMAT_FABRIC 0x3 1079#define RSCN_ADDRESS_FORMAT_MASK 0x3 1080 1081/* 1082 * Structure to define all ELS Payload types 1083 */ 1084 1085typedef struct _ELS_PKT { /* Structure is in Big Endian format */ 1086 uint8_t elsCode; /* FC Word 0, bit 24:31 */ 1087 uint8_t elsByte1; 1088 uint8_t elsByte2; 1089 uint8_t elsByte3; 1090 union { 1091 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */ 1092 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */ 1093 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */ 1094 PRLI prli; /* Payload for PRLI/ACC */ 1095 PRLO prlo; /* Payload for PRLO/ACC */ 1096 ADISC adisc; /* Payload for ADISC/ACC */ 1097 FARP farp; /* Payload for FARP/ACC */ 1098 FAN fan; /* Payload for FAN */ 1099 SCR scr; /* Payload for SCR/ACC */ 1100 RNID rnid; /* Payload for RNID */ 1101 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */ 1102 } un; 1103} ELS_PKT; 1104 1105/* 1106 * Link Cable Beacon (LCB) ELS Frame 1107 */ 1108 1109struct fc_lcb_request_frame { 1110 uint32_t lcb_command; /* ELS command opcode (0x81) */ 1111 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */ 1112#define LPFC_LCB_ON 0x1 1113#define LPFC_LCB_OFF 0x2 1114 uint8_t reserved[2]; 1115 uint8_t capability; /* LCB Payload Word 1, bit 0:7 */ 1116 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */ 1117#define LPFC_LCB_GREEN 0x1 1118#define LPFC_LCB_AMBER 0x2 1119 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */ 1120#define LCB_CAPABILITY_DURATION 1 1121#define BEACON_VERSION_V1 1 1122#define BEACON_VERSION_V0 0 1123 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */ 1124}; 1125 1126/* 1127 * Link Cable Beacon (LCB) ELS Response Frame 1128 */ 1129struct fc_lcb_res_frame { 1130 uint32_t lcb_ls_acc; /* Acceptance of LCB request (0x02) */ 1131 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */ 1132 uint8_t reserved[2]; 1133 uint8_t capability; /* LCB Payload Word 1, bit 0:7 */ 1134 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */ 1135 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */ 1136 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */ 1137}; 1138 1139/* 1140 * Read Diagnostic Parameters (RDP) ELS frame. 1141 */ 1142#define SFF_PG0_IDENT_SFP 0x3 1143 1144#define SFP_FLAG_PT_OPTICAL 0x0 1145#define SFP_FLAG_PT_SWLASER 0x01 1146#define SFP_FLAG_PT_LWLASER_LC1310 0x02 1147#define SFP_FLAG_PT_LWLASER_LL1550 0x03 1148#define SFP_FLAG_PT_MASK 0x0F 1149#define SFP_FLAG_PT_SHIFT 0 1150 1151#define SFP_FLAG_IS_OPTICAL_PORT 0x01 1152#define SFP_FLAG_IS_OPTICAL_MASK 0x010 1153#define SFP_FLAG_IS_OPTICAL_SHIFT 4 1154 1155#define SFP_FLAG_IS_DESC_VALID 0x01 1156#define SFP_FLAG_IS_DESC_VALID_MASK 0x020 1157#define SFP_FLAG_IS_DESC_VALID_SHIFT 5 1158 1159#define SFP_FLAG_CT_UNKNOWN 0x0 1160#define SFP_FLAG_CT_SFP_PLUS 0x01 1161#define SFP_FLAG_CT_MASK 0x3C 1162#define SFP_FLAG_CT_SHIFT 6 1163 1164struct fc_rdp_port_name_info { 1165 uint8_t wwnn[8]; 1166 uint8_t wwpn[8]; 1167}; 1168 1169 1170/* 1171 * Link Error Status Block Structure (FC-FS-3) for RDP 1172 * This similar to RPS ELS 1173 */ 1174struct fc_link_status { 1175 uint32_t link_failure_cnt; 1176 uint32_t loss_of_synch_cnt; 1177 uint32_t loss_of_signal_cnt; 1178 uint32_t primitive_seq_proto_err; 1179 uint32_t invalid_trans_word; 1180 uint32_t invalid_crc_cnt; 1181 1182}; 1183 1184#define RDP_PORT_NAMES_DESC_TAG 0x00010003 1185struct fc_rdp_port_name_desc { 1186 uint32_t tag; /* 0001 0003h */ 1187 uint32_t length; /* set to size of payload struct */ 1188 struct fc_rdp_port_name_info port_names; 1189}; 1190 1191 1192struct fc_rdp_fec_info { 1193 uint32_t CorrectedBlocks; 1194 uint32_t UncorrectableBlocks; 1195}; 1196 1197#define RDP_FEC_DESC_TAG 0x00010005 1198struct fc_fec_rdp_desc { 1199 uint32_t tag; 1200 uint32_t length; 1201 struct fc_rdp_fec_info info; 1202}; 1203 1204struct fc_rdp_link_error_status_payload_info { 1205 struct fc_link_status link_status; /* 24 bytes */ 1206 uint32_t port_type; /* bits 31-30 only */ 1207}; 1208 1209#define RDP_LINK_ERROR_STATUS_DESC_TAG 0x00010002 1210struct fc_rdp_link_error_status_desc { 1211 uint32_t tag; /* 0001 0002h */ 1212 uint32_t length; /* set to size of payload struct */ 1213 struct fc_rdp_link_error_status_payload_info info; 1214}; 1215 1216#define VN_PT_PHY_UNKNOWN 0x00 1217#define VN_PT_PHY_PF_PORT 0x01 1218#define VN_PT_PHY_ETH_MAC 0x10 1219#define VN_PT_PHY_SHIFT 30 1220 1221#define RDP_PS_1GB 0x8000 1222#define RDP_PS_2GB 0x4000 1223#define RDP_PS_4GB 0x2000 1224#define RDP_PS_10GB 0x1000 1225#define RDP_PS_8GB 0x0800 1226#define RDP_PS_16GB 0x0400 1227#define RDP_PS_32GB 0x0200 1228#define RDP_PS_64GB 0x0100 1229#define RDP_PS_128GB 0x0080 1230#define RDP_PS_256GB 0x0040 1231 1232#define RDP_CAP_USER_CONFIGURED 0x0002 1233#define RDP_CAP_UNKNOWN 0x0001 1234#define RDP_PS_UNKNOWN 0x0002 1235#define RDP_PS_NOT_ESTABLISHED 0x0001 1236 1237struct fc_rdp_port_speed { 1238 uint16_t capabilities; 1239 uint16_t speed; 1240}; 1241 1242struct fc_rdp_port_speed_info { 1243 struct fc_rdp_port_speed port_speed; 1244}; 1245 1246#define RDP_PORT_SPEED_DESC_TAG 0x00010001 1247struct fc_rdp_port_speed_desc { 1248 uint32_t tag; /* 00010001h */ 1249 uint32_t length; /* set to size of payload struct */ 1250 struct fc_rdp_port_speed_info info; 1251}; 1252 1253#define RDP_NPORT_ID_SIZE 4 1254#define RDP_N_PORT_DESC_TAG 0x00000003 1255struct fc_rdp_nport_desc { 1256 uint32_t tag; /* 0000 0003h, big endian */ 1257 uint32_t length; /* size of RDP_N_PORT_ID struct */ 1258 uint32_t nport_id : 12; 1259 uint32_t reserved : 8; 1260}; 1261 1262 1263struct fc_rdp_link_service_info { 1264 uint32_t els_req; /* Request payload word 0 value.*/ 1265}; 1266 1267#define RDP_LINK_SERVICE_DESC_TAG 0x00000001 1268struct fc_rdp_link_service_desc { 1269 uint32_t tag; /* Descriptor tag 1 */ 1270 uint32_t length; /* set to size of payload struct. */ 1271 struct fc_rdp_link_service_info payload; 1272 /* must be ELS req Word 0(0x18) */ 1273}; 1274 1275struct fc_rdp_sfp_info { 1276 uint16_t temperature; 1277 uint16_t vcc; 1278 uint16_t tx_bias; 1279 uint16_t tx_power; 1280 uint16_t rx_power; 1281 uint16_t flags; 1282}; 1283 1284#define RDP_SFP_DESC_TAG 0x00010000 1285struct fc_rdp_sfp_desc { 1286 uint32_t tag; 1287 uint32_t length; /* set to size of sfp_info struct */ 1288 struct fc_rdp_sfp_info sfp_info; 1289}; 1290 1291/* Buffer Credit Descriptor */ 1292struct fc_rdp_bbc_info { 1293 uint32_t port_bbc; /* FC_Port buffer-to-buffer credit */ 1294 uint32_t attached_port_bbc; 1295 uint32_t rtt; /* Round trip time */ 1296}; 1297#define RDP_BBC_DESC_TAG 0x00010006 1298struct fc_rdp_bbc_desc { 1299 uint32_t tag; 1300 uint32_t length; 1301 struct fc_rdp_bbc_info bbc_info; 1302}; 1303 1304/* Optical Element Type Transgression Flags */ 1305#define RDP_OET_LOW_WARNING 0x1 1306#define RDP_OET_HIGH_WARNING 0x2 1307#define RDP_OET_LOW_ALARM 0x4 1308#define RDP_OET_HIGH_ALARM 0x8 1309 1310#define RDP_OED_TEMPERATURE 0x1 1311#define RDP_OED_VOLTAGE 0x2 1312#define RDP_OED_TXBIAS 0x3 1313#define RDP_OED_TXPOWER 0x4 1314#define RDP_OED_RXPOWER 0x5 1315 1316#define RDP_OED_TYPE_SHIFT 28 1317/* Optical Element Data descriptor */ 1318struct fc_rdp_oed_info { 1319 uint16_t hi_alarm; 1320 uint16_t lo_alarm; 1321 uint16_t hi_warning; 1322 uint16_t lo_warning; 1323 uint32_t function_flags; 1324}; 1325#define RDP_OED_DESC_TAG 0x00010007 1326struct fc_rdp_oed_sfp_desc { 1327 uint32_t tag; 1328 uint32_t length; 1329 struct fc_rdp_oed_info oed_info; 1330}; 1331 1332/* Optical Product Data descriptor */ 1333struct fc_rdp_opd_sfp_info { 1334 uint8_t vendor_name[16]; 1335 uint8_t model_number[16]; 1336 uint8_t serial_number[16]; 1337 uint8_t revision[4]; 1338 uint8_t date[8]; 1339}; 1340 1341#define RDP_OPD_DESC_TAG 0x00010008 1342struct fc_rdp_opd_sfp_desc { 1343 uint32_t tag; 1344 uint32_t length; 1345 struct fc_rdp_opd_sfp_info opd_info; 1346}; 1347 1348struct fc_rdp_req_frame { 1349 uint32_t rdp_command; /* ELS command opcode (0x18)*/ 1350 uint32_t rdp_des_length; /* RDP Payload Word 1 */ 1351 struct fc_rdp_nport_desc nport_id_desc; /* RDP Payload Word 2 - 4 */ 1352}; 1353 1354 1355struct fc_rdp_res_frame { 1356 uint32_t reply_sequence; /* FC word0 LS_ACC or LS_RJT */ 1357 uint32_t length; /* FC Word 1 */ 1358 struct fc_rdp_link_service_desc link_service_desc; /* Word 2 -4 */ 1359 struct fc_rdp_sfp_desc sfp_desc; /* Word 5 -9 */ 1360 struct fc_rdp_port_speed_desc portspeed_desc; /* Word 10 -12 */ 1361 struct fc_rdp_link_error_status_desc link_error_desc; /* Word 13 -21 */ 1362 struct fc_rdp_port_name_desc diag_port_names_desc; /* Word 22 -27 */ 1363 struct fc_rdp_port_name_desc attached_port_names_desc;/* Word 28 -33 */ 1364 struct fc_fec_rdp_desc fec_desc; /* FC word 34-37*/ 1365 struct fc_rdp_bbc_desc bbc_desc; /* FC Word 38-42*/ 1366 struct fc_rdp_oed_sfp_desc oed_temp_desc; /* FC Word 43-47*/ 1367 struct fc_rdp_oed_sfp_desc oed_voltage_desc; /* FC word 48-52*/ 1368 struct fc_rdp_oed_sfp_desc oed_txbias_desc; /* FC word 53-57*/ 1369 struct fc_rdp_oed_sfp_desc oed_txpower_desc; /* FC word 58-62*/ 1370 struct fc_rdp_oed_sfp_desc oed_rxpower_desc; /* FC word 63-67*/ 1371 struct fc_rdp_opd_sfp_desc opd_desc; /* FC word 68-84*/ 1372}; 1373 1374 1375/* UVEM */ 1376 1377#define LPFC_UVEM_SIZE 60 1378#define LPFC_UVEM_VEM_ID_DESC_SIZE 16 1379#define LPFC_UVEM_VE_MAP_DESC_SIZE 20 1380 1381#define VEM_ID_DESC_TAG 0x0001000A 1382struct lpfc_vem_id_desc { 1383 uint32_t tag; 1384 uint32_t length; 1385 uint8_t vem_id[16]; 1386}; 1387 1388#define LPFC_QFPA_SIZE 4 1389 1390#define INSTANTIATED_VE_DESC_TAG 0x0001000B 1391struct instantiated_ve_desc { 1392 uint32_t tag; 1393 uint32_t length; 1394 uint8_t global_vem_id[16]; 1395 uint32_t word6; 1396#define lpfc_instantiated_local_id_SHIFT 0 1397#define lpfc_instantiated_local_id_MASK 0x000000ff 1398#define lpfc_instantiated_local_id_WORD word6 1399#define lpfc_instantiated_nport_id_SHIFT 8 1400#define lpfc_instantiated_nport_id_MASK 0x00ffffff 1401#define lpfc_instantiated_nport_id_WORD word6 1402}; 1403 1404#define DEINSTANTIATED_VE_DESC_TAG 0x0001000C 1405struct deinstantiated_ve_desc { 1406 uint32_t tag; 1407 uint32_t length; 1408 uint8_t global_vem_id[16]; 1409 uint32_t word6; 1410#define lpfc_deinstantiated_nport_id_SHIFT 0 1411#define lpfc_deinstantiated_nport_id_MASK 0x000000ff 1412#define lpfc_deinstantiated_nport_id_WORD word6 1413#define lpfc_deinstantiated_local_id_SHIFT 24 1414#define lpfc_deinstantiated_local_id_MASK 0x00ffffff 1415#define lpfc_deinstantiated_local_id_WORD word6 1416}; 1417 1418/* Query Fabric Priority Allocation Response */ 1419#define LPFC_PRIORITY_RANGE_DESC_SIZE 12 1420 1421struct priority_range_desc { 1422 uint32_t tag; 1423 uint32_t length; 1424 uint8_t lo_range; 1425 uint8_t hi_range; 1426 uint8_t qos_priority; 1427 uint8_t local_ve_id; 1428}; 1429 1430struct fc_qfpa_res { 1431 uint32_t reply_sequence; /* LS_ACC or LS_RJT */ 1432 uint32_t length; /* FC Word 1 */ 1433 struct priority_range_desc desc[1]; 1434}; 1435 1436/* Application Server command code */ 1437/* VMID */ 1438 1439#define SLI_CT_APP_SEV_Subtypes 0x20 /* Application Server subtype */ 1440 1441#define SLI_CTAS_GAPPIA_ENT 0x0100 /* Get Application Identifier */ 1442#define SLI_CTAS_GALLAPPIA 0x0101 /* Get All Application Identifier */ 1443#define SLI_CTAS_GALLAPPIA_ID 0x0102 /* Get All Application Identifier */ 1444 /* for Nport */ 1445#define SLI_CTAS_GAPPIA_IDAPP 0x0103 /* Get Application Identifier */ 1446 /* for Nport */ 1447#define SLI_CTAS_RAPP_IDENT 0x0200 /* Register Application Identifier */ 1448#define SLI_CTAS_DAPP_IDENT 0x0300 /* Deregister Application */ 1449 /* Identifier */ 1450#define SLI_CTAS_DALLAPP_ID 0x0301 /* Deregister All Application */ 1451 /* Identifier */ 1452 1453struct entity_id_object { 1454 uint8_t entity_id_len; 1455 uint8_t entity_id[255]; /* VM UUID */ 1456}; 1457 1458struct app_id_object { 1459 __be32 port_id; 1460 __be32 app_id; 1461 struct entity_id_object obj; 1462}; 1463 1464struct lpfc_vmid_rapp_ident_list { 1465 __be32 no_of_objects; 1466 struct entity_id_object obj[]; 1467}; 1468 1469struct lpfc_vmid_dapp_ident_list { 1470 __be32 no_of_objects; 1471 struct entity_id_object obj[]; 1472}; 1473 1474#define GALLAPPIA_ID_LAST 0x80 1475struct lpfc_vmid_gallapp_ident_list { 1476 uint8_t control; 1477 uint8_t reserved[3]; 1478 struct app_id_object app_id; 1479}; 1480 1481#define RAPP_IDENT_OFFSET (offsetof(struct lpfc_sli_ct_request, un) + 4) 1482#define DAPP_IDENT_OFFSET (offsetof(struct lpfc_sli_ct_request, un) + 4) 1483#define GALLAPPIA_ID_SIZE (offsetof(struct lpfc_sli_ct_request, un) + 4) 1484#define DALLAPP_ID_SIZE (offsetof(struct lpfc_sli_ct_request, un) + 4) 1485 1486/******** FDMI ********/ 1487 1488/* lpfc_sli_ct_request defines the CT_IU preamble for FDMI commands */ 1489#define SLI_CT_FDMI_Subtypes 0x10 /* Management Service Subtype */ 1490 1491/* Definitions for HBA / Port attribute entries */ 1492 1493/* Attribute Entry Structures */ 1494 1495struct lpfc_fdmi_attr_u32 { 1496 __be16 type; 1497 __be16 len; 1498 __be32 value_u32; 1499}; 1500 1501struct lpfc_fdmi_attr_wwn { 1502 __be16 type; 1503 __be16 len; 1504 1505 /* Keep as u8[8] instead of __be64 to avoid accidental zero padding 1506 * by compiler 1507 */ 1508 u8 name[8]; 1509}; 1510 1511struct lpfc_fdmi_attr_fullwwn { 1512 __be16 type; 1513 __be16 len; 1514 1515 /* Keep as u8[8] instead of __be64 to avoid accidental zero padding 1516 * by compiler 1517 */ 1518 u8 nname[8]; 1519 u8 pname[8]; 1520}; 1521 1522struct lpfc_fdmi_attr_fc4types { 1523 __be16 type; 1524 __be16 len; 1525 u8 value_types[32]; 1526}; 1527 1528struct lpfc_fdmi_attr_string { 1529 __be16 type; 1530 __be16 len; 1531 char value_string[256]; 1532}; 1533 1534/* Maximum FDMI attribute length is Type+Len (4 bytes) + 256 byte string */ 1535#define FDMI_MAX_ATTRLEN sizeof(struct lpfc_fdmi_attr_string) 1536 1537/* 1538 * HBA Attribute Block 1539 */ 1540struct lpfc_fdmi_attr_block { 1541 uint32_t EntryCnt; /* Number of HBA attribute entries */ 1542 /* Variable Length Attribute Entry TLV's follow */ 1543}; 1544 1545/* 1546 * Port Entry 1547 */ 1548struct lpfc_fdmi_port_entry { 1549 struct lpfc_name PortName; 1550}; 1551 1552/* 1553 * HBA Identifier 1554 */ 1555struct lpfc_fdmi_hba_ident { 1556 struct lpfc_name PortName; 1557}; 1558 1559/* 1560 * Registered Port List Format 1561 */ 1562struct lpfc_fdmi_reg_port_list { 1563 __be32 EntryCnt; 1564 struct lpfc_fdmi_port_entry pe; 1565}; 1566 1567/* 1568 * Register HBA(RHBA) 1569 */ 1570struct lpfc_fdmi_reg_hba { 1571 struct lpfc_fdmi_hba_ident hi; 1572 struct lpfc_fdmi_reg_port_list rpl; 1573}; 1574 1575/******** MI MIB ********/ 1576#define SLI_CT_MIB_Subtypes 0x11 1577 1578/* 1579 * Register HBA Attributes (RHAT) 1580 */ 1581struct lpfc_fdmi_reg_hbaattr { 1582 struct lpfc_name HBA_PortName; 1583 struct lpfc_fdmi_attr_block ab; 1584}; 1585 1586/* 1587 * Register Port Attributes (RPA) 1588 */ 1589struct lpfc_fdmi_reg_portattr { 1590 struct lpfc_name PortName; 1591 struct lpfc_fdmi_attr_block ab; 1592}; 1593 1594/* 1595 * HBA MAnagement Operations Command Codes 1596 */ 1597#define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */ 1598#define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */ 1599#define SLI_MGMT_GRPL 0x102 /* Get registered Port list */ 1600#define SLI_MGMT_GPAT 0x110 /* Get Port attributes */ 1601#define SLI_MGMT_GPAS 0x120 /* Get Port Statistics */ 1602#define SLI_MGMT_RHBA 0x200 /* Register HBA */ 1603#define SLI_MGMT_RHAT 0x201 /* Register HBA attributes */ 1604#define SLI_MGMT_RPRT 0x210 /* Register Port */ 1605#define SLI_MGMT_RPA 0x211 /* Register Port attributes */ 1606#define SLI_MGMT_DHBA 0x300 /* De-register HBA */ 1607#define SLI_MGMT_DHAT 0x301 /* De-register HBA attributes */ 1608#define SLI_MGMT_DPRT 0x310 /* De-register Port */ 1609#define SLI_MGMT_DPA 0x311 /* De-register Port attributes */ 1610 1611#define LPFC_FDMI_MAX_RETRY 3 /* Max retries for a FDMI command */ 1612 1613/* 1614 * HBA Attribute Types 1615 */ 1616#define RHBA_NODENAME 0x1 /* 8 byte WWNN */ 1617#define RHBA_MANUFACTURER 0x2 /* 4 to 64 byte ASCII string */ 1618#define RHBA_SERIAL_NUMBER 0x3 /* 4 to 64 byte ASCII string */ 1619#define RHBA_MODEL 0x4 /* 4 to 256 byte ASCII string */ 1620#define RHBA_MODEL_DESCRIPTION 0x5 /* 4 to 256 byte ASCII string */ 1621#define RHBA_HARDWARE_VERSION 0x6 /* 4 to 256 byte ASCII string */ 1622#define RHBA_DRIVER_VERSION 0x7 /* 4 to 256 byte ASCII string */ 1623#define RHBA_OPTION_ROM_VERSION 0x8 /* 4 to 256 byte ASCII string */ 1624#define RHBA_FIRMWARE_VERSION 0x9 /* 4 to 256 byte ASCII string */ 1625#define RHBA_OS_NAME_VERSION 0xa /* 4 to 256 byte ASCII string */ 1626#define RHBA_MAX_CT_PAYLOAD_LEN 0xb /* 32-bit unsigned int */ 1627#define RHBA_SYM_NODENAME 0xc /* 4 to 256 byte ASCII string */ 1628#define RHBA_VENDOR_INFO 0xd /* 32-bit unsigned int */ 1629#define RHBA_NUM_PORTS 0xe /* 32-bit unsigned int */ 1630#define RHBA_FABRIC_WWNN 0xf /* 8 byte WWNN */ 1631#define RHBA_BIOS_VERSION 0x10 /* 4 to 256 byte ASCII string */ 1632#define RHBA_BIOS_STATE 0x11 /* 32-bit unsigned int */ 1633#define RHBA_VENDOR_ID 0xe0 /* 8 byte ASCII string */ 1634 1635/* Bit mask for all individual HBA attributes */ 1636#define LPFC_FDMI_HBA_ATTR_wwnn 0x00000001 1637#define LPFC_FDMI_HBA_ATTR_manufacturer 0x00000002 1638#define LPFC_FDMI_HBA_ATTR_sn 0x00000004 1639#define LPFC_FDMI_HBA_ATTR_model 0x00000008 1640#define LPFC_FDMI_HBA_ATTR_description 0x00000010 1641#define LPFC_FDMI_HBA_ATTR_hdw_ver 0x00000020 1642#define LPFC_FDMI_HBA_ATTR_drvr_ver 0x00000040 1643#define LPFC_FDMI_HBA_ATTR_rom_ver 0x00000080 1644#define LPFC_FDMI_HBA_ATTR_fmw_ver 0x00000100 1645#define LPFC_FDMI_HBA_ATTR_os_ver 0x00000200 1646#define LPFC_FDMI_HBA_ATTR_ct_len 0x00000400 1647#define LPFC_FDMI_HBA_ATTR_symbolic_name 0x00000800 1648#define LPFC_FDMI_HBA_ATTR_vendor_info 0x00001000 /* Not used */ 1649#define LPFC_FDMI_HBA_ATTR_num_ports 0x00002000 1650#define LPFC_FDMI_HBA_ATTR_fabric_wwnn 0x00004000 1651#define LPFC_FDMI_HBA_ATTR_bios_ver 0x00008000 1652#define LPFC_FDMI_HBA_ATTR_bios_state 0x00010000 /* Not used */ 1653#define LPFC_FDMI_HBA_ATTR_vendor_id 0x00020000 1654 1655/* Bit mask for FDMI-1 defined HBA attributes */ 1656#define LPFC_FDMI1_HBA_ATTR 0x000007ff 1657 1658/* Bit mask for FDMI-2 defined HBA attributes */ 1659/* Skip vendor_info and bios_state */ 1660#define LPFC_FDMI2_HBA_ATTR 0x0002efff 1661 1662/* 1663 * Port Attribute Types 1664 */ 1665#define RPRT_SUPPORTED_FC4_TYPES 0x1 /* 32 byte binary array */ 1666#define RPRT_SUPPORTED_SPEED 0x2 /* 32-bit unsigned int */ 1667#define RPRT_PORT_SPEED 0x3 /* 32-bit unsigned int */ 1668#define RPRT_MAX_FRAME_SIZE 0x4 /* 32-bit unsigned int */ 1669#define RPRT_OS_DEVICE_NAME 0x5 /* 4 to 256 byte ASCII string */ 1670#define RPRT_HOST_NAME 0x6 /* 4 to 256 byte ASCII string */ 1671#define RPRT_NODENAME 0x7 /* 8 byte WWNN */ 1672#define RPRT_PORTNAME 0x8 /* 8 byte WWPN */ 1673#define RPRT_SYM_PORTNAME 0x9 /* 4 to 256 byte ASCII string */ 1674#define RPRT_PORT_TYPE 0xa /* 32-bit unsigned int */ 1675#define RPRT_SUPPORTED_CLASS 0xb /* 32-bit unsigned int */ 1676#define RPRT_FABRICNAME 0xc /* 8 byte Fabric WWPN */ 1677#define RPRT_ACTIVE_FC4_TYPES 0xd /* 32 byte binary array */ 1678#define RPRT_PORT_STATE 0x101 /* 32-bit unsigned int */ 1679#define RPRT_DISC_PORT 0x102 /* 32-bit unsigned int */ 1680#define RPRT_PORT_ID 0x103 /* 32-bit unsigned int */ 1681#define RPRT_VENDOR_MI 0xf047 /* vendor ascii string */ 1682#define RPRT_SMART_SERVICE 0xf100 /* 4 to 256 byte ASCII string */ 1683#define RPRT_SMART_GUID 0xf101 /* 8 byte WWNN + 8 byte WWPN */ 1684#define RPRT_SMART_VERSION 0xf102 /* 4 to 256 byte ASCII string */ 1685#define RPRT_SMART_MODEL 0xf103 /* 4 to 256 byte ASCII string */ 1686#define RPRT_SMART_PORT_INFO 0xf104 /* 32-bit unsigned int */ 1687#define RPRT_SMART_QOS 0xf105 /* 32-bit unsigned int */ 1688#define RPRT_SMART_SECURITY 0xf106 /* 32-bit unsigned int */ 1689 1690/* Bit mask for all individual PORT attributes */ 1691#define LPFC_FDMI_PORT_ATTR_fc4type 0x00000001 1692#define LPFC_FDMI_PORT_ATTR_support_speed 0x00000002 1693#define LPFC_FDMI_PORT_ATTR_speed 0x00000004 1694#define LPFC_FDMI_PORT_ATTR_max_frame 0x00000008 1695#define LPFC_FDMI_PORT_ATTR_os_devname 0x00000010 1696#define LPFC_FDMI_PORT_ATTR_host_name 0x00000020 1697#define LPFC_FDMI_PORT_ATTR_wwnn 0x00000040 1698#define LPFC_FDMI_PORT_ATTR_wwpn 0x00000080 1699#define LPFC_FDMI_PORT_ATTR_symbolic_name 0x00000100 1700#define LPFC_FDMI_PORT_ATTR_port_type 0x00000200 1701#define LPFC_FDMI_PORT_ATTR_class 0x00000400 1702#define LPFC_FDMI_PORT_ATTR_fabric_wwpn 0x00000800 1703#define LPFC_FDMI_PORT_ATTR_port_state 0x00001000 1704#define LPFC_FDMI_PORT_ATTR_active_fc4type 0x00002000 1705#define LPFC_FDMI_PORT_ATTR_num_disc 0x00004000 1706#define LPFC_FDMI_PORT_ATTR_nportid 0x00008000 1707#define LPFC_FDMI_SMART_ATTR_service 0x00010000 /* Vendor specific */ 1708#define LPFC_FDMI_SMART_ATTR_guid 0x00020000 /* Vendor specific */ 1709#define LPFC_FDMI_SMART_ATTR_version 0x00040000 /* Vendor specific */ 1710#define LPFC_FDMI_SMART_ATTR_model 0x00080000 /* Vendor specific */ 1711#define LPFC_FDMI_SMART_ATTR_port_info 0x00100000 /* Vendor specific */ 1712#define LPFC_FDMI_SMART_ATTR_qos 0x00200000 /* Vendor specific */ 1713#define LPFC_FDMI_SMART_ATTR_security 0x00400000 /* Vendor specific */ 1714#define LPFC_FDMI_VENDOR_ATTR_mi 0x00800000 /* Vendor specific */ 1715 1716/* Bit mask for FDMI-1 defined PORT attributes */ 1717#define LPFC_FDMI1_PORT_ATTR 0x0000003f 1718 1719/* Bit mask for FDMI-2 defined PORT attributes */ 1720#define LPFC_FDMI2_PORT_ATTR 0x0000ffff 1721 1722/* Bit mask for Smart SAN defined PORT attributes */ 1723#define LPFC_FDMI2_SMART_ATTR 0x007fffff 1724 1725/* Defines for PORT port state attribute */ 1726#define LPFC_FDMI_PORTSTATE_UNKNOWN 1 1727#define LPFC_FDMI_PORTSTATE_ONLINE 2 1728 1729/* Defines for PORT port type attribute */ 1730#define LPFC_FDMI_PORTTYPE_UNKNOWN 0 1731#define LPFC_FDMI_PORTTYPE_NPORT 1 1732#define LPFC_FDMI_PORTTYPE_NLPORT 2 1733 1734/* 1735 * Begin HBA configuration parameters. 1736 * The PCI configuration register BAR assignments are: 1737 * BAR0, offset 0x10 - SLIM base memory address 1738 * BAR1, offset 0x14 - SLIM base memory high address 1739 * BAR2, offset 0x18 - REGISTER base memory address 1740 * BAR3, offset 0x1c - REGISTER base memory high address 1741 * BAR4, offset 0x20 - BIU I/O registers 1742 * BAR5, offset 0x24 - REGISTER base io high address 1743 */ 1744 1745/* Number of rings currently used and available. */ 1746#define MAX_SLI3_CONFIGURED_RINGS 3 1747#define MAX_SLI3_RINGS 4 1748 1749/* IOCB / Mailbox is owned by FireFly */ 1750#define OWN_CHIP 1 1751 1752/* IOCB / Mailbox is owned by Host */ 1753#define OWN_HOST 0 1754 1755/* Number of 4-byte words in an IOCB. */ 1756#define IOCB_WORD_SZ 8 1757 1758/* network headers for Dfctl field */ 1759#define FC_NET_HDR 0x20 1760 1761/* Start FireFly Register definitions */ 1762#define PCI_VENDOR_ID_EMULEX 0x10df 1763#define PCI_DEVICE_ID_FIREFLY 0x1ae5 1764#define PCI_DEVICE_ID_PROTEUS_VF 0xe100 1765#define PCI_DEVICE_ID_BALIUS 0xe131 1766#define PCI_DEVICE_ID_PROTEUS_PF 0xe180 1767#define PCI_DEVICE_ID_LANCER_FC 0xe200 1768#define PCI_DEVICE_ID_LANCER_FC_VF 0xe208 1769#define PCI_DEVICE_ID_LANCER_FCOE 0xe260 1770#define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268 1771#define PCI_DEVICE_ID_LANCER_G6_FC 0xe300 1772#define PCI_DEVICE_ID_LANCER_G7_FC 0xf400 1773#define PCI_DEVICE_ID_LANCER_G7P_FC 0xf500 1774#define PCI_DEVICE_ID_SAT_SMB 0xf011 1775#define PCI_DEVICE_ID_SAT_MID 0xf015 1776#define PCI_DEVICE_ID_RFLY 0xf095 1777#define PCI_DEVICE_ID_PFLY 0xf098 1778#define PCI_DEVICE_ID_LP101 0xf0a1 1779#define PCI_DEVICE_ID_TFLY 0xf0a5 1780#define PCI_DEVICE_ID_BSMB 0xf0d1 1781#define PCI_DEVICE_ID_BMID 0xf0d5 1782#define PCI_DEVICE_ID_ZSMB 0xf0e1 1783#define PCI_DEVICE_ID_ZMID 0xf0e5 1784#define PCI_DEVICE_ID_NEPTUNE 0xf0f5 1785#define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6 1786#define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7 1787#define PCI_DEVICE_ID_SAT 0xf100 1788#define PCI_DEVICE_ID_SAT_SCSP 0xf111 1789#define PCI_DEVICE_ID_SAT_DCSP 0xf112 1790#define PCI_DEVICE_ID_FALCON 0xf180 1791#define PCI_DEVICE_ID_SUPERFLY 0xf700 1792#define PCI_DEVICE_ID_DRAGONFLY 0xf800 1793#define PCI_DEVICE_ID_CENTAUR 0xf900 1794#define PCI_DEVICE_ID_PEGASUS 0xf980 1795#define PCI_DEVICE_ID_THOR 0xfa00 1796#define PCI_DEVICE_ID_VIPER 0xfb00 1797#define PCI_DEVICE_ID_LP10000S 0xfc00 1798#define PCI_DEVICE_ID_LP11000S 0xfc10 1799#define PCI_DEVICE_ID_LPE11000S 0xfc20 1800#define PCI_DEVICE_ID_SAT_S 0xfc40 1801#define PCI_DEVICE_ID_PROTEUS_S 0xfc50 1802#define PCI_DEVICE_ID_HELIOS 0xfd00 1803#define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11 1804#define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12 1805#define PCI_DEVICE_ID_ZEPHYR 0xfe00 1806#define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11 1807#define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12 1808#define PCI_VENDOR_ID_SERVERENGINE 0x19a2 1809#define PCI_DEVICE_ID_TIGERSHARK 0x0704 1810#define PCI_DEVICE_ID_TOMCAT 0x0714 1811#define PCI_DEVICE_ID_SKYHAWK 0x0724 1812#define PCI_DEVICE_ID_SKYHAWK_VF 0x072c 1813#define PCI_VENDOR_ID_ATTO 0x117c 1814#define PCI_DEVICE_ID_CLRY_16XE 0x0064 1815#define PCI_DEVICE_ID_CLRY_161E 0x0063 1816#define PCI_DEVICE_ID_CLRY_162E 0x0064 1817#define PCI_DEVICE_ID_CLRY_164E 0x0065 1818#define PCI_DEVICE_ID_CLRY_16XP 0x0094 1819#define PCI_DEVICE_ID_CLRY_161P 0x00a0 1820#define PCI_DEVICE_ID_CLRY_162P 0x0094 1821#define PCI_DEVICE_ID_CLRY_164P 0x00a1 1822#define PCI_DEVICE_ID_CLRY_32XE 0x0094 1823#define PCI_DEVICE_ID_CLRY_321E 0x00a2 1824#define PCI_DEVICE_ID_CLRY_322E 0x00a3 1825#define PCI_DEVICE_ID_CLRY_324E 0x00ac 1826#define PCI_DEVICE_ID_CLRY_32XP 0x00bb 1827#define PCI_DEVICE_ID_CLRY_321P 0x00bc 1828#define PCI_DEVICE_ID_CLRY_322P 0x00bd 1829#define PCI_DEVICE_ID_CLRY_324P 0x00be 1830#define PCI_DEVICE_ID_TLFC_2 0x0064 1831#define PCI_DEVICE_ID_TLFC_2XX2 0x4064 1832#define PCI_DEVICE_ID_TLFC_3 0x0094 1833#define PCI_DEVICE_ID_TLFC_3162 0x40a6 1834#define PCI_DEVICE_ID_TLFC_3322 0x40a7 1835 1836#define JEDEC_ID_ADDRESS 0x0080001c 1837#define FIREFLY_JEDEC_ID 0x1ACC 1838#define SUPERFLY_JEDEC_ID 0x0020 1839#define DRAGONFLY_JEDEC_ID 0x0021 1840#define DRAGONFLY_V2_JEDEC_ID 0x0025 1841#define CENTAUR_2G_JEDEC_ID 0x0026 1842#define CENTAUR_1G_JEDEC_ID 0x0028 1843#define PEGASUS_ORION_JEDEC_ID 0x0036 1844#define PEGASUS_JEDEC_ID 0x0038 1845#define THOR_JEDEC_ID 0x0012 1846#define HELIOS_JEDEC_ID 0x0364 1847#define ZEPHYR_JEDEC_ID 0x0577 1848#define VIPER_JEDEC_ID 0x4838 1849#define SATURN_JEDEC_ID 0x1004 1850 1851#define JEDEC_ID_MASK 0x0FFFF000 1852#define JEDEC_ID_SHIFT 12 1853#define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT) 1854 1855typedef struct { /* FireFly BIU registers */ 1856 uint32_t hostAtt; /* See definitions for Host Attention 1857 register */ 1858 uint32_t chipAtt; /* See definitions for Chip Attention 1859 register */ 1860 uint32_t hostStatus; /* See definitions for Host Status register */ 1861 uint32_t hostControl; /* See definitions for Host Control register */ 1862 uint32_t buiConfig; /* See definitions for BIU configuration 1863 register */ 1864} FF_REGS; 1865 1866/* IO Register size in bytes */ 1867#define FF_REG_AREA_SIZE 256 1868 1869/* Host Attention Register */ 1870 1871#define HA_REG_OFFSET 0 /* Byte offset from register base address */ 1872 1873#define HA_R0RE_REQ 0x00000001 /* Bit 0 */ 1874#define HA_R0CE_RSP 0x00000002 /* Bit 1 */ 1875#define HA_R0ATT 0x00000008 /* Bit 3 */ 1876#define HA_R1RE_REQ 0x00000010 /* Bit 4 */ 1877#define HA_R1CE_RSP 0x00000020 /* Bit 5 */ 1878#define HA_R1ATT 0x00000080 /* Bit 7 */ 1879#define HA_R2RE_REQ 0x00000100 /* Bit 8 */ 1880#define HA_R2CE_RSP 0x00000200 /* Bit 9 */ 1881#define HA_R2ATT 0x00000800 /* Bit 11 */ 1882#define HA_R3RE_REQ 0x00001000 /* Bit 12 */ 1883#define HA_R3CE_RSP 0x00002000 /* Bit 13 */ 1884#define HA_R3ATT 0x00008000 /* Bit 15 */ 1885#define HA_LATT 0x20000000 /* Bit 29 */ 1886#define HA_MBATT 0x40000000 /* Bit 30 */ 1887#define HA_ERATT 0x80000000 /* Bit 31 */ 1888 1889#define HA_RXRE_REQ 0x00000001 /* Bit 0 */ 1890#define HA_RXCE_RSP 0x00000002 /* Bit 1 */ 1891#define HA_RXATT 0x00000008 /* Bit 3 */ 1892#define HA_RXMASK 0x0000000f 1893 1894#define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT) 1895#define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT) 1896#define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT) 1897#define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT) 1898 1899#define HA_R0_POS 3 1900#define HA_R1_POS 7 1901#define HA_R2_POS 11 1902#define HA_R3_POS 15 1903#define HA_LE_POS 29 1904#define HA_MB_POS 30 1905#define HA_ER_POS 31 1906/* Chip Attention Register */ 1907 1908#define CA_REG_OFFSET 4 /* Byte offset from register base address */ 1909 1910#define CA_R0CE_REQ 0x00000001 /* Bit 0 */ 1911#define CA_R0RE_RSP 0x00000002 /* Bit 1 */ 1912#define CA_R0ATT 0x00000008 /* Bit 3 */ 1913#define CA_R1CE_REQ 0x00000010 /* Bit 4 */ 1914#define CA_R1RE_RSP 0x00000020 /* Bit 5 */ 1915#define CA_R1ATT 0x00000080 /* Bit 7 */ 1916#define CA_R2CE_REQ 0x00000100 /* Bit 8 */ 1917#define CA_R2RE_RSP 0x00000200 /* Bit 9 */ 1918#define CA_R2ATT 0x00000800 /* Bit 11 */ 1919#define CA_R3CE_REQ 0x00001000 /* Bit 12 */ 1920#define CA_R3RE_RSP 0x00002000 /* Bit 13 */ 1921#define CA_R3ATT 0x00008000 /* Bit 15 */ 1922#define CA_MBATT 0x40000000 /* Bit 30 */ 1923 1924/* Host Status Register */ 1925 1926#define HS_REG_OFFSET 8 /* Byte offset from register base address */ 1927 1928#define HS_MBRDY 0x00400000 /* Bit 22 */ 1929#define HS_FFRDY 0x00800000 /* Bit 23 */ 1930#define HS_FFER8 0x01000000 /* Bit 24 */ 1931#define HS_FFER7 0x02000000 /* Bit 25 */ 1932#define HS_FFER6 0x04000000 /* Bit 26 */ 1933#define HS_FFER5 0x08000000 /* Bit 27 */ 1934#define HS_FFER4 0x10000000 /* Bit 28 */ 1935#define HS_FFER3 0x20000000 /* Bit 29 */ 1936#define HS_FFER2 0x40000000 /* Bit 30 */ 1937#define HS_FFER1 0x80000000 /* Bit 31 */ 1938#define HS_CRIT_TEMP 0x00000100 /* Bit 8 */ 1939#define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */ 1940#define UNPLUG_ERR 0x00000001 /* Indicate pci hot unplug */ 1941/* Host Control Register */ 1942 1943#define HC_REG_OFFSET 12 /* Byte offset from register base address */ 1944 1945#define HC_MBINT_ENA 0x00000001 /* Bit 0 */ 1946#define HC_R0INT_ENA 0x00000002 /* Bit 1 */ 1947#define HC_R1INT_ENA 0x00000004 /* Bit 2 */ 1948#define HC_R2INT_ENA 0x00000008 /* Bit 3 */ 1949#define HC_R3INT_ENA 0x00000010 /* Bit 4 */ 1950#define HC_INITHBI 0x02000000 /* Bit 25 */ 1951#define HC_INITMB 0x04000000 /* Bit 26 */ 1952#define HC_INITFF 0x08000000 /* Bit 27 */ 1953#define HC_LAINT_ENA 0x20000000 /* Bit 29 */ 1954#define HC_ERINT_ENA 0x80000000 /* Bit 31 */ 1955 1956/* Message Signaled Interrupt eXtension (MSI-X) message identifiers */ 1957#define MSIX_DFLT_ID 0 1958#define MSIX_RNG0_ID 0 1959#define MSIX_RNG1_ID 1 1960#define MSIX_RNG2_ID 2 1961#define MSIX_RNG3_ID 3 1962 1963#define MSIX_LINK_ID 4 1964#define MSIX_MBOX_ID 5 1965 1966#define MSIX_SPARE0_ID 6 1967#define MSIX_SPARE1_ID 7 1968 1969/* Mailbox Commands */ 1970#define MBX_SHUTDOWN 0x00 /* terminate testing */ 1971#define MBX_LOAD_SM 0x01 1972#define MBX_READ_NV 0x02 1973#define MBX_WRITE_NV 0x03 1974#define MBX_RUN_BIU_DIAG 0x04 1975#define MBX_INIT_LINK 0x05 1976#define MBX_DOWN_LINK 0x06 1977#define MBX_CONFIG_LINK 0x07 1978#define MBX_CONFIG_RING 0x09 1979#define MBX_RESET_RING 0x0A 1980#define MBX_READ_CONFIG 0x0B 1981#define MBX_READ_RCONFIG 0x0C 1982#define MBX_READ_SPARM 0x0D 1983#define MBX_READ_STATUS 0x0E 1984#define MBX_READ_RPI 0x0F 1985#define MBX_READ_XRI 0x10 1986#define MBX_READ_REV 0x11 1987#define MBX_READ_LNK_STAT 0x12 1988#define MBX_REG_LOGIN 0x13 1989#define MBX_UNREG_LOGIN 0x14 1990#define MBX_CLEAR_LA 0x16 1991#define MBX_DUMP_MEMORY 0x17 1992#define MBX_DUMP_CONTEXT 0x18 1993#define MBX_RUN_DIAGS 0x19 1994#define MBX_RESTART 0x1A 1995#define MBX_UPDATE_CFG 0x1B 1996#define MBX_DOWN_LOAD 0x1C 1997#define MBX_DEL_LD_ENTRY 0x1D 1998#define MBX_RUN_PROGRAM 0x1E 1999#define MBX_SET_MASK 0x20 2000#define MBX_SET_VARIABLE 0x21 2001#define MBX_UNREG_D_ID 0x23 2002#define MBX_KILL_BOARD 0x24 2003#define MBX_CONFIG_FARP 0x25 2004#define MBX_BEACON 0x2A 2005#define MBX_CONFIG_MSI 0x30 2006#define MBX_HEARTBEAT 0x31 2007#define MBX_WRITE_VPARMS 0x32 2008#define MBX_ASYNCEVT_ENABLE 0x33 2009#define MBX_READ_EVENT_LOG_STATUS 0x37 2010#define MBX_READ_EVENT_LOG 0x38 2011#define MBX_WRITE_EVENT_LOG 0x39 2012 2013#define MBX_PORT_CAPABILITIES 0x3B 2014#define MBX_PORT_IOV_CONTROL 0x3C 2015 2016#define MBX_CONFIG_HBQ 0x7C 2017#define MBX_LOAD_AREA 0x81 2018#define MBX_RUN_BIU_DIAG64 0x84 2019#define MBX_CONFIG_PORT 0x88 2020#define MBX_READ_SPARM64 0x8D 2021#define MBX_READ_RPI64 0x8F 2022#define MBX_REG_LOGIN64 0x93 2023#define MBX_READ_TOPOLOGY 0x95 2024#define MBX_REG_VPI 0x96 2025#define MBX_UNREG_VPI 0x97 2026 2027#define MBX_WRITE_WWN 0x98 2028#define MBX_SET_DEBUG 0x99 2029#define MBX_LOAD_EXP_ROM 0x9C 2030#define MBX_SLI4_CONFIG 0x9B 2031#define MBX_SLI4_REQ_FTRS 0x9D 2032#define MBX_MAX_CMDS 0x9E 2033#define MBX_RESUME_RPI 0x9E 2034#define MBX_SLI2_CMD_MASK 0x80 2035#define MBX_REG_VFI 0x9F 2036#define MBX_REG_FCFI 0xA0 2037#define MBX_UNREG_VFI 0xA1 2038#define MBX_UNREG_FCFI 0xA2 2039#define MBX_INIT_VFI 0xA3 2040#define MBX_INIT_VPI 0xA4 2041#define MBX_ACCESS_VDATA 0xA5 2042#define MBX_REG_FCFI_MRQ 0xAF 2043 2044#define MBX_AUTH_PORT 0xF8 2045#define MBX_SECURITY_MGMT 0xF9 2046 2047/* IOCB Commands */ 2048 2049#define CMD_RCV_SEQUENCE_CX 0x01 2050#define CMD_XMIT_SEQUENCE_CR 0x02 2051#define CMD_XMIT_SEQUENCE_CX 0x03 2052#define CMD_XMIT_BCAST_CN 0x04 2053#define CMD_XMIT_BCAST_CX 0x05 2054#define CMD_QUE_RING_BUF_CN 0x06 2055#define CMD_QUE_XRI_BUF_CX 0x07 2056#define CMD_IOCB_CONTINUE_CN 0x08 2057#define CMD_RET_XRI_BUF_CX 0x09 2058#define CMD_ELS_REQUEST_CR 0x0A 2059#define CMD_ELS_REQUEST_CX 0x0B 2060#define CMD_RCV_ELS_REQ_CX 0x0D 2061#define CMD_ABORT_XRI_CN 0x0E 2062#define CMD_ABORT_XRI_CX 0x0F 2063#define CMD_CLOSE_XRI_CN 0x10 2064#define CMD_CLOSE_XRI_CX 0x11 2065#define CMD_CREATE_XRI_CR 0x12 2066#define CMD_CREATE_XRI_CX 0x13 2067#define CMD_GET_RPI_CN 0x14 2068#define CMD_XMIT_ELS_RSP_CX 0x15 2069#define CMD_GET_RPI_CR 0x16 2070#define CMD_XRI_ABORTED_CX 0x17 2071#define CMD_FCP_IWRITE_CR 0x18 2072#define CMD_FCP_IWRITE_CX 0x19 2073#define CMD_FCP_IREAD_CR 0x1A 2074#define CMD_FCP_IREAD_CX 0x1B 2075#define CMD_FCP_ICMND_CR 0x1C 2076#define CMD_FCP_ICMND_CX 0x1D 2077#define CMD_FCP_TSEND_CX 0x1F 2078#define CMD_FCP_TRECEIVE_CX 0x21 2079#define CMD_FCP_TRSP_CX 0x23 2080#define CMD_FCP_AUTO_TRSP_CX 0x29 2081 2082#define CMD_ADAPTER_MSG 0x20 2083#define CMD_ADAPTER_DUMP 0x22 2084 2085/* SLI_2 IOCB Command Set */ 2086 2087#define CMD_ASYNC_STATUS 0x7C 2088#define CMD_RCV_SEQUENCE64_CX 0x81 2089#define CMD_XMIT_SEQUENCE64_CR 0x82 2090#define CMD_XMIT_SEQUENCE64_CX 0x83 2091#define CMD_XMIT_BCAST64_CN 0x84 2092#define CMD_XMIT_BCAST64_CX 0x85 2093#define CMD_QUE_RING_BUF64_CN 0x86 2094#define CMD_QUE_XRI_BUF64_CX 0x87 2095#define CMD_IOCB_CONTINUE64_CN 0x88 2096#define CMD_RET_XRI_BUF64_CX 0x89 2097#define CMD_ELS_REQUEST64_CR 0x8A 2098#define CMD_ELS_REQUEST64_CX 0x8B 2099#define CMD_ABORT_MXRI64_CN 0x8C 2100#define CMD_RCV_ELS_REQ64_CX 0x8D 2101#define CMD_XMIT_ELS_RSP64_CX 0x95 2102#define CMD_XMIT_BLS_RSP64_CX 0x97 2103#define CMD_FCP_IWRITE64_CR 0x98 2104#define CMD_FCP_IWRITE64_CX 0x99 2105#define CMD_FCP_IREAD64_CR 0x9A 2106#define CMD_FCP_IREAD64_CX 0x9B 2107#define CMD_FCP_ICMND64_CR 0x9C 2108#define CMD_FCP_ICMND64_CX 0x9D 2109#define CMD_FCP_TSEND64_CX 0x9F 2110#define CMD_FCP_TRECEIVE64_CX 0xA1 2111#define CMD_FCP_TRSP64_CX 0xA3 2112 2113#define CMD_QUE_XRI64_CX 0xB3 2114#define CMD_IOCB_RCV_SEQ64_CX 0xB5 2115#define CMD_IOCB_RCV_ELS64_CX 0xB7 2116#define CMD_IOCB_RET_XRI64_CX 0xB9 2117#define CMD_IOCB_RCV_CONT64_CX 0xBB 2118 2119#define CMD_GEN_REQUEST64_CR 0xC2 2120#define CMD_GEN_REQUEST64_CX 0xC3 2121 2122/* Unhandled SLI-3 Commands */ 2123#define CMD_IOCB_XMIT_MSEQ64_CR 0xB0 2124#define CMD_IOCB_XMIT_MSEQ64_CX 0xB1 2125#define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1 2126#define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD 2127#define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6 2128#define CMD_IOCB_ABORT_EXTENDED_CN 0xBA 2129#define CMD_IOCB_RET_HBQE64_CN 0xCA 2130#define CMD_IOCB_FCP_IBIDIR64_CR 0xAC 2131#define CMD_IOCB_FCP_IBIDIR64_CX 0xAD 2132#define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF 2133#define CMD_IOCB_LOGENTRY_CN 0x94 2134#define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96 2135 2136/* Data Security SLI Commands */ 2137#define DSSCMD_IWRITE64_CR 0xF8 2138#define DSSCMD_IWRITE64_CX 0xF9 2139#define DSSCMD_IREAD64_CR 0xFA 2140#define DSSCMD_IREAD64_CX 0xFB 2141 2142#define CMD_MAX_IOCB_CMD 0xFB 2143#define CMD_IOCB_MASK 0xff 2144 2145#define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG 2146 iocb */ 2147#define LPFC_MAX_ADPTMSG 32 /* max msg data */ 2148/* 2149 * Define Status 2150 */ 2151#define MBX_SUCCESS 0 2152#define MBXERR_NUM_RINGS 1 2153#define MBXERR_NUM_IOCBS 2 2154#define MBXERR_IOCBS_EXCEEDED 3 2155#define MBXERR_BAD_RING_NUMBER 4 2156#define MBXERR_MASK_ENTRIES_RANGE 5 2157#define MBXERR_MASKS_EXCEEDED 6 2158#define MBXERR_BAD_PROFILE 7 2159#define MBXERR_BAD_DEF_CLASS 8 2160#define MBXERR_BAD_MAX_RESPONDER 9 2161#define MBXERR_BAD_MAX_ORIGINATOR 10 2162#define MBXERR_RPI_REGISTERED 11 2163#define MBXERR_RPI_FULL 12 2164#define MBXERR_NO_RESOURCES 13 2165#define MBXERR_BAD_RCV_LENGTH 14 2166#define MBXERR_DMA_ERROR 15 2167#define MBXERR_ERROR 16 2168#define MBXERR_LINK_DOWN 0x33 2169#define MBXERR_SEC_NO_PERMISSION 0xF02 2170#define MBX_NOT_FINISHED 255 2171 2172#define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */ 2173#define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */ 2174 2175#define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */ 2176 2177/* 2178 * return code Fail 2179 */ 2180#define FAILURE 1 2181 2182/* 2183 * Begin Structure Definitions for Mailbox Commands 2184 */ 2185 2186typedef struct { 2187#ifdef __BIG_ENDIAN_BITFIELD 2188 uint8_t tval; 2189 uint8_t tmask; 2190 uint8_t rval; 2191 uint8_t rmask; 2192#else /* __LITTLE_ENDIAN_BITFIELD */ 2193 uint8_t rmask; 2194 uint8_t rval; 2195 uint8_t tmask; 2196 uint8_t tval; 2197#endif 2198} RR_REG; 2199 2200struct ulp_bde { 2201 uint32_t bdeAddress; 2202#ifdef __BIG_ENDIAN_BITFIELD 2203 uint32_t bdeReserved:4; 2204 uint32_t bdeAddrHigh:4; 2205 uint32_t bdeSize:24; 2206#else /* __LITTLE_ENDIAN_BITFIELD */ 2207 uint32_t bdeSize:24; 2208 uint32_t bdeAddrHigh:4; 2209 uint32_t bdeReserved:4; 2210#endif 2211}; 2212 2213typedef struct ULP_BDL { /* SLI-2 */ 2214#ifdef __BIG_ENDIAN_BITFIELD 2215 uint32_t bdeFlags:8; /* BDL Flags */ 2216 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 2217#else /* __LITTLE_ENDIAN_BITFIELD */ 2218 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 2219 uint32_t bdeFlags:8; /* BDL Flags */ 2220#endif 2221 2222 uint32_t addrLow; /* Address 0:31 */ 2223 uint32_t addrHigh; /* Address 32:63 */ 2224 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */ 2225} ULP_BDL; 2226 2227/* 2228 * BlockGuard Definitions 2229 */ 2230 2231enum lpfc_protgrp_type { 2232 LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */ 2233 LPFC_PG_TYPE_NO_DIF, /* no DIF data pointed to by prot grp */ 2234 LPFC_PG_TYPE_EMBD_DIF, /* DIF is embedded (inline) with data */ 2235 LPFC_PG_TYPE_DIF_BUF /* DIF has its own scatter/gather list */ 2236}; 2237 2238/* PDE Descriptors */ 2239#define LPFC_PDE5_DESCRIPTOR 0x85 2240#define LPFC_PDE6_DESCRIPTOR 0x86 2241#define LPFC_PDE7_DESCRIPTOR 0x87 2242 2243/* BlockGuard Opcodes */ 2244#define BG_OP_IN_NODIF_OUT_CRC 0x0 2245#define BG_OP_IN_CRC_OUT_NODIF 0x1 2246#define BG_OP_IN_NODIF_OUT_CSUM 0x2 2247#define BG_OP_IN_CSUM_OUT_NODIF 0x3 2248#define BG_OP_IN_CRC_OUT_CRC 0x4 2249#define BG_OP_IN_CSUM_OUT_CSUM 0x5 2250#define BG_OP_IN_CRC_OUT_CSUM 0x6 2251#define BG_OP_IN_CSUM_OUT_CRC 0x7 2252#define BG_OP_RAW_MODE 0x8 2253 2254struct lpfc_pde5 { 2255 uint32_t word0; 2256#define pde5_type_SHIFT 24 2257#define pde5_type_MASK 0x000000ff 2258#define pde5_type_WORD word0 2259#define pde5_rsvd0_SHIFT 0 2260#define pde5_rsvd0_MASK 0x00ffffff 2261#define pde5_rsvd0_WORD word0 2262 uint32_t reftag; /* Reference Tag Value */ 2263 uint32_t reftagtr; /* Reference Tag Translation Value */ 2264}; 2265 2266struct lpfc_pde6 { 2267 uint32_t word0; 2268#define pde6_type_SHIFT 24 2269#define pde6_type_MASK 0x000000ff 2270#define pde6_type_WORD word0 2271#define pde6_rsvd0_SHIFT 0 2272#define pde6_rsvd0_MASK 0x00ffffff 2273#define pde6_rsvd0_WORD word0 2274 uint32_t word1; 2275#define pde6_rsvd1_SHIFT 26 2276#define pde6_rsvd1_MASK 0x0000003f 2277#define pde6_rsvd1_WORD word1 2278#define pde6_na_SHIFT 25 2279#define pde6_na_MASK 0x00000001 2280#define pde6_na_WORD word1 2281#define pde6_rsvd2_SHIFT 16 2282#define pde6_rsvd2_MASK 0x000001FF 2283#define pde6_rsvd2_WORD word1 2284#define pde6_apptagtr_SHIFT 0 2285#define pde6_apptagtr_MASK 0x0000ffff 2286#define pde6_apptagtr_WORD word1 2287 uint32_t word2; 2288#define pde6_optx_SHIFT 28 2289#define pde6_optx_MASK 0x0000000f 2290#define pde6_optx_WORD word2 2291#define pde6_oprx_SHIFT 24 2292#define pde6_oprx_MASK 0x0000000f 2293#define pde6_oprx_WORD word2 2294#define pde6_nr_SHIFT 23 2295#define pde6_nr_MASK 0x00000001 2296#define pde6_nr_WORD word2 2297#define pde6_ce_SHIFT 22 2298#define pde6_ce_MASK 0x00000001 2299#define pde6_ce_WORD word2 2300#define pde6_re_SHIFT 21 2301#define pde6_re_MASK 0x00000001 2302#define pde6_re_WORD word2 2303#define pde6_ae_SHIFT 20 2304#define pde6_ae_MASK 0x00000001 2305#define pde6_ae_WORD word2 2306#define pde6_ai_SHIFT 19 2307#define pde6_ai_MASK 0x00000001 2308#define pde6_ai_WORD word2 2309#define pde6_bs_SHIFT 16 2310#define pde6_bs_MASK 0x00000007 2311#define pde6_bs_WORD word2 2312#define pde6_apptagval_SHIFT 0 2313#define pde6_apptagval_MASK 0x0000ffff 2314#define pde6_apptagval_WORD word2 2315}; 2316 2317struct lpfc_pde7 { 2318 uint32_t word0; 2319#define pde7_type_SHIFT 24 2320#define pde7_type_MASK 0x000000ff 2321#define pde7_type_WORD word0 2322#define pde7_rsvd0_SHIFT 0 2323#define pde7_rsvd0_MASK 0x00ffffff 2324#define pde7_rsvd0_WORD word0 2325 uint32_t addrHigh; 2326 uint32_t addrLow; 2327}; 2328 2329/* Structure for MB Command LOAD_SM and DOWN_LOAD */ 2330 2331typedef struct { 2332#ifdef __BIG_ENDIAN_BITFIELD 2333 uint32_t rsvd2:25; 2334 uint32_t acknowledgment:1; 2335 uint32_t version:1; 2336 uint32_t erase_or_prog:1; 2337 uint32_t update_flash:1; 2338 uint32_t update_ram:1; 2339 uint32_t method:1; 2340 uint32_t load_cmplt:1; 2341#else /* __LITTLE_ENDIAN_BITFIELD */ 2342 uint32_t load_cmplt:1; 2343 uint32_t method:1; 2344 uint32_t update_ram:1; 2345 uint32_t update_flash:1; 2346 uint32_t erase_or_prog:1; 2347 uint32_t version:1; 2348 uint32_t acknowledgment:1; 2349 uint32_t rsvd2:25; 2350#endif 2351 2352 uint32_t dl_to_adr_low; 2353 uint32_t dl_to_adr_high; 2354 uint32_t dl_len; 2355 union { 2356 uint32_t dl_from_mbx_offset; 2357 struct ulp_bde dl_from_bde; 2358 struct ulp_bde64 dl_from_bde64; 2359 } un; 2360 2361} LOAD_SM_VAR; 2362 2363/* Structure for MB Command READ_NVPARM (02) */ 2364 2365typedef struct { 2366 uint32_t rsvd1[3]; /* Read as all one's */ 2367 uint32_t rsvd2; /* Read as all zero's */ 2368 uint32_t portname[2]; /* N_PORT name */ 2369 uint32_t nodename[2]; /* NODE name */ 2370 2371#ifdef __BIG_ENDIAN_BITFIELD 2372 uint32_t pref_DID:24; 2373 uint32_t hardAL_PA:8; 2374#else /* __LITTLE_ENDIAN_BITFIELD */ 2375 uint32_t hardAL_PA:8; 2376 uint32_t pref_DID:24; 2377#endif 2378 2379 uint32_t rsvd3[21]; /* Read as all one's */ 2380} READ_NV_VAR; 2381 2382/* Structure for MB Command WRITE_NVPARMS (03) */ 2383 2384typedef struct { 2385 uint32_t rsvd1[3]; /* Must be all one's */ 2386 uint32_t rsvd2; /* Must be all zero's */ 2387 uint32_t portname[2]; /* N_PORT name */ 2388 uint32_t nodename[2]; /* NODE name */ 2389 2390#ifdef __BIG_ENDIAN_BITFIELD 2391 uint32_t pref_DID:24; 2392 uint32_t hardAL_PA:8; 2393#else /* __LITTLE_ENDIAN_BITFIELD */ 2394 uint32_t hardAL_PA:8; 2395 uint32_t pref_DID:24; 2396#endif 2397 2398 uint32_t rsvd3[21]; /* Must be all one's */ 2399} WRITE_NV_VAR; 2400 2401/* Structure for MB Command RUN_BIU_DIAG (04) */ 2402/* Structure for MB Command RUN_BIU_DIAG64 (0x84) */ 2403 2404typedef struct { 2405 uint32_t rsvd1; 2406 union { 2407 struct { 2408 struct ulp_bde xmit_bde; 2409 struct ulp_bde rcv_bde; 2410 } s1; 2411 struct { 2412 struct ulp_bde64 xmit_bde64; 2413 struct ulp_bde64 rcv_bde64; 2414 } s2; 2415 } un; 2416} BIU_DIAG_VAR; 2417 2418/* Structure for MB command READ_EVENT_LOG (0x38) */ 2419struct READ_EVENT_LOG_VAR { 2420 uint32_t word1; 2421#define lpfc_event_log_SHIFT 29 2422#define lpfc_event_log_MASK 0x00000001 2423#define lpfc_event_log_WORD word1 2424#define USE_MAILBOX_RESPONSE 1 2425 uint32_t offset; 2426 struct ulp_bde64 rcv_bde64; 2427}; 2428 2429/* Structure for MB Command INIT_LINK (05) */ 2430 2431typedef struct { 2432#ifdef __BIG_ENDIAN_BITFIELD 2433 uint32_t rsvd1:24; 2434 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 2435#else /* __LITTLE_ENDIAN_BITFIELD */ 2436 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 2437 uint32_t rsvd1:24; 2438#endif 2439 2440#ifdef __BIG_ENDIAN_BITFIELD 2441 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 2442 uint8_t rsvd2; 2443 uint16_t link_flags; 2444#else /* __LITTLE_ENDIAN_BITFIELD */ 2445 uint16_t link_flags; 2446 uint8_t rsvd2; 2447 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 2448#endif 2449 2450#define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */ 2451#define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */ 2452#define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */ 2453#define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */ 2454#define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */ 2455#define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */ 2456#define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */ 2457 2458#define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */ 2459#define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */ 2460#define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */ 2461 2462 uint32_t link_speed; 2463#define LINK_SPEED_AUTO 0x0 /* Auto selection */ 2464#define LINK_SPEED_1G 0x1 /* 1 Gigabaud */ 2465#define LINK_SPEED_2G 0x2 /* 2 Gigabaud */ 2466#define LINK_SPEED_4G 0x4 /* 4 Gigabaud */ 2467#define LINK_SPEED_8G 0x8 /* 8 Gigabaud */ 2468#define LINK_SPEED_10G 0x10 /* 10 Gigabaud */ 2469#define LINK_SPEED_16G 0x11 /* 16 Gigabaud */ 2470#define LINK_SPEED_32G 0x14 /* 32 Gigabaud */ 2471#define LINK_SPEED_64G 0x17 /* 64 Gigabaud */ 2472#define LINK_SPEED_128G 0x1A /* 128 Gigabaud */ 2473#define LINK_SPEED_256G 0x1D /* 256 Gigabaud */ 2474 2475} INIT_LINK_VAR; 2476 2477/* Structure for MB Command DOWN_LINK (06) */ 2478 2479typedef struct { 2480 uint32_t rsvd1; 2481} DOWN_LINK_VAR; 2482 2483/* Structure for MB Command CONFIG_LINK (07) */ 2484 2485typedef struct { 2486#ifdef __BIG_ENDIAN_BITFIELD 2487 uint32_t cr:1; 2488 uint32_t ci:1; 2489 uint32_t cr_delay:6; 2490 uint32_t cr_count:8; 2491 uint32_t rsvd1:8; 2492 uint32_t MaxBBC:8; 2493#else /* __LITTLE_ENDIAN_BITFIELD */ 2494 uint32_t MaxBBC:8; 2495 uint32_t rsvd1:8; 2496 uint32_t cr_count:8; 2497 uint32_t cr_delay:6; 2498 uint32_t ci:1; 2499 uint32_t cr:1; 2500#endif 2501 2502 uint32_t myId; 2503 uint32_t rsvd2; 2504 uint32_t edtov; 2505 uint32_t arbtov; 2506 uint32_t ratov; 2507 uint32_t rttov; 2508 uint32_t altov; 2509 uint32_t crtov; 2510 2511#ifdef __BIG_ENDIAN_BITFIELD 2512 uint32_t rsvd4:19; 2513 uint32_t cscn:1; 2514 uint32_t bbscn:4; 2515 uint32_t rsvd3:8; 2516#else /* __LITTLE_ENDIAN_BITFIELD */ 2517 uint32_t rsvd3:8; 2518 uint32_t bbscn:4; 2519 uint32_t cscn:1; 2520 uint32_t rsvd4:19; 2521#endif 2522 2523#ifdef __BIG_ENDIAN_BITFIELD 2524 uint32_t rrq_enable:1; 2525 uint32_t rrq_immed:1; 2526 uint32_t rsvd5:29; 2527 uint32_t ack0_enable:1; 2528#else /* __LITTLE_ENDIAN_BITFIELD */ 2529 uint32_t ack0_enable:1; 2530 uint32_t rsvd5:29; 2531 uint32_t rrq_immed:1; 2532 uint32_t rrq_enable:1; 2533#endif 2534} CONFIG_LINK; 2535 2536/* Structure for MB Command PART_SLIM (08) 2537 * will be removed since SLI1 is no longer supported! 2538 */ 2539typedef struct { 2540#ifdef __BIG_ENDIAN_BITFIELD 2541 uint16_t offCiocb; 2542 uint16_t numCiocb; 2543 uint16_t offRiocb; 2544 uint16_t numRiocb; 2545#else /* __LITTLE_ENDIAN_BITFIELD */ 2546 uint16_t numCiocb; 2547 uint16_t offCiocb; 2548 uint16_t numRiocb; 2549 uint16_t offRiocb; 2550#endif 2551} RING_DEF; 2552 2553typedef struct { 2554#ifdef __BIG_ENDIAN_BITFIELD 2555 uint32_t unused1:24; 2556 uint32_t numRing:8; 2557#else /* __LITTLE_ENDIAN_BITFIELD */ 2558 uint32_t numRing:8; 2559 uint32_t unused1:24; 2560#endif 2561 2562 RING_DEF ringdef[4]; 2563 uint32_t hbainit; 2564} PART_SLIM_VAR; 2565 2566/* Structure for MB Command CONFIG_RING (09) */ 2567 2568typedef struct { 2569#ifdef __BIG_ENDIAN_BITFIELD 2570 uint32_t unused2:6; 2571 uint32_t recvSeq:1; 2572 uint32_t recvNotify:1; 2573 uint32_t numMask:8; 2574 uint32_t profile:8; 2575 uint32_t unused1:4; 2576 uint32_t ring:4; 2577#else /* __LITTLE_ENDIAN_BITFIELD */ 2578 uint32_t ring:4; 2579 uint32_t unused1:4; 2580 uint32_t profile:8; 2581 uint32_t numMask:8; 2582 uint32_t recvNotify:1; 2583 uint32_t recvSeq:1; 2584 uint32_t unused2:6; 2585#endif 2586 2587#ifdef __BIG_ENDIAN_BITFIELD 2588 uint16_t maxRespXchg; 2589 uint16_t maxOrigXchg; 2590#else /* __LITTLE_ENDIAN_BITFIELD */ 2591 uint16_t maxOrigXchg; 2592 uint16_t maxRespXchg; 2593#endif 2594 2595 RR_REG rrRegs[6]; 2596} CONFIG_RING_VAR; 2597 2598/* Structure for MB Command RESET_RING (10) */ 2599 2600typedef struct { 2601 uint32_t ring_no; 2602} RESET_RING_VAR; 2603 2604/* Structure for MB Command READ_CONFIG (11) */ 2605 2606typedef struct { 2607#ifdef __BIG_ENDIAN_BITFIELD 2608 uint32_t cr:1; 2609 uint32_t ci:1; 2610 uint32_t cr_delay:6; 2611 uint32_t cr_count:8; 2612 uint32_t InitBBC:8; 2613 uint32_t MaxBBC:8; 2614#else /* __LITTLE_ENDIAN_BITFIELD */ 2615 uint32_t MaxBBC:8; 2616 uint32_t InitBBC:8; 2617 uint32_t cr_count:8; 2618 uint32_t cr_delay:6; 2619 uint32_t ci:1; 2620 uint32_t cr:1; 2621#endif 2622 2623#ifdef __BIG_ENDIAN_BITFIELD 2624 uint32_t topology:8; 2625 uint32_t myDid:24; 2626#else /* __LITTLE_ENDIAN_BITFIELD */ 2627 uint32_t myDid:24; 2628 uint32_t topology:8; 2629#endif 2630 2631 /* Defines for topology (defined previously) */ 2632#ifdef __BIG_ENDIAN_BITFIELD 2633 uint32_t AR:1; 2634 uint32_t IR:1; 2635 uint32_t rsvd1:29; 2636 uint32_t ack0:1; 2637#else /* __LITTLE_ENDIAN_BITFIELD */ 2638 uint32_t ack0:1; 2639 uint32_t rsvd1:29; 2640 uint32_t IR:1; 2641 uint32_t AR:1; 2642#endif 2643 2644 uint32_t edtov; 2645 uint32_t arbtov; 2646 uint32_t ratov; 2647 uint32_t rttov; 2648 uint32_t altov; 2649 uint32_t lmt; 2650#define LMT_RESERVED 0x000 /* Not used */ 2651#define LMT_1Gb 0x004 2652#define LMT_2Gb 0x008 2653#define LMT_4Gb 0x040 2654#define LMT_8Gb 0x080 2655#define LMT_10Gb 0x100 2656#define LMT_16Gb 0x200 2657#define LMT_32Gb 0x400 2658#define LMT_64Gb 0x800 2659#define LMT_128Gb 0x1000 2660#define LMT_256Gb 0x2000 2661 uint32_t rsvd2; 2662 uint32_t rsvd3; 2663 uint32_t max_xri; 2664 uint32_t max_iocb; 2665 uint32_t max_rpi; 2666 uint32_t avail_xri; 2667 uint32_t avail_iocb; 2668 uint32_t avail_rpi; 2669 uint32_t max_vpi; 2670 uint32_t rsvd4; 2671 uint32_t rsvd5; 2672 uint32_t avail_vpi; 2673} READ_CONFIG_VAR; 2674 2675/* Structure for MB Command READ_RCONFIG (12) */ 2676 2677typedef struct { 2678#ifdef __BIG_ENDIAN_BITFIELD 2679 uint32_t rsvd2:7; 2680 uint32_t recvNotify:1; 2681 uint32_t numMask:8; 2682 uint32_t profile:8; 2683 uint32_t rsvd1:4; 2684 uint32_t ring:4; 2685#else /* __LITTLE_ENDIAN_BITFIELD */ 2686 uint32_t ring:4; 2687 uint32_t rsvd1:4; 2688 uint32_t profile:8; 2689 uint32_t numMask:8; 2690 uint32_t recvNotify:1; 2691 uint32_t rsvd2:7; 2692#endif 2693 2694#ifdef __BIG_ENDIAN_BITFIELD 2695 uint16_t maxResp; 2696 uint16_t maxOrig; 2697#else /* __LITTLE_ENDIAN_BITFIELD */ 2698 uint16_t maxOrig; 2699 uint16_t maxResp; 2700#endif 2701 2702 RR_REG rrRegs[6]; 2703 2704#ifdef __BIG_ENDIAN_BITFIELD 2705 uint16_t cmdRingOffset; 2706 uint16_t cmdEntryCnt; 2707 uint16_t rspRingOffset; 2708 uint16_t rspEntryCnt; 2709 uint16_t nextCmdOffset; 2710 uint16_t rsvd3; 2711 uint16_t nextRspOffset; 2712 uint16_t rsvd4; 2713#else /* __LITTLE_ENDIAN_BITFIELD */ 2714 uint16_t cmdEntryCnt; 2715 uint16_t cmdRingOffset; 2716 uint16_t rspEntryCnt; 2717 uint16_t rspRingOffset; 2718 uint16_t rsvd3; 2719 uint16_t nextCmdOffset; 2720 uint16_t rsvd4; 2721 uint16_t nextRspOffset; 2722#endif 2723} READ_RCONF_VAR; 2724 2725/* Structure for MB Command READ_SPARM (13) */ 2726/* Structure for MB Command READ_SPARM64 (0x8D) */ 2727 2728typedef struct { 2729 uint32_t rsvd1; 2730 uint32_t rsvd2; 2731 union { 2732 struct ulp_bde sp; /* This BDE points to struct serv_parm 2733 structure */ 2734 struct ulp_bde64 sp64; 2735 } un; 2736#ifdef __BIG_ENDIAN_BITFIELD 2737 uint16_t rsvd3; 2738 uint16_t vpi; 2739#else /* __LITTLE_ENDIAN_BITFIELD */ 2740 uint16_t vpi; 2741 uint16_t rsvd3; 2742#endif 2743} READ_SPARM_VAR; 2744 2745/* Structure for MB Command READ_STATUS (14) */ 2746enum read_status_word1 { 2747 RD_ST_CC = 0x01, 2748 RD_ST_XKB = 0x80, 2749}; 2750 2751enum read_status_word17 { 2752 RD_ST_XMIT_XKB_MASK = 0x3fffff, 2753}; 2754 2755enum read_status_word18 { 2756 RD_ST_RCV_XKB_MASK = 0x3fffff, 2757}; 2758 2759typedef struct { 2760 u8 clear_counters; /* rsvd 7:1, cc 0 */ 2761 u8 rsvd5; 2762 u8 rsvd6; 2763 u8 xkb; /* xkb 7, rsvd 6:0 */ 2764 2765 u32 rsvd8; 2766 2767 uint32_t xmitByteCnt; 2768 uint32_t rcvByteCnt; 2769 uint32_t xmitFrameCnt; 2770 uint32_t rcvFrameCnt; 2771 uint32_t xmitSeqCnt; 2772 uint32_t rcvSeqCnt; 2773 uint32_t totalOrigExchanges; 2774 uint32_t totalRespExchanges; 2775 uint32_t rcvPbsyCnt; 2776 uint32_t rcvFbsyCnt; 2777 2778 u32 drop_frame_no_rq; 2779 u32 empty_rq; 2780 u32 drop_frame_no_xri; 2781 u32 empty_xri; 2782 2783 u32 xmit_xkb; /* rsvd 31:22, xmit_xkb 21:0 */ 2784 u32 rcv_xkb; /* rsvd 31:22, rcv_xkb 21:0 */ 2785} READ_STATUS_VAR; 2786 2787/* Structure for MB Command READ_RPI (15) */ 2788/* Structure for MB Command READ_RPI64 (0x8F) */ 2789 2790typedef struct { 2791#ifdef __BIG_ENDIAN_BITFIELD 2792 uint16_t nextRpi; 2793 uint16_t reqRpi; 2794 uint32_t rsvd2:8; 2795 uint32_t DID:24; 2796#else /* __LITTLE_ENDIAN_BITFIELD */ 2797 uint16_t reqRpi; 2798 uint16_t nextRpi; 2799 uint32_t DID:24; 2800 uint32_t rsvd2:8; 2801#endif 2802 2803 union { 2804 struct ulp_bde sp; 2805 struct ulp_bde64 sp64; 2806 } un; 2807 2808} READ_RPI_VAR; 2809 2810/* Structure for MB Command READ_XRI (16) */ 2811 2812typedef struct { 2813#ifdef __BIG_ENDIAN_BITFIELD 2814 uint16_t nextXri; 2815 uint16_t reqXri; 2816 uint16_t rsvd1; 2817 uint16_t rpi; 2818 uint32_t rsvd2:8; 2819 uint32_t DID:24; 2820 uint32_t rsvd3:8; 2821 uint32_t SID:24; 2822 uint32_t rsvd4; 2823 uint8_t seqId; 2824 uint8_t rsvd5; 2825 uint16_t seqCount; 2826 uint16_t oxId; 2827 uint16_t rxId; 2828 uint32_t rsvd6:30; 2829 uint32_t si:1; 2830 uint32_t exchOrig:1; 2831#else /* __LITTLE_ENDIAN_BITFIELD */ 2832 uint16_t reqXri; 2833 uint16_t nextXri; 2834 uint16_t rpi; 2835 uint16_t rsvd1; 2836 uint32_t DID:24; 2837 uint32_t rsvd2:8; 2838 uint32_t SID:24; 2839 uint32_t rsvd3:8; 2840 uint32_t rsvd4; 2841 uint16_t seqCount; 2842 uint8_t rsvd5; 2843 uint8_t seqId; 2844 uint16_t rxId; 2845 uint16_t oxId; 2846 uint32_t exchOrig:1; 2847 uint32_t si:1; 2848 uint32_t rsvd6:30; 2849#endif 2850} READ_XRI_VAR; 2851 2852/* Structure for MB Command READ_REV (17) */ 2853 2854typedef struct { 2855#ifdef __BIG_ENDIAN_BITFIELD 2856 uint32_t cv:1; 2857 uint32_t rr:1; 2858 uint32_t rsvd2:2; 2859 uint32_t v3req:1; 2860 uint32_t v3rsp:1; 2861 uint32_t rsvd1:25; 2862 uint32_t rv:1; 2863#else /* __LITTLE_ENDIAN_BITFIELD */ 2864 uint32_t rv:1; 2865 uint32_t rsvd1:25; 2866 uint32_t v3rsp:1; 2867 uint32_t v3req:1; 2868 uint32_t rsvd2:2; 2869 uint32_t rr:1; 2870 uint32_t cv:1; 2871#endif 2872 2873 uint32_t biuRev; 2874 uint32_t smRev; 2875 union { 2876 uint32_t smFwRev; 2877 struct { 2878#ifdef __BIG_ENDIAN_BITFIELD 2879 uint8_t ProgType; 2880 uint8_t ProgId; 2881 uint16_t ProgVer:4; 2882 uint16_t ProgRev:4; 2883 uint16_t ProgFixLvl:2; 2884 uint16_t ProgDistType:2; 2885 uint16_t DistCnt:4; 2886#else /* __LITTLE_ENDIAN_BITFIELD */ 2887 uint16_t DistCnt:4; 2888 uint16_t ProgDistType:2; 2889 uint16_t ProgFixLvl:2; 2890 uint16_t ProgRev:4; 2891 uint16_t ProgVer:4; 2892 uint8_t ProgId; 2893 uint8_t ProgType; 2894#endif 2895 2896 } b; 2897 } un; 2898 uint32_t endecRev; 2899#ifdef __BIG_ENDIAN_BITFIELD 2900 uint8_t feaLevelHigh; 2901 uint8_t feaLevelLow; 2902 uint8_t fcphHigh; 2903 uint8_t fcphLow; 2904#else /* __LITTLE_ENDIAN_BITFIELD */ 2905 uint8_t fcphLow; 2906 uint8_t fcphHigh; 2907 uint8_t feaLevelLow; 2908 uint8_t feaLevelHigh; 2909#endif 2910 2911 uint32_t postKernRev; 2912 uint32_t opFwRev; 2913 uint8_t opFwName[16]; 2914 uint32_t sli1FwRev; 2915 uint8_t sli1FwName[16]; 2916 uint32_t sli2FwRev; 2917 uint8_t sli2FwName[16]; 2918 uint32_t sli3Feat; 2919 uint32_t RandomData[6]; 2920} READ_REV_VAR; 2921 2922/* Structure for MB Command READ_LINK_STAT (18) */ 2923 2924typedef struct { 2925 uint32_t word0; 2926 2927#define lpfc_read_link_stat_rec_SHIFT 0 2928#define lpfc_read_link_stat_rec_MASK 0x1 2929#define lpfc_read_link_stat_rec_WORD word0 2930 2931#define lpfc_read_link_stat_gec_SHIFT 1 2932#define lpfc_read_link_stat_gec_MASK 0x1 2933#define lpfc_read_link_stat_gec_WORD word0 2934 2935#define lpfc_read_link_stat_w02oftow23of_SHIFT 2 2936#define lpfc_read_link_stat_w02oftow23of_MASK 0x3FFFFF 2937#define lpfc_read_link_stat_w02oftow23of_WORD word0 2938 2939#define lpfc_read_link_stat_rsvd_SHIFT 24 2940#define lpfc_read_link_stat_rsvd_MASK 0x1F 2941#define lpfc_read_link_stat_rsvd_WORD word0 2942 2943#define lpfc_read_link_stat_gec2_SHIFT 29 2944#define lpfc_read_link_stat_gec2_MASK 0x1 2945#define lpfc_read_link_stat_gec2_WORD word0 2946 2947#define lpfc_read_link_stat_clrc_SHIFT 30 2948#define lpfc_read_link_stat_clrc_MASK 0x1 2949#define lpfc_read_link_stat_clrc_WORD word0 2950 2951#define lpfc_read_link_stat_clof_SHIFT 31 2952#define lpfc_read_link_stat_clof_MASK 0x1 2953#define lpfc_read_link_stat_clof_WORD word0 2954 2955 uint32_t linkFailureCnt; 2956 uint32_t lossSyncCnt; 2957 uint32_t lossSignalCnt; 2958 uint32_t primSeqErrCnt; 2959 uint32_t invalidXmitWord; 2960 uint32_t crcCnt; 2961 uint32_t primSeqTimeout; 2962 uint32_t elasticOverrun; 2963 uint32_t arbTimeout; 2964 uint32_t advRecBufCredit; 2965 uint32_t curRecBufCredit; 2966 uint32_t advTransBufCredit; 2967 uint32_t curTransBufCredit; 2968 uint32_t recEofCount; 2969 uint32_t recEofdtiCount; 2970 uint32_t recEofniCount; 2971 uint32_t recSofcount; 2972 uint32_t rsvd1; 2973 uint32_t rsvd2; 2974 uint32_t recDrpXriCount; 2975 uint32_t fecCorrBlkCount; 2976 uint32_t fecUncorrBlkCount; 2977} READ_LNK_VAR; 2978 2979/* Structure for MB Command REG_LOGIN (19) */ 2980/* Structure for MB Command REG_LOGIN64 (0x93) */ 2981 2982typedef struct { 2983#ifdef __BIG_ENDIAN_BITFIELD 2984 uint16_t rsvd1; 2985 uint16_t rpi; 2986 uint32_t rsvd2:8; 2987 uint32_t did:24; 2988#else /* __LITTLE_ENDIAN_BITFIELD */ 2989 uint16_t rpi; 2990 uint16_t rsvd1; 2991 uint32_t did:24; 2992 uint32_t rsvd2:8; 2993#endif 2994 2995 union { 2996 struct ulp_bde sp; 2997 struct ulp_bde64 sp64; 2998 } un; 2999 3000#ifdef __BIG_ENDIAN_BITFIELD 3001 uint16_t rsvd6; 3002 uint16_t vpi; 3003#else /* __LITTLE_ENDIAN_BITFIELD */ 3004 uint16_t vpi; 3005 uint16_t rsvd6; 3006#endif 3007 3008} REG_LOGIN_VAR; 3009 3010/* Word 30 contents for REG_LOGIN */ 3011typedef union { 3012 struct { 3013#ifdef __BIG_ENDIAN_BITFIELD 3014 uint16_t rsvd1:12; 3015 uint16_t wd30_class:4; 3016 uint16_t xri; 3017#else /* __LITTLE_ENDIAN_BITFIELD */ 3018 uint16_t xri; 3019 uint16_t wd30_class:4; 3020 uint16_t rsvd1:12; 3021#endif 3022 } f; 3023 uint32_t word; 3024} REG_WD30; 3025 3026/* Structure for MB Command UNREG_LOGIN (20) */ 3027 3028typedef struct { 3029#ifdef __BIG_ENDIAN_BITFIELD 3030 uint16_t rsvd1; 3031 uint16_t rpi; 3032 uint32_t rsvd2; 3033 uint32_t rsvd3; 3034 uint32_t rsvd4; 3035 uint32_t rsvd5; 3036 uint16_t rsvd6; 3037 uint16_t vpi; 3038#else /* __LITTLE_ENDIAN_BITFIELD */ 3039 uint16_t rpi; 3040 uint16_t rsvd1; 3041 uint32_t rsvd2; 3042 uint32_t rsvd3; 3043 uint32_t rsvd4; 3044 uint32_t rsvd5; 3045 uint16_t vpi; 3046 uint16_t rsvd6; 3047#endif 3048} UNREG_LOGIN_VAR; 3049 3050/* Structure for MB Command REG_VPI (0x96) */ 3051typedef struct { 3052#ifdef __BIG_ENDIAN_BITFIELD 3053 uint32_t rsvd1; 3054 uint32_t rsvd2:7; 3055 uint32_t upd:1; 3056 uint32_t sid:24; 3057 uint32_t wwn[2]; 3058 uint32_t rsvd5; 3059 uint16_t vfi; 3060 uint16_t vpi; 3061#else /* __LITTLE_ENDIAN */ 3062 uint32_t rsvd1; 3063 uint32_t sid:24; 3064 uint32_t upd:1; 3065 uint32_t rsvd2:7; 3066 uint32_t wwn[2]; 3067 uint32_t rsvd5; 3068 uint16_t vpi; 3069 uint16_t vfi; 3070#endif 3071} REG_VPI_VAR; 3072 3073/* Structure for MB Command UNREG_VPI (0x97) */ 3074typedef struct { 3075 uint32_t rsvd1; 3076#ifdef __BIG_ENDIAN_BITFIELD 3077 uint16_t rsvd2; 3078 uint16_t sli4_vpi; 3079#else /* __LITTLE_ENDIAN */ 3080 uint16_t sli4_vpi; 3081 uint16_t rsvd2; 3082#endif 3083 uint32_t rsvd3; 3084 uint32_t rsvd4; 3085 uint32_t rsvd5; 3086#ifdef __BIG_ENDIAN_BITFIELD 3087 uint16_t rsvd6; 3088 uint16_t vpi; 3089#else /* __LITTLE_ENDIAN */ 3090 uint16_t vpi; 3091 uint16_t rsvd6; 3092#endif 3093} UNREG_VPI_VAR; 3094 3095/* Structure for MB Command UNREG_D_ID (0x23) */ 3096 3097typedef struct { 3098 uint32_t did; 3099 uint32_t rsvd2; 3100 uint32_t rsvd3; 3101 uint32_t rsvd4; 3102 uint32_t rsvd5; 3103#ifdef __BIG_ENDIAN_BITFIELD 3104 uint16_t rsvd6; 3105 uint16_t vpi; 3106#else 3107 uint16_t vpi; 3108 uint16_t rsvd6; 3109#endif 3110} UNREG_D_ID_VAR; 3111 3112/* Structure for MB Command READ_TOPOLOGY (0x95) */ 3113struct lpfc_mbx_read_top { 3114 uint32_t eventTag; /* Event tag */ 3115 uint32_t word2; 3116#define lpfc_mbx_read_top_fa_SHIFT 12 3117#define lpfc_mbx_read_top_fa_MASK 0x00000001 3118#define lpfc_mbx_read_top_fa_WORD word2 3119#define lpfc_mbx_read_top_mm_SHIFT 11 3120#define lpfc_mbx_read_top_mm_MASK 0x00000001 3121#define lpfc_mbx_read_top_mm_WORD word2 3122#define lpfc_mbx_read_top_pb_SHIFT 9 3123#define lpfc_mbx_read_top_pb_MASK 0X00000001 3124#define lpfc_mbx_read_top_pb_WORD word2 3125#define lpfc_mbx_read_top_il_SHIFT 8 3126#define lpfc_mbx_read_top_il_MASK 0x00000001 3127#define lpfc_mbx_read_top_il_WORD word2 3128#define lpfc_mbx_read_top_att_type_SHIFT 0 3129#define lpfc_mbx_read_top_att_type_MASK 0x000000FF 3130#define lpfc_mbx_read_top_att_type_WORD word2 3131#define LPFC_ATT_RESERVED 0x00 /* Reserved - attType */ 3132#define LPFC_ATT_LINK_UP 0x01 /* Link is up */ 3133#define LPFC_ATT_LINK_DOWN 0x02 /* Link is down */ 3134#define LPFC_ATT_UNEXP_WWPN 0x06 /* Link is down Unexpected WWWPN */ 3135 uint32_t word3; 3136#define lpfc_mbx_read_top_alpa_granted_SHIFT 24 3137#define lpfc_mbx_read_top_alpa_granted_MASK 0x000000FF 3138#define lpfc_mbx_read_top_alpa_granted_WORD word3 3139#define lpfc_mbx_read_top_lip_alps_SHIFT 16 3140#define lpfc_mbx_read_top_lip_alps_MASK 0x000000FF 3141#define lpfc_mbx_read_top_lip_alps_WORD word3 3142#define lpfc_mbx_read_top_lip_type_SHIFT 8 3143#define lpfc_mbx_read_top_lip_type_MASK 0x000000FF 3144#define lpfc_mbx_read_top_lip_type_WORD word3 3145#define lpfc_mbx_read_top_topology_SHIFT 0 3146#define lpfc_mbx_read_top_topology_MASK 0x000000FF 3147#define lpfc_mbx_read_top_topology_WORD word3 3148#define LPFC_TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */ 3149#define LPFC_TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */ 3150 /* store the LILP AL_PA position map into */ 3151 struct ulp_bde64 lilpBde64; 3152#define LPFC_ALPA_MAP_SIZE 128 3153 uint32_t word7; 3154#define lpfc_mbx_read_top_ld_lu_SHIFT 31 3155#define lpfc_mbx_read_top_ld_lu_MASK 0x00000001 3156#define lpfc_mbx_read_top_ld_lu_WORD word7 3157#define lpfc_mbx_read_top_ld_tf_SHIFT 30 3158#define lpfc_mbx_read_top_ld_tf_MASK 0x00000001 3159#define lpfc_mbx_read_top_ld_tf_WORD word7 3160#define lpfc_mbx_read_top_ld_link_spd_SHIFT 8 3161#define lpfc_mbx_read_top_ld_link_spd_MASK 0x000000FF 3162#define lpfc_mbx_read_top_ld_link_spd_WORD word7 3163#define lpfc_mbx_read_top_ld_nl_port_SHIFT 4 3164#define lpfc_mbx_read_top_ld_nl_port_MASK 0x0000000F 3165#define lpfc_mbx_read_top_ld_nl_port_WORD word7 3166#define lpfc_mbx_read_top_ld_tx_SHIFT 2 3167#define lpfc_mbx_read_top_ld_tx_MASK 0x00000003 3168#define lpfc_mbx_read_top_ld_tx_WORD word7 3169#define lpfc_mbx_read_top_ld_rx_SHIFT 0 3170#define lpfc_mbx_read_top_ld_rx_MASK 0x00000003 3171#define lpfc_mbx_read_top_ld_rx_WORD word7 3172 uint32_t word8; 3173#define lpfc_mbx_read_top_lu_SHIFT 31 3174#define lpfc_mbx_read_top_lu_MASK 0x00000001 3175#define lpfc_mbx_read_top_lu_WORD word8 3176#define lpfc_mbx_read_top_tf_SHIFT 30 3177#define lpfc_mbx_read_top_tf_MASK 0x00000001 3178#define lpfc_mbx_read_top_tf_WORD word8 3179#define lpfc_mbx_read_top_link_spd_SHIFT 8 3180#define lpfc_mbx_read_top_link_spd_MASK 0x000000FF 3181#define lpfc_mbx_read_top_link_spd_WORD word8 3182#define lpfc_mbx_read_top_nl_port_SHIFT 4 3183#define lpfc_mbx_read_top_nl_port_MASK 0x0000000F 3184#define lpfc_mbx_read_top_nl_port_WORD word8 3185#define lpfc_mbx_read_top_tx_SHIFT 2 3186#define lpfc_mbx_read_top_tx_MASK 0x00000003 3187#define lpfc_mbx_read_top_tx_WORD word8 3188#define lpfc_mbx_read_top_rx_SHIFT 0 3189#define lpfc_mbx_read_top_rx_MASK 0x00000003 3190#define lpfc_mbx_read_top_rx_WORD word8 3191#define LPFC_LINK_SPEED_UNKNOWN 0x0 3192#define LPFC_LINK_SPEED_1GHZ 0x04 3193#define LPFC_LINK_SPEED_2GHZ 0x08 3194#define LPFC_LINK_SPEED_4GHZ 0x10 3195#define LPFC_LINK_SPEED_8GHZ 0x20 3196#define LPFC_LINK_SPEED_10GHZ 0x40 3197#define LPFC_LINK_SPEED_16GHZ 0x80 3198#define LPFC_LINK_SPEED_32GHZ 0x90 3199#define LPFC_LINK_SPEED_64GHZ 0xA0 3200#define LPFC_LINK_SPEED_128GHZ 0xB0 3201#define LPFC_LINK_SPEED_256GHZ 0xC0 3202}; 3203 3204/* Structure for MB Command CLEAR_LA (22) */ 3205 3206typedef struct { 3207 uint32_t eventTag; /* Event tag */ 3208 uint32_t rsvd1; 3209} CLEAR_LA_VAR; 3210 3211/* Structure for MB Command DUMP */ 3212 3213typedef struct { 3214#ifdef __BIG_ENDIAN_BITFIELD 3215 uint32_t rsvd:25; 3216 uint32_t ra:1; 3217 uint32_t co:1; 3218 uint32_t cv:1; 3219 uint32_t type:4; 3220 uint32_t entry_index:16; 3221 uint32_t region_id:16; 3222#else /* __LITTLE_ENDIAN_BITFIELD */ 3223 uint32_t type:4; 3224 uint32_t cv:1; 3225 uint32_t co:1; 3226 uint32_t ra:1; 3227 uint32_t rsvd:25; 3228 uint32_t region_id:16; 3229 uint32_t entry_index:16; 3230#endif 3231 3232 uint32_t sli4_length; 3233 uint32_t word_cnt; 3234 uint32_t resp_offset; 3235} DUMP_VAR; 3236 3237#define DMP_MEM_REG 0x1 3238#define DMP_NV_PARAMS 0x2 3239#define DMP_LMSD 0x3 /* Link Module Serial Data */ 3240#define DMP_WELL_KNOWN 0x4 3241 3242#define DMP_REGION_VPD 0xe 3243#define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */ 3244#define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */ 3245#define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */ 3246 3247#define DMP_REGION_VPORT 0x16 /* VPort info region */ 3248#define DMP_VPORT_REGION_SIZE 0x200 3249#define DMP_MBOX_OFFSET_WORD 0x5 3250 3251#define DMP_REGION_23 0x17 /* fcoe param and port state region */ 3252#define DMP_RGN23_SIZE 0x400 3253 3254#define WAKE_UP_PARMS_REGION_ID 4 3255#define WAKE_UP_PARMS_WORD_SIZE 15 3256 3257struct vport_rec { 3258 uint8_t wwpn[8]; 3259 uint8_t wwnn[8]; 3260}; 3261 3262#define VPORT_INFO_SIG 0x32324752 3263#define VPORT_INFO_REV_MASK 0xff 3264#define VPORT_INFO_REV 0x1 3265#define MAX_STATIC_VPORT_COUNT 16 3266struct static_vport_info { 3267 uint32_t signature; 3268 uint32_t rev; 3269 struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT]; 3270 uint32_t resvd[66]; 3271}; 3272 3273/* Option rom version structure */ 3274struct prog_id { 3275#ifdef __BIG_ENDIAN_BITFIELD 3276 uint8_t type; 3277 uint8_t id; 3278 uint32_t ver:4; /* Major Version */ 3279 uint32_t rev:4; /* Revision */ 3280 uint32_t lev:2; /* Level */ 3281 uint32_t dist:2; /* Dist Type */ 3282 uint32_t num:4; /* number after dist type */ 3283#else /* __LITTLE_ENDIAN_BITFIELD */ 3284 uint32_t num:4; /* number after dist type */ 3285 uint32_t dist:2; /* Dist Type */ 3286 uint32_t lev:2; /* Level */ 3287 uint32_t rev:4; /* Revision */ 3288 uint32_t ver:4; /* Major Version */ 3289 uint8_t id; 3290 uint8_t type; 3291#endif 3292}; 3293 3294/* Structure for MB Command UPDATE_CFG (0x1B) */ 3295 3296struct update_cfg_var { 3297#ifdef __BIG_ENDIAN_BITFIELD 3298 uint32_t rsvd2:16; 3299 uint32_t type:8; 3300 uint32_t rsvd:1; 3301 uint32_t ra:1; 3302 uint32_t co:1; 3303 uint32_t cv:1; 3304 uint32_t req:4; 3305 uint32_t entry_length:16; 3306 uint32_t region_id:16; 3307#else /* __LITTLE_ENDIAN_BITFIELD */ 3308 uint32_t req:4; 3309 uint32_t cv:1; 3310 uint32_t co:1; 3311 uint32_t ra:1; 3312 uint32_t rsvd:1; 3313 uint32_t type:8; 3314 uint32_t rsvd2:16; 3315 uint32_t region_id:16; 3316 uint32_t entry_length:16; 3317#endif 3318 3319 uint32_t resp_info; 3320 uint32_t byte_cnt; 3321 uint32_t data_offset; 3322}; 3323 3324struct hbq_mask { 3325#ifdef __BIG_ENDIAN_BITFIELD 3326 uint8_t tmatch; 3327 uint8_t tmask; 3328 uint8_t rctlmatch; 3329 uint8_t rctlmask; 3330#else /* __LITTLE_ENDIAN */ 3331 uint8_t rctlmask; 3332 uint8_t rctlmatch; 3333 uint8_t tmask; 3334 uint8_t tmatch; 3335#endif 3336}; 3337 3338 3339/* Structure for MB Command CONFIG_HBQ (7c) */ 3340 3341struct config_hbq_var { 3342#ifdef __BIG_ENDIAN_BITFIELD 3343 uint32_t rsvd1 :7; 3344 uint32_t recvNotify :1; /* Receive Notification */ 3345 uint32_t numMask :8; /* # Mask Entries */ 3346 uint32_t profile :8; /* Selection Profile */ 3347 uint32_t rsvd2 :8; 3348#else /* __LITTLE_ENDIAN */ 3349 uint32_t rsvd2 :8; 3350 uint32_t profile :8; /* Selection Profile */ 3351 uint32_t numMask :8; /* # Mask Entries */ 3352 uint32_t recvNotify :1; /* Receive Notification */ 3353 uint32_t rsvd1 :7; 3354#endif 3355 3356#ifdef __BIG_ENDIAN_BITFIELD 3357 uint32_t hbqId :16; 3358 uint32_t rsvd3 :12; 3359 uint32_t ringMask :4; 3360#else /* __LITTLE_ENDIAN */ 3361 uint32_t ringMask :4; 3362 uint32_t rsvd3 :12; 3363 uint32_t hbqId :16; 3364#endif 3365 3366#ifdef __BIG_ENDIAN_BITFIELD 3367 uint32_t entry_count :16; 3368 uint32_t rsvd4 :8; 3369 uint32_t headerLen :8; 3370#else /* __LITTLE_ENDIAN */ 3371 uint32_t headerLen :8; 3372 uint32_t rsvd4 :8; 3373 uint32_t entry_count :16; 3374#endif 3375 3376 uint32_t hbqaddrLow; 3377 uint32_t hbqaddrHigh; 3378 3379#ifdef __BIG_ENDIAN_BITFIELD 3380 uint32_t rsvd5 :31; 3381 uint32_t logEntry :1; 3382#else /* __LITTLE_ENDIAN */ 3383 uint32_t logEntry :1; 3384 uint32_t rsvd5 :31; 3385#endif 3386 3387 uint32_t rsvd6; /* w7 */ 3388 uint32_t rsvd7; /* w8 */ 3389 uint32_t rsvd8; /* w9 */ 3390 3391 struct hbq_mask hbqMasks[6]; 3392 3393 3394 union { 3395 uint32_t allprofiles[12]; 3396 3397 struct { 3398 #ifdef __BIG_ENDIAN_BITFIELD 3399 uint32_t seqlenoff :16; 3400 uint32_t maxlen :16; 3401 #else /* __LITTLE_ENDIAN */ 3402 uint32_t maxlen :16; 3403 uint32_t seqlenoff :16; 3404 #endif 3405 #ifdef __BIG_ENDIAN_BITFIELD 3406 uint32_t rsvd1 :28; 3407 uint32_t seqlenbcnt :4; 3408 #else /* __LITTLE_ENDIAN */ 3409 uint32_t seqlenbcnt :4; 3410 uint32_t rsvd1 :28; 3411 #endif 3412 uint32_t rsvd[10]; 3413 } profile2; 3414 3415 struct { 3416 #ifdef __BIG_ENDIAN_BITFIELD 3417 uint32_t seqlenoff :16; 3418 uint32_t maxlen :16; 3419 #else /* __LITTLE_ENDIAN */ 3420 uint32_t maxlen :16; 3421 uint32_t seqlenoff :16; 3422 #endif 3423 #ifdef __BIG_ENDIAN_BITFIELD 3424 uint32_t cmdcodeoff :28; 3425 uint32_t rsvd1 :12; 3426 uint32_t seqlenbcnt :4; 3427 #else /* __LITTLE_ENDIAN */ 3428 uint32_t seqlenbcnt :4; 3429 uint32_t rsvd1 :12; 3430 uint32_t cmdcodeoff :28; 3431 #endif 3432 uint32_t cmdmatch[8]; 3433 3434 uint32_t rsvd[2]; 3435 } profile3; 3436 3437 struct { 3438 #ifdef __BIG_ENDIAN_BITFIELD 3439 uint32_t seqlenoff :16; 3440 uint32_t maxlen :16; 3441 #else /* __LITTLE_ENDIAN */ 3442 uint32_t maxlen :16; 3443 uint32_t seqlenoff :16; 3444 #endif 3445 #ifdef __BIG_ENDIAN_BITFIELD 3446 uint32_t cmdcodeoff :28; 3447 uint32_t rsvd1 :12; 3448 uint32_t seqlenbcnt :4; 3449 #else /* __LITTLE_ENDIAN */ 3450 uint32_t seqlenbcnt :4; 3451 uint32_t rsvd1 :12; 3452 uint32_t cmdcodeoff :28; 3453 #endif 3454 uint32_t cmdmatch[8]; 3455 3456 uint32_t rsvd[2]; 3457 } profile5; 3458 3459 } profiles; 3460 3461}; 3462 3463 3464 3465/* Structure for MB Command CONFIG_PORT (0x88) */ 3466typedef struct { 3467#ifdef __BIG_ENDIAN_BITFIELD 3468 uint32_t cBE : 1; 3469 uint32_t cET : 1; 3470 uint32_t cHpcb : 1; 3471 uint32_t cMA : 1; 3472 uint32_t sli_mode : 4; 3473 uint32_t pcbLen : 24; /* bit 23:0 of memory based port 3474 * config block */ 3475#else /* __LITTLE_ENDIAN */ 3476 uint32_t pcbLen : 24; /* bit 23:0 of memory based port 3477 * config block */ 3478 uint32_t sli_mode : 4; 3479 uint32_t cMA : 1; 3480 uint32_t cHpcb : 1; 3481 uint32_t cET : 1; 3482 uint32_t cBE : 1; 3483#endif 3484 3485 uint32_t pcbLow; /* bit 31:0 of memory based port config block */ 3486 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */ 3487 uint32_t hbainit[5]; 3488#ifdef __BIG_ENDIAN_BITFIELD 3489 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */ 3490 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */ 3491#else /* __LITTLE_ENDIAN */ 3492 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */ 3493 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */ 3494#endif 3495 3496#ifdef __BIG_ENDIAN_BITFIELD 3497 uint32_t rsvd1 : 20; /* Reserved */ 3498 uint32_t casabt : 1; /* Configure async abts status notice */ 3499 uint32_t rsvd2 : 2; /* Reserved */ 3500 uint32_t cbg : 1; /* Configure BlockGuard */ 3501 uint32_t cmv : 1; /* Configure Max VPIs */ 3502 uint32_t ccrp : 1; /* Config Command Ring Polling */ 3503 uint32_t csah : 1; /* Configure Synchronous Abort Handling */ 3504 uint32_t chbs : 1; /* Cofigure Host Backing store */ 3505 uint32_t cinb : 1; /* Enable Interrupt Notification Block */ 3506 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ 3507 uint32_t cmx : 1; /* Configure Max XRIs */ 3508 uint32_t cmr : 1; /* Configure Max RPIs */ 3509#else /* __LITTLE_ENDIAN */ 3510 uint32_t cmr : 1; /* Configure Max RPIs */ 3511 uint32_t cmx : 1; /* Configure Max XRIs */ 3512 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ 3513 uint32_t cinb : 1; /* Enable Interrupt Notification Block */ 3514 uint32_t chbs : 1; /* Cofigure Host Backing store */ 3515 uint32_t csah : 1; /* Configure Synchronous Abort Handling */ 3516 uint32_t ccrp : 1; /* Config Command Ring Polling */ 3517 uint32_t cmv : 1; /* Configure Max VPIs */ 3518 uint32_t cbg : 1; /* Configure BlockGuard */ 3519 uint32_t rsvd2 : 2; /* Reserved */ 3520 uint32_t casabt : 1; /* Configure async abts status notice */ 3521 uint32_t rsvd1 : 20; /* Reserved */ 3522#endif 3523#ifdef __BIG_ENDIAN_BITFIELD 3524 uint32_t rsvd3 : 20; /* Reserved */ 3525 uint32_t gasabt : 1; /* Grant async abts status notice */ 3526 uint32_t rsvd4 : 2; /* Reserved */ 3527 uint32_t gbg : 1; /* Grant BlockGuard */ 3528 uint32_t gmv : 1; /* Grant Max VPIs */ 3529 uint32_t gcrp : 1; /* Grant Command Ring Polling */ 3530 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ 3531 uint32_t ghbs : 1; /* Grant Host Backing Store */ 3532 uint32_t ginb : 1; /* Grant Interrupt Notification Block */ 3533 uint32_t gerbm : 1; /* Grant ERBM Request */ 3534 uint32_t gmx : 1; /* Grant Max XRIs */ 3535 uint32_t gmr : 1; /* Grant Max RPIs */ 3536#else /* __LITTLE_ENDIAN */ 3537 uint32_t gmr : 1; /* Grant Max RPIs */ 3538 uint32_t gmx : 1; /* Grant Max XRIs */ 3539 uint32_t gerbm : 1; /* Grant ERBM Request */ 3540 uint32_t ginb : 1; /* Grant Interrupt Notification Block */ 3541 uint32_t ghbs : 1; /* Grant Host Backing Store */ 3542 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ 3543 uint32_t gcrp : 1; /* Grant Command Ring Polling */ 3544 uint32_t gmv : 1; /* Grant Max VPIs */ 3545 uint32_t gbg : 1; /* Grant BlockGuard */ 3546 uint32_t rsvd4 : 2; /* Reserved */ 3547 uint32_t gasabt : 1; /* Grant async abts status notice */ 3548 uint32_t rsvd3 : 20; /* Reserved */ 3549#endif 3550 3551#ifdef __BIG_ENDIAN_BITFIELD 3552 uint32_t max_rpi : 16; /* Max RPIs Port should configure */ 3553 uint32_t max_xri : 16; /* Max XRIs Port should configure */ 3554#else /* __LITTLE_ENDIAN */ 3555 uint32_t max_xri : 16; /* Max XRIs Port should configure */ 3556 uint32_t max_rpi : 16; /* Max RPIs Port should configure */ 3557#endif 3558 3559#ifdef __BIG_ENDIAN_BITFIELD 3560 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ 3561 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */ 3562#else /* __LITTLE_ENDIAN */ 3563 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */ 3564 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ 3565#endif 3566 3567 uint32_t rsvd6; /* Reserved */ 3568 3569#ifdef __BIG_ENDIAN_BITFIELD 3570 uint32_t rsvd7 : 16; 3571 uint32_t max_vpi : 16; /* Max number of virt N-Ports */ 3572#else /* __LITTLE_ENDIAN */ 3573 uint32_t max_vpi : 16; /* Max number of virt N-Ports */ 3574 uint32_t rsvd7 : 16; 3575#endif 3576 3577} CONFIG_PORT_VAR; 3578 3579/* Structure for MB Command CONFIG_MSI (0x30) */ 3580struct config_msi_var { 3581#ifdef __BIG_ENDIAN_BITFIELD 3582 uint32_t dfltMsgNum:8; /* Default message number */ 3583 uint32_t rsvd1:11; /* Reserved */ 3584 uint32_t NID:5; /* Number of secondary attention IDs */ 3585 uint32_t rsvd2:5; /* Reserved */ 3586 uint32_t dfltPresent:1; /* Default message number present */ 3587 uint32_t addFlag:1; /* Add association flag */ 3588 uint32_t reportFlag:1; /* Report association flag */ 3589#else /* __LITTLE_ENDIAN_BITFIELD */ 3590 uint32_t reportFlag:1; /* Report association flag */ 3591 uint32_t addFlag:1; /* Add association flag */ 3592 uint32_t dfltPresent:1; /* Default message number present */ 3593 uint32_t rsvd2:5; /* Reserved */ 3594 uint32_t NID:5; /* Number of secondary attention IDs */ 3595 uint32_t rsvd1:11; /* Reserved */ 3596 uint32_t dfltMsgNum:8; /* Default message number */ 3597#endif 3598 uint32_t attentionConditions[2]; 3599 uint8_t attentionId[16]; 3600 uint8_t messageNumberByHA[64]; 3601 uint8_t messageNumberByID[16]; 3602 uint32_t autoClearHA[2]; 3603#ifdef __BIG_ENDIAN_BITFIELD 3604 uint32_t rsvd3:16; 3605 uint32_t autoClearID:16; 3606#else /* __LITTLE_ENDIAN_BITFIELD */ 3607 uint32_t autoClearID:16; 3608 uint32_t rsvd3:16; 3609#endif 3610 uint32_t rsvd4; 3611}; 3612 3613/* SLI-2 Port Control Block */ 3614 3615/* SLIM POINTER */ 3616#define SLIMOFF 0x30 /* WORD */ 3617 3618typedef struct _SLI2_RDSC { 3619 uint32_t cmdEntries; 3620 uint32_t cmdAddrLow; 3621 uint32_t cmdAddrHigh; 3622 3623 uint32_t rspEntries; 3624 uint32_t rspAddrLow; 3625 uint32_t rspAddrHigh; 3626} SLI2_RDSC; 3627 3628typedef struct _PCB { 3629#ifdef __BIG_ENDIAN_BITFIELD 3630 uint32_t type:8; 3631#define TYPE_NATIVE_SLI2 0x01 3632 uint32_t feature:8; 3633#define FEATURE_INITIAL_SLI2 0x01 3634 uint32_t rsvd:12; 3635 uint32_t maxRing:4; 3636#else /* __LITTLE_ENDIAN_BITFIELD */ 3637 uint32_t maxRing:4; 3638 uint32_t rsvd:12; 3639 uint32_t feature:8; 3640#define FEATURE_INITIAL_SLI2 0x01 3641 uint32_t type:8; 3642#define TYPE_NATIVE_SLI2 0x01 3643#endif 3644 3645 uint32_t mailBoxSize; 3646 uint32_t mbAddrLow; 3647 uint32_t mbAddrHigh; 3648 3649 uint32_t hgpAddrLow; 3650 uint32_t hgpAddrHigh; 3651 3652 uint32_t pgpAddrLow; 3653 uint32_t pgpAddrHigh; 3654 SLI2_RDSC rdsc[MAX_SLI3_RINGS]; 3655} PCB_t; 3656 3657/* NEW_FEATURE */ 3658typedef struct { 3659#ifdef __BIG_ENDIAN_BITFIELD 3660 uint32_t rsvd0:27; 3661 uint32_t discardFarp:1; 3662 uint32_t IPEnable:1; 3663 uint32_t nodeName:1; 3664 uint32_t portName:1; 3665 uint32_t filterEnable:1; 3666#else /* __LITTLE_ENDIAN_BITFIELD */ 3667 uint32_t filterEnable:1; 3668 uint32_t portName:1; 3669 uint32_t nodeName:1; 3670 uint32_t IPEnable:1; 3671 uint32_t discardFarp:1; 3672 uint32_t rsvd:27; 3673#endif 3674 3675 uint8_t portname[8]; /* Used to be struct lpfc_name */ 3676 uint8_t nodename[8]; 3677 uint32_t rsvd1; 3678 uint32_t rsvd2; 3679 uint32_t rsvd3; 3680 uint32_t IPAddress; 3681} CONFIG_FARP_VAR; 3682 3683/* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */ 3684 3685typedef struct { 3686#ifdef __BIG_ENDIAN_BITFIELD 3687 uint32_t rsvd:30; 3688 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ 3689#else /* __LITTLE_ENDIAN */ 3690 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ 3691 uint32_t rsvd:30; 3692#endif 3693} ASYNCEVT_ENABLE_VAR; 3694 3695/* Union of all Mailbox Command types */ 3696#define MAILBOX_CMD_WSIZE 32 3697#define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t)) 3698/* ext_wsize times 4 bytes should not be greater than max xmit size */ 3699#define MAILBOX_EXT_WSIZE 512 3700#define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t)) 3701#define MAILBOX_HBA_EXT_OFFSET 0x100 3702/* max mbox xmit size is a page size for sysfs IO operations */ 3703#define MAILBOX_SYSFS_MAX 4096 3704 3705typedef union { 3706 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/ 3707 * feature/max ring number 3708 */ 3709 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */ 3710 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */ 3711 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */ 3712 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */ 3713 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */ 3714 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */ 3715 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */ 3716 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */ 3717 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */ 3718 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */ 3719 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */ 3720 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */ 3721 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */ 3722 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */ 3723 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */ 3724 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */ 3725 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */ 3726 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */ 3727 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */ 3728 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */ 3729 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */ 3730 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */ 3731 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */ 3732 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP) 3733 * NEW_FEATURE 3734 */ 3735 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */ 3736 struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/ 3737 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */ 3738 struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */ 3739 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */ 3740 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */ 3741 ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */ 3742 struct READ_EVENT_LOG_VAR varRdEventLog; /* cmd = 0x38 3743 * (READ_EVENT_LOG) 3744 */ 3745 struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */ 3746} MAILVARIANTS; 3747 3748/* 3749 * SLI-2 specific structures 3750 */ 3751 3752struct lpfc_hgp { 3753 __le32 cmdPutInx; 3754 __le32 rspGetInx; 3755}; 3756 3757struct lpfc_pgp { 3758 __le32 cmdGetInx; 3759 __le32 rspPutInx; 3760}; 3761 3762struct sli2_desc { 3763 uint32_t unused1[16]; 3764 struct lpfc_hgp host[MAX_SLI3_RINGS]; 3765 struct lpfc_pgp port[MAX_SLI3_RINGS]; 3766}; 3767 3768struct sli3_desc { 3769 struct lpfc_hgp host[MAX_SLI3_RINGS]; 3770 uint32_t reserved[8]; 3771 uint32_t hbq_put[16]; 3772}; 3773 3774struct sli3_pgp { 3775 struct lpfc_pgp port[MAX_SLI3_RINGS]; 3776 uint32_t hbq_get[16]; 3777}; 3778 3779union sli_var { 3780 struct sli2_desc s2; 3781 struct sli3_desc s3; 3782 struct sli3_pgp s3_pgp; 3783}; 3784 3785typedef struct { 3786 struct_group_tagged(MAILBOX_word0, bits, 3787 union { 3788 struct { 3789#ifdef __BIG_ENDIAN_BITFIELD 3790 uint16_t mbxStatus; 3791 uint8_t mbxCommand; 3792 uint8_t mbxReserved:6; 3793 uint8_t mbxHc:1; 3794 uint8_t mbxOwner:1; /* Low order bit first word */ 3795#else /* __LITTLE_ENDIAN_BITFIELD */ 3796 uint8_t mbxOwner:1; /* Low order bit first word */ 3797 uint8_t mbxHc:1; 3798 uint8_t mbxReserved:6; 3799 uint8_t mbxCommand; 3800 uint16_t mbxStatus; 3801#endif 3802 }; 3803 u32 word0; 3804 }; 3805 ); 3806 3807 MAILVARIANTS un; 3808 union sli_var us; 3809} MAILBOX_t; 3810 3811/* 3812 * Begin Structure Definitions for IOCB Commands 3813 */ 3814 3815typedef struct { 3816#ifdef __BIG_ENDIAN_BITFIELD 3817 uint8_t statAction; 3818 uint8_t statRsn; 3819 uint8_t statBaExp; 3820 uint8_t statLocalError; 3821#else /* __LITTLE_ENDIAN_BITFIELD */ 3822 uint8_t statLocalError; 3823 uint8_t statBaExp; 3824 uint8_t statRsn; 3825 uint8_t statAction; 3826#endif 3827 /* statRsn P/F_RJT reason codes */ 3828#define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */ 3829#define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */ 3830#define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */ 3831#define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */ 3832#define RJT_UNSUP_CLASS 0x05 /* Class not supported */ 3833#define RJT_DELIM_ERR 0x06 /* Delimiter usage error */ 3834#define RJT_UNSUP_TYPE 0x07 /* Type not supported */ 3835#define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */ 3836#define RJT_BAD_RCTL 0x09 /* R_CTL invalid */ 3837#define RJT_BAD_FCTL 0x0A /* F_CTL invalid */ 3838#define RJT_BAD_OXID 0x0B /* OX_ID invalid */ 3839#define RJT_BAD_RXID 0x0C /* RX_ID invalid */ 3840#define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */ 3841#define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */ 3842#define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */ 3843#define RJT_BAD_PARM 0x10 /* Param. field invalid */ 3844#define RJT_XCHG_ERR 0x11 /* Exchange error */ 3845#define RJT_PROT_ERR 0x12 /* Protocol error */ 3846#define RJT_BAD_LENGTH 0x13 /* Invalid Length */ 3847#define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */ 3848#define RJT_LOGIN_REQUIRED 0x16 /* Login required */ 3849#define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */ 3850#define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */ 3851#define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */ 3852#define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */ 3853#define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */ 3854 3855#define IOERR_SUCCESS 0x00 /* statLocalError */ 3856#define IOERR_MISSING_CONTINUE 0x01 3857#define IOERR_SEQUENCE_TIMEOUT 0x02 3858#define IOERR_INTERNAL_ERROR 0x03 3859#define IOERR_INVALID_RPI 0x04 3860#define IOERR_NO_XRI 0x05 3861#define IOERR_ILLEGAL_COMMAND 0x06 3862#define IOERR_XCHG_DROPPED 0x07 3863#define IOERR_ILLEGAL_FIELD 0x08 3864#define IOERR_RPI_SUSPENDED 0x09 3865#define IOERR_TOO_MANY_BUFFERS 0x0A 3866#define IOERR_RCV_BUFFER_WAITING 0x0B 3867#define IOERR_NO_CONNECTION 0x0C 3868#define IOERR_TX_DMA_FAILED 0x0D 3869#define IOERR_RX_DMA_FAILED 0x0E 3870#define IOERR_ILLEGAL_FRAME 0x0F 3871#define IOERR_EXTRA_DATA 0x10 3872#define IOERR_NO_RESOURCES 0x11 3873#define IOERR_RESERVED 0x12 3874#define IOERR_ILLEGAL_LENGTH 0x13 3875#define IOERR_UNSUPPORTED_FEATURE 0x14 3876#define IOERR_ABORT_IN_PROGRESS 0x15 3877#define IOERR_ABORT_REQUESTED 0x16 3878#define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17 3879#define IOERR_LOOP_OPEN_FAILURE 0x18 3880#define IOERR_RING_RESET 0x19 3881#define IOERR_LINK_DOWN 0x1A 3882#define IOERR_CORRUPTED_DATA 0x1B 3883#define IOERR_CORRUPTED_RPI 0x1C 3884#define IOERR_OUT_OF_ORDER_DATA 0x1D 3885#define IOERR_OUT_OF_ORDER_ACK 0x1E 3886#define IOERR_DUP_FRAME 0x1F 3887#define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */ 3888#define IOERR_BAD_HOST_ADDRESS 0x21 3889#define IOERR_RCV_HDRBUF_WAITING 0x22 3890#define IOERR_MISSING_HDR_BUFFER 0x23 3891#define IOERR_MSEQ_CHAIN_CORRUPTED 0x24 3892#define IOERR_ABORTMULT_REQUESTED 0x25 3893#define IOERR_BUFFER_SHORTAGE 0x28 3894#define IOERR_DEFAULT 0x29 3895#define IOERR_CNT 0x2A 3896#define IOERR_SLER_FAILURE 0x46 3897#define IOERR_SLER_CMD_RCV_FAILURE 0x47 3898#define IOERR_SLER_REC_RJT_ERR 0x48 3899#define IOERR_SLER_REC_SRR_RETRY_ERR 0x49 3900#define IOERR_SLER_SRR_RJT_ERR 0x4A 3901#define IOERR_SLER_RRQ_RJT_ERR 0x4C 3902#define IOERR_SLER_RRQ_RETRY_ERR 0x4D 3903#define IOERR_SLER_ABTS_ERR 0x4E 3904#define IOERR_ELXSEC_KEY_UNWRAP_ERROR 0xF0 3905#define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR 0xF1 3906#define IOERR_ELXSEC_CRYPTO_ERROR 0xF2 3907#define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR 0xF3 3908#define IOERR_DRVR_MASK 0x100 3909#define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */ 3910#define IOERR_SLI_BRESET 0x102 3911#define IOERR_SLI_ABORTED 0x103 3912#define IOERR_PARAM_MASK 0x1ff 3913} PARM_ERR; 3914 3915typedef union { 3916 struct { 3917#ifdef __BIG_ENDIAN_BITFIELD 3918 uint8_t Rctl; /* R_CTL field */ 3919 uint8_t Type; /* TYPE field */ 3920 uint8_t Dfctl; /* DF_CTL field */ 3921 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 3922#else /* __LITTLE_ENDIAN_BITFIELD */ 3923 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 3924 uint8_t Dfctl; /* DF_CTL field */ 3925 uint8_t Type; /* TYPE field */ 3926 uint8_t Rctl; /* R_CTL field */ 3927#endif 3928 3929#define BC 0x02 /* Broadcast Received - Fctl */ 3930#define SI 0x04 /* Sequence Initiative */ 3931#define LA 0x08 /* Ignore Link Attention state */ 3932#define LS 0x80 /* Last Sequence */ 3933 } hcsw; 3934 uint32_t reserved; 3935} WORD5; 3936 3937/* IOCB Command template for a generic response */ 3938typedef struct { 3939 uint32_t reserved[4]; 3940 PARM_ERR perr; 3941} GENERIC_RSP; 3942 3943/* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */ 3944typedef struct { 3945 struct ulp_bde xrsqbde[2]; 3946 uint32_t xrsqRo; /* Starting Relative Offset */ 3947 WORD5 w5; /* Header control/status word */ 3948} XR_SEQ_FIELDS; 3949 3950/* IOCB Command template for ELS_REQUEST */ 3951typedef struct { 3952 struct ulp_bde elsReq; 3953 struct ulp_bde elsRsp; 3954 3955#ifdef __BIG_ENDIAN_BITFIELD 3956 uint32_t word4Rsvd:7; 3957 uint32_t fl:1; 3958 uint32_t myID:24; 3959 uint32_t word5Rsvd:8; 3960 uint32_t remoteID:24; 3961#else /* __LITTLE_ENDIAN_BITFIELD */ 3962 uint32_t myID:24; 3963 uint32_t fl:1; 3964 uint32_t word4Rsvd:7; 3965 uint32_t remoteID:24; 3966 uint32_t word5Rsvd:8; 3967#endif 3968} ELS_REQUEST; 3969 3970/* IOCB Command template for RCV_ELS_REQ */ 3971typedef struct { 3972 struct ulp_bde elsReq[2]; 3973 uint32_t parmRo; 3974 3975#ifdef __BIG_ENDIAN_BITFIELD 3976 uint32_t word5Rsvd:8; 3977 uint32_t remoteID:24; 3978#else /* __LITTLE_ENDIAN_BITFIELD */ 3979 uint32_t remoteID:24; 3980 uint32_t word5Rsvd:8; 3981#endif 3982} RCV_ELS_REQ; 3983 3984/* IOCB Command template for ABORT / CLOSE_XRI */ 3985typedef struct { 3986 uint32_t rsvd[3]; 3987 uint32_t abortType; 3988#define ABORT_TYPE_ABTX 0x00000000 3989#define ABORT_TYPE_ABTS 0x00000001 3990 uint32_t parm; 3991#ifdef __BIG_ENDIAN_BITFIELD 3992 uint16_t abortContextTag; /* ulpContext from command to abort/close */ 3993 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 3994#else /* __LITTLE_ENDIAN_BITFIELD */ 3995 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 3996 uint16_t abortContextTag; /* ulpContext from command to abort/close */ 3997#endif 3998} AC_XRI; 3999 4000/* IOCB Command template for ABORT_MXRI64 */ 4001typedef struct { 4002 uint32_t rsvd[3]; 4003 uint32_t abortType; 4004 uint32_t parm; 4005 uint32_t iotag32; 4006} A_MXRI64; 4007 4008/* IOCB Command template for GET_RPI */ 4009typedef struct { 4010 uint32_t rsvd[4]; 4011 uint32_t parmRo; 4012#ifdef __BIG_ENDIAN_BITFIELD 4013 uint32_t word5Rsvd:8; 4014 uint32_t remoteID:24; 4015#else /* __LITTLE_ENDIAN_BITFIELD */ 4016 uint32_t remoteID:24; 4017 uint32_t word5Rsvd:8; 4018#endif 4019} GET_RPI; 4020 4021/* IOCB Command template for all FCP Initiator commands */ 4022typedef struct { 4023 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */ 4024 struct ulp_bde fcpi_rsp; /* Rcv buffer */ 4025 uint32_t fcpi_parm; 4026 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 4027} FCPI_FIELDS; 4028 4029/* IOCB Command template for all FCP Target commands */ 4030typedef struct { 4031 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */ 4032 uint32_t fcpt_Offset; 4033 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 4034} FCPT_FIELDS; 4035 4036/* SLI-2 IOCB structure definitions */ 4037 4038/* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */ 4039typedef struct { 4040 ULP_BDL bdl; 4041 uint32_t xrsqRo; /* Starting Relative Offset */ 4042 WORD5 w5; /* Header control/status word */ 4043} XMT_SEQ_FIELDS64; 4044 4045/* This word is remote ports D_ID for XMIT_ELS_RSP64 */ 4046#define xmit_els_remoteID xrsqRo 4047 4048/* IOCB Command template for 64 bit RCV_SEQUENCE64 */ 4049typedef struct { 4050 struct ulp_bde64 rcvBde; 4051 uint32_t rsvd1; 4052 uint32_t xrsqRo; /* Starting Relative Offset */ 4053 WORD5 w5; /* Header control/status word */ 4054} RCV_SEQ_FIELDS64; 4055 4056/* IOCB Command template for ELS_REQUEST64 */ 4057typedef struct { 4058 ULP_BDL bdl; 4059#ifdef __BIG_ENDIAN_BITFIELD 4060 uint32_t word4Rsvd:7; 4061 uint32_t fl:1; 4062 uint32_t myID:24; 4063 uint32_t word5Rsvd:8; 4064 uint32_t remoteID:24; 4065#else /* __LITTLE_ENDIAN_BITFIELD */ 4066 uint32_t myID:24; 4067 uint32_t fl:1; 4068 uint32_t word4Rsvd:7; 4069 uint32_t remoteID:24; 4070 uint32_t word5Rsvd:8; 4071#endif 4072} ELS_REQUEST64; 4073 4074/* IOCB Command template for GEN_REQUEST64 */ 4075typedef struct { 4076 ULP_BDL bdl; 4077 uint32_t xrsqRo; /* Starting Relative Offset */ 4078 WORD5 w5; /* Header control/status word */ 4079} GEN_REQUEST64; 4080 4081/* IOCB Command template for RCV_ELS_REQ64 */ 4082typedef struct { 4083 struct ulp_bde64 elsReq; 4084 uint32_t rcvd1; 4085 uint32_t parmRo; 4086 4087#ifdef __BIG_ENDIAN_BITFIELD 4088 uint32_t word5Rsvd:8; 4089 uint32_t remoteID:24; 4090#else /* __LITTLE_ENDIAN_BITFIELD */ 4091 uint32_t remoteID:24; 4092 uint32_t word5Rsvd:8; 4093#endif 4094} RCV_ELS_REQ64; 4095 4096/* IOCB Command template for RCV_SEQ64 */ 4097struct rcv_seq64 { 4098 struct ulp_bde64 elsReq; 4099 uint32_t hbq_1; 4100 uint32_t parmRo; 4101#ifdef __BIG_ENDIAN_BITFIELD 4102 uint32_t rctl:8; 4103 uint32_t type:8; 4104 uint32_t dfctl:8; 4105 uint32_t ls:1; 4106 uint32_t fs:1; 4107 uint32_t rsvd2:3; 4108 uint32_t si:1; 4109 uint32_t bc:1; 4110 uint32_t rsvd3:1; 4111#else /* __LITTLE_ENDIAN_BITFIELD */ 4112 uint32_t rsvd3:1; 4113 uint32_t bc:1; 4114 uint32_t si:1; 4115 uint32_t rsvd2:3; 4116 uint32_t fs:1; 4117 uint32_t ls:1; 4118 uint32_t dfctl:8; 4119 uint32_t type:8; 4120 uint32_t rctl:8; 4121#endif 4122}; 4123 4124/* IOCB Command template for all 64 bit FCP Initiator commands */ 4125typedef struct { 4126 ULP_BDL bdl; 4127 uint32_t fcpi_parm; 4128 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 4129} FCPI_FIELDS64; 4130 4131/* IOCB Command template for all 64 bit FCP Target commands */ 4132typedef struct { 4133 ULP_BDL bdl; 4134 uint32_t fcpt_Offset; 4135 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 4136} FCPT_FIELDS64; 4137 4138/* IOCB Command template for Async Status iocb commands */ 4139typedef struct { 4140 uint32_t rsvd[4]; 4141 uint32_t param; 4142#ifdef __BIG_ENDIAN_BITFIELD 4143 uint16_t evt_code; /* High order bits word 5 */ 4144 uint16_t sub_ctxt_tag; /* Low order bits word 5 */ 4145#else /* __LITTLE_ENDIAN_BITFIELD */ 4146 uint16_t sub_ctxt_tag; /* High order bits word 5 */ 4147 uint16_t evt_code; /* Low order bits word 5 */ 4148#endif 4149} ASYNCSTAT_FIELDS; 4150#define ASYNC_TEMP_WARN 0x100 4151#define ASYNC_TEMP_SAFE 0x101 4152#define ASYNC_STATUS_CN 0x102 4153 4154/* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7) 4155 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */ 4156 4157struct rcv_sli3 { 4158#ifdef __BIG_ENDIAN_BITFIELD 4159 uint16_t ox_id; 4160 uint16_t seq_cnt; 4161 4162 uint16_t vpi; 4163 uint16_t word9Rsvd; 4164#else /* __LITTLE_ENDIAN */ 4165 uint16_t seq_cnt; 4166 uint16_t ox_id; 4167 4168 uint16_t word9Rsvd; 4169 uint16_t vpi; 4170#endif 4171 uint32_t word10Rsvd; 4172 uint32_t acc_len; /* accumulated length */ 4173 struct ulp_bde64 bde2; 4174}; 4175 4176/* Structure used for a single HBQ entry */ 4177struct lpfc_hbq_entry { 4178 struct ulp_bde64 bde; 4179 uint32_t buffer_tag; 4180}; 4181 4182/* IOCB Command template for QUE_XRI64_CX (0xB3) command */ 4183typedef struct { 4184 struct lpfc_hbq_entry buff; 4185 uint32_t rsvd; 4186 uint32_t rsvd1; 4187} QUE_XRI64_CX_FIELDS; 4188 4189struct que_xri64cx_ext_fields { 4190 uint32_t iotag64_low; 4191 uint32_t iotag64_high; 4192 uint32_t ebde_count; 4193 uint32_t rsvd; 4194 struct lpfc_hbq_entry buff[5]; 4195}; 4196 4197struct sli3_bg_fields { 4198 uint32_t filler[6]; /* word 8-13 in IOCB */ 4199 uint32_t bghm; /* word 14 - BlockGuard High Water Mark */ 4200/* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */ 4201#define BGS_BIDIR_BG_PROF_MASK 0xff000000 4202#define BGS_BIDIR_BG_PROF_SHIFT 24 4203#define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000 4204#define BGS_BIDIR_ERR_COND_SHIFT 16 4205#define BGS_BG_PROFILE_MASK 0x0000ff00 4206#define BGS_BG_PROFILE_SHIFT 8 4207#define BGS_INVALID_PROF_MASK 0x00000020 4208#define BGS_INVALID_PROF_SHIFT 5 4209#define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010 4210#define BGS_UNINIT_DIF_BLOCK_SHIFT 4 4211#define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008 4212#define BGS_HI_WATER_MARK_PRESENT_SHIFT 3 4213#define BGS_REFTAG_ERR_MASK 0x00000004 4214#define BGS_REFTAG_ERR_SHIFT 2 4215#define BGS_APPTAG_ERR_MASK 0x00000002 4216#define BGS_APPTAG_ERR_SHIFT 1 4217#define BGS_GUARD_ERR_MASK 0x00000001 4218#define BGS_GUARD_ERR_SHIFT 0 4219 uint32_t bgstat; /* word 15 - BlockGuard Status */ 4220}; 4221 4222static inline uint32_t 4223lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat) 4224{ 4225 return (bgstat & BGS_BIDIR_BG_PROF_MASK) >> 4226 BGS_BIDIR_BG_PROF_SHIFT; 4227} 4228 4229static inline uint32_t 4230lpfc_bgs_get_bidir_err_cond(uint32_t bgstat) 4231{ 4232 return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >> 4233 BGS_BIDIR_ERR_COND_SHIFT; 4234} 4235 4236static inline uint32_t 4237lpfc_bgs_get_bg_prof(uint32_t bgstat) 4238{ 4239 return (bgstat & BGS_BG_PROFILE_MASK) >> 4240 BGS_BG_PROFILE_SHIFT; 4241} 4242 4243static inline uint32_t 4244lpfc_bgs_get_invalid_prof(uint32_t bgstat) 4245{ 4246 return (bgstat & BGS_INVALID_PROF_MASK) >> 4247 BGS_INVALID_PROF_SHIFT; 4248} 4249 4250static inline uint32_t 4251lpfc_bgs_get_uninit_dif_block(uint32_t bgstat) 4252{ 4253 return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >> 4254 BGS_UNINIT_DIF_BLOCK_SHIFT; 4255} 4256 4257static inline uint32_t 4258lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat) 4259{ 4260 return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >> 4261 BGS_HI_WATER_MARK_PRESENT_SHIFT; 4262} 4263 4264static inline uint32_t 4265lpfc_bgs_get_reftag_err(uint32_t bgstat) 4266{ 4267 return (bgstat & BGS_REFTAG_ERR_MASK) >> 4268 BGS_REFTAG_ERR_SHIFT; 4269} 4270 4271static inline uint32_t 4272lpfc_bgs_get_apptag_err(uint32_t bgstat) 4273{ 4274 return (bgstat & BGS_APPTAG_ERR_MASK) >> 4275 BGS_APPTAG_ERR_SHIFT; 4276} 4277 4278static inline uint32_t 4279lpfc_bgs_get_guard_err(uint32_t bgstat) 4280{ 4281 return (bgstat & BGS_GUARD_ERR_MASK) >> 4282 BGS_GUARD_ERR_SHIFT; 4283} 4284 4285#define LPFC_EXT_DATA_BDE_COUNT 3 4286struct fcp_irw_ext { 4287 uint32_t io_tag64_low; 4288 uint32_t io_tag64_high; 4289#ifdef __BIG_ENDIAN_BITFIELD 4290 uint8_t reserved1; 4291 uint8_t reserved2; 4292 uint8_t reserved3; 4293 uint8_t ebde_count; 4294#else /* __LITTLE_ENDIAN */ 4295 uint8_t ebde_count; 4296 uint8_t reserved3; 4297 uint8_t reserved2; 4298 uint8_t reserved1; 4299#endif 4300 uint32_t reserved4; 4301 struct ulp_bde64 rbde; /* response bde */ 4302 struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */ 4303 uint8_t icd[32]; /* immediate command data (32 bytes) */ 4304}; 4305 4306typedef struct _IOCB { /* IOCB structure */ 4307 union { 4308 GENERIC_RSP grsp; /* Generic response */ 4309 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */ 4310 struct ulp_bde cont[3]; /* up to 3 continuation bdes */ 4311 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */ 4312 AC_XRI acxri; /* ABORT / CLOSE_XRI template */ 4313 A_MXRI64 amxri; /* abort multiple xri command overlay */ 4314 GET_RPI getrpi; /* GET_RPI template */ 4315 FCPI_FIELDS fcpi; /* FCP Initiator template */ 4316 FCPT_FIELDS fcpt; /* FCP target template */ 4317 4318 /* SLI-2 structures */ 4319 4320 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation 4321 * bde_64s */ 4322 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */ 4323 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */ 4324 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */ 4325 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */ 4326 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */ 4327 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */ 4328 ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */ 4329 QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */ 4330 struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */ 4331 struct sli4_bls_rsp bls_rsp; /* UNSOL ABTS BLS_RSP params */ 4332 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */ 4333 } un; 4334 union { 4335 struct { 4336#ifdef __BIG_ENDIAN_BITFIELD 4337 uint16_t ulpContext; /* High order bits word 6 */ 4338 uint16_t ulpIoTag; /* Low order bits word 6 */ 4339#else /* __LITTLE_ENDIAN_BITFIELD */ 4340 uint16_t ulpIoTag; /* Low order bits word 6 */ 4341 uint16_t ulpContext; /* High order bits word 6 */ 4342#endif 4343 } t1; 4344 struct { 4345#ifdef __BIG_ENDIAN_BITFIELD 4346 uint16_t ulpContext; /* High order bits word 6 */ 4347 uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 4348 uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 4349#else /* __LITTLE_ENDIAN_BITFIELD */ 4350 uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 4351 uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 4352 uint16_t ulpContext; /* High order bits word 6 */ 4353#endif 4354 } t2; 4355 } un1; 4356#define ulpContext un1.t1.ulpContext 4357#define ulpIoTag un1.t1.ulpIoTag 4358#define ulpIoTag0 un1.t2.ulpIoTag0 4359 4360#ifdef __BIG_ENDIAN_BITFIELD 4361 uint32_t ulpTimeout:8; 4362 uint32_t ulpXS:1; 4363 uint32_t ulpFCP2Rcvy:1; 4364 uint32_t ulpPU:2; 4365 uint32_t ulpIr:1; 4366 uint32_t ulpClass:3; 4367 uint32_t ulpCommand:8; 4368 uint32_t ulpStatus:4; 4369 uint32_t ulpBdeCount:2; 4370 uint32_t ulpLe:1; 4371 uint32_t ulpOwner:1; /* Low order bit word 7 */ 4372#else /* __LITTLE_ENDIAN_BITFIELD */ 4373 uint32_t ulpOwner:1; /* Low order bit word 7 */ 4374 uint32_t ulpLe:1; 4375 uint32_t ulpBdeCount:2; 4376 uint32_t ulpStatus:4; 4377 uint32_t ulpCommand:8; 4378 uint32_t ulpClass:3; 4379 uint32_t ulpIr:1; 4380 uint32_t ulpPU:2; 4381 uint32_t ulpFCP2Rcvy:1; 4382 uint32_t ulpXS:1; 4383 uint32_t ulpTimeout:8; 4384#endif 4385 4386 union { 4387 struct rcv_sli3 rcvsli3; /* words 8 - 15 */ 4388 4389 /* words 8-31 used for que_xri_cx iocb */ 4390 struct que_xri64cx_ext_fields que_xri64cx_ext_words; 4391 struct fcp_irw_ext fcp_ext; 4392 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */ 4393 4394 /* words 8-15 for BlockGuard */ 4395 struct sli3_bg_fields sli3_bg; 4396 } unsli3; 4397 4398#define ulpCt_h ulpXS 4399#define ulpCt_l ulpFCP2Rcvy 4400 4401#define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */ 4402#define IOCB_IP 2 /* IOCB is used for IP ELS cmds */ 4403#define PARM_UNUSED 0 /* PU field (Word 4) not used */ 4404#define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */ 4405#define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */ 4406#define PARM_NPIV_DID 3 4407#define CLASS1 0 /* Class 1 */ 4408#define CLASS2 1 /* Class 2 */ 4409#define CLASS3 2 /* Class 3 */ 4410#define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */ 4411 4412#define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */ 4413#define IOSTAT_FCP_RSP_ERROR 0x1 4414#define IOSTAT_REMOTE_STOP 0x2 4415#define IOSTAT_LOCAL_REJECT 0x3 4416#define IOSTAT_NPORT_RJT 0x4 4417#define IOSTAT_FABRIC_RJT 0x5 4418#define IOSTAT_NPORT_BSY 0x6 4419#define IOSTAT_FABRIC_BSY 0x7 4420#define IOSTAT_INTERMED_RSP 0x8 4421#define IOSTAT_LS_RJT 0x9 4422#define IOSTAT_BA_RJT 0xA 4423#define IOSTAT_RSVD1 0xB 4424#define IOSTAT_RSVD2 0xC 4425#define IOSTAT_RSVD3 0xD 4426#define IOSTAT_RSVD4 0xE 4427#define IOSTAT_NEED_BUFFER 0xF 4428#define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */ 4429#define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */ 4430#define IOSTAT_CNT 0x11 4431 4432} IOCB_t; 4433 4434 4435#define SLI1_SLIM_SIZE (4 * 1024) 4436 4437/* Up to 498 IOCBs will fit into 16k 4438 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384 4439 */ 4440#define SLI2_SLIM_SIZE (64 * 1024) 4441 4442/* Maximum IOCBs that will fit in SLI2 slim */ 4443#define MAX_SLI2_IOCB 498 4444#define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \ 4445 (sizeof(MAILBOX_t) + sizeof(PCB_t) + \ 4446 sizeof(uint32_t) * MAILBOX_EXT_WSIZE)) 4447 4448/* HBQ entries are 4 words each = 4k */ 4449#define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \ 4450 lpfc_sli_hbq_count()) 4451 4452struct lpfc_sli2_slim { 4453 MAILBOX_t mbx; 4454 uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE]; 4455 PCB_t pcb; 4456 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE]; 4457}; 4458 4459/* 4460 * This function checks PCI device to allow special handling for LC HBAs. 4461 * 4462 * Parameters: 4463 * device : struct pci_dev 's device field 4464 * 4465 * return 1 => TRUE 4466 * 0 => FALSE 4467 */ 4468static inline int 4469lpfc_is_LC_HBA(unsigned short device) 4470{ 4471 if ((device == PCI_DEVICE_ID_TFLY) || 4472 (device == PCI_DEVICE_ID_PFLY) || 4473 (device == PCI_DEVICE_ID_LP101) || 4474 (device == PCI_DEVICE_ID_BMID) || 4475 (device == PCI_DEVICE_ID_BSMB) || 4476 (device == PCI_DEVICE_ID_ZMID) || 4477 (device == PCI_DEVICE_ID_ZSMB) || 4478 (device == PCI_DEVICE_ID_SAT_MID) || 4479 (device == PCI_DEVICE_ID_SAT_SMB) || 4480 (device == PCI_DEVICE_ID_RFLY)) 4481 return 1; 4482 else 4483 return 0; 4484} 4485 4486#define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */
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