hisi_sas_v3_hw.c

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * Copyright (c) 2017 Hisilicon Limited.
   4 */
   5
   6#include <linux/sched/clock.h>
   7#include "hisi_sas.h"
   8#define DRV_NAME "hisi_sas_v3_hw"
   9
  10/* global registers need init */
  11#define DLVRY_QUEUE_ENABLE		0x0
  12#define IOST_BASE_ADDR_LO		0x8
  13#define IOST_BASE_ADDR_HI		0xc
  14#define ITCT_BASE_ADDR_LO		0x10
  15#define ITCT_BASE_ADDR_HI		0x14
  16#define IO_BROKEN_MSG_ADDR_LO		0x18
  17#define IO_BROKEN_MSG_ADDR_HI		0x1c
  18#define PHY_CONTEXT			0x20
  19#define PHY_STATE			0x24
  20#define PHY_PORT_NUM_MA			0x28
  21#define PHY_CONN_RATE			0x30
  22#define ITCT_CLR			0x44
  23#define ITCT_CLR_EN_OFF			16
  24#define ITCT_CLR_EN_MSK			(0x1 << ITCT_CLR_EN_OFF)
  25#define ITCT_DEV_OFF			0
  26#define ITCT_DEV_MSK			(0x7ff << ITCT_DEV_OFF)
  27#define SAS_AXI_USER3			0x50
  28#define IO_SATA_BROKEN_MSG_ADDR_LO	0x58
  29#define IO_SATA_BROKEN_MSG_ADDR_HI	0x5c
  30#define SATA_INITI_D2H_STORE_ADDR_LO	0x60
  31#define SATA_INITI_D2H_STORE_ADDR_HI	0x64
  32#define CFG_MAX_TAG			0x68
  33#define TRANS_LOCK_ICT_TIME		0X70
  34#define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL	0x84
  35#define HGC_SAS_TXFAIL_RETRY_CTRL	0x88
  36#define HGC_GET_ITV_TIME		0x90
  37#define DEVICE_MSG_WORK_MODE		0x94
  38#define OPENA_WT_CONTI_TIME		0x9c
  39#define I_T_NEXUS_LOSS_TIME		0xa0
  40#define MAX_CON_TIME_LIMIT_TIME		0xa4
  41#define BUS_INACTIVE_LIMIT_TIME		0xa8
  42#define REJECT_TO_OPEN_LIMIT_TIME	0xac
  43#define CQ_INT_CONVERGE_EN		0xb0
  44#define CFG_AGING_TIME			0xbc
  45#define HGC_DFX_CFG2			0xc0
  46#define CFG_ICT_TIMER_STEP_TRSH		0xc8
  47#define CFG_ABT_SET_QUERY_IPTT	0xd4
  48#define CFG_SET_ABORTED_IPTT_OFF	0
  49#define CFG_SET_ABORTED_IPTT_MSK	(0xfff << CFG_SET_ABORTED_IPTT_OFF)
  50#define CFG_SET_ABORTED_EN_OFF	12
  51#define CFG_ABT_SET_IPTT_DONE	0xd8
  52#define CFG_ABT_SET_IPTT_DONE_OFF	0
  53#define HGC_IOMB_PROC1_STATUS	0x104
  54#define HGC_LM_DFX_STATUS2		0x128
  55#define HGC_LM_DFX_STATUS2_IOSTLIST_OFF		0
  56#define HGC_LM_DFX_STATUS2_IOSTLIST_MSK	(0xfff << \
  57					 HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
  58#define HGC_LM_DFX_STATUS2_ITCTLIST_OFF		12
  59#define HGC_LM_DFX_STATUS2_ITCTLIST_MSK	(0x7ff << \
  60					 HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
  61#define HGC_CQE_ECC_ADDR		0x13c
  62#define HGC_CQE_ECC_1B_ADDR_OFF	0
  63#define HGC_CQE_ECC_1B_ADDR_MSK	(0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
  64#define HGC_CQE_ECC_MB_ADDR_OFF	8
  65#define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
  66#define HGC_IOST_ECC_ADDR		0x140
  67#define HGC_IOST_ECC_1B_ADDR_OFF	0
  68#define HGC_IOST_ECC_1B_ADDR_MSK	(0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
  69#define HGC_IOST_ECC_MB_ADDR_OFF	16
  70#define HGC_IOST_ECC_MB_ADDR_MSK	(0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
  71#define HGC_DQE_ECC_ADDR		0x144
  72#define HGC_DQE_ECC_1B_ADDR_OFF	0
  73#define HGC_DQE_ECC_1B_ADDR_MSK	(0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
  74#define HGC_DQE_ECC_MB_ADDR_OFF	16
  75#define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
  76#define CHNL_INT_STATUS			0x148
  77#define TAB_DFX				0x14c
  78#define HGC_ITCT_ECC_ADDR		0x150
  79#define HGC_ITCT_ECC_1B_ADDR_OFF		0
  80#define HGC_ITCT_ECC_1B_ADDR_MSK		(0x3ff << \
  81						 HGC_ITCT_ECC_1B_ADDR_OFF)
  82#define HGC_ITCT_ECC_MB_ADDR_OFF		16
  83#define HGC_ITCT_ECC_MB_ADDR_MSK		(0x3ff << \
  84						 HGC_ITCT_ECC_MB_ADDR_OFF)
  85#define HGC_AXI_FIFO_ERR_INFO  0x154
  86#define AXI_ERR_INFO_OFF               0
  87#define AXI_ERR_INFO_MSK               (0xff << AXI_ERR_INFO_OFF)
  88#define FIFO_ERR_INFO_OFF              8
  89#define FIFO_ERR_INFO_MSK              (0xff << FIFO_ERR_INFO_OFF)
  90#define TAB_RD_TYPE			0x15c
  91#define INT_COAL_EN			0x19c
  92#define OQ_INT_COAL_TIME		0x1a0
  93#define OQ_INT_COAL_CNT			0x1a4
  94#define ENT_INT_COAL_TIME		0x1a8
  95#define ENT_INT_COAL_CNT		0x1ac
  96#define OQ_INT_SRC			0x1b0
  97#define OQ_INT_SRC_MSK			0x1b4
  98#define ENT_INT_SRC1			0x1b8
  99#define ENT_INT_SRC1_D2H_FIS_CH0_OFF	0
 100#define ENT_INT_SRC1_D2H_FIS_CH0_MSK	(0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
 101#define ENT_INT_SRC1_D2H_FIS_CH1_OFF	8
 102#define ENT_INT_SRC1_D2H_FIS_CH1_MSK	(0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
 103#define ENT_INT_SRC2			0x1bc
 104#define ENT_INT_SRC3			0x1c0
 105#define ENT_INT_SRC3_WP_DEPTH_OFF		8
 106#define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF	9
 107#define ENT_INT_SRC3_RP_DEPTH_OFF		10
 108#define ENT_INT_SRC3_AXI_OFF			11
 109#define ENT_INT_SRC3_FIFO_OFF			12
 110#define ENT_INT_SRC3_LM_OFF				14
 111#define ENT_INT_SRC3_ITC_INT_OFF	15
 112#define ENT_INT_SRC3_ITC_INT_MSK	(0x1 << ENT_INT_SRC3_ITC_INT_OFF)
 113#define ENT_INT_SRC3_ABT_OFF		16
 114#define ENT_INT_SRC3_DQE_POISON_OFF	18
 115#define ENT_INT_SRC3_IOST_POISON_OFF	19
 116#define ENT_INT_SRC3_ITCT_POISON_OFF	20
 117#define ENT_INT_SRC3_ITCT_NCQ_POISON_OFF	21
 118#define ENT_INT_SRC_MSK1		0x1c4
 119#define ENT_INT_SRC_MSK2		0x1c8
 120#define ENT_INT_SRC_MSK3		0x1cc
 121#define ENT_INT_SRC_MSK3_ENT95_MSK_OFF	31
 122#define CHNL_PHYUPDOWN_INT_MSK		0x1d0
 123#define CHNL_ENT_INT_MSK			0x1d4
 124#define HGC_COM_INT_MSK				0x1d8
 125#define ENT_INT_SRC_MSK3_ENT95_MSK_MSK	(0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
 126#define SAS_ECC_INTR			0x1e8
 127#define SAS_ECC_INTR_DQE_ECC_1B_OFF		0
 128#define SAS_ECC_INTR_DQE_ECC_MB_OFF		1
 129#define SAS_ECC_INTR_IOST_ECC_1B_OFF	2
 130#define SAS_ECC_INTR_IOST_ECC_MB_OFF	3
 131#define SAS_ECC_INTR_ITCT_ECC_1B_OFF	4
 132#define SAS_ECC_INTR_ITCT_ECC_MB_OFF	5
 133#define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF	6
 134#define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF	7
 135#define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF	8
 136#define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF	9
 137#define SAS_ECC_INTR_CQE_ECC_1B_OFF		10
 138#define SAS_ECC_INTR_CQE_ECC_MB_OFF		11
 139#define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF	12
 140#define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF	13
 141#define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF	14
 142#define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF	15
 143#define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF	16
 144#define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF	17
 145#define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF	18
 146#define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF	19
 147#define SAS_ECC_INTR_OOO_RAM_ECC_1B_OFF		20
 148#define SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF		21
 149#define SAS_ECC_INTR_MSK		0x1ec
 150#define HGC_ERR_STAT_EN			0x238
 151#define CQE_SEND_CNT			0x248
 152#define DLVRY_Q_0_BASE_ADDR_LO		0x260
 153#define DLVRY_Q_0_BASE_ADDR_HI		0x264
 154#define DLVRY_Q_0_DEPTH			0x268
 155#define DLVRY_Q_0_WR_PTR		0x26c
 156#define DLVRY_Q_0_RD_PTR		0x270
 157#define HYPER_STREAM_ID_EN_CFG		0xc80
 158#define OQ0_INT_SRC_MSK			0xc90
 159#define COMPL_Q_0_BASE_ADDR_LO		0x4e0
 160#define COMPL_Q_0_BASE_ADDR_HI		0x4e4
 161#define COMPL_Q_0_DEPTH			0x4e8
 162#define COMPL_Q_0_WR_PTR		0x4ec
 163#define COMPL_Q_0_RD_PTR		0x4f0
 164#define HGC_RXM_DFX_STATUS14		0xae8
 165#define HGC_RXM_DFX_STATUS14_MEM0_OFF	0
 166#define HGC_RXM_DFX_STATUS14_MEM0_MSK	(0x1ff << \
 167					 HGC_RXM_DFX_STATUS14_MEM0_OFF)
 168#define HGC_RXM_DFX_STATUS14_MEM1_OFF	9
 169#define HGC_RXM_DFX_STATUS14_MEM1_MSK	(0x1ff << \
 170					 HGC_RXM_DFX_STATUS14_MEM1_OFF)
 171#define HGC_RXM_DFX_STATUS14_MEM2_OFF	18
 172#define HGC_RXM_DFX_STATUS14_MEM2_MSK	(0x1ff << \
 173					 HGC_RXM_DFX_STATUS14_MEM2_OFF)
 174#define HGC_RXM_DFX_STATUS15		0xaec
 175#define HGC_RXM_DFX_STATUS15_MEM3_OFF	0
 176#define HGC_RXM_DFX_STATUS15_MEM3_MSK	(0x1ff << \
 177					 HGC_RXM_DFX_STATUS15_MEM3_OFF)
 178#define AWQOS_AWCACHE_CFG	0xc84
 179#define ARQOS_ARCACHE_CFG	0xc88
 180#define HILINK_ERR_DFX		0xe04
 181#define SAS_GPIO_CFG_0		0x1000
 182#define SAS_GPIO_CFG_1		0x1004
 183#define SAS_GPIO_TX_0_1	0x1040
 184#define SAS_CFG_DRIVE_VLD	0x1070
 185
 186/* phy registers requiring init */
 187#define PORT_BASE			(0x2000)
 188#define PHY_CFG				(PORT_BASE + 0x0)
 189#define HARD_PHY_LINKRATE		(PORT_BASE + 0x4)
 190#define PHY_CFG_ENA_OFF			0
 191#define PHY_CFG_ENA_MSK			(0x1 << PHY_CFG_ENA_OFF)
 192#define PHY_CFG_DC_OPT_OFF		2
 193#define PHY_CFG_DC_OPT_MSK		(0x1 << PHY_CFG_DC_OPT_OFF)
 194#define PHY_CFG_PHY_RST_OFF		3
 195#define PHY_CFG_PHY_RST_MSK		(0x1 << PHY_CFG_PHY_RST_OFF)
 196#define PROG_PHY_LINK_RATE		(PORT_BASE + 0x8)
 197#define CFG_PROG_PHY_LINK_RATE_OFF	0
 198#define CFG_PROG_PHY_LINK_RATE_MSK	(0xff << CFG_PROG_PHY_LINK_RATE_OFF)
 199#define CFG_PROG_OOB_PHY_LINK_RATE_OFF	8
 200#define CFG_PROG_OOB_PHY_LINK_RATE_MSK	(0xf << CFG_PROG_OOB_PHY_LINK_RATE_OFF)
 201#define PHY_CTRL			(PORT_BASE + 0x14)
 202#define PHY_CTRL_RESET_OFF		0
 203#define PHY_CTRL_RESET_MSK		(0x1 << PHY_CTRL_RESET_OFF)
 204#define CMD_HDR_PIR_OFF			8
 205#define CMD_HDR_PIR_MSK			(0x1 << CMD_HDR_PIR_OFF)
 206#define SERDES_CFG			(PORT_BASE + 0x1c)
 207#define CFG_ALOS_CHK_DISABLE_OFF	9
 208#define CFG_ALOS_CHK_DISABLE_MSK	(0x1 << CFG_ALOS_CHK_DISABLE_OFF)
 209#define SAS_PHY_BIST_CTRL		(PORT_BASE + 0x2c)
 210#define CFG_BIST_MODE_SEL_OFF		0
 211#define CFG_BIST_MODE_SEL_MSK		(0xf << CFG_BIST_MODE_SEL_OFF)
 212#define CFG_LOOP_TEST_MODE_OFF		14
 213#define CFG_LOOP_TEST_MODE_MSK		(0x3 << CFG_LOOP_TEST_MODE_OFF)
 214#define CFG_RX_BIST_EN_OFF		16
 215#define CFG_RX_BIST_EN_MSK		(0x1 << CFG_RX_BIST_EN_OFF)
 216#define CFG_TX_BIST_EN_OFF		17
 217#define CFG_TX_BIST_EN_MSK		(0x1 << CFG_TX_BIST_EN_OFF)
 218#define CFG_BIST_TEST_OFF		18
 219#define CFG_BIST_TEST_MSK		(0x1 << CFG_BIST_TEST_OFF)
 220#define SAS_PHY_BIST_CODE		(PORT_BASE + 0x30)
 221#define SAS_PHY_BIST_CODE1		(PORT_BASE + 0x34)
 222#define SAS_BIST_ERR_CNT		(PORT_BASE + 0x38)
 223#define SL_CFG				(PORT_BASE + 0x84)
 224#define AIP_LIMIT			(PORT_BASE + 0x90)
 225#define SL_CONTROL			(PORT_BASE + 0x94)
 226#define SL_CONTROL_NOTIFY_EN_OFF	0
 227#define SL_CONTROL_NOTIFY_EN_MSK	(0x1 << SL_CONTROL_NOTIFY_EN_OFF)
 228#define SL_CTA_OFF		17
 229#define SL_CTA_MSK		(0x1 << SL_CTA_OFF)
 230#define RX_PRIMS_STATUS			(PORT_BASE + 0x98)
 231#define RX_BCAST_CHG_OFF		1
 232#define RX_BCAST_CHG_MSK		(0x1 << RX_BCAST_CHG_OFF)
 233#define TX_ID_DWORD0			(PORT_BASE + 0x9c)
 234#define TX_ID_DWORD1			(PORT_BASE + 0xa0)
 235#define TX_ID_DWORD2			(PORT_BASE + 0xa4)
 236#define TX_ID_DWORD3			(PORT_BASE + 0xa8)
 237#define TX_ID_DWORD4			(PORT_BASE + 0xaC)
 238#define TX_ID_DWORD5			(PORT_BASE + 0xb0)
 239#define TX_ID_DWORD6			(PORT_BASE + 0xb4)
 240#define TXID_AUTO				(PORT_BASE + 0xb8)
 241#define CT3_OFF		1
 242#define CT3_MSK		(0x1 << CT3_OFF)
 243#define TX_HARDRST_OFF          2
 244#define TX_HARDRST_MSK          (0x1 << TX_HARDRST_OFF)
 245#define RX_IDAF_DWORD0			(PORT_BASE + 0xc4)
 246#define RXOP_CHECK_CFG_H		(PORT_BASE + 0xfc)
 247#define STP_LINK_TIMER			(PORT_BASE + 0x120)
 248#define STP_LINK_TIMEOUT_STATE		(PORT_BASE + 0x124)
 249#define CON_CFG_DRIVER			(PORT_BASE + 0x130)
 250#define SAS_SSP_CON_TIMER_CFG		(PORT_BASE + 0x134)
 251#define SAS_SMP_CON_TIMER_CFG		(PORT_BASE + 0x138)
 252#define SAS_STP_CON_TIMER_CFG		(PORT_BASE + 0x13c)
 253#define CHL_INT0			(PORT_BASE + 0x1b4)
 254#define CHL_INT0_HOTPLUG_TOUT_OFF	0
 255#define CHL_INT0_HOTPLUG_TOUT_MSK	(0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
 256#define CHL_INT0_SL_RX_BCST_ACK_OFF	1
 257#define CHL_INT0_SL_RX_BCST_ACK_MSK	(0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
 258#define CHL_INT0_SL_PHY_ENABLE_OFF	2
 259#define CHL_INT0_SL_PHY_ENABLE_MSK	(0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
 260#define CHL_INT0_NOT_RDY_OFF		4
 261#define CHL_INT0_NOT_RDY_MSK		(0x1 << CHL_INT0_NOT_RDY_OFF)
 262#define CHL_INT0_PHY_RDY_OFF		5
 263#define CHL_INT0_PHY_RDY_MSK		(0x1 << CHL_INT0_PHY_RDY_OFF)
 264#define CHL_INT1			(PORT_BASE + 0x1b8)
 265#define CHL_INT1_DMAC_TX_ECC_MB_ERR_OFF	15
 266#define CHL_INT1_DMAC_TX_ECC_1B_ERR_OFF	16
 267#define CHL_INT1_DMAC_RX_ECC_MB_ERR_OFF	17
 268#define CHL_INT1_DMAC_RX_ECC_1B_ERR_OFF	18
 269#define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF	19
 270#define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF	20
 271#define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF	21
 272#define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF	22
 273#define CHL_INT1_DMAC_TX_FIFO_ERR_OFF	23
 274#define CHL_INT1_DMAC_RX_FIFO_ERR_OFF	24
 275#define CHL_INT1_DMAC_TX_AXI_RUSER_ERR_OFF	26
 276#define CHL_INT1_DMAC_RX_AXI_RUSER_ERR_OFF	27
 277#define CHL_INT2			(PORT_BASE + 0x1bc)
 278#define CHL_INT2_SL_IDAF_TOUT_CONF_OFF	0
 279#define CHL_INT2_RX_DISP_ERR_OFF	28
 280#define CHL_INT2_RX_CODE_ERR_OFF	29
 281#define CHL_INT2_RX_INVLD_DW_OFF	30
 282#define CHL_INT2_STP_LINK_TIMEOUT_OFF	31
 283#define CHL_INT0_MSK			(PORT_BASE + 0x1c0)
 284#define CHL_INT1_MSK			(PORT_BASE + 0x1c4)
 285#define CHL_INT2_MSK			(PORT_BASE + 0x1c8)
 286#define SAS_EC_INT_COAL_TIME		(PORT_BASE + 0x1cc)
 287#define CHL_INT_COAL_EN			(PORT_BASE + 0x1d0)
 288#define SAS_RX_TRAIN_TIMER		(PORT_BASE + 0x2a4)
 289#define PHY_CTRL_RDY_MSK		(PORT_BASE + 0x2b0)
 290#define PHYCTRL_NOT_RDY_MSK		(PORT_BASE + 0x2b4)
 291#define PHYCTRL_DWS_RESET_MSK		(PORT_BASE + 0x2b8)
 292#define PHYCTRL_PHY_ENA_MSK		(PORT_BASE + 0x2bc)
 293#define SL_RX_BCAST_CHK_MSK		(PORT_BASE + 0x2c0)
 294#define PHYCTRL_OOB_RESTART_MSK		(PORT_BASE + 0x2c4)
 295#define DMA_TX_STATUS			(PORT_BASE + 0x2d0)
 296#define DMA_TX_STATUS_BUSY_OFF		0
 297#define DMA_TX_STATUS_BUSY_MSK		(0x1 << DMA_TX_STATUS_BUSY_OFF)
 298#define DMA_RX_STATUS			(PORT_BASE + 0x2e8)
 299#define DMA_RX_STATUS_BUSY_OFF		0
 300#define DMA_RX_STATUS_BUSY_MSK		(0x1 << DMA_RX_STATUS_BUSY_OFF)
 301
 302#define COARSETUNE_TIME			(PORT_BASE + 0x304)
 303#define TXDEEMPH_G1			(PORT_BASE + 0x350)
 304#define ERR_CNT_DWS_LOST		(PORT_BASE + 0x380)
 305#define ERR_CNT_RESET_PROB		(PORT_BASE + 0x384)
 306#define ERR_CNT_INVLD_DW		(PORT_BASE + 0x390)
 307#define ERR_CNT_CODE_ERR		(PORT_BASE + 0x394)
 308#define ERR_CNT_DISP_ERR		(PORT_BASE + 0x398)
 309#define DFX_FIFO_CTRL			(PORT_BASE + 0x3a0)
 310#define DFX_FIFO_CTRL_TRIGGER_MODE_OFF	0
 311#define DFX_FIFO_CTRL_TRIGGER_MODE_MSK	(0x7 << DFX_FIFO_CTRL_TRIGGER_MODE_OFF)
 312#define DFX_FIFO_CTRL_DUMP_MODE_OFF	3
 313#define DFX_FIFO_CTRL_DUMP_MODE_MSK	(0x7 << DFX_FIFO_CTRL_DUMP_MODE_OFF)
 314#define DFX_FIFO_CTRL_SIGNAL_SEL_OFF	6
 315#define DFX_FIFO_CTRL_SIGNAL_SEL_MSK	(0xF << DFX_FIFO_CTRL_SIGNAL_SEL_OFF)
 316#define DFX_FIFO_CTRL_DUMP_DISABLE_OFF	10
 317#define DFX_FIFO_CTRL_DUMP_DISABLE_MSK	(0x1 << DFX_FIFO_CTRL_DUMP_DISABLE_OFF)
 318#define DFX_FIFO_TRIGGER		(PORT_BASE + 0x3a4)
 319#define DFX_FIFO_TRIGGER_MSK		(PORT_BASE + 0x3a8)
 320#define DFX_FIFO_DUMP_MSK		(PORT_BASE + 0x3aC)
 321#define DFX_FIFO_RD_DATA		(PORT_BASE + 0x3b0)
 322
 323#define DEFAULT_ITCT_HW		2048 /* reset value, not reprogrammed */
 324#if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW)
 325#error Max ITCT exceeded
 326#endif
 327
 328#define AXI_MASTER_CFG_BASE		(0x5000)
 329#define AM_CTRL_GLOBAL			(0x0)
 330#define AM_CTRL_SHUTDOWN_REQ_OFF	0
 331#define AM_CTRL_SHUTDOWN_REQ_MSK	(0x1 << AM_CTRL_SHUTDOWN_REQ_OFF)
 332#define AM_CURR_TRANS_RETURN	(0x150)
 333
 334#define AM_CFG_MAX_TRANS		(0x5010)
 335#define AM_CFG_SINGLE_PORT_MAX_TRANS	(0x5014)
 336#define AXI_CFG					(0x5100)
 337#define AM_ROB_ECC_ERR_ADDR		(0x510c)
 338#define AM_ROB_ECC_ERR_ADDR_OFF	0
 339#define AM_ROB_ECC_ERR_ADDR_MSK	0xffffffff
 340
 341/* RAS registers need init */
 342#define RAS_BASE		(0x6000)
 343#define SAS_RAS_INTR0			(RAS_BASE)
 344#define SAS_RAS_INTR1			(RAS_BASE + 0x04)
 345#define SAS_RAS_INTR0_MASK		(RAS_BASE + 0x08)
 346#define SAS_RAS_INTR1_MASK		(RAS_BASE + 0x0c)
 347#define CFG_SAS_RAS_INTR_MASK		(RAS_BASE + 0x1c)
 348#define SAS_RAS_INTR2			(RAS_BASE + 0x20)
 349#define SAS_RAS_INTR2_MASK		(RAS_BASE + 0x24)
 350
 351/* HW dma structures */
 352/* Delivery queue header */
 353/* dw0 */
 354#define CMD_HDR_ABORT_FLAG_OFF		0
 355#define CMD_HDR_ABORT_FLAG_MSK		(0x3 << CMD_HDR_ABORT_FLAG_OFF)
 356#define CMD_HDR_ABORT_DEVICE_TYPE_OFF	2
 357#define CMD_HDR_ABORT_DEVICE_TYPE_MSK	(0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
 358#define CMD_HDR_RESP_REPORT_OFF		5
 359#define CMD_HDR_RESP_REPORT_MSK		(0x1 << CMD_HDR_RESP_REPORT_OFF)
 360#define CMD_HDR_TLR_CTRL_OFF		6
 361#define CMD_HDR_TLR_CTRL_MSK		(0x3 << CMD_HDR_TLR_CTRL_OFF)
 362#define CMD_HDR_PHY_ID_OFF		8
 363#define CMD_HDR_PHY_ID_MSK		(0x1ff << CMD_HDR_PHY_ID_OFF)
 364#define CMD_HDR_FORCE_PHY_OFF		17
 365#define CMD_HDR_FORCE_PHY_MSK		(0x1U << CMD_HDR_FORCE_PHY_OFF)
 366#define CMD_HDR_PORT_OFF		18
 367#define CMD_HDR_PORT_MSK		(0xf << CMD_HDR_PORT_OFF)
 368#define CMD_HDR_PRIORITY_OFF		27
 369#define CMD_HDR_PRIORITY_MSK		(0x1 << CMD_HDR_PRIORITY_OFF)
 370#define CMD_HDR_CMD_OFF			29
 371#define CMD_HDR_CMD_MSK			(0x7 << CMD_HDR_CMD_OFF)
 372/* dw1 */
 373#define CMD_HDR_UNCON_CMD_OFF	3
 374#define CMD_HDR_DIR_OFF			5
 375#define CMD_HDR_DIR_MSK			(0x3 << CMD_HDR_DIR_OFF)
 376#define CMD_HDR_RESET_OFF		7
 377#define CMD_HDR_RESET_MSK		(0x1 << CMD_HDR_RESET_OFF)
 378#define CMD_HDR_VDTL_OFF		10
 379#define CMD_HDR_VDTL_MSK		(0x1 << CMD_HDR_VDTL_OFF)
 380#define CMD_HDR_FRAME_TYPE_OFF		11
 381#define CMD_HDR_FRAME_TYPE_MSK		(0x1f << CMD_HDR_FRAME_TYPE_OFF)
 382#define CMD_HDR_DEV_ID_OFF		16
 383#define CMD_HDR_DEV_ID_MSK		(0xffff << CMD_HDR_DEV_ID_OFF)
 384/* dw2 */
 385#define CMD_HDR_CFL_OFF			0
 386#define CMD_HDR_CFL_MSK			(0x1ff << CMD_HDR_CFL_OFF)
 387#define CMD_HDR_NCQ_TAG_OFF		10
 388#define CMD_HDR_NCQ_TAG_MSK		(0x1f << CMD_HDR_NCQ_TAG_OFF)
 389#define CMD_HDR_MRFL_OFF		15
 390#define CMD_HDR_MRFL_MSK		(0x1ff << CMD_HDR_MRFL_OFF)
 391#define CMD_HDR_SG_MOD_OFF		24
 392#define CMD_HDR_SG_MOD_MSK		(0x3 << CMD_HDR_SG_MOD_OFF)
 393/* dw3 */
 394#define CMD_HDR_IPTT_OFF		0
 395#define CMD_HDR_IPTT_MSK		(0xffff << CMD_HDR_IPTT_OFF)
 396/* dw6 */
 397#define CMD_HDR_DIF_SGL_LEN_OFF		0
 398#define CMD_HDR_DIF_SGL_LEN_MSK		(0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
 399#define CMD_HDR_DATA_SGL_LEN_OFF	16
 400#define CMD_HDR_DATA_SGL_LEN_MSK	(0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
 401/* dw7 */
 402#define CMD_HDR_ADDR_MODE_SEL_OFF		15
 403#define CMD_HDR_ADDR_MODE_SEL_MSK		(1 << CMD_HDR_ADDR_MODE_SEL_OFF)
 404#define CMD_HDR_ABORT_IPTT_OFF		16
 405#define CMD_HDR_ABORT_IPTT_MSK		(0xffff << CMD_HDR_ABORT_IPTT_OFF)
 406
 407/* Completion header */
 408/* dw0 */
 409#define CMPLT_HDR_CMPLT_OFF		0
 410#define CMPLT_HDR_CMPLT_MSK		(0x3 << CMPLT_HDR_CMPLT_OFF)
 411#define CMPLT_HDR_ERROR_PHASE_OFF   2
 412#define CMPLT_HDR_ERROR_PHASE_MSK   (0xff << CMPLT_HDR_ERROR_PHASE_OFF)
 413/* bit[9:2] Error Phase */
 414#define ERR_PHASE_RESPONSE_FRAME_REV_STAGE_OFF	\
 415					8
 416#define ERR_PHASE_RESPONSE_FRAME_REV_STAGE_MSK	\
 417	(0x1 << ERR_PHASE_RESPONSE_FRAME_REV_STAGE_OFF)
 418#define CMPLT_HDR_RSPNS_XFRD_OFF	10
 419#define CMPLT_HDR_RSPNS_XFRD_MSK	(0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
 420#define CMPLT_HDR_RSPNS_GOOD_OFF	11
 421#define CMPLT_HDR_RSPNS_GOOD_MSK	(0x1 << CMPLT_HDR_RSPNS_GOOD_OFF)
 422#define CMPLT_HDR_ERX_OFF		12
 423#define CMPLT_HDR_ERX_MSK		(0x1 << CMPLT_HDR_ERX_OFF)
 424#define CMPLT_HDR_ABORT_STAT_OFF	13
 425#define CMPLT_HDR_ABORT_STAT_MSK	(0x7 << CMPLT_HDR_ABORT_STAT_OFF)
 426/* abort_stat */
 427#define STAT_IO_NOT_VALID		0x1
 428#define STAT_IO_NO_DEVICE		0x2
 429#define STAT_IO_COMPLETE		0x3
 430#define STAT_IO_ABORTED			0x4
 431/* dw1 */
 432#define CMPLT_HDR_IPTT_OFF		0
 433#define CMPLT_HDR_IPTT_MSK		(0xffff << CMPLT_HDR_IPTT_OFF)
 434#define CMPLT_HDR_DEV_ID_OFF		16
 435#define CMPLT_HDR_DEV_ID_MSK		(0xffff << CMPLT_HDR_DEV_ID_OFF)
 436/* dw3 */
 437#define SATA_DISK_IN_ERROR_STATUS_OFF	8
 438#define SATA_DISK_IN_ERROR_STATUS_MSK	(0x1 << SATA_DISK_IN_ERROR_STATUS_OFF)
 439#define CMPLT_HDR_SATA_DISK_ERR_OFF	16
 440#define CMPLT_HDR_SATA_DISK_ERR_MSK	(0x1 << CMPLT_HDR_SATA_DISK_ERR_OFF)
 441#define CMPLT_HDR_IO_IN_TARGET_OFF	17
 442#define CMPLT_HDR_IO_IN_TARGET_MSK	(0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
 443/* bit[23:18] ERR_FIS_ATA_STATUS */
 444#define FIS_ATA_STATUS_ERR_OFF		18
 445#define FIS_ATA_STATUS_ERR_MSK		(0x1 << FIS_ATA_STATUS_ERR_OFF)
 446#define FIS_TYPE_SDB_OFF		31
 447#define FIS_TYPE_SDB_MSK		(0x1 << FIS_TYPE_SDB_OFF)
 448
 449/* ITCT header */
 450/* qw0 */
 451#define ITCT_HDR_DEV_TYPE_OFF		0
 452#define ITCT_HDR_DEV_TYPE_MSK		(0x3 << ITCT_HDR_DEV_TYPE_OFF)
 453#define ITCT_HDR_VALID_OFF		2
 454#define ITCT_HDR_VALID_MSK		(0x1 << ITCT_HDR_VALID_OFF)
 455#define ITCT_HDR_MCR_OFF		5
 456#define ITCT_HDR_MCR_MSK		(0xf << ITCT_HDR_MCR_OFF)
 457#define ITCT_HDR_VLN_OFF		9
 458#define ITCT_HDR_VLN_MSK		(0xf << ITCT_HDR_VLN_OFF)
 459#define ITCT_HDR_SMP_TIMEOUT_OFF	16
 460#define ITCT_HDR_AWT_CONTINUE_OFF	25
 461#define ITCT_HDR_PORT_ID_OFF		28
 462#define ITCT_HDR_PORT_ID_MSK		(0xf << ITCT_HDR_PORT_ID_OFF)
 463/* qw2 */
 464#define ITCT_HDR_INLT_OFF		0
 465#define ITCT_HDR_INLT_MSK		(0xffffULL << ITCT_HDR_INLT_OFF)
 466#define ITCT_HDR_RTOLT_OFF		48
 467#define ITCT_HDR_RTOLT_MSK		(0xffffULL << ITCT_HDR_RTOLT_OFF)
 468
 469/*debugfs*/
 470#define TWO_PARA_PER_LINE 2
 471#define FOUR_PARA_PER_LINE 4
 472#define	DUMP_BUF_SIZE 8
 473#define BIST_BUF_SIZE 16
 474
 475struct hisi_sas_protect_iu_v3_hw {
 476	u32 dw0;
 477	u32 lbrtcv;
 478	u32 lbrtgv;
 479	u32 dw3;
 480	u32 dw4;
 481	u32 dw5;
 482	u32 rsv;
 483};
 484
 485struct hisi_sas_complete_v3_hdr {
 486	__le32 dw0;
 487	__le32 dw1;
 488	__le32 act;
 489	__le32 dw3;
 490};
 491
 492struct hisi_sas_err_record_v3 {
 493	/* dw0 */
 494	__le32 trans_tx_fail_type;
 495
 496	/* dw1 */
 497	__le32 trans_rx_fail_type;
 498
 499	/* dw2 */
 500	__le16 dma_tx_err_type;
 501	__le16 sipc_rx_err_type;
 502
 503	/* dw3 */
 504	__le32 dma_rx_err_type;
 505};
 506
 507#define RX_DATA_LEN_UNDERFLOW_OFF	6
 508#define RX_DATA_LEN_UNDERFLOW_MSK	(1 << RX_DATA_LEN_UNDERFLOW_OFF)
 509
 510#define RX_FIS_STATUS_ERR_OFF		0
 511#define RX_FIS_STATUS_ERR_MSK		(1 << RX_FIS_STATUS_ERR_OFF)
 512
 513#define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
 514#define HISI_SAS_MSI_COUNT_V3_HW 32
 515
 516#define DIR_NO_DATA 0
 517#define DIR_TO_INI 1
 518#define DIR_TO_DEVICE 2
 519#define DIR_RESERVED 3
 520
 521#define FIS_CMD_IS_UNCONSTRAINED(fis) \
 522	((fis.command == ATA_CMD_READ_LOG_EXT) || \
 523	(fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \
 524	((fis.command == ATA_CMD_DEV_RESET) && \
 525	((fis.control & ATA_SRST) != 0)))
 526
 527#define T10_INSRT_EN_OFF    0
 528#define T10_INSRT_EN_MSK    (1 << T10_INSRT_EN_OFF)
 529#define T10_RMV_EN_OFF	    1
 530#define T10_RMV_EN_MSK	    (1 << T10_RMV_EN_OFF)
 531#define T10_RPLC_EN_OFF	    2
 532#define T10_RPLC_EN_MSK	    (1 << T10_RPLC_EN_OFF)
 533#define T10_CHK_EN_OFF	    3
 534#define T10_CHK_EN_MSK	    (1 << T10_CHK_EN_OFF)
 535#define INCR_LBRT_OFF	    5
 536#define INCR_LBRT_MSK	    (1 << INCR_LBRT_OFF)
 537#define USR_DATA_BLOCK_SZ_OFF	20
 538#define USR_DATA_BLOCK_SZ_MSK	(0x3 << USR_DATA_BLOCK_SZ_OFF)
 539#define T10_CHK_MSK_OFF	    16
 540#define T10_CHK_REF_TAG_MSK (0xf0 << T10_CHK_MSK_OFF)
 541#define T10_CHK_APP_TAG_MSK (0xc << T10_CHK_MSK_OFF)
 542
 543#define BASE_VECTORS_V3_HW  16
 544#define MIN_AFFINE_VECTORS_V3_HW  (BASE_VECTORS_V3_HW + 1)
 545#define IRQ_PHY_UP_DOWN_INDEX 1
 546#define IRQ_CHL_INDEX 2
 547#define IRQ_AXI_INDEX 11
 548
 549#define DELAY_FOR_RESET_HW 100
 550#define HDR_SG_MOD 0x2
 551#define LUN_SIZE 8
 552#define ATTR_PRIO_REGION 9
 553#define CDB_REGION 12
 554#define PRIO_OFF 3
 555#define TMF_REGION 10
 556#define TAG_MSB 12
 557#define TAG_LSB 13
 558#define SMP_FRAME_TYPE 2
 559#define SMP_CRC_SIZE 4
 560#define HDR_TAG_OFF 3
 561#define HOST_NO_OFF 6
 562#define PHY_NO_OFF 7
 563#define IDENTIFY_REG_READ 6
 564#define LINK_RESET_TIMEOUT_OFF 4
 565#define DECIMALISM_FLAG 10
 566#define WAIT_RETRY 100
 567#define WAIT_TMROUT 5000
 568
 569#define ID_DWORD0_INDEX 0
 570#define ID_DWORD1_INDEX 1
 571#define ID_DWORD2_INDEX 2
 572#define ID_DWORD3_INDEX 3
 573#define ID_DWORD4_INDEX 4
 574#define ID_DWORD5_INDEX 5
 575#define TICKS_BIT_INDEX 24
 576#define COUNT_BIT_INDEX 8
 577
 578#define PORT_REG_LENGTH	    0x100
 579#define GLOBAL_REG_LENGTH   0x800
 580#define	AXI_REG_LENGTH	    0x61
 581#define RAS_REG_LENGTH	    0x10
 582
 583#define CHNL_INT_STS_MSK	0xeeeeeeee
 584#define CHNL_INT_STS_PHY_MSK	0xe
 585#define CHNL_INT_STS_INT0_MSK BIT(1)
 586#define CHNL_INT_STS_INT1_MSK BIT(2)
 587#define CHNL_INT_STS_INT2_MSK BIT(3)
 588#define CHNL_WIDTH 4
 589
 590#define BAR_NO_V3_HW	5
 591
 592enum {
 593	DSM_FUNC_ERR_HANDLE_MSI = 0,
 594};
 595
 596static bool hisi_sas_intr_conv;
 597MODULE_PARM_DESC(intr_conv, "interrupt converge enable (0-1)");
 598
 599/* permit overriding the host protection capabilities mask (EEDP/T10 PI) */
 600static int prot_mask;
 601module_param(prot_mask, int, 0444);
 602MODULE_PARM_DESC(prot_mask, " host protection capabilities mask, def=0x0 ");
 603
 604/* the index of iopoll queues are bigger than interrupt queues' */
 605static int experimental_iopoll_q_cnt;
 606module_param(experimental_iopoll_q_cnt, int, 0444);
 607MODULE_PARM_DESC(experimental_iopoll_q_cnt, "number of queues to be used as poll mode, def=0");
 608
 609static int debugfs_snapshot_regs_v3_hw(struct hisi_hba *hisi_hba);
 610
 611static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
 612{
 613	void __iomem *regs = hisi_hba->regs + off;
 614
 615	return readl(regs);
 616}
 617
 618static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
 619{
 620	void __iomem *regs = hisi_hba->regs + off;
 621
 622	writel(val, regs);
 623}
 624
 625static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
 626				 u32 off, u32 val)
 627{
 628	void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
 629
 630	writel(val, regs);
 631}
 632
 633static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
 634				      int phy_no, u32 off)
 635{
 636	void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
 637
 638	return readl(regs);
 639}
 640
 641#define hisi_sas_read32_poll_timeout(off, val, cond, delay_us,		\
 642				     timeout_us)			\
 643({									\
 644	void __iomem *regs = hisi_hba->regs + off;			\
 645	readl_poll_timeout(regs, val, cond, delay_us, timeout_us);	\
 646})
 647
 648#define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us,	\
 649					    timeout_us)			\
 650({									\
 651	void __iomem *regs = hisi_hba->regs + off;			\
 652	readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\
 653})
 654
 655static void interrupt_enable_v3_hw(struct hisi_hba *hisi_hba)
 656{
 657	int i;
 658
 659	for (i = 0; i < hisi_hba->queue_count; i++)
 660		hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0);
 661
 662	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe);
 663	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe);
 664	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffc220ff);
 665	hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x155555);
 666
 667	for (i = 0; i < hisi_hba->n_phy; i++) {
 668		hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xf2057fff);
 669		hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe);
 670		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
 671		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
 672		hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
 673	}
 674}
 675
 676static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
 677{
 678	struct pci_dev *pdev = hisi_hba->pci_dev;
 679	int i, j;
 680
 681	/* Global registers init */
 682	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
 683			 (u32)((1ULL << hisi_hba->queue_count) - 1));
 684	hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400);
 685	/* time / CLK_AHB = 2.5s / 2ns = 0x4A817C80 */
 686	hisi_sas_write32(hisi_hba, TRANS_LOCK_ICT_TIME, 0x4A817C80);
 687	hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
 688	hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
 689	hisi_sas_write32(hisi_hba, CFG_ICT_TIMER_STEP_TRSH, 0xf4240);
 690	hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x3);
 691	/* configure the interrupt coalescing timeout period 10us */
 692	hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0xa);
 693	/* configure the count of CQ entries 10 */
 694	hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0xa);
 695	hisi_sas_write32(hisi_hba, CQ_INT_CONVERGE_EN,
 696			 hisi_sas_intr_conv);
 697	hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff);
 698	hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
 699	hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
 700	hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
 701	hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0);
 702	hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0);
 703	hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0);
 704	hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0);
 705	hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0);
 706	hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
 707
 708	if (pdev->revision < 0x30)
 709		hisi_sas_write32(hisi_hba, SAS_AXI_USER3, 0);
 710
 711	interrupt_enable_v3_hw(hisi_hba);
 712	for (i = 0; i < hisi_hba->n_phy; i++) {
 713		enum sas_linkrate max;
 714		struct hisi_sas_phy *phy = &hisi_hba->phy[i];
 715		struct asd_sas_phy *sas_phy = &phy->sas_phy;
 716		u32 prog_phy_link_rate = hisi_sas_phy_read32(hisi_hba, i,
 717							   PROG_PHY_LINK_RATE);
 718
 719		prog_phy_link_rate &= ~CFG_PROG_PHY_LINK_RATE_MSK;
 720		if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate <
 721				SAS_LINK_RATE_1_5_GBPS))
 722			max = SAS_LINK_RATE_12_0_GBPS;
 723		else
 724			max = sas_phy->phy->maximum_linkrate;
 725		prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
 726		hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE,
 727			prog_phy_link_rate);
 728		hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80);
 729		hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
 730		hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
 731		hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
 732		hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
 733		hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
 734		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
 735		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1);
 736		hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7ffffff);
 737		hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x2a0a01);
 738		hisi_sas_phy_write32(hisi_hba, i, SAS_EC_INT_COAL_TIME,
 739				     0x30f4240);
 740		hisi_sas_phy_write32(hisi_hba, i, AIP_LIMIT, 0x2ffff);
 741
 742		/* set value through firmware for 920B and later version */
 743		if (pdev->revision < 0x30) {
 744			hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG, 0x32);
 745			hisi_sas_phy_write32(hisi_hba, i, SERDES_CFG, 0xffc00);
 746			/* used for 12G negotiate */
 747			hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e);
 748		}
 749
 750		/* get default FFE configuration for BIST */
 751		for (j = 0; j < FFE_CFG_MAX; j++) {
 752			u32 val = hisi_sas_phy_read32(hisi_hba, i,
 753						      TXDEEMPH_G1 + (j * 0x4));
 754			hisi_hba->debugfs_bist_ffe[i][j] = val;
 755		}
 756	}
 757
 758	for (i = 0; i < hisi_hba->queue_count; i++) {
 759		/* Delivery queue */
 760		hisi_sas_write32(hisi_hba,
 761				 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
 762				 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
 763
 764		hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
 765				 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
 766
 767		hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
 768				 HISI_SAS_QUEUE_SLOTS);
 769
 770		/* Completion queue */
 771		hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
 772				 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
 773
 774		hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
 775				 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
 776
 777		hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
 778				 HISI_SAS_QUEUE_SLOTS);
 779	}
 780
 781	/* itct */
 782	hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
 783			 lower_32_bits(hisi_hba->itct_dma));
 784
 785	hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
 786			 upper_32_bits(hisi_hba->itct_dma));
 787
 788	/* iost */
 789	hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
 790			 lower_32_bits(hisi_hba->iost_dma));
 791
 792	hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
 793			 upper_32_bits(hisi_hba->iost_dma));
 794
 795	/* breakpoint */
 796	hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
 797			 lower_32_bits(hisi_hba->breakpoint_dma));
 798
 799	hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
 800			 upper_32_bits(hisi_hba->breakpoint_dma));
 801
 802	/* SATA broken msg */
 803	hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
 804			 lower_32_bits(hisi_hba->sata_breakpoint_dma));
 805
 806	hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
 807			 upper_32_bits(hisi_hba->sata_breakpoint_dma));
 808
 809	/* SATA initial fis */
 810	hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
 811			 lower_32_bits(hisi_hba->initial_fis_dma));
 812
 813	hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
 814			 upper_32_bits(hisi_hba->initial_fis_dma));
 815
 816	/* RAS registers init */
 817	hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0);
 818	hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0);
 819	hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0);
 820	hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0);
 821
 822	/* LED registers init */
 823	hisi_sas_write32(hisi_hba, SAS_CFG_DRIVE_VLD, 0x80000ff);
 824	hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1, 0x80808080);
 825	hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1 + 0x4, 0x80808080);
 826	/* Configure blink generator rate A to 1Hz and B to 4Hz */
 827	hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_1, 0x121700);
 828	hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_0, 0x800000);
 829}
 830
 831static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
 832{
 833	u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 834
 835	cfg &= ~PHY_CFG_DC_OPT_MSK;
 836	cfg |= 1 << PHY_CFG_DC_OPT_OFF;
 837	hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 838}
 839
 840static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
 841{
 842	struct sas_identify_frame identify_frame;
 843	u32 *identify_buffer;
 844
 845	memset(&identify_frame, 0, sizeof(identify_frame));
 846	identify_frame.dev_type = SAS_END_DEVICE;
 847	identify_frame.frame_type = 0;
 848	identify_frame._un1 = 1;
 849	identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
 850	identify_frame.target_bits = SAS_PROTOCOL_NONE;
 851	memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
 852	memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr,	SAS_ADDR_SIZE);
 853	identify_frame.phy_id = phy_no;
 854	identify_buffer = (u32 *)(&identify_frame);
 855
 856	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
 857			__swab32(identify_buffer[ID_DWORD0_INDEX]));
 858	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
 859			__swab32(identify_buffer[ID_DWORD1_INDEX]));
 860	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
 861			__swab32(identify_buffer[ID_DWORD2_INDEX]));
 862	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
 863			__swab32(identify_buffer[ID_DWORD3_INDEX]));
 864	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
 865			__swab32(identify_buffer[ID_DWORD4_INDEX]));
 866	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
 867			__swab32(identify_buffer[ID_DWORD5_INDEX]));
 868}
 869
 870static void setup_itct_v3_hw(struct hisi_hba *hisi_hba,
 871			     struct hisi_sas_device *sas_dev)
 872{
 873	struct domain_device *device = sas_dev->sas_device;
 874	struct device *dev = hisi_hba->dev;
 875	u64 qw0, device_id = sas_dev->device_id;
 876	struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
 877	struct asd_sas_port *sas_port = device->port;
 878	struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
 879	u64 sas_addr;
 880
 881	memset(itct, 0, sizeof(*itct));
 882
 883	/* qw0 */
 884	qw0 = 0;
 885	switch (sas_dev->dev_type) {
 886	case SAS_END_DEVICE:
 887	case SAS_EDGE_EXPANDER_DEVICE:
 888	case SAS_FANOUT_EXPANDER_DEVICE:
 889		qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
 890		break;
 891	case SAS_SATA_DEV:
 892	case SAS_SATA_PENDING:
 893		if (dev_parent_is_expander(device))
 894			qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
 895		else
 896			qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
 897		break;
 898	default:
 899		dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
 900			 sas_dev->dev_type);
 901	}
 902
 903	qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
 904		(device->linkrate << ITCT_HDR_MCR_OFF) |
 905		(1 << ITCT_HDR_VLN_OFF) |
 906		(0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) |
 907		(1 << ITCT_HDR_AWT_CONTINUE_OFF) |
 908		(port->id << ITCT_HDR_PORT_ID_OFF));
 909	itct->qw0 = cpu_to_le64(qw0);
 910
 911	/* qw1 */
 912	memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE);
 913	itct->sas_addr = cpu_to_le64(__swab64(sas_addr));
 914
 915	/* qw2 */
 916	if (!dev_is_sata(device))
 917		itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
 918					(0x1ULL << ITCT_HDR_RTOLT_OFF));
 919}
 920
 921static int clear_itct_v3_hw(struct hisi_hba *hisi_hba,
 922			    struct hisi_sas_device *sas_dev)
 923{
 924	DECLARE_COMPLETION_ONSTACK(completion);
 925	u64 dev_id = sas_dev->device_id;
 926	struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
 927	u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
 928	struct device *dev = hisi_hba->dev;
 929
 930	sas_dev->completion = &completion;
 931
 932	/* clear the itct interrupt state */
 933	if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
 934		hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
 935				 ENT_INT_SRC3_ITC_INT_MSK);
 936
 937	/* clear the itct table */
 938	reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
 939	hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
 940
 941	if (!wait_for_completion_timeout(sas_dev->completion,
 942					 HISI_SAS_CLEAR_ITCT_TIMEOUT)) {
 943		dev_warn(dev, "failed to clear ITCT\n");
 944		return -ETIMEDOUT;
 945	}
 946
 947	memset(itct, 0, sizeof(struct hisi_sas_itct));
 948	return 0;
 949}
 950
 951static void dereg_device_v3_hw(struct hisi_hba *hisi_hba,
 952				struct domain_device *device)
 953{
 954	struct hisi_sas_slot *slot, *slot2;
 955	struct hisi_sas_device *sas_dev = device->lldd_dev;
 956	u32 cfg_abt_set_query_iptt;
 957
 958	cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba,
 959		CFG_ABT_SET_QUERY_IPTT);
 960	spin_lock(&sas_dev->lock);
 961	list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) {
 962		cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK;
 963		cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) |
 964			(slot->idx << CFG_SET_ABORTED_IPTT_OFF);
 965		hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
 966			cfg_abt_set_query_iptt);
 967	}
 968	spin_unlock(&sas_dev->lock);
 969	cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF);
 970	hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
 971		cfg_abt_set_query_iptt);
 972	hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE,
 973					1 << CFG_ABT_SET_IPTT_DONE_OFF);
 974}
 975
 976static int reset_hw_v3_hw(struct hisi_hba *hisi_hba)
 977{
 978	struct device *dev = hisi_hba->dev;
 979	int ret;
 980	u32 val;
 981
 982	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
 983
 984	/* Disable all of the PHYs */
 985	hisi_sas_stop_phys(hisi_hba);
 986	udelay(HISI_SAS_DELAY_FOR_PHY_DISABLE);
 987
 988	/* Ensure axi bus idle */
 989	ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val,
 990					   20000, 1000000);
 991	if (ret) {
 992		dev_err(dev, "axi bus is not idle, ret = %d!\n", ret);
 993		return -EIO;
 994	}
 995
 996	if (ACPI_HANDLE(dev)) {
 997		acpi_status s;
 998
 999		s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
1000		if (ACPI_FAILURE(s)) {
1001			dev_err(dev, "Reset failed\n");
1002			return -EIO;
1003		}
1004	} else {
1005		dev_err(dev, "no reset method!\n");
1006		return -EINVAL;
1007	}
1008
1009	return 0;
1010}
1011
1012static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
1013{
1014	struct device *dev = hisi_hba->dev;
1015	struct acpi_device *acpi_dev;
1016	union acpi_object *obj;
1017	guid_t guid;
1018	int rc;
1019
1020	rc = reset_hw_v3_hw(hisi_hba);
1021	if (rc) {
1022		dev_err(dev, "hisi_sas_reset_hw failed, rc=%d\n", rc);
1023		return rc;
1024	}
1025
1026	msleep(DELAY_FOR_RESET_HW);
1027	init_reg_v3_hw(hisi_hba);
1028
1029	if (guid_parse("D5918B4B-37AE-4E10-A99F-E5E8A6EF4C1F", &guid)) {
1030		dev_err(dev, "Parse GUID failed\n");
1031		return -EINVAL;
1032	}
1033
1034	/*
1035	 * This DSM handles some hardware-related configurations:
1036	 * 1. Switch over to MSI error handling in kernel
1037	 * 2. BIOS *may* reset some register values through this method
1038	 */
1039	obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid, 0,
1040				DSM_FUNC_ERR_HANDLE_MSI, NULL);
1041	if (!obj)
1042		dev_warn(dev, "can not find DSM method, ignore\n");
1043	else
1044		ACPI_FREE(obj);
1045
1046	acpi_dev = ACPI_COMPANION(dev);
1047	if (!acpi_device_power_manageable(acpi_dev))
1048		dev_notice(dev, "neither _PS0 nor _PR0 is defined\n");
1049	return 0;
1050}
1051
1052static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1053{
1054	u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1055
1056	cfg |= PHY_CFG_ENA_MSK;
1057	cfg &= ~PHY_CFG_PHY_RST_MSK;
1058	hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1059}
1060
1061static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1062{
1063	u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1064	u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK);
1065	static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) |
1066			       BIT(CHL_INT2_RX_CODE_ERR_OFF) |
1067			       BIT(CHL_INT2_RX_INVLD_DW_OFF);
1068	u32 state;
1069
1070	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, msk | irq_msk);
1071
1072	cfg &= ~PHY_CFG_ENA_MSK;
1073	hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1074
1075	mdelay(HISI_SAS_DELAY_FOR_PHY_DISABLE);
1076
1077	state = hisi_sas_read32(hisi_hba, PHY_STATE);
1078	if (state & BIT(phy_no)) {
1079		cfg |= PHY_CFG_PHY_RST_MSK;
1080		hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1081	}
1082
1083	udelay(1);
1084
1085	hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
1086	hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
1087	hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR);
1088
1089	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, msk);
1090	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, irq_msk);
1091}
1092
1093static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1094{
1095	config_id_frame_v3_hw(hisi_hba, phy_no);
1096	config_phy_opt_mode_v3_hw(hisi_hba, phy_no);
1097	enable_phy_v3_hw(hisi_hba, phy_no);
1098}
1099
1100static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1101{
1102	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1103	u32 txid_auto;
1104
1105	hisi_sas_phy_enable(hisi_hba, phy_no, 0);
1106	if (phy->identify.device_type == SAS_END_DEVICE) {
1107		txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1108		hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1109					txid_auto | TX_HARDRST_MSK);
1110	}
1111	msleep(HISI_SAS_DELAY_FOR_PHY_DISABLE);
1112	hisi_sas_phy_enable(hisi_hba, phy_no, 1);
1113}
1114
1115static enum sas_linkrate phy_get_max_linkrate_v3_hw(void)
1116{
1117	return SAS_LINK_RATE_12_0_GBPS;
1118}
1119
1120static void phys_init_v3_hw(struct hisi_hba *hisi_hba)
1121{
1122	int i;
1123
1124	for (i = 0; i < hisi_hba->n_phy; i++) {
1125		struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1126		struct asd_sas_phy *sas_phy = &phy->sas_phy;
1127
1128		if (!sas_phy->phy->enabled)
1129			continue;
1130
1131		hisi_sas_phy_enable(hisi_hba, i, 1);
1132	}
1133}
1134
1135static void sl_notify_ssp_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1136{
1137	u32 sl_control;
1138
1139	sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1140	sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
1141	hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1142	msleep(1);
1143	sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1144	sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
1145	hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1146}
1147
1148static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id)
1149{
1150	int i, bitmap = 0;
1151	u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1152	u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1153
1154	for (i = 0; i < hisi_hba->n_phy; i++)
1155		if (phy_state & BIT(i))
1156			if (((phy_port_num_ma >> (i * HISI_SAS_REG_MEM_SIZE)) & 0xf) ==
1157			    port_id)
1158				bitmap |= BIT(i);
1159
1160	return bitmap;
1161}
1162
1163static void start_delivery_v3_hw(struct hisi_sas_dq *dq)
1164{
1165	struct hisi_hba *hisi_hba = dq->hisi_hba;
1166	struct hisi_sas_slot *s, *s1, *s2 = NULL;
1167	int dlvry_queue = dq->id;
1168	int wp;
1169
1170	list_for_each_entry_safe(s, s1, &dq->list, delivery) {
1171		if (!s->ready)
1172			break;
1173		s2 = s;
1174		list_del(&s->delivery);
1175	}
1176
1177	if (!s2)
1178		return;
1179
1180	/*
1181	 * Ensure that memories for slots built on other CPUs is observed.
1182	 */
1183	smp_rmb();
1184	wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS;
1185
1186	hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp);
1187}
1188
1189static void prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba,
1190			      struct hisi_sas_slot *slot,
1191			      struct hisi_sas_cmd_hdr *hdr,
1192			      struct scatterlist *scatter,
1193			      int n_elem)
1194{
1195	struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
1196	struct scatterlist *sg;
1197	int i;
1198
1199	for_each_sg(scatter, sg, n_elem, i) {
1200		struct hisi_sas_sge *entry = &sge_page->sge[i];
1201
1202		entry->addr = cpu_to_le64(sg_dma_address(sg));
1203		entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
1204		entry->data_len = cpu_to_le32(sg_dma_len(sg));
1205		entry->data_off = 0;
1206	}
1207
1208	hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
1209
1210	hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
1211}
1212
1213static void prep_prd_sge_dif_v3_hw(struct hisi_hba *hisi_hba,
1214				   struct hisi_sas_slot *slot,
1215				   struct hisi_sas_cmd_hdr *hdr,
1216				   struct scatterlist *scatter,
1217				   int n_elem)
1218{
1219	struct hisi_sas_sge_dif_page *sge_dif_page;
1220	struct scatterlist *sg;
1221	int i;
1222
1223	sge_dif_page = hisi_sas_sge_dif_addr_mem(slot);
1224
1225	for_each_sg(scatter, sg, n_elem, i) {
1226		struct hisi_sas_sge *entry = &sge_dif_page->sge[i];
1227
1228		entry->addr = cpu_to_le64(sg_dma_address(sg));
1229		entry->page_ctrl_0 = 0;
1230		entry->page_ctrl_1 = 0;
1231		entry->data_len = cpu_to_le32(sg_dma_len(sg));
1232		entry->data_off = 0;
1233	}
1234
1235	hdr->dif_prd_table_addr =
1236		cpu_to_le64(hisi_sas_sge_dif_addr_dma(slot));
1237
1238	hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DIF_SGL_LEN_OFF);
1239}
1240
1241static u32 get_prot_chk_msk_v3_hw(struct scsi_cmnd *scsi_cmnd)
1242{
1243	unsigned char prot_flags = scsi_cmnd->prot_flags;
1244
1245	if (prot_flags & SCSI_PROT_REF_CHECK)
1246		return T10_CHK_APP_TAG_MSK;
1247	return T10_CHK_REF_TAG_MSK | T10_CHK_APP_TAG_MSK;
1248}
1249
1250static void fill_prot_v3_hw(struct scsi_cmnd *scsi_cmnd,
1251			    struct hisi_sas_protect_iu_v3_hw *prot)
1252{
1253	unsigned char prot_op = scsi_get_prot_op(scsi_cmnd);
1254	unsigned int interval = scsi_prot_interval(scsi_cmnd);
1255	u32 lbrt_chk_val = t10_pi_ref_tag(scsi_cmd_to_rq(scsi_cmnd));
1256
1257	switch (prot_op) {
1258	case SCSI_PROT_READ_INSERT:
1259		prot->dw0 |= T10_INSRT_EN_MSK;
1260		prot->lbrtgv = lbrt_chk_val;
1261		break;
1262	case SCSI_PROT_READ_STRIP:
1263		prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK);
1264		prot->lbrtcv = lbrt_chk_val;
1265		prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
1266		break;
1267	case SCSI_PROT_READ_PASS:
1268		prot->dw0 |= T10_CHK_EN_MSK;
1269		prot->lbrtcv = lbrt_chk_val;
1270		prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
1271		break;
1272	case SCSI_PROT_WRITE_INSERT:
1273		prot->dw0 |= T10_INSRT_EN_MSK;
1274		prot->lbrtgv = lbrt_chk_val;
1275		break;
1276	case SCSI_PROT_WRITE_STRIP:
1277		prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK);
1278		prot->lbrtcv = lbrt_chk_val;
1279		break;
1280	case SCSI_PROT_WRITE_PASS:
1281		prot->dw0 |= T10_CHK_EN_MSK;
1282		prot->lbrtcv = lbrt_chk_val;
1283		prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
1284		break;
1285	default:
1286		WARN(1, "prot_op(0x%x) is not valid\n", prot_op);
1287		break;
1288	}
1289
1290	switch (interval) {
1291	case 512:
1292		break;
1293	case 4096:
1294		prot->dw0 |= (0x1 << USR_DATA_BLOCK_SZ_OFF);
1295		break;
1296	case 520:
1297		prot->dw0 |= (0x2 << USR_DATA_BLOCK_SZ_OFF);
1298		break;
1299	default:
1300		WARN(1, "protection interval (0x%x) invalid\n",
1301		     interval);
1302		break;
1303	}
1304
1305	prot->dw0 |= INCR_LBRT_MSK;
1306}
1307
1308static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
1309			  struct hisi_sas_slot *slot)
1310{
1311	struct sas_task *task = slot->task;
1312	struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1313	struct domain_device *device = task->dev;
1314	struct hisi_sas_device *sas_dev = device->lldd_dev;
1315	struct hisi_sas_port *port = slot->port;
1316	struct sas_ssp_task *ssp_task = &task->ssp_task;
1317	struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1318	struct sas_tmf_task *tmf = slot->tmf;
1319	int has_data = 0, priority = !!tmf;
1320	unsigned char prot_op;
1321	u8 *buf_cmd;
1322	u32 dw1 = 0, dw2 = 0, len = 0;
1323
1324	hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1325			       (2 << CMD_HDR_TLR_CTRL_OFF) |
1326			       (port->id << CMD_HDR_PORT_OFF) |
1327			       (priority << CMD_HDR_PRIORITY_OFF) |
1328			       (1 << CMD_HDR_CMD_OFF)); /* ssp */
1329
1330	dw1 = 1 << CMD_HDR_VDTL_OFF;
1331	if (tmf) {
1332		dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1333		dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1334	} else {
1335		prot_op = scsi_get_prot_op(scsi_cmnd);
1336		dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1337		switch (scsi_cmnd->sc_data_direction) {
1338		case DMA_TO_DEVICE:
1339			has_data = 1;
1340			dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1341			break;
1342		case DMA_FROM_DEVICE:
1343			has_data = 1;
1344			dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1345			break;
1346		default:
1347			dw1 &= ~CMD_HDR_DIR_MSK;
1348		}
1349	}
1350
1351	/* map itct entry */
1352	dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1353
1354	dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr) +
1355	         3) / BYTE_TO_DW) << CMD_HDR_CFL_OFF) |
1356	      ((HISI_SAS_MAX_SSP_RESP_SZ / BYTE_TO_DW) << CMD_HDR_MRFL_OFF) |
1357	      (HDR_SG_MOD << CMD_HDR_SG_MOD_OFF);
1358	hdr->dw2 = cpu_to_le32(dw2);
1359	hdr->transfer_tags = cpu_to_le32(slot->idx);
1360
1361	if (has_data) {
1362		prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
1363				   slot->n_elem);
1364
1365		if (scsi_prot_sg_count(scsi_cmnd))
1366			prep_prd_sge_dif_v3_hw(hisi_hba, slot, hdr,
1367					       scsi_prot_sglist(scsi_cmnd),
1368					       slot->n_elem_dif);
1369	}
1370
1371	hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1372	hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1373
1374	buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
1375		sizeof(struct ssp_frame_hdr);
1376
1377	memcpy(buf_cmd, &task->ssp_task.LUN, LUN_SIZE);
1378	if (!tmf) {
1379		buf_cmd[ATTR_PRIO_REGION] = ssp_task->task_attr;
1380		memcpy(buf_cmd + CDB_REGION, scsi_cmnd->cmnd,
1381		       scsi_cmnd->cmd_len);
1382	} else {
1383		buf_cmd[TMF_REGION] = tmf->tmf;
1384		switch (tmf->tmf) {
1385		case TMF_ABORT_TASK:
1386		case TMF_QUERY_TASK:
1387			buf_cmd[TAG_MSB] =
1388				(tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1389			buf_cmd[TAG_LSB] =
1390				tmf->tag_of_task_to_be_managed & 0xff;
1391			break;
1392		default:
1393			break;
1394		}
1395	}
1396
1397	if (has_data && (prot_op != SCSI_PROT_NORMAL)) {
1398		struct hisi_sas_protect_iu_v3_hw prot;
1399		u8 *buf_cmd_prot;
1400
1401		hdr->dw7 |= cpu_to_le32(1 << CMD_HDR_ADDR_MODE_SEL_OFF);
1402		dw1 |= CMD_HDR_PIR_MSK;
1403		buf_cmd_prot = hisi_sas_cmd_hdr_addr_mem(slot) +
1404			       sizeof(struct ssp_frame_hdr) +
1405			       sizeof(struct ssp_command_iu);
1406
1407		memset(&prot, 0, sizeof(struct hisi_sas_protect_iu_v3_hw));
1408		fill_prot_v3_hw(scsi_cmnd, &prot);
1409		memcpy(buf_cmd_prot, &prot,
1410		       sizeof(struct hisi_sas_protect_iu_v3_hw));
1411		/*
1412		 * For READ, we need length of info read to memory, while for
1413		 * WRITE we need length of data written to the disk.
1414		 */
1415		if (prot_op == SCSI_PROT_WRITE_INSERT ||
1416		    prot_op == SCSI_PROT_READ_INSERT ||
1417		    prot_op == SCSI_PROT_WRITE_PASS ||
1418		    prot_op == SCSI_PROT_READ_PASS) {
1419			unsigned int interval = scsi_prot_interval(scsi_cmnd);
1420			unsigned int ilog2_interval = ilog2(interval);
1421
1422			len = (task->total_xfer_len >> ilog2_interval) *
1423			      BYTE_TO_DDW;
1424		}
1425	}
1426
1427	hdr->dw1 = cpu_to_le32(dw1);
1428
1429	hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len + len);
1430}
1431
1432static void prep_smp_v3_hw(struct hisi_hba *hisi_hba,
1433			  struct hisi_sas_slot *slot)
1434{
1435	struct sas_task *task = slot->task;
1436	struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1437	struct domain_device *device = task->dev;
1438	struct hisi_sas_port *port = slot->port;
1439	struct scatterlist *sg_req;
1440	struct hisi_sas_device *sas_dev = device->lldd_dev;
1441	dma_addr_t req_dma_addr;
1442	unsigned int req_len;
1443	u32 cfl;
1444
1445	/* req */
1446	sg_req = &task->smp_task.smp_req;
1447	req_len = sg_dma_len(sg_req);
1448	req_dma_addr = sg_dma_address(sg_req);
1449
1450	/* create header */
1451	/* dw0 */
1452	hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1453			       (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1454			       (SMP_FRAME_TYPE << CMD_HDR_CMD_OFF)); /* smp */
1455
1456	/* map itct entry */
1457	hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1458			       (1 << CMD_HDR_FRAME_TYPE_OFF) |
1459			       (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1460
1461	/* dw2 */
1462	cfl = (req_len - SMP_CRC_SIZE) / BYTE_TO_DW;
1463	hdr->dw2 = cpu_to_le32((cfl << CMD_HDR_CFL_OFF) |
1464			       (HISI_SAS_MAX_SMP_RESP_SZ / BYTE_TO_DW <<
1465			       CMD_HDR_MRFL_OFF));
1466
1467	hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1468
1469	hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1470	hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1471}
1472
1473static void prep_ata_v3_hw(struct hisi_hba *hisi_hba,
1474			  struct hisi_sas_slot *slot)
1475{
1476	struct sas_task *task = slot->task;
1477	struct domain_device *device = task->dev;
1478	struct hisi_sas_device *sas_dev = device->lldd_dev;
1479	struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1480	struct asd_sas_port *sas_port = device->port;
1481	struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
1482	int phy_id;
1483	u8 *buf_cmd;
1484	int has_data = 0, hdr_tag = 0;
1485	u32 dw1 = 0, dw2 = 0;
1486
1487	hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
1488	if (dev_parent_is_expander(device)) {
1489		hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
1490	} else {
1491		phy_id = device->phy->identify.phy_identifier;
1492		hdr->dw0 |= cpu_to_le32((1U << phy_id)
1493				<< CMD_HDR_PHY_ID_OFF);
1494		hdr->dw0 |= CMD_HDR_FORCE_PHY_MSK;
1495		hdr->dw0 |= cpu_to_le32(4U << CMD_HDR_CMD_OFF);
1496	}
1497
1498	switch (task->data_dir) {
1499	case DMA_TO_DEVICE:
1500		has_data = 1;
1501		dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1502		break;
1503	case DMA_FROM_DEVICE:
1504		has_data = 1;
1505		dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1506		break;
1507	default:
1508		dw1 &= ~CMD_HDR_DIR_MSK;
1509	}
1510
1511	if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
1512			(task->ata_task.fis.control & ATA_SRST))
1513		dw1 |= 1 << CMD_HDR_RESET_OFF;
1514
1515	dw1 |= (hisi_sas_get_ata_protocol(task)) << CMD_HDR_FRAME_TYPE_OFF;
1516	dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1517
1518	if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis))
1519		dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF;
1520
1521	hdr->dw1 = cpu_to_le32(dw1);
1522
1523	/* dw2 */
1524	if (task->ata_task.use_ncq) {
1525		struct ata_queued_cmd *qc = task->uldd_task;
1526
1527		hdr_tag = qc->tag;
1528		task->ata_task.fis.sector_count |=
1529				(u8)(hdr_tag << HDR_TAG_OFF);
1530		dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
1531	}
1532
1533	dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / BYTE_TO_DW) << CMD_HDR_CFL_OFF |
1534		HDR_SG_MOD << CMD_HDR_SG_MOD_OFF;
1535	hdr->dw2 = cpu_to_le32(dw2);
1536
1537	/* dw3 */
1538	hdr->transfer_tags = cpu_to_le32(slot->idx);
1539
1540	if (has_data)
1541		prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
1542					slot->n_elem);
1543
1544	hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1545	hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1546	hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1547
1548	buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
1549
1550	if (likely(!task->ata_task.device_control_reg_update))
1551		task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
1552	/* fill in command FIS */
1553	memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
1554}
1555
1556static void prep_abort_v3_hw(struct hisi_hba *hisi_hba,
1557			     struct hisi_sas_slot *slot)
1558{
1559	struct sas_task *task = slot->task;
1560	struct sas_internal_abort_task *abort = &task->abort_task;
1561	struct domain_device *dev = task->dev;
1562	struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1563	struct hisi_sas_port *port = slot->port;
1564	struct hisi_sas_device *sas_dev = dev->lldd_dev;
1565	bool sata = dev_is_sata(dev);
1566
1567	/* dw0 */
1568	hdr->dw0 = cpu_to_le32((5U << CMD_HDR_CMD_OFF) | /* abort */
1569			       (port->id << CMD_HDR_PORT_OFF) |
1570				(sata << CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
1571				(abort->type << CMD_HDR_ABORT_FLAG_OFF));
1572
1573	/* dw1 */
1574	hdr->dw1 = cpu_to_le32(sas_dev->device_id
1575			<< CMD_HDR_DEV_ID_OFF);
1576
1577	/* dw7 */
1578	hdr->dw7 = cpu_to_le32(abort->tag << CMD_HDR_ABORT_IPTT_OFF);
1579	hdr->transfer_tags = cpu_to_le32(slot->idx);
1580}
1581
1582static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1583{
1584	int i;
1585	irqreturn_t res;
1586	u32 context, port_id, link_rate;
1587	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1588	struct asd_sas_phy *sas_phy = &phy->sas_phy;
1589	struct device *dev = hisi_hba->dev;
1590
1591	hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
1592
1593	port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1594	port_id = (port_id >> (HISI_SAS_REG_MEM_SIZE * phy_no)) & 0xf;
1595	link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1596	link_rate = (link_rate >> (phy_no * HISI_SAS_REG_MEM_SIZE)) & 0xf;
1597
1598	if (port_id == 0xf) {
1599		dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1600		res = IRQ_NONE;
1601		goto end;
1602	}
1603	sas_phy->linkrate = link_rate;
1604	phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1605
1606	/* Check for SATA dev */
1607	context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1608	if (context & (1 << phy_no)) {
1609		struct hisi_sas_initial_fis *initial_fis;
1610		struct dev_to_host_fis *fis;
1611		u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
1612		struct Scsi_Host *shost = hisi_hba->shost;
1613
1614		dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate);
1615		initial_fis = &hisi_hba->initial_fis[phy_no];
1616		fis = &initial_fis->fis;
1617
1618		/* check ERR bit of Status Register */
1619		if (fis->status & ATA_ERR) {
1620			dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n",
1621				 phy_no, fis->status);
1622			hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1623			res = IRQ_NONE;
1624			goto end;
1625		}
1626
1627		sas_phy->oob_mode = SATA_OOB_MODE;
1628		attached_sas_addr[0] = 0x50;
1629		attached_sas_addr[HOST_NO_OFF] = shost->host_no;
1630		attached_sas_addr[PHY_NO_OFF] = phy_no;
1631		memcpy(sas_phy->attached_sas_addr,
1632		       attached_sas_addr,
1633		       SAS_ADDR_SIZE);
1634		memcpy(sas_phy->frame_rcvd, fis,
1635		       sizeof(struct dev_to_host_fis));
1636		phy->phy_type |= PORT_TYPE_SATA;
1637		phy->identify.device_type = SAS_SATA_DEV;
1638		phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
1639		phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
1640	} else {
1641		u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1642		struct sas_identify_frame *id =
1643			(struct sas_identify_frame *)frame_rcvd;
1644
1645		dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1646		for (i = 0; i < IDENTIFY_REG_READ; i++) {
1647			u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1648					       RX_IDAF_DWORD0 + (i * 4));
1649			frame_rcvd[i] = __swab32(idaf);
1650		}
1651		sas_phy->oob_mode = SAS_OOB_MODE;
1652		memcpy(sas_phy->attached_sas_addr,
1653		       &id->sas_addr,
1654		       SAS_ADDR_SIZE);
1655		phy->phy_type |= PORT_TYPE_SAS;
1656		phy->identify.device_type = id->dev_type;
1657		phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
1658		if (phy->identify.device_type == SAS_END_DEVICE)
1659			phy->identify.target_port_protocols =
1660				SAS_PROTOCOL_SSP;
1661		else if (phy->identify.device_type != SAS_PHY_UNUSED)
1662			phy->identify.target_port_protocols =
1663				SAS_PROTOCOL_SMP;
1664	}
1665
1666	phy->port_id = port_id;
1667	spin_lock(&phy->lock);
1668	/* Delete timer and set phy_attached atomically */
1669	timer_delete(&phy->timer);
1670	phy->phy_attached = 1;
1671	spin_unlock(&phy->lock);
1672
1673	/*
1674	 * Call pm_runtime_get_noresume() which pairs with
1675	 * hisi_sas_phyup_pm_work() -> pm_runtime_put_sync().
1676	 * For failure call pm_runtime_put() as we are in a hardirq context.
1677	 */
1678	pm_runtime_get_noresume(dev);
1679	res = hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP_PM);
1680	if (!res)
1681		pm_runtime_put(dev);
1682
1683	res = IRQ_HANDLED;
1684
1685end:
1686	if (phy->reset_completion)
1687		complete(phy->reset_completion);
1688	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1689			     CHL_INT0_SL_PHY_ENABLE_MSK);
1690	hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
1691
1692	return res;
1693}
1694
1695static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1696{
1697	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1698	u32 phy_state, sl_ctrl, txid_auto;
1699	struct device *dev = hisi_hba->dev;
1700
1701	atomic_inc(&phy->down_cnt);
1702
1703	timer_delete(&phy->timer);
1704	hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
1705
1706	phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1707	dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
1708	hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0,
1709			  GFP_ATOMIC);
1710
1711	sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1712	hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
1713						sl_ctrl&(~SL_CTA_MSK));
1714
1715	txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1716	hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1717						txid_auto | CT3_MSK);
1718
1719	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
1720	hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
1721
1722	return IRQ_HANDLED;
1723}
1724
1725static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1726{
1727	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1728	u32 bcast_status;
1729
1730	hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
1731	bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
1732	if (bcast_status & RX_BCAST_CHG_MSK)
1733		hisi_sas_phy_bcast(phy);
1734	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1735			     CHL_INT0_SL_RX_BCST_ACK_MSK);
1736	hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
1737
1738	return IRQ_HANDLED;
1739}
1740
1741static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p)
1742{
1743	struct hisi_hba *hisi_hba = p;
1744	u32 irq_msk;
1745	int phy_no = 0;
1746	irqreturn_t res = IRQ_NONE;
1747
1748	irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1749				& 0x11111111;
1750	while (irq_msk) {
1751		if (irq_msk & 1) {
1752			u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1753							    CHL_INT0);
1754			u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1755			int rdy = phy_state & (1 << phy_no);
1756
1757			if (rdy) {
1758				if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
1759					/* phy up */
1760					if (phy_up_v3_hw(phy_no, hisi_hba)
1761							== IRQ_HANDLED)
1762						res = IRQ_HANDLED;
1763				if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK)
1764					/* phy bcast */
1765					if (phy_bcast_v3_hw(phy_no, hisi_hba)
1766							== IRQ_HANDLED)
1767						res = IRQ_HANDLED;
1768			} else {
1769				if (irq_value & CHL_INT0_NOT_RDY_MSK)
1770					/* phy down */
1771					if (phy_down_v3_hw(phy_no, hisi_hba)
1772							== IRQ_HANDLED)
1773						res = IRQ_HANDLED;
1774			}
1775		}
1776		irq_msk >>= 4;
1777		phy_no++;
1778	}
1779
1780	return res;
1781}
1782
1783static const struct hisi_sas_hw_error port_axi_error[] = {
1784	{
1785		.irq_msk = BIT(CHL_INT1_DMAC_TX_ECC_MB_ERR_OFF),
1786		.msg = "dmac_tx_ecc_bad_err",
1787	},
1788	{
1789		.irq_msk = BIT(CHL_INT1_DMAC_RX_ECC_MB_ERR_OFF),
1790		.msg = "dmac_rx_ecc_bad_err",
1791	},
1792	{
1793		.irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
1794		.msg = "dma_tx_axi_wr_err",
1795	},
1796	{
1797		.irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
1798		.msg = "dma_tx_axi_rd_err",
1799	},
1800	{
1801		.irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
1802		.msg = "dma_rx_axi_wr_err",
1803	},
1804	{
1805		.irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
1806		.msg = "dma_rx_axi_rd_err",
1807	},
1808	{
1809		.irq_msk = BIT(CHL_INT1_DMAC_TX_FIFO_ERR_OFF),
1810		.msg = "dma_tx_fifo_err",
1811	},
1812	{
1813		.irq_msk = BIT(CHL_INT1_DMAC_RX_FIFO_ERR_OFF),
1814		.msg = "dma_rx_fifo_err",
1815	},
1816	{
1817		.irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RUSER_ERR_OFF),
1818		.msg = "dma_tx_axi_ruser_err",
1819	},
1820	{
1821		.irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RUSER_ERR_OFF),
1822		.msg = "dma_rx_axi_ruser_err",
1823	},
1824};
1825
1826static void handle_chl_int1_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1827{
1828	u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1);
1829	u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1_MSK);
1830	struct device *dev = hisi_hba->dev;
1831	int i;
1832
1833	irq_value &= ~irq_msk;
1834	if (!irq_value) {
1835		dev_warn(dev, "phy%d channel int 1 received with status bits cleared\n",
1836			 phy_no);
1837		return;
1838	}
1839
1840	for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) {
1841		const struct hisi_sas_hw_error *error = &port_axi_error[i];
1842
1843		if (!(irq_value & error->irq_msk))
1844			continue;
1845
1846		dev_err(dev, "%s error (phy%d 0x%x) found!\n",
1847			error->msg, phy_no, irq_value);
1848		queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1849	}
1850
1851	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT1, irq_value);
1852}
1853
1854static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1855{
1856	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1857	struct asd_sas_phy *sas_phy = &phy->sas_phy;
1858	struct sas_phy *sphy = sas_phy->phy;
1859	unsigned long flags;
1860	u32 reg_value;
1861
1862	spin_lock_irqsave(&phy->lock, flags);
1863
1864	/* loss dword sync */
1865	reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST);
1866	sphy->loss_of_dword_sync_count += reg_value;
1867
1868	/* phy reset problem */
1869	reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB);
1870	sphy->phy_reset_problem_count += reg_value;
1871
1872	/* invalid dword */
1873	reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
1874	sphy->invalid_dword_count += reg_value;
1875
1876	/* disparity err */
1877	reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
1878	sphy->running_disparity_error_count += reg_value;
1879
1880	/* code violation error */
1881	reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR);
1882	phy->code_violation_err_count += reg_value;
1883
1884	spin_unlock_irqrestore(&phy->lock, flags);
1885}
1886
1887static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1888{
1889	u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK);
1890	u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2);
1891	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1892	struct pci_dev *pci_dev = hisi_hba->pci_dev;
1893	struct device *dev = hisi_hba->dev;
1894	static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) |
1895			BIT(CHL_INT2_RX_CODE_ERR_OFF) |
1896			BIT(CHL_INT2_RX_INVLD_DW_OFF);
1897
1898	irq_value &= ~irq_msk;
1899	if (!irq_value) {
1900		dev_warn(dev, "phy%d channel int 2 received with status bits cleared\n",
1901			 phy_no);
1902		return;
1903	}
1904
1905	if (irq_value & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
1906		dev_warn(dev, "phy%d identify timeout\n", phy_no);
1907		hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1908	}
1909
1910	if (irq_value & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) {
1911		u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1912				STP_LINK_TIMEOUT_STATE);
1913
1914		dev_warn(dev, "phy%d stp link timeout (0x%x)\n",
1915			 phy_no, reg_value);
1916		if (reg_value & BIT(LINK_RESET_TIMEOUT_OFF))
1917			hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1918	}
1919
1920	if (pci_dev->revision > 0x20 && (irq_value & msk)) {
1921		struct asd_sas_phy *sas_phy = &phy->sas_phy;
1922		struct sas_phy *sphy = sas_phy->phy;
1923
1924		phy_get_events_v3_hw(hisi_hba, phy_no);
1925
1926		if (irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF))
1927			dev_info(dev, "phy%d invalid dword cnt:   %u\n", phy_no,
1928				 sphy->invalid_dword_count);
1929
1930		if (irq_value & BIT(CHL_INT2_RX_CODE_ERR_OFF))
1931			dev_info(dev, "phy%d code violation cnt:  %u\n", phy_no,
1932				 phy->code_violation_err_count);
1933
1934		if (irq_value & BIT(CHL_INT2_RX_DISP_ERR_OFF))
1935			dev_info(dev, "phy%d disparity error cnt: %u\n", phy_no,
1936				 sphy->running_disparity_error_count);
1937	}
1938
1939	if ((irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) &&
1940	    (pci_dev->revision == 0x20)) {
1941		u32 reg_value;
1942		int rc;
1943
1944		rc = hisi_sas_read32_poll_timeout_atomic(
1945				HILINK_ERR_DFX, reg_value,
1946				!((reg_value >> 8) & BIT(phy_no)),
1947				1000, 10000);
1948		if (rc)
1949			hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1950	}
1951
1952	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value);
1953}
1954
1955static void handle_chl_int0_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1956{
1957	u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0);
1958
1959	if (irq_value0 & CHL_INT0_PHY_RDY_MSK)
1960		hisi_sas_phy_oob_ready(hisi_hba, phy_no);
1961
1962	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1963			     irq_value0 & (~CHL_INT0_SL_RX_BCST_ACK_MSK)
1964			     & (~CHL_INT0_SL_PHY_ENABLE_MSK)
1965			     & (~CHL_INT0_NOT_RDY_MSK));
1966}
1967
1968static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
1969{
1970	struct hisi_hba *hisi_hba = p;
1971	u32 irq_msk;
1972	int phy_no = 0;
1973
1974	irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) & CHNL_INT_STS_MSK;
1975
1976	while (irq_msk) {
1977		if (irq_msk & (CHNL_INT_STS_INT0_MSK << (phy_no * CHNL_WIDTH)))
1978			handle_chl_int0_v3_hw(hisi_hba, phy_no);
1979
1980		if (irq_msk & (CHNL_INT_STS_INT1_MSK << (phy_no * CHNL_WIDTH)))
1981			handle_chl_int1_v3_hw(hisi_hba, phy_no);
1982
1983		if (irq_msk & (CHNL_INT_STS_INT2_MSK << (phy_no * CHNL_WIDTH)))
1984			handle_chl_int2_v3_hw(hisi_hba, phy_no);
1985
1986		irq_msk &= ~(CHNL_INT_STS_PHY_MSK << (phy_no * CHNL_WIDTH));
1987		phy_no++;
1988	}
1989
1990	return IRQ_HANDLED;
1991}
1992
1993static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = {
1994	{
1995		.irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF),
1996		.msk = HGC_DQE_ECC_MB_ADDR_MSK,
1997		.shift = HGC_DQE_ECC_MB_ADDR_OFF,
1998		.msg = "hgc_dqe_eccbad_intr",
1999		.reg = HGC_DQE_ECC_ADDR,
2000	},
2001	{
2002		.irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF),
2003		.msk = HGC_IOST_ECC_MB_ADDR_MSK,
2004		.shift = HGC_IOST_ECC_MB_ADDR_OFF,
2005		.msg = "hgc_iost_eccbad_intr",
2006		.reg = HGC_IOST_ECC_ADDR,
2007	},
2008	{
2009		.irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF),
2010		.msk = HGC_ITCT_ECC_MB_ADDR_MSK,
2011		.shift = HGC_ITCT_ECC_MB_ADDR_OFF,
2012		.msg = "hgc_itct_eccbad_intr",
2013		.reg = HGC_ITCT_ECC_ADDR,
2014	},
2015	{
2016		.irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF),
2017		.msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
2018		.shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
2019		.msg = "hgc_iostl_eccbad_intr",
2020		.reg = HGC_LM_DFX_STATUS2,
2021	},
2022	{
2023		.irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF),
2024		.msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
2025		.shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
2026		.msg = "hgc_itctl_eccbad_intr",
2027		.reg = HGC_LM_DFX_STATUS2,
2028	},
2029	{
2030		.irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF),
2031		.msk = HGC_CQE_ECC_MB_ADDR_MSK,
2032		.shift = HGC_CQE_ECC_MB_ADDR_OFF,
2033		.msg = "hgc_cqe_eccbad_intr",
2034		.reg = HGC_CQE_ECC_ADDR,
2035	},
2036	{
2037		.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF),
2038		.msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
2039		.shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
2040		.msg = "rxm_mem0_eccbad_intr",
2041		.reg = HGC_RXM_DFX_STATUS14,
2042	},
2043	{
2044		.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF),
2045		.msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
2046		.shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
2047		.msg = "rxm_mem1_eccbad_intr",
2048		.reg = HGC_RXM_DFX_STATUS14,
2049	},
2050	{
2051		.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF),
2052		.msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
2053		.shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
2054		.msg = "rxm_mem2_eccbad_intr",
2055		.reg = HGC_RXM_DFX_STATUS14,
2056	},
2057	{
2058		.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF),
2059		.msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
2060		.shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
2061		.msg = "rxm_mem3_eccbad_intr",
2062		.reg = HGC_RXM_DFX_STATUS15,
2063	},
2064	{
2065		.irq_msk = BIT(SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF),
2066		.msk = AM_ROB_ECC_ERR_ADDR_MSK,
2067		.shift = AM_ROB_ECC_ERR_ADDR_OFF,
2068		.msg = "ooo_ram_eccbad_intr",
2069		.reg = AM_ROB_ECC_ERR_ADDR,
2070	},
2071};
2072
2073static void multi_bit_ecc_error_process_v3_hw(struct hisi_hba *hisi_hba,
2074					      u32 irq_value)
2075{
2076	struct device *dev = hisi_hba->dev;
2077	const struct hisi_sas_hw_error *ecc_error;
2078	u32 val;
2079	int i;
2080
2081	for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) {
2082		ecc_error = &multi_bit_ecc_errors[i];
2083		if (irq_value & ecc_error->irq_msk) {
2084			val = hisi_sas_read32(hisi_hba, ecc_error->reg);
2085			val &= ecc_error->msk;
2086			val >>= ecc_error->shift;
2087			dev_err(dev, "%s (0x%x) found: mem addr is 0x%08X\n",
2088				ecc_error->msg, irq_value, val);
2089			queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2090		}
2091	}
2092}
2093
2094static void fatal_ecc_int_v3_hw(struct hisi_hba *hisi_hba)
2095{
2096	u32 irq_value, irq_msk;
2097
2098	irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK);
2099	hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
2100
2101	irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
2102	if (irq_value)
2103		multi_bit_ecc_error_process_v3_hw(hisi_hba, irq_value);
2104
2105	hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value);
2106	hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk);
2107}
2108
2109static const struct hisi_sas_hw_error axi_error[] = {
2110	{ .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
2111	{ .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
2112	{ .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
2113	{ .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
2114	{ .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
2115	{ .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
2116	{ .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
2117	{ .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
2118	{}
2119};
2120
2121static const struct hisi_sas_hw_error fifo_error[] = {
2122	{ .msk = BIT(8),  .msg = "CQE_WINFO_FIFO" },
2123	{ .msk = BIT(9),  .msg = "CQE_MSG_FIFIO" },
2124	{ .msk = BIT(10), .msg = "GETDQE_FIFO" },
2125	{ .msk = BIT(11), .msg = "CMDP_FIFO" },
2126	{ .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
2127	{}
2128};
2129
2130static const struct hisi_sas_hw_error fatal_axi_error[] = {
2131	{
2132		.irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
2133		.msg = "write pointer and depth",
2134	},
2135	{
2136		.irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
2137		.msg = "iptt no match slot",
2138	},
2139	{
2140		.irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
2141		.msg = "read pointer and depth",
2142	},
2143	{
2144		.irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
2145		.reg = HGC_AXI_FIFO_ERR_INFO,
2146		.sub = axi_error,
2147	},
2148	{
2149		.irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
2150		.reg = HGC_AXI_FIFO_ERR_INFO,
2151		.sub = fifo_error,
2152	},
2153	{
2154		.irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
2155		.msg = "LM add/fetch list",
2156	},
2157	{
2158		.irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
2159		.msg = "SAS_HGC_ABT fetch LM list",
2160	},
2161	{
2162		.irq_msk = BIT(ENT_INT_SRC3_DQE_POISON_OFF),
2163		.msg = "read dqe poison",
2164	},
2165	{
2166		.irq_msk = BIT(ENT_INT_SRC3_IOST_POISON_OFF),
2167		.msg = "read iost poison",
2168	},
2169	{
2170		.irq_msk = BIT(ENT_INT_SRC3_ITCT_POISON_OFF),
2171		.msg = "read itct poison",
2172	},
2173	{
2174		.irq_msk = BIT(ENT_INT_SRC3_ITCT_NCQ_POISON_OFF),
2175		.msg = "read itct ncq poison",
2176	},
2177
2178};
2179
2180static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p)
2181{
2182	u32 irq_value, irq_msk;
2183	struct hisi_hba *hisi_hba = p;
2184	struct device *dev = hisi_hba->dev;
2185	struct pci_dev *pdev = hisi_hba->pci_dev;
2186	int i;
2187
2188	irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
2189	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00);
2190
2191	irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
2192	irq_value &= ~irq_msk;
2193
2194	for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) {
2195		const struct hisi_sas_hw_error *error = &fatal_axi_error[i];
2196
2197		if (!(irq_value & error->irq_msk))
2198			continue;
2199
2200		if (error->sub) {
2201			const struct hisi_sas_hw_error *sub = error->sub;
2202			u32 err_value = hisi_sas_read32(hisi_hba, error->reg);
2203
2204			for (; sub->msk || sub->msg; sub++) {
2205				if (!(err_value & sub->msk))
2206					continue;
2207
2208				dev_err(dev, "%s error (0x%x) found!\n",
2209					sub->msg, irq_value);
2210				queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2211			}
2212		} else {
2213			dev_err(dev, "%s error (0x%x) found!\n",
2214				error->msg, irq_value);
2215			queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2216		}
2217
2218		if (pdev->revision < 0x21) {
2219			u32 reg_val;
2220
2221			reg_val = hisi_sas_read32(hisi_hba,
2222						  AXI_MASTER_CFG_BASE +
2223						  AM_CTRL_GLOBAL);
2224			reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK;
2225			hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
2226					 AM_CTRL_GLOBAL, reg_val);
2227		}
2228	}
2229
2230	fatal_ecc_int_v3_hw(hisi_hba);
2231
2232	if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
2233		u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
2234		u32 dev_id = reg_val & ITCT_DEV_MSK;
2235		struct hisi_sas_device *sas_dev =
2236				&hisi_hba->devices[dev_id];
2237
2238		hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
2239		dev_dbg(dev, "clear ITCT ok\n");
2240		complete(sas_dev->completion);
2241	}
2242
2243	hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00);
2244	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
2245
2246	return IRQ_HANDLED;
2247}
2248
2249static bool is_ncq_err_v3_hw(struct hisi_sas_complete_v3_hdr *complete_hdr)
2250{
2251	u32 dw0, dw3;
2252
2253	dw0 = le32_to_cpu(complete_hdr->dw0);
2254	dw3 = le32_to_cpu(complete_hdr->dw3);
2255
2256	return (dw0 & ERR_PHASE_RESPONSE_FRAME_REV_STAGE_MSK) &&
2257	       (dw3 & FIS_TYPE_SDB_MSK) &&
2258	       (dw3 & FIS_ATA_STATUS_ERR_MSK);
2259}
2260
2261static bool
2262slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
2263	       struct hisi_sas_slot *slot)
2264{
2265	struct task_status_struct *ts = &task->task_status;
2266	struct hisi_sas_complete_v3_hdr *complete_queue =
2267			hisi_hba->complete_hdr[slot->cmplt_queue];
2268	struct hisi_sas_complete_v3_hdr *complete_hdr =
2269			&complete_queue[slot->cmplt_queue_slot];
2270	struct hisi_sas_err_record_v3 *record =
2271			hisi_sas_status_buf_addr_mem(slot);
2272	u32 dma_rx_err_type = le32_to_cpu(record->dma_rx_err_type);
2273	u32 trans_tx_fail_type = le32_to_cpu(record->trans_tx_fail_type);
2274	u16 sipc_rx_err_type = le16_to_cpu(record->sipc_rx_err_type);
2275	u32 dw3 = le32_to_cpu(complete_hdr->dw3);
2276	u32 dw0 = le32_to_cpu(complete_hdr->dw0);
2277
2278	switch (task->task_proto) {
2279	case SAS_PROTOCOL_SSP:
2280		if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
2281			/*
2282			 * If returned response frame is incorrect because of data underflow,
2283			 * but I/O information has been written to the host memory, we examine
2284			 * response IU.
2285			 */
2286			if (!(dw0 & CMPLT_HDR_RSPNS_GOOD_MSK) &&
2287			    (dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))
2288				return false;
2289
2290			ts->residual = trans_tx_fail_type;
2291			ts->stat = SAS_DATA_UNDERRUN;
2292		} else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
2293			ts->stat = SAS_QUEUE_FULL;
2294			slot->abort = 1;
2295		} else {
2296			ts->stat = SAS_OPEN_REJECT;
2297			ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2298		}
2299		break;
2300	case SAS_PROTOCOL_SATA:
2301	case SAS_PROTOCOL_STP:
2302	case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2303		if ((dw0 & CMPLT_HDR_RSPNS_XFRD_MSK) &&
2304		    (sipc_rx_err_type & RX_FIS_STATUS_ERR_MSK)) {
2305			if (task->ata_task.use_ncq) {
2306				struct domain_device *device = task->dev;
2307				struct hisi_sas_device *sas_dev = device->lldd_dev;
2308
2309				sas_dev->dev_status = HISI_SAS_DEV_NCQ_ERR;
2310				slot->abort = 1;
2311			} else {
2312				ts->stat = SAS_PROTO_RESPONSE;
2313			}
2314		} else if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
2315			ts->residual = trans_tx_fail_type;
2316			ts->stat = SAS_DATA_UNDERRUN;
2317		} else if ((dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) ||
2318			   (dw3 & SATA_DISK_IN_ERROR_STATUS_MSK)) {
2319			ts->stat = SAS_PHY_DOWN;
2320			slot->abort = 1;
2321		} else {
2322			ts->stat = SAS_OPEN_REJECT;
2323			ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2324		}
2325		if (dw0 & CMPLT_HDR_RSPNS_XFRD_MSK)
2326			hisi_sas_sata_done(task, slot);
2327		break;
2328	case SAS_PROTOCOL_SMP:
2329		ts->stat = SAS_SAM_STAT_CHECK_CONDITION;
2330		break;
2331	default:
2332		break;
2333	}
2334	return true;
2335}
2336
2337static void slot_complete_v3_hw(struct hisi_hba *hisi_hba,
2338				struct hisi_sas_slot *slot)
2339{
2340	struct sas_task *task = slot->task;
2341	struct hisi_sas_device *sas_dev;
2342	struct device *dev = hisi_hba->dev;
2343	struct task_status_struct *ts;
2344	struct domain_device *device;
2345	struct sas_ha_struct *ha;
2346	struct hisi_sas_complete_v3_hdr *complete_queue =
2347			hisi_hba->complete_hdr[slot->cmplt_queue];
2348	struct hisi_sas_complete_v3_hdr *complete_hdr =
2349			&complete_queue[slot->cmplt_queue_slot];
2350	unsigned long flags;
2351	bool is_internal = slot->is_internal;
2352	u32 dw0, dw1, dw3;
2353
2354	if (unlikely(!task || !task->lldd_task || !task->dev))
2355		return;
2356
2357	ts = &task->task_status;
2358	device = task->dev;
2359	ha = device->port->ha;
2360	sas_dev = device->lldd_dev;
2361
2362	spin_lock_irqsave(&task->task_state_lock, flags);
2363	task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2364	spin_unlock_irqrestore(&task->task_state_lock, flags);
2365
2366	memset(ts, 0, sizeof(*ts));
2367	ts->resp = SAS_TASK_COMPLETE;
2368
2369	if (unlikely(!sas_dev)) {
2370		dev_dbg(dev, "slot complete: port has not device\n");
2371		ts->stat = SAS_PHY_DOWN;
2372		goto out;
2373	}
2374
2375	dw0 = le32_to_cpu(complete_hdr->dw0);
2376	dw1 = le32_to_cpu(complete_hdr->dw1);
2377	dw3 = le32_to_cpu(complete_hdr->dw3);
2378
2379	/*
2380	 * Use SAS+TMF status codes
2381	 */
2382	switch ((dw0 & CMPLT_HDR_ABORT_STAT_MSK) >> CMPLT_HDR_ABORT_STAT_OFF) {
2383	case STAT_IO_ABORTED:
2384		/* this IO has been aborted by abort command */
2385		ts->stat = SAS_ABORTED_TASK;
2386		goto out;
2387	case STAT_IO_COMPLETE:
2388		/* internal abort command complete */
2389		ts->stat = TMF_RESP_FUNC_SUCC;
2390		goto out;
2391	case STAT_IO_NO_DEVICE:
2392		ts->stat = TMF_RESP_FUNC_COMPLETE;
2393		goto out;
2394	case STAT_IO_NOT_VALID:
2395		/*
2396		 * abort single IO, the controller can't find the IO
2397		 */
2398		ts->stat = TMF_RESP_FUNC_FAILED;
2399		goto out;
2400	default:
2401		break;
2402	}
2403
2404	/* check for erroneous completion */
2405	if ((dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) {
2406		u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
2407
2408		if (slot_err_v3_hw(hisi_hba, task, slot)) {
2409			if (ts->stat != SAS_DATA_UNDERRUN)
2410				dev_info(dev, "erroneous completion iptt=%d task=%p dev id=%d addr=%016llx CQ hdr: 0x%x 0x%x 0x%x 0x%x Error info: 0x%x 0x%x 0x%x 0x%x\n",
2411					slot->idx, task, sas_dev->device_id,
2412					SAS_ADDR(device->sas_addr),
2413					dw0, dw1, complete_hdr->act, dw3,
2414					error_info[0], error_info[1],
2415					error_info[2], error_info[3]);
2416			if (unlikely(slot->abort)) {
2417				if (dev_is_sata(device) && task->ata_task.use_ncq)
2418					sas_ata_device_link_abort(device, true);
2419				else
2420					sas_task_abort(task);
2421
2422				return;
2423			}
2424			goto out;
2425		}
2426	}
2427
2428	switch (task->task_proto) {
2429	case SAS_PROTOCOL_SSP: {
2430		struct ssp_response_iu *iu =
2431			hisi_sas_status_buf_addr_mem(slot) +
2432			sizeof(struct hisi_sas_err_record);
2433
2434		sas_ssp_task_response(dev, task, iu);
2435		break;
2436	}
2437	case SAS_PROTOCOL_SMP: {
2438		struct scatterlist *sg_resp = &task->smp_task.smp_resp;
2439		void *to = page_address(sg_page(sg_resp));
2440
2441		ts->stat = SAS_SAM_STAT_GOOD;
2442
2443		memcpy(to + sg_resp->offset,
2444			hisi_sas_status_buf_addr_mem(slot) +
2445		       sizeof(struct hisi_sas_err_record),
2446		       sg_resp->length);
2447		break;
2448	}
2449	case SAS_PROTOCOL_SATA:
2450	case SAS_PROTOCOL_STP:
2451	case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2452		ts->stat = SAS_SAM_STAT_GOOD;
2453		if (dw0 & CMPLT_HDR_RSPNS_XFRD_MSK)
2454			hisi_sas_sata_done(task, slot);
2455		break;
2456	default:
2457		ts->stat = SAS_SAM_STAT_CHECK_CONDITION;
2458		break;
2459	}
2460
2461	if (!slot->port->port_attached) {
2462		dev_warn(dev, "slot complete: port %d has removed\n",
2463			slot->port->sas_port.id);
2464		ts->stat = SAS_PHY_DOWN;
2465	}
2466
2467out:
2468	spin_lock_irqsave(&task->task_state_lock, flags);
2469	if (task->task_state_flags & SAS_TASK_STATE_ABORTED) {
2470		spin_unlock_irqrestore(&task->task_state_lock, flags);
2471		dev_info(dev, "slot complete: task(%p) aborted\n", task);
2472		return;
2473	}
2474	task->task_state_flags |= SAS_TASK_STATE_DONE;
2475	spin_unlock_irqrestore(&task->task_state_lock, flags);
2476	hisi_sas_slot_task_free(hisi_hba, task, slot, true);
2477
2478	if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) {
2479		spin_lock_irqsave(&device->done_lock, flags);
2480		if (test_bit(SAS_HA_FROZEN, &ha->state)) {
2481			spin_unlock_irqrestore(&device->done_lock, flags);
2482			dev_info(dev, "slot complete: task(%p) ignored\n",
2483				 task);
2484			return;
2485		}
2486		spin_unlock_irqrestore(&device->done_lock, flags);
2487	}
2488
2489	if (task->task_done)
2490		task->task_done(task);
2491}
2492
2493static int complete_v3_hw(struct hisi_sas_cq *cq)
2494{
2495	struct hisi_sas_complete_v3_hdr *complete_queue;
2496	struct hisi_hba *hisi_hba = cq->hisi_hba;
2497	u32 rd_point, wr_point;
2498	int queue = cq->id;
2499	int completed;
2500
2501	rd_point = cq->rd_point;
2502	complete_queue = hisi_hba->complete_hdr[queue];
2503
2504	wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
2505				   (0x14 * queue));
2506	completed = (wr_point + HISI_SAS_QUEUE_SLOTS - rd_point) % HISI_SAS_QUEUE_SLOTS;
2507
2508	while (rd_point != wr_point) {
2509		struct hisi_sas_complete_v3_hdr *complete_hdr;
2510		struct device *dev = hisi_hba->dev;
2511		struct hisi_sas_slot *slot;
2512		u32 dw0, dw1, dw3;
2513		int iptt;
2514
2515		complete_hdr = &complete_queue[rd_point];
2516		dw0 = le32_to_cpu(complete_hdr->dw0);
2517		dw1 = le32_to_cpu(complete_hdr->dw1);
2518		dw3 = le32_to_cpu(complete_hdr->dw3);
2519
2520		iptt = dw1 & CMPLT_HDR_IPTT_MSK;
2521		if (unlikely((dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) &&
2522			     (dw3 & CMPLT_HDR_SATA_DISK_ERR_MSK)) {
2523			int device_id = (dw1 & CMPLT_HDR_DEV_ID_MSK) >>
2524					CMPLT_HDR_DEV_ID_OFF;
2525			struct hisi_sas_itct *itct =
2526				&hisi_hba->itct[device_id];
2527			struct hisi_sas_device *sas_dev =
2528				&hisi_hba->devices[device_id];
2529			struct domain_device *device = sas_dev->sas_device;
2530
2531			dev_err(dev, "erroneous completion disk err dev id=%d sas_addr=0x%llx CQ hdr: 0x%x 0x%x 0x%x 0x%x\n",
2532				device_id, itct->sas_addr, dw0, dw1,
2533				complete_hdr->act, dw3);
2534
2535			if (is_ncq_err_v3_hw(complete_hdr))
2536				sas_dev->dev_status = HISI_SAS_DEV_NCQ_ERR;
2537
2538			sas_ata_device_link_abort(device, true);
2539		} else if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) {
2540			slot = &hisi_hba->slot_info[iptt];
2541			slot->cmplt_queue_slot = rd_point;
2542			slot->cmplt_queue = queue;
2543			slot_complete_v3_hw(hisi_hba, slot);
2544		} else
2545			dev_err(dev, "IPTT %d is invalid, discard it.\n", iptt);
2546
2547		if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
2548			rd_point = 0;
2549	}
2550
2551	/* update rd_point */
2552	cq->rd_point = rd_point;
2553	hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
2554	cond_resched();
2555
2556	return completed;
2557}
2558
2559static int queue_complete_v3_hw(struct Scsi_Host *shost, unsigned int queue)
2560{
2561	struct hisi_hba *hisi_hba = shost_priv(shost);
2562	struct hisi_sas_cq *cq = &hisi_hba->cq[queue];
2563	int completed;
2564
2565	spin_lock(&cq->poll_lock);
2566	completed = complete_v3_hw(cq);
2567	spin_unlock(&cq->poll_lock);
2568
2569	return completed;
2570}
2571
2572static irqreturn_t cq_thread_v3_hw(int irq_no, void *p)
2573{
2574	struct hisi_sas_cq *cq = p;
2575
2576	complete_v3_hw(cq);
2577
2578	return IRQ_HANDLED;
2579}
2580
2581static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p)
2582{
2583	struct hisi_sas_cq *cq = p;
2584	struct hisi_hba *hisi_hba = cq->hisi_hba;
2585	int queue = cq->id;
2586
2587	hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
2588
2589	return IRQ_WAKE_THREAD;
2590}
2591
2592static void hisi_sas_v3_free_vectors(void *data)
2593{
2594	struct pci_dev *pdev = data;
2595
2596	pci_free_irq_vectors(pdev);
2597}
2598
2599static int interrupt_preinit_v3_hw(struct hisi_hba *hisi_hba)
2600{
2601	/* Allocate all MSI vectors to avoid re-insertion issue */
2602	int max_msi = HISI_SAS_MSI_COUNT_V3_HW;
2603	int vectors, min_msi;
2604	struct Scsi_Host *shost = hisi_hba->shost;
2605	struct pci_dev *pdev = hisi_hba->pci_dev;
2606	struct irq_affinity desc = {
2607		.pre_vectors = BASE_VECTORS_V3_HW,
2608	};
2609
2610	min_msi = MIN_AFFINE_VECTORS_V3_HW;
2611	vectors = pci_alloc_irq_vectors_affinity(pdev,
2612						 min_msi, max_msi,
2613						 PCI_IRQ_MSI |
2614						 PCI_IRQ_AFFINITY,
2615						 &desc);
2616	if (vectors < 0)
2617		return -ENOENT;
2618
2619	hisi_hba->cq_nvecs = vectors - BASE_VECTORS_V3_HW - hisi_hba->iopoll_q_cnt;
2620	shost->nr_hw_queues = hisi_hba->cq_nvecs + hisi_hba->iopoll_q_cnt;
2621
2622	return devm_add_action(&pdev->dev, hisi_sas_v3_free_vectors, pdev);
2623}
2624
2625static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
2626{
2627	struct device *dev = hisi_hba->dev;
2628	struct pci_dev *pdev = hisi_hba->pci_dev;
2629	int rc, i;
2630
2631	rc = devm_request_irq(dev, pci_irq_vector(pdev, IRQ_PHY_UP_DOWN_INDEX),
2632			      int_phy_up_down_bcast_v3_hw, 0,
2633			      DRV_NAME " phy", hisi_hba);
2634	if (rc) {
2635		dev_err(dev, "could not request phy interrupt, rc=%d\n", rc);
2636		return -ENOENT;
2637	}
2638
2639	rc = devm_request_irq(dev, pci_irq_vector(pdev, IRQ_CHL_INDEX),
2640			      int_chnl_int_v3_hw, 0,
2641			      DRV_NAME " channel", hisi_hba);
2642	if (rc) {
2643		dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc);
2644		return -ENOENT;
2645	}
2646
2647	rc = devm_request_irq(dev, pci_irq_vector(pdev, IRQ_AXI_INDEX),
2648			      fatal_axi_int_v3_hw, 0,
2649			      DRV_NAME " fatal", hisi_hba);
2650	if (rc) {
2651		dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc);
2652		return -ENOENT;
2653	}
2654
2655	if (hisi_sas_intr_conv)
2656		dev_info(dev, "Enable interrupt converge\n");
2657
2658	for (i = 0; i < hisi_hba->cq_nvecs; i++) {
2659		struct hisi_sas_cq *cq = &hisi_hba->cq[i];
2660		int nr = hisi_sas_intr_conv ? BASE_VECTORS_V3_HW :
2661					      BASE_VECTORS_V3_HW + i;
2662		unsigned long irqflags = hisi_sas_intr_conv ? IRQF_SHARED :
2663							      IRQF_ONESHOT;
2664
2665		cq->irq_no = pci_irq_vector(pdev, nr);
2666		rc = devm_request_threaded_irq(dev, cq->irq_no,
2667				      cq_interrupt_v3_hw,
2668				      cq_thread_v3_hw,
2669				      irqflags,
2670				      DRV_NAME " cq", cq);
2671		if (rc) {
2672			dev_err(dev, "could not request cq%d interrupt, rc=%d\n",
2673				i, rc);
2674			return -ENOENT;
2675		}
2676		cq->irq_mask = pci_irq_get_affinity(pdev, i + BASE_VECTORS_V3_HW);
2677		if (!cq->irq_mask) {
2678			dev_err(dev, "could not get cq%d irq affinity!\n", i);
2679			return -ENOENT;
2680		}
2681	}
2682
2683	return 0;
2684}
2685
2686static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
2687{
2688	int rc;
2689
2690	rc = hw_init_v3_hw(hisi_hba);
2691	if (rc)
2692		return rc;
2693
2694	rc = interrupt_init_v3_hw(hisi_hba);
2695	if (rc)
2696		return rc;
2697
2698	return 0;
2699}
2700
2701static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no,
2702		struct sas_phy_linkrates *r)
2703{
2704	enum sas_linkrate max = r->maximum_linkrate;
2705	u32 prog_phy_link_rate = hisi_sas_phy_read32(hisi_hba, phy_no,
2706						     PROG_PHY_LINK_RATE);
2707
2708	prog_phy_link_rate &= ~CFG_PROG_PHY_LINK_RATE_MSK;
2709	prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
2710	hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
2711			     prog_phy_link_rate);
2712}
2713
2714static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba)
2715{
2716	struct pci_dev *pdev = hisi_hba->pci_dev;
2717	int i;
2718
2719	synchronize_irq(pci_irq_vector(pdev, IRQ_PHY_UP_DOWN_INDEX));
2720	synchronize_irq(pci_irq_vector(pdev, IRQ_CHL_INDEX));
2721	synchronize_irq(pci_irq_vector(pdev, IRQ_AXI_INDEX));
2722	for (i = 0; i < hisi_hba->queue_count; i++)
2723		hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
2724
2725	for (i = 0; i < hisi_hba->cq_nvecs; i++)
2726		synchronize_irq(pci_irq_vector(pdev, i + BASE_VECTORS_V3_HW));
2727
2728	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
2729	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
2730	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
2731	hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
2732
2733	for (i = 0; i < hisi_hba->n_phy; i++) {
2734		hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
2735		hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
2736		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1);
2737		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1);
2738		hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1);
2739	}
2740}
2741
2742static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba)
2743{
2744	return hisi_sas_read32(hisi_hba, PHY_STATE);
2745}
2746
2747static int disable_host_v3_hw(struct hisi_hba *hisi_hba)
2748{
2749	struct device *dev = hisi_hba->dev;
2750	u32 status, reg_val;
2751	int rc;
2752
2753	hisi_sas_sync_poll_cqs(hisi_hba);
2754	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
2755
2756	hisi_sas_stop_phys(hisi_hba);
2757
2758	mdelay(HISI_SAS_DELAY_FOR_PHY_DISABLE);
2759
2760	reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
2761				  AM_CTRL_GLOBAL);
2762	reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK;
2763	hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
2764			 AM_CTRL_GLOBAL, reg_val);
2765
2766	/* wait until bus idle */
2767	rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE +
2768					  AM_CURR_TRANS_RETURN, status,
2769					  status == 0x3, 10, 100);
2770	if (rc) {
2771		dev_err(dev, "axi bus is not idle, rc=%d\n", rc);
2772		return rc;
2773	}
2774
2775	return 0;
2776}
2777
2778static int soft_reset_v3_hw(struct hisi_hba *hisi_hba)
2779{
2780	struct device *dev = hisi_hba->dev;
2781	int rc;
2782
2783	interrupt_disable_v3_hw(hisi_hba);
2784	rc = disable_host_v3_hw(hisi_hba);
2785	if (rc) {
2786		dev_err(dev, "soft reset: disable host failed rc=%d\n", rc);
2787		return rc;
2788	}
2789
2790	hisi_sas_init_mem(hisi_hba);
2791
2792	return hw_init_v3_hw(hisi_hba);
2793}
2794
2795static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type,
2796			u8 reg_index, u8 reg_count, u8 *write_data)
2797{
2798	struct device *dev = hisi_hba->dev;
2799	u32 *data = (u32 *)write_data;
2800	int i;
2801
2802	switch (reg_type) {
2803	case SAS_GPIO_REG_TX:
2804		if ((reg_index + reg_count) > ((hisi_hba->n_phy + 3) / 4)) {
2805			dev_err(dev, "write gpio: invalid reg range[%d, %d]\n",
2806				reg_index, reg_index + reg_count - 1);
2807			return -EINVAL;
2808		}
2809
2810		for (i = 0; i < reg_count; i++)
2811			hisi_sas_write32(hisi_hba,
2812					 SAS_GPIO_TX_0_1 + (reg_index + i) * 4,
2813					 data[i]);
2814		break;
2815	default:
2816		dev_err(dev, "write gpio: unsupported or bad reg type %d\n",
2817			reg_type);
2818		return -EINVAL;
2819	}
2820
2821	return 0;
2822}
2823
2824static void wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba,
2825					     int delay_ms, int timeout_ms)
2826{
2827	struct device *dev = hisi_hba->dev;
2828	int entries, entries_old = 0, time;
2829
2830	for (time = 0; time < timeout_ms; time += delay_ms) {
2831		entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT);
2832		if (entries == entries_old)
2833			break;
2834
2835		entries_old = entries;
2836		msleep(delay_ms);
2837	}
2838
2839	if (time >= timeout_ms) {
2840		dev_dbg(dev, "Wait commands complete timeout!\n");
2841		return;
2842	}
2843
2844	dev_dbg(dev, "wait commands complete %dms\n", time);
2845}
2846
2847static ssize_t intr_conv_v3_hw_show(struct device *dev,
2848				    struct device_attribute *attr, char *buf)
2849{
2850	return scnprintf(buf, PAGE_SIZE, "%u\n", hisi_sas_intr_conv);
2851}
2852static DEVICE_ATTR_RO(intr_conv_v3_hw);
2853
2854static void config_intr_coal_v3_hw(struct hisi_hba *hisi_hba)
2855{
2856	/* config those registers between enable and disable PHYs */
2857	hisi_sas_stop_phys(hisi_hba);
2858	hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x3);
2859
2860	if (hisi_hba->intr_coal_ticks == 0 ||
2861	    hisi_hba->intr_coal_count == 0) {
2862		/* configure the interrupt coalescing timeout period 10us */
2863		hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0xa);
2864		/* configure the count of CQ entries 10 */
2865		hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0xa);
2866	} else {
2867		hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME,
2868				 hisi_hba->intr_coal_ticks);
2869		hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT,
2870				 hisi_hba->intr_coal_count);
2871	}
2872	phys_init_v3_hw(hisi_hba);
2873}
2874
2875static ssize_t intr_coal_ticks_v3_hw_show(struct device *dev,
2876					  struct device_attribute *attr,
2877					  char *buf)
2878{
2879	struct Scsi_Host *shost = class_to_shost(dev);
2880	struct hisi_hba *hisi_hba = shost_priv(shost);
2881
2882	return scnprintf(buf, PAGE_SIZE, "%u\n",
2883			 hisi_hba->intr_coal_ticks);
2884}
2885
2886static ssize_t intr_coal_ticks_v3_hw_store(struct device *dev,
2887					   struct device_attribute *attr,
2888					   const char *buf, size_t count)
2889{
2890	struct Scsi_Host *shost = class_to_shost(dev);
2891	struct hisi_hba *hisi_hba = shost_priv(shost);
2892	u32 intr_coal_ticks;
2893	int ret;
2894
2895	ret = kstrtou32(buf, DECIMALISM_FLAG, &intr_coal_ticks);
2896	if (ret) {
2897		dev_err(dev, "Input data of interrupt coalesce unmatch\n");
2898		return -EINVAL;
2899	}
2900
2901	if (intr_coal_ticks >= BIT(TICKS_BIT_INDEX)) {
2902		dev_err(dev, "intr_coal_ticks must be less than 2^24!\n");
2903		return -EINVAL;
2904	}
2905
2906	hisi_hba->intr_coal_ticks = intr_coal_ticks;
2907
2908	config_intr_coal_v3_hw(hisi_hba);
2909
2910	return count;
2911}
2912static DEVICE_ATTR_RW(intr_coal_ticks_v3_hw);
2913
2914static ssize_t intr_coal_count_v3_hw_show(struct device *dev,
2915					  struct device_attribute
2916					  *attr, char *buf)
2917{
2918	struct Scsi_Host *shost = class_to_shost(dev);
2919	struct hisi_hba *hisi_hba = shost_priv(shost);
2920
2921	return scnprintf(buf, PAGE_SIZE, "%u\n",
2922			 hisi_hba->intr_coal_count);
2923}
2924
2925static ssize_t intr_coal_count_v3_hw_store(struct device *dev,
2926		struct device_attribute
2927		*attr, const char *buf, size_t count)
2928{
2929	struct Scsi_Host *shost = class_to_shost(dev);
2930	struct hisi_hba *hisi_hba = shost_priv(shost);
2931	u32 intr_coal_count;
2932	int ret;
2933
2934	ret = kstrtou32(buf, DECIMALISM_FLAG, &intr_coal_count);
2935	if (ret) {
2936		dev_err(dev, "Input data of interrupt coalesce unmatch\n");
2937		return -EINVAL;
2938	}
2939
2940	if (intr_coal_count >= BIT(COUNT_BIT_INDEX)) {
2941		dev_err(dev, "intr_coal_count must be less than 2^8!\n");
2942		return -EINVAL;
2943	}
2944
2945	hisi_hba->intr_coal_count = intr_coal_count;
2946
2947	config_intr_coal_v3_hw(hisi_hba);
2948
2949	return count;
2950}
2951static DEVICE_ATTR_RW(intr_coal_count_v3_hw);
2952
2953static ssize_t iopoll_q_cnt_v3_hw_show(struct device *dev,
2954					  struct device_attribute
2955					  *attr, char *buf)
2956{
2957	struct Scsi_Host *shost = class_to_shost(dev);
2958	struct hisi_hba *hisi_hba = shost_priv(shost);
2959
2960	return scnprintf(buf, PAGE_SIZE, "%u\n",
2961			 hisi_hba->iopoll_q_cnt);
2962}
2963static DEVICE_ATTR_RO(iopoll_q_cnt_v3_hw);
2964
2965static int sdev_configure_v3_hw(struct scsi_device *sdev,
2966				struct queue_limits *lim)
2967{
2968	struct Scsi_Host *shost = dev_to_shost(&sdev->sdev_gendev);
2969	struct hisi_hba *hisi_hba = shost_priv(shost);
2970	int ret = hisi_sas_sdev_configure(sdev, lim);
2971	struct device *dev = hisi_hba->dev;
2972
2973	if (ret)
2974		return ret;
2975
2976	if (sdev->type == TYPE_ENCLOSURE)
2977		return 0;
2978
2979	if (!device_link_add(&sdev->sdev_gendev, dev,
2980			     DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE)) {
2981		if (pm_runtime_enabled(dev)) {
2982			dev_info(dev, "add device link failed, disable runtime PM for the host\n");
2983			pm_runtime_disable(dev);
2984		}
2985	}
2986
2987	return 0;
2988}
2989
2990static struct attribute *host_v3_hw_attrs[] = {
2991	&dev_attr_phy_event_threshold.attr,
2992	&dev_attr_intr_conv_v3_hw.attr,
2993	&dev_attr_intr_coal_ticks_v3_hw.attr,
2994	&dev_attr_intr_coal_count_v3_hw.attr,
2995	&dev_attr_iopoll_q_cnt_v3_hw.attr,
2996	NULL
2997};
2998
2999ATTRIBUTE_GROUPS(host_v3_hw);
3000
3001static const struct attribute_group *sdev_groups_v3_hw[] = {
3002	&sas_ata_sdev_attr_group,
3003	NULL
3004};
3005
3006#define HISI_SAS_DEBUGFS_REG(x) {#x, x}
3007
3008struct hisi_sas_debugfs_reg_lu {
3009	char *name;
3010	int off;
3011};
3012
3013struct hisi_sas_debugfs_reg {
3014	const struct hisi_sas_debugfs_reg_lu *lu;
3015	int count;
3016	int base_off;
3017};
3018
3019static const struct hisi_sas_debugfs_reg_lu debugfs_port_reg_lu[] = {
3020	HISI_SAS_DEBUGFS_REG(PHY_CFG),
3021	HISI_SAS_DEBUGFS_REG(HARD_PHY_LINKRATE),
3022	HISI_SAS_DEBUGFS_REG(PROG_PHY_LINK_RATE),
3023	HISI_SAS_DEBUGFS_REG(PHY_CTRL),
3024	HISI_SAS_DEBUGFS_REG(SL_CFG),
3025	HISI_SAS_DEBUGFS_REG(AIP_LIMIT),
3026	HISI_SAS_DEBUGFS_REG(SL_CONTROL),
3027	HISI_SAS_DEBUGFS_REG(RX_PRIMS_STATUS),
3028	HISI_SAS_DEBUGFS_REG(TX_ID_DWORD0),
3029	HISI_SAS_DEBUGFS_REG(TX_ID_DWORD1),
3030	HISI_SAS_DEBUGFS_REG(TX_ID_DWORD2),
3031	HISI_SAS_DEBUGFS_REG(TX_ID_DWORD3),
3032	HISI_SAS_DEBUGFS_REG(TX_ID_DWORD4),
3033	HISI_SAS_DEBUGFS_REG(TX_ID_DWORD5),
3034	HISI_SAS_DEBUGFS_REG(TX_ID_DWORD6),
3035	HISI_SAS_DEBUGFS_REG(TXID_AUTO),
3036	HISI_SAS_DEBUGFS_REG(RX_IDAF_DWORD0),
3037	HISI_SAS_DEBUGFS_REG(RXOP_CHECK_CFG_H),
3038	HISI_SAS_DEBUGFS_REG(STP_LINK_TIMER),
3039	HISI_SAS_DEBUGFS_REG(STP_LINK_TIMEOUT_STATE),
3040	HISI_SAS_DEBUGFS_REG(CON_CFG_DRIVER),
3041	HISI_SAS_DEBUGFS_REG(SAS_SSP_CON_TIMER_CFG),
3042	HISI_SAS_DEBUGFS_REG(SAS_SMP_CON_TIMER_CFG),
3043	HISI_SAS_DEBUGFS_REG(SAS_STP_CON_TIMER_CFG),
3044	HISI_SAS_DEBUGFS_REG(CHL_INT0),
3045	HISI_SAS_DEBUGFS_REG(CHL_INT1),
3046	HISI_SAS_DEBUGFS_REG(CHL_INT2),
3047	HISI_SAS_DEBUGFS_REG(CHL_INT0_MSK),
3048	HISI_SAS_DEBUGFS_REG(CHL_INT1_MSK),
3049	HISI_SAS_DEBUGFS_REG(CHL_INT2_MSK),
3050	HISI_SAS_DEBUGFS_REG(SAS_EC_INT_COAL_TIME),
3051	HISI_SAS_DEBUGFS_REG(CHL_INT_COAL_EN),
3052	HISI_SAS_DEBUGFS_REG(SAS_RX_TRAIN_TIMER),
3053	HISI_SAS_DEBUGFS_REG(PHY_CTRL_RDY_MSK),
3054	HISI_SAS_DEBUGFS_REG(PHYCTRL_NOT_RDY_MSK),
3055	HISI_SAS_DEBUGFS_REG(PHYCTRL_DWS_RESET_MSK),
3056	HISI_SAS_DEBUGFS_REG(PHYCTRL_PHY_ENA_MSK),
3057	HISI_SAS_DEBUGFS_REG(SL_RX_BCAST_CHK_MSK),
3058	HISI_SAS_DEBUGFS_REG(PHYCTRL_OOB_RESTART_MSK),
3059	HISI_SAS_DEBUGFS_REG(DMA_TX_STATUS),
3060	HISI_SAS_DEBUGFS_REG(DMA_RX_STATUS),
3061	HISI_SAS_DEBUGFS_REG(COARSETUNE_TIME),
3062	HISI_SAS_DEBUGFS_REG(ERR_CNT_DWS_LOST),
3063	HISI_SAS_DEBUGFS_REG(ERR_CNT_RESET_PROB),
3064	HISI_SAS_DEBUGFS_REG(ERR_CNT_INVLD_DW),
3065	HISI_SAS_DEBUGFS_REG(ERR_CNT_CODE_ERR),
3066	HISI_SAS_DEBUGFS_REG(ERR_CNT_DISP_ERR),
3067	{}
3068};
3069
3070static const struct hisi_sas_debugfs_reg debugfs_port_reg = {
3071	.lu = debugfs_port_reg_lu,
3072	.count = PORT_REG_LENGTH,
3073	.base_off = PORT_BASE,
3074};
3075
3076static const struct hisi_sas_debugfs_reg_lu debugfs_global_reg_lu[] = {
3077	HISI_SAS_DEBUGFS_REG(DLVRY_QUEUE_ENABLE),
3078	HISI_SAS_DEBUGFS_REG(PHY_CONTEXT),
3079	HISI_SAS_DEBUGFS_REG(PHY_STATE),
3080	HISI_SAS_DEBUGFS_REG(PHY_PORT_NUM_MA),
3081	HISI_SAS_DEBUGFS_REG(PHY_CONN_RATE),
3082	HISI_SAS_DEBUGFS_REG(ITCT_CLR),
3083	HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_LO),
3084	HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_HI),
3085	HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_LO),
3086	HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_HI),
3087	HISI_SAS_DEBUGFS_REG(CFG_MAX_TAG),
3088	HISI_SAS_DEBUGFS_REG(TRANS_LOCK_ICT_TIME),
3089	HISI_SAS_DEBUGFS_REG(HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL),
3090	HISI_SAS_DEBUGFS_REG(HGC_SAS_TXFAIL_RETRY_CTRL),
3091	HISI_SAS_DEBUGFS_REG(HGC_GET_ITV_TIME),
3092	HISI_SAS_DEBUGFS_REG(DEVICE_MSG_WORK_MODE),
3093	HISI_SAS_DEBUGFS_REG(OPENA_WT_CONTI_TIME),
3094	HISI_SAS_DEBUGFS_REG(I_T_NEXUS_LOSS_TIME),
3095	HISI_SAS_DEBUGFS_REG(MAX_CON_TIME_LIMIT_TIME),
3096	HISI_SAS_DEBUGFS_REG(BUS_INACTIVE_LIMIT_TIME),
3097	HISI_SAS_DEBUGFS_REG(REJECT_TO_OPEN_LIMIT_TIME),
3098	HISI_SAS_DEBUGFS_REG(CQ_INT_CONVERGE_EN),
3099	HISI_SAS_DEBUGFS_REG(CFG_AGING_TIME),
3100	HISI_SAS_DEBUGFS_REG(HGC_DFX_CFG2),
3101	HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_QUERY_IPTT),
3102	HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_IPTT_DONE),
3103	HISI_SAS_DEBUGFS_REG(HGC_IOMB_PROC1_STATUS),
3104	HISI_SAS_DEBUGFS_REG(CHNL_INT_STATUS),
3105	HISI_SAS_DEBUGFS_REG(HGC_AXI_FIFO_ERR_INFO),
3106	HISI_SAS_DEBUGFS_REG(INT_COAL_EN),
3107	HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_TIME),
3108	HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_CNT),
3109	HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_TIME),
3110	HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_CNT),
3111	HISI_SAS_DEBUGFS_REG(OQ_INT_SRC),
3112	HISI_SAS_DEBUGFS_REG(OQ_INT_SRC_MSK),
3113	HISI_SAS_DEBUGFS_REG(ENT_INT_SRC1),
3114	HISI_SAS_DEBUGFS_REG(ENT_INT_SRC2),
3115	HISI_SAS_DEBUGFS_REG(ENT_INT_SRC3),
3116	HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK1),
3117	HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK2),
3118	HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK3),
3119	HISI_SAS_DEBUGFS_REG(CHNL_PHYUPDOWN_INT_MSK),
3120	HISI_SAS_DEBUGFS_REG(CHNL_ENT_INT_MSK),
3121	HISI_SAS_DEBUGFS_REG(HGC_COM_INT_MSK),
3122	HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR),
3123	HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR_MSK),
3124	HISI_SAS_DEBUGFS_REG(HGC_ERR_STAT_EN),
3125	HISI_SAS_DEBUGFS_REG(CQE_SEND_CNT),
3126	HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_DEPTH),
3127	HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_WR_PTR),
3128	HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_RD_PTR),
3129	HISI_SAS_DEBUGFS_REG(HYPER_STREAM_ID_EN_CFG),
3130	HISI_SAS_DEBUGFS_REG(OQ0_INT_SRC_MSK),
3131	HISI_SAS_DEBUGFS_REG(COMPL_Q_0_DEPTH),
3132	HISI_SAS_DEBUGFS_REG(COMPL_Q_0_WR_PTR),
3133	HISI_SAS_DEBUGFS_REG(COMPL_Q_0_RD_PTR),
3134	HISI_SAS_DEBUGFS_REG(AWQOS_AWCACHE_CFG),
3135	HISI_SAS_DEBUGFS_REG(ARQOS_ARCACHE_CFG),
3136	HISI_SAS_DEBUGFS_REG(HILINK_ERR_DFX),
3137	HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_0),
3138	HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_1),
3139	HISI_SAS_DEBUGFS_REG(SAS_GPIO_TX_0_1),
3140	HISI_SAS_DEBUGFS_REG(SAS_CFG_DRIVE_VLD),
3141	{}
3142};
3143
3144static const struct hisi_sas_debugfs_reg debugfs_global_reg = {
3145	.lu = debugfs_global_reg_lu,
3146	.count = GLOBAL_REG_LENGTH,
3147};
3148
3149static const struct hisi_sas_debugfs_reg_lu debugfs_axi_reg_lu[] = {
3150	HISI_SAS_DEBUGFS_REG(AM_CFG_MAX_TRANS),
3151	HISI_SAS_DEBUGFS_REG(AM_CFG_SINGLE_PORT_MAX_TRANS),
3152	HISI_SAS_DEBUGFS_REG(AXI_CFG),
3153	HISI_SAS_DEBUGFS_REG(AM_ROB_ECC_ERR_ADDR),
3154	{}
3155};
3156
3157static const struct hisi_sas_debugfs_reg debugfs_axi_reg = {
3158	.lu = debugfs_axi_reg_lu,
3159	.count = AXI_REG_LENGTH,
3160	.base_off = AXI_MASTER_CFG_BASE,
3161};
3162
3163static const struct hisi_sas_debugfs_reg_lu debugfs_ras_reg_lu[] = {
3164	HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR0),
3165	HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR1),
3166	HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR0_MASK),
3167	HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR1_MASK),
3168	HISI_SAS_DEBUGFS_REG(CFG_SAS_RAS_INTR_MASK),
3169	HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR2),
3170	HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR2_MASK),
3171	{}
3172};
3173
3174static const struct hisi_sas_debugfs_reg debugfs_ras_reg = {
3175	.lu = debugfs_ras_reg_lu,
3176	.count = RAS_REG_LENGTH,
3177	.base_off = RAS_BASE,
3178};
3179
3180static void debugfs_snapshot_prepare_v3_hw(struct hisi_hba *hisi_hba)
3181{
3182	struct Scsi_Host *shost = hisi_hba->shost;
3183
3184	scsi_block_requests(shost);
3185	wait_cmds_complete_timeout_v3_hw(hisi_hba, WAIT_RETRY, WAIT_TMROUT);
3186
3187	set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
3188	hisi_sas_sync_cqs(hisi_hba);
3189	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
3190}
3191
3192static void debugfs_snapshot_restore_v3_hw(struct hisi_hba *hisi_hba)
3193{
3194	struct Scsi_Host *shost = hisi_hba->shost;
3195
3196	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
3197			 (u32)((1ULL << hisi_hba->queue_count) - 1));
3198
3199	clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
3200	scsi_unblock_requests(shost);
3201}
3202
3203static void read_iost_itct_cache_v3_hw(struct hisi_hba *hisi_hba,
3204				       enum hisi_sas_debugfs_cache_type type,
3205				       u32 *cache)
3206{
3207	u32 cache_dw_size = HISI_SAS_IOST_ITCT_CACHE_DW_SZ *
3208			    HISI_SAS_IOST_ITCT_CACHE_NUM;
3209	struct device *dev = hisi_hba->dev;
3210	u32 *buf = cache;
3211	u32 i, val;
3212
3213	hisi_sas_write32(hisi_hba, TAB_RD_TYPE, type);
3214
3215	for (i = 0; i < HISI_SAS_IOST_ITCT_CACHE_DW_SZ; i++) {
3216		val = hisi_sas_read32(hisi_hba, TAB_DFX);
3217		if (val == 0xffffffff)
3218			break;
3219	}
3220
3221	if (val != 0xffffffff) {
3222		dev_err(dev, "Issue occurred in reading IOST/ITCT cache!\n");
3223		return;
3224	}
3225
3226	memset(buf, 0, cache_dw_size * BYTE_TO_DW);
3227	buf[0] = val;
3228
3229	for (i = 1; i < cache_dw_size; i++)
3230		buf[i] = hisi_sas_read32(hisi_hba, TAB_DFX);
3231}
3232
3233static void hisi_sas_bist_test_prep_v3_hw(struct hisi_hba *hisi_hba)
3234{
3235	u32 reg_val;
3236	int phy_no = hisi_hba->debugfs_bist_phy_no;
3237	int i;
3238
3239	/* disable PHY */
3240	hisi_sas_phy_enable(hisi_hba, phy_no, 0);
3241
3242	/* update FFE */
3243	for (i = 0; i < FFE_CFG_MAX; i++)
3244		hisi_sas_phy_write32(hisi_hba, phy_no, TXDEEMPH_G1 + (i * 0x4),
3245				     hisi_hba->debugfs_bist_ffe[phy_no][i]);
3246
3247	/* disable ALOS */
3248	reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SERDES_CFG);
3249	reg_val |= CFG_ALOS_CHK_DISABLE_MSK;
3250	hisi_sas_phy_write32(hisi_hba, phy_no, SERDES_CFG, reg_val);
3251}
3252
3253static void hisi_sas_bist_test_restore_v3_hw(struct hisi_hba *hisi_hba)
3254{
3255	u32 reg_val;
3256	int phy_no = hisi_hba->debugfs_bist_phy_no;
3257
3258	/* disable loopback */
3259	reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL);
3260	reg_val &= ~(CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK |
3261		     CFG_BIST_TEST_MSK);
3262	hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL, reg_val);
3263
3264	/* enable ALOS */
3265	reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SERDES_CFG);
3266	reg_val &= ~CFG_ALOS_CHK_DISABLE_MSK;
3267	hisi_sas_phy_write32(hisi_hba, phy_no, SERDES_CFG, reg_val);
3268
3269	/* restore the linkrate */
3270	reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
3271	/* init OOB link rate as 1.5 Gbits */
3272	reg_val &= ~CFG_PROG_OOB_PHY_LINK_RATE_MSK;
3273	reg_val |= (SAS_LINK_RATE_1_5_GBPS << CFG_PROG_OOB_PHY_LINK_RATE_OFF);
3274	hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, reg_val);
3275
3276	/* enable PHY */
3277	hisi_sas_phy_enable(hisi_hba, phy_no, 1);
3278}
3279
3280#define SAS_PHY_BIST_CODE_INIT	0x1
3281#define SAS_PHY_BIST_CODE1_INIT	0X80
3282#define SAS_PHY_BIST_INIT_DELAY 100
3283#define SAS_PHY_BIST_LOOP_TEST_0 1
3284#define SAS_PHY_BIST_LOOP_TEST_1 2
3285static int debugfs_set_bist_v3_hw(struct hisi_hba *hisi_hba, bool enable)
3286{
3287	u32 reg_val, mode_tmp;
3288	u32 linkrate = hisi_hba->debugfs_bist_linkrate;
3289	u32 phy_no = hisi_hba->debugfs_bist_phy_no;
3290	u32 *ffe = hisi_hba->debugfs_bist_ffe[phy_no];
3291	u32 code_mode = hisi_hba->debugfs_bist_code_mode;
3292	u32 path_mode = hisi_hba->debugfs_bist_mode;
3293	u32 *fix_code = &hisi_hba->debugfs_bist_fixed_code[0];
3294	struct device *dev = hisi_hba->dev;
3295
3296	dev_info(dev, "BIST info:phy%d link_rate=%d code_mode=%d path_mode=%d ffe={0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x} fixed_code={0x%x, 0x%x}\n",
3297		 phy_no, linkrate, code_mode, path_mode,
3298		 ffe[FFE_SAS_1_5_GBPS], ffe[FFE_SAS_3_0_GBPS],
3299		 ffe[FFE_SAS_6_0_GBPS], ffe[FFE_SAS_12_0_GBPS],
3300		 ffe[FFE_SATA_1_5_GBPS], ffe[FFE_SATA_3_0_GBPS],
3301		 ffe[FFE_SATA_6_0_GBPS], fix_code[FIXED_CODE],
3302		 fix_code[FIXED_CODE_1]);
3303	mode_tmp = path_mode ? SAS_PHY_BIST_LOOP_TEST_1 :
3304			       SAS_PHY_BIST_LOOP_TEST_0;
3305	if (enable) {
3306		/* some preparations before bist test */
3307		hisi_sas_bist_test_prep_v3_hw(hisi_hba);
3308
3309		/* set linkrate of bit test */
3310		reg_val = hisi_sas_phy_read32(hisi_hba, phy_no,
3311					      PROG_PHY_LINK_RATE);
3312		reg_val &= ~CFG_PROG_OOB_PHY_LINK_RATE_MSK;
3313		reg_val |= (linkrate << CFG_PROG_OOB_PHY_LINK_RATE_OFF);
3314		hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
3315				     reg_val);
3316
3317		/* set code mode of bit test */
3318		reg_val = hisi_sas_phy_read32(hisi_hba, phy_no,
3319					      SAS_PHY_BIST_CTRL);
3320		reg_val &= ~(CFG_BIST_MODE_SEL_MSK | CFG_LOOP_TEST_MODE_MSK |
3321			     CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK |
3322			     CFG_BIST_TEST_MSK);
3323		reg_val |= ((code_mode << CFG_BIST_MODE_SEL_OFF) |
3324			    (mode_tmp << CFG_LOOP_TEST_MODE_OFF) |
3325			    CFG_BIST_TEST_MSK);
3326		hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL,
3327				     reg_val);
3328
3329		/* set the bist init value */
3330		if (code_mode == HISI_SAS_BIST_CODE_MODE_FIXED_DATA) {
3331			reg_val = hisi_hba->debugfs_bist_fixed_code[0];
3332			hisi_sas_phy_write32(hisi_hba, phy_no,
3333					     SAS_PHY_BIST_CODE, reg_val);
3334
3335			reg_val = hisi_hba->debugfs_bist_fixed_code[1];
3336			hisi_sas_phy_write32(hisi_hba, phy_no,
3337					     SAS_PHY_BIST_CODE1, reg_val);
3338		} else {
3339			hisi_sas_phy_write32(hisi_hba, phy_no,
3340					     SAS_PHY_BIST_CODE,
3341					     SAS_PHY_BIST_CODE_INIT);
3342			hisi_sas_phy_write32(hisi_hba, phy_no,
3343					     SAS_PHY_BIST_CODE1,
3344					     SAS_PHY_BIST_CODE1_INIT);
3345		}
3346
3347		mdelay(SAS_PHY_BIST_INIT_DELAY);
3348		reg_val |= (CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK);
3349		hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL,
3350				     reg_val);
3351
3352		/* clear error bit */
3353		mdelay(SAS_PHY_BIST_INIT_DELAY);
3354		hisi_sas_phy_read32(hisi_hba, phy_no, SAS_BIST_ERR_CNT);
3355	} else {
3356		/* disable bist test and recover it */
3357		hisi_hba->debugfs_bist_cnt += hisi_sas_phy_read32(hisi_hba,
3358				phy_no, SAS_BIST_ERR_CNT);
3359		hisi_sas_bist_test_restore_v3_hw(hisi_hba);
3360	}
3361
3362	return 0;
3363}
3364
3365static void hisi_sas_map_queues(struct Scsi_Host *shost)
3366{
3367	struct hisi_hba *hisi_hba = shost_priv(shost);
3368	struct blk_mq_queue_map *qmap;
3369	int i, qoff;
3370
3371	for (i = 0, qoff = 0; i < shost->nr_maps; i++) {
3372		qmap = &shost->tag_set.map[i];
3373		if (i == HCTX_TYPE_DEFAULT) {
3374			qmap->nr_queues = hisi_hba->cq_nvecs;
3375		} else if (i == HCTX_TYPE_POLL) {
3376			qmap->nr_queues = hisi_hba->iopoll_q_cnt;
3377		} else {
3378			qmap->nr_queues = 0;
3379			continue;
3380		}
3381
3382		/* At least one interrupt hardware queue */
3383		if (!qmap->nr_queues)
3384			WARN_ON(i == HCTX_TYPE_DEFAULT);
3385		qmap->queue_offset = qoff;
3386		if (i == HCTX_TYPE_POLL)
3387			blk_mq_map_queues(qmap);
3388		else
3389			blk_mq_map_hw_queues(qmap, hisi_hba->dev,
3390					     BASE_VECTORS_V3_HW);
3391		qoff += qmap->nr_queues;
3392	}
3393}
3394
3395static const struct scsi_host_template sht_v3_hw = {
3396	LIBSAS_SHT_BASE_NO_SLAVE_INIT
3397	.sdev_configure		= sdev_configure_v3_hw,
3398	.scan_finished		= hisi_sas_scan_finished,
3399	.scan_start		= hisi_sas_scan_start,
3400	.map_queues		= hisi_sas_map_queues,
3401	.sg_tablesize		= HISI_SAS_SGE_PAGE_CNT,
3402	.sg_prot_tablesize	= HISI_SAS_SGE_PAGE_CNT,
3403	.sdev_init		= hisi_sas_sdev_init,
3404	.shost_groups		= host_v3_hw_groups,
3405	.sdev_groups		= sdev_groups_v3_hw,
3406	.tag_alloc_policy_rr	= true,
3407	.host_reset		= hisi_sas_host_reset,
3408	.host_tagset		= 1,
3409	.mq_poll		= queue_complete_v3_hw,
3410};
3411
3412static const struct hisi_sas_hw hisi_sas_v3_hw = {
3413	.setup_itct = setup_itct_v3_hw,
3414	.get_wideport_bitmap = get_wideport_bitmap_v3_hw,
3415	.complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
3416	.clear_itct = clear_itct_v3_hw,
3417	.sl_notify_ssp = sl_notify_ssp_v3_hw,
3418	.prep_ssp = prep_ssp_v3_hw,
3419	.prep_smp = prep_smp_v3_hw,
3420	.prep_stp = prep_ata_v3_hw,
3421	.prep_abort = prep_abort_v3_hw,
3422	.start_delivery = start_delivery_v3_hw,
3423	.phys_init = phys_init_v3_hw,
3424	.phy_start = start_phy_v3_hw,
3425	.phy_disable = disable_phy_v3_hw,
3426	.phy_hard_reset = phy_hard_reset_v3_hw,
3427	.phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,
3428	.phy_set_linkrate = phy_set_linkrate_v3_hw,
3429	.dereg_device = dereg_device_v3_hw,
3430	.soft_reset = soft_reset_v3_hw,
3431	.get_phys_state = get_phys_state_v3_hw,
3432	.get_events = phy_get_events_v3_hw,
3433	.write_gpio = write_gpio_v3_hw,
3434	.wait_cmds_complete_timeout = wait_cmds_complete_timeout_v3_hw,
3435	.debugfs_snapshot_regs = debugfs_snapshot_regs_v3_hw,
3436};
3437
3438static int check_fw_info_v3_hw(struct hisi_hba *hisi_hba)
3439{
3440	struct device *dev = hisi_hba->dev;
3441
3442	if (hisi_hba->n_phy < 0 || hisi_hba->n_phy > 8) {
3443		dev_err(dev, "invalid phy number from FW\n");
3444		return -EINVAL;
3445	}
3446
3447	if (hisi_hba->queue_count < 0 || hisi_hba->queue_count > 16) {
3448		dev_err(dev, "invalid queue count from FW\n");
3449		return -EINVAL;
3450	}
3451
3452	return 0;
3453}
3454
3455static struct Scsi_Host *
3456hisi_sas_shost_alloc_pci(struct pci_dev *pdev)
3457{
3458	struct Scsi_Host *shost;
3459	struct hisi_hba *hisi_hba;
3460	struct device *dev = &pdev->dev;
3461
3462	shost = scsi_host_alloc(&sht_v3_hw, sizeof(*hisi_hba));
3463	if (!shost) {
3464		dev_err(dev, "shost alloc failed\n");
3465		return NULL;
3466	}
3467	hisi_hba = shost_priv(shost);
3468
3469	INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler);
3470	hisi_hba->hw = &hisi_sas_v3_hw;
3471	hisi_hba->pci_dev = pdev;
3472	hisi_hba->dev = dev;
3473	hisi_hba->shost = shost;
3474	SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
3475
3476	if (prot_mask & ~HISI_SAS_PROT_MASK)
3477		dev_err(dev, "unsupported protection mask 0x%x, using default (0x0)\n",
3478			prot_mask);
3479	else
3480		hisi_hba->prot_mask = prot_mask;
3481
3482	if (hisi_sas_get_fw_info(hisi_hba) < 0)
3483		goto err_out;
3484
3485	if (check_fw_info_v3_hw(hisi_hba) < 0)
3486		goto err_out;
3487
3488	if (experimental_iopoll_q_cnt < 0 ||
3489		experimental_iopoll_q_cnt >= hisi_hba->queue_count)
3490		dev_err(dev, "iopoll queue count %d cannot exceed or equal 16, using default 0\n",
3491			experimental_iopoll_q_cnt);
3492	else
3493		hisi_hba->iopoll_q_cnt = experimental_iopoll_q_cnt;
3494
3495	if (hisi_sas_alloc(hisi_hba)) {
3496		hisi_sas_free(hisi_hba);
3497		goto err_out;
3498	}
3499
3500	return shost;
3501err_out:
3502	scsi_host_put(shost);
3503	dev_err(dev, "shost alloc failed\n");
3504	return NULL;
3505}
3506
3507static void debugfs_snapshot_cq_reg_v3_hw(struct hisi_hba *hisi_hba)
3508{
3509	int queue_entry_size = hisi_hba->hw->complete_hdr_size;
3510	int dump_index = hisi_hba->debugfs_dump_index;
3511	int i;
3512
3513	for (i = 0; i < hisi_hba->queue_count; i++)
3514		memcpy(hisi_hba->debugfs_cq[dump_index][i].complete_hdr,
3515		       hisi_hba->complete_hdr[i],
3516		       HISI_SAS_QUEUE_SLOTS * queue_entry_size);
3517}
3518
3519static void debugfs_snapshot_dq_reg_v3_hw(struct hisi_hba *hisi_hba)
3520{
3521	int queue_entry_size = sizeof(struct hisi_sas_cmd_hdr);
3522	int dump_index = hisi_hba->debugfs_dump_index;
3523	int i;
3524
3525	for (i = 0; i < hisi_hba->queue_count; i++) {
3526		struct hisi_sas_cmd_hdr *debugfs_cmd_hdr, *cmd_hdr;
3527		int j;
3528
3529		debugfs_cmd_hdr = hisi_hba->debugfs_dq[dump_index][i].hdr;
3530		cmd_hdr = hisi_hba->cmd_hdr[i];
3531
3532		for (j = 0; j < HISI_SAS_QUEUE_SLOTS; j++)
3533			memcpy(&debugfs_cmd_hdr[j], &cmd_hdr[j],
3534			       queue_entry_size);
3535	}
3536}
3537
3538static void debugfs_snapshot_port_reg_v3_hw(struct hisi_hba *hisi_hba)
3539{
3540	int dump_index = hisi_hba->debugfs_dump_index;
3541	const struct hisi_sas_debugfs_reg *port = &debugfs_port_reg;
3542	int i, phy_cnt;
3543	u32 offset;
3544	u32 *databuf;
3545
3546	for (phy_cnt = 0; phy_cnt < hisi_hba->n_phy; phy_cnt++) {
3547		databuf = hisi_hba->debugfs_port_reg[dump_index][phy_cnt].data;
3548		for (i = 0; i < port->count; i++, databuf++) {
3549			offset = port->base_off + HISI_SAS_REG_MEM_SIZE * i;
3550			*databuf = hisi_sas_phy_read32(hisi_hba, phy_cnt,
3551						       offset);
3552		}
3553	}
3554}
3555
3556static void debugfs_snapshot_global_reg_v3_hw(struct hisi_hba *hisi_hba)
3557{
3558	int dump_index = hisi_hba->debugfs_dump_index;
3559	u32 *databuf = hisi_hba->debugfs_regs[dump_index][DEBUGFS_GLOBAL].data;
3560	int i;
3561
3562	for (i = 0; i < debugfs_global_reg.count; i++, databuf++)
3563		*databuf = hisi_sas_read32(hisi_hba,
3564					   HISI_SAS_REG_MEM_SIZE * i);
3565}
3566
3567static void debugfs_snapshot_axi_reg_v3_hw(struct hisi_hba *hisi_hba)
3568{
3569	int dump_index = hisi_hba->debugfs_dump_index;
3570	u32 *databuf = hisi_hba->debugfs_regs[dump_index][DEBUGFS_AXI].data;
3571	const struct hisi_sas_debugfs_reg *axi = &debugfs_axi_reg;
3572	int i;
3573
3574	for (i = 0; i < axi->count; i++, databuf++)
3575		*databuf = hisi_sas_read32(hisi_hba,
3576					   HISI_SAS_REG_MEM_SIZE * i +
3577					   axi->base_off);
3578}
3579
3580static void debugfs_snapshot_ras_reg_v3_hw(struct hisi_hba *hisi_hba)
3581{
3582	int dump_index = hisi_hba->debugfs_dump_index;
3583	u32 *databuf = hisi_hba->debugfs_regs[dump_index][DEBUGFS_RAS].data;
3584	const struct hisi_sas_debugfs_reg *ras = &debugfs_ras_reg;
3585	int i;
3586
3587	for (i = 0; i < ras->count; i++, databuf++)
3588		*databuf = hisi_sas_read32(hisi_hba,
3589					   HISI_SAS_REG_MEM_SIZE * i +
3590					   ras->base_off);
3591}
3592
3593static void debugfs_snapshot_itct_reg_v3_hw(struct hisi_hba *hisi_hba)
3594{
3595	int dump_index = hisi_hba->debugfs_dump_index;
3596	void *cachebuf = hisi_hba->debugfs_itct_cache[dump_index].cache;
3597	void *databuf = hisi_hba->debugfs_itct[dump_index].itct;
3598	struct hisi_sas_itct *itct;
3599	int i;
3600
3601	read_iost_itct_cache_v3_hw(hisi_hba, HISI_SAS_ITCT_CACHE, cachebuf);
3602
3603	itct = hisi_hba->itct;
3604
3605	for (i = 0; i < HISI_SAS_MAX_ITCT_ENTRIES; i++, itct++) {
3606		memcpy(databuf, itct, sizeof(struct hisi_sas_itct));
3607		databuf += sizeof(struct hisi_sas_itct);
3608	}
3609}
3610
3611static void debugfs_snapshot_iost_reg_v3_hw(struct hisi_hba *hisi_hba)
3612{
3613	int dump_index = hisi_hba->debugfs_dump_index;
3614	int max_command_entries = HISI_SAS_MAX_COMMANDS;
3615	void *cachebuf = hisi_hba->debugfs_iost_cache[dump_index].cache;
3616	void *databuf = hisi_hba->debugfs_iost[dump_index].iost;
3617	struct hisi_sas_iost *iost;
3618	int i;
3619
3620	read_iost_itct_cache_v3_hw(hisi_hba, HISI_SAS_IOST_CACHE, cachebuf);
3621
3622	iost = hisi_hba->iost;
3623
3624	for (i = 0; i < max_command_entries; i++, iost++) {
3625		memcpy(databuf, iost, sizeof(struct hisi_sas_iost));
3626		databuf += sizeof(struct hisi_sas_iost);
3627	}
3628}
3629
3630static const char *
3631debugfs_to_reg_name_v3_hw(int off, int base_off,
3632			  const struct hisi_sas_debugfs_reg_lu *lu)
3633{
3634	for (; lu->name; lu++) {
3635		if (off == lu->off - base_off)
3636			return lu->name;
3637	}
3638
3639	return NULL;
3640}
3641
3642static bool debugfs_dump_is_generated_v3_hw(void *p)
3643{
3644	return p ? true : false;
3645}
3646
3647static void debugfs_print_reg_v3_hw(u32 *regs_val, struct seq_file *s,
3648				    const struct hisi_sas_debugfs_reg *reg)
3649{
3650	int i;
3651
3652	for (i = 0; i < reg->count; i++) {
3653		int off = i * HISI_SAS_REG_MEM_SIZE;
3654		const char *name;
3655
3656		name = debugfs_to_reg_name_v3_hw(off, reg->base_off,
3657						 reg->lu);
3658		if (name)
3659			seq_printf(s, "0x%08x 0x%08x %s\n", off,
3660				   regs_val[i], name);
3661		else
3662			seq_printf(s, "0x%08x 0x%08x\n", off,
3663				   regs_val[i]);
3664	}
3665}
3666
3667static int debugfs_global_v3_hw_show(struct seq_file *s, void *p)
3668{
3669	struct hisi_sas_debugfs_regs *global = s->private;
3670
3671	if (!debugfs_dump_is_generated_v3_hw(global->data))
3672		return -EPERM;
3673
3674	debugfs_print_reg_v3_hw(global->data, s,
3675				&debugfs_global_reg);
3676
3677	return 0;
3678}
3679DEFINE_SHOW_ATTRIBUTE(debugfs_global_v3_hw);
3680
3681static int debugfs_axi_v3_hw_show(struct seq_file *s, void *p)
3682{
3683	struct hisi_sas_debugfs_regs *axi = s->private;
3684
3685	if (!debugfs_dump_is_generated_v3_hw(axi->data))
3686		return -EPERM;
3687
3688	debugfs_print_reg_v3_hw(axi->data, s,
3689				&debugfs_axi_reg);
3690
3691	return 0;
3692}
3693DEFINE_SHOW_ATTRIBUTE(debugfs_axi_v3_hw);
3694
3695static int debugfs_ras_v3_hw_show(struct seq_file *s, void *p)
3696{
3697	struct hisi_sas_debugfs_regs *ras = s->private;
3698
3699	if (!debugfs_dump_is_generated_v3_hw(ras->data))
3700		return -EPERM;
3701
3702	debugfs_print_reg_v3_hw(ras->data, s,
3703				&debugfs_ras_reg);
3704
3705	return 0;
3706}
3707DEFINE_SHOW_ATTRIBUTE(debugfs_ras_v3_hw);
3708
3709static int debugfs_port_v3_hw_show(struct seq_file *s, void *p)
3710{
3711	struct hisi_sas_debugfs_port *port = s->private;
3712	const struct hisi_sas_debugfs_reg *reg_port = &debugfs_port_reg;
3713
3714	if (!debugfs_dump_is_generated_v3_hw(port->data))
3715		return -EPERM;
3716
3717	debugfs_print_reg_v3_hw(port->data, s, reg_port);
3718
3719	return 0;
3720}
3721DEFINE_SHOW_ATTRIBUTE(debugfs_port_v3_hw);
3722
3723static void debugfs_show_row_64_v3_hw(struct seq_file *s, int index,
3724				      int sz, __le64 *ptr)
3725{
3726	int i;
3727
3728	/* completion header size not fixed per HW version */
3729	seq_printf(s, "index %04d:\n\t", index);
3730	for (i = 1; i <= sz / BYTE_TO_DDW; i++, ptr++) {
3731		seq_printf(s, " 0x%016llx", le64_to_cpu(*ptr));
3732		if (!(i % TWO_PARA_PER_LINE))
3733			seq_puts(s, "\n\t");
3734	}
3735
3736	seq_puts(s, "\n");
3737}
3738
3739static void debugfs_show_row_32_v3_hw(struct seq_file *s, int index,
3740				      int sz, __le32 *ptr)
3741{
3742	int i;
3743
3744	/* completion header size not fixed per HW version */
3745	seq_printf(s, "index %04d:\n\t", index);
3746	for (i = 1; i <= sz / BYTE_TO_DW; i++, ptr++) {
3747		seq_printf(s, " 0x%08x", le32_to_cpu(*ptr));
3748		if (!(i % FOUR_PARA_PER_LINE))
3749			seq_puts(s, "\n\t");
3750	}
3751	seq_puts(s, "\n");
3752}
3753
3754static void debugfs_cq_show_slot_v3_hw(struct seq_file *s, int slot,
3755				       struct hisi_sas_debugfs_cq *debugfs_cq)
3756{
3757	struct hisi_sas_cq *cq = debugfs_cq->cq;
3758	struct hisi_hba *hisi_hba = cq->hisi_hba;
3759	__le32 *complete_hdr = debugfs_cq->complete_hdr +
3760			       (hisi_hba->hw->complete_hdr_size * slot);
3761
3762	debugfs_show_row_32_v3_hw(s, slot,
3763				  hisi_hba->hw->complete_hdr_size,
3764				  complete_hdr);
3765}
3766
3767static int debugfs_cq_v3_hw_show(struct seq_file *s, void *p)
3768{
3769	struct hisi_sas_debugfs_cq *debugfs_cq = s->private;
3770	int slot;
3771
3772	if (!debugfs_dump_is_generated_v3_hw(debugfs_cq->complete_hdr))
3773		return -EPERM;
3774
3775	for (slot = 0; slot < HISI_SAS_QUEUE_SLOTS; slot++)
3776		debugfs_cq_show_slot_v3_hw(s, slot, debugfs_cq);
3777
3778	return 0;
3779}
3780DEFINE_SHOW_ATTRIBUTE(debugfs_cq_v3_hw);
3781
3782static void debugfs_dq_show_slot_v3_hw(struct seq_file *s, int slot,
3783				       void *dq_ptr)
3784{
3785	struct hisi_sas_debugfs_dq *debugfs_dq = dq_ptr;
3786	void *cmd_queue = debugfs_dq->hdr;
3787	__le32 *cmd_hdr = cmd_queue +
3788		sizeof(struct hisi_sas_cmd_hdr) * slot;
3789
3790	debugfs_show_row_32_v3_hw(s, slot, sizeof(struct hisi_sas_cmd_hdr),
3791				  cmd_hdr);
3792}
3793
3794static int debugfs_dq_v3_hw_show(struct seq_file *s, void *p)
3795{
3796	struct hisi_sas_debugfs_dq *debugfs_dq = s->private;
3797	int slot;
3798
3799	if (!debugfs_dump_is_generated_v3_hw(debugfs_dq->hdr))
3800		return -EPERM;
3801
3802	for (slot = 0; slot < HISI_SAS_QUEUE_SLOTS; slot++)
3803		debugfs_dq_show_slot_v3_hw(s, slot, s->private);
3804
3805	return 0;
3806}
3807DEFINE_SHOW_ATTRIBUTE(debugfs_dq_v3_hw);
3808
3809static int debugfs_iost_v3_hw_show(struct seq_file *s, void *p)
3810{
3811	struct hisi_sas_debugfs_iost *debugfs_iost = s->private;
3812	struct hisi_sas_iost *iost = debugfs_iost->iost;
3813	int i, max_command_entries = HISI_SAS_MAX_COMMANDS;
3814
3815	if (!debugfs_dump_is_generated_v3_hw(iost))
3816		return -EPERM;
3817
3818	for (i = 0; i < max_command_entries; i++, iost++) {
3819		__le64 *data = &iost->qw0;
3820
3821		debugfs_show_row_64_v3_hw(s, i, sizeof(*iost), data);
3822	}
3823
3824	return 0;
3825}
3826DEFINE_SHOW_ATTRIBUTE(debugfs_iost_v3_hw);
3827
3828static int debugfs_iost_cache_v3_hw_show(struct seq_file *s, void *p)
3829{
3830	struct hisi_sas_debugfs_iost_cache *debugfs_iost_cache = s->private;
3831	struct hisi_sas_iost_itct_cache *iost_cache =
3832						debugfs_iost_cache->cache;
3833	u32 cache_size = HISI_SAS_IOST_ITCT_CACHE_DW_SZ * BYTE_TO_DW;
3834	int i, tab_idx;
3835	__le64 *iost;
3836
3837	if (!debugfs_dump_is_generated_v3_hw(iost_cache))
3838		return -EPERM;
3839
3840	for (i = 0; i < HISI_SAS_IOST_ITCT_CACHE_NUM; i++, iost_cache++) {
3841		/*
3842		 * Data struct of IOST cache:
3843		 * Data[1]: BIT0~15: Table index
3844		 *	    Bit16:   Valid mask
3845		 * Data[2]~[9]: IOST table
3846		 */
3847		tab_idx = (iost_cache->data[1] & 0xffff);
3848		iost = (__le64 *)iost_cache;
3849
3850		debugfs_show_row_64_v3_hw(s, tab_idx, cache_size, iost);
3851	}
3852
3853	return 0;
3854}
3855DEFINE_SHOW_ATTRIBUTE(debugfs_iost_cache_v3_hw);
3856
3857static int debugfs_itct_v3_hw_show(struct seq_file *s, void *p)
3858{
3859	int i;
3860	struct hisi_sas_debugfs_itct *debugfs_itct = s->private;
3861	struct hisi_sas_itct *itct = debugfs_itct->itct;
3862
3863	if (!debugfs_dump_is_generated_v3_hw(itct))
3864		return -EPERM;
3865
3866	for (i = 0; i < HISI_SAS_MAX_ITCT_ENTRIES; i++, itct++) {
3867		__le64 *data = &itct->qw0;
3868
3869		debugfs_show_row_64_v3_hw(s, i, sizeof(*itct), data);
3870	}
3871
3872	return 0;
3873}
3874DEFINE_SHOW_ATTRIBUTE(debugfs_itct_v3_hw);
3875
3876static int debugfs_itct_cache_v3_hw_show(struct seq_file *s, void *p)
3877{
3878	struct hisi_sas_debugfs_itct_cache *debugfs_itct_cache = s->private;
3879	struct hisi_sas_iost_itct_cache *itct_cache =
3880						debugfs_itct_cache->cache;
3881	u32 cache_size = HISI_SAS_IOST_ITCT_CACHE_DW_SZ * BYTE_TO_DW;
3882	int i, tab_idx;
3883	__le64 *itct;
3884
3885	if (!debugfs_dump_is_generated_v3_hw(itct_cache))
3886		return -EPERM;
3887
3888	for (i = 0; i < HISI_SAS_IOST_ITCT_CACHE_NUM; i++, itct_cache++) {
3889		/*
3890		 * Data struct of ITCT cache:
3891		 * Data[1]: BIT0~15: Table index
3892		 *	    Bit16:   Valid mask
3893		 * Data[2]~[9]: ITCT table
3894		 */
3895		tab_idx = itct_cache->data[1] & 0xffff;
3896		itct = (__le64 *)itct_cache;
3897
3898		debugfs_show_row_64_v3_hw(s, tab_idx, cache_size, itct);
3899	}
3900
3901	return 0;
3902}
3903DEFINE_SHOW_ATTRIBUTE(debugfs_itct_cache_v3_hw);
3904
3905static void debugfs_create_files_v3_hw(struct hisi_hba *hisi_hba, int index)
3906{
3907	u64 *debugfs_timestamp;
3908	struct dentry *dump_dentry;
3909	struct dentry *dentry;
3910	char name[NAME_BUF_SIZE];
3911	int p;
3912	int c;
3913	int d;
3914
3915	snprintf(name, NAME_BUF_SIZE, "%d", index);
3916
3917	dump_dentry = debugfs_create_dir(name, hisi_hba->debugfs_dump_dentry);
3918
3919	debugfs_timestamp = &hisi_hba->debugfs_timestamp[index];
3920
3921	debugfs_create_u64("timestamp", 0400, dump_dentry,
3922			   debugfs_timestamp);
3923
3924	debugfs_create_file("global", 0400, dump_dentry,
3925			    &hisi_hba->debugfs_regs[index][DEBUGFS_GLOBAL],
3926			    &debugfs_global_v3_hw_fops);
3927
3928	/* Create port dir and files */
3929	dentry = debugfs_create_dir("port", dump_dentry);
3930	for (p = 0; p < hisi_hba->n_phy; p++) {
3931		snprintf(name, NAME_BUF_SIZE, "%d", p);
3932
3933		debugfs_create_file(name, 0400, dentry,
3934				    &hisi_hba->debugfs_port_reg[index][p],
3935				    &debugfs_port_v3_hw_fops);
3936	}
3937
3938	/* Create CQ dir and files */
3939	dentry = debugfs_create_dir("cq", dump_dentry);
3940	for (c = 0; c < hisi_hba->queue_count; c++) {
3941		snprintf(name, NAME_BUF_SIZE, "%d", c);
3942
3943		debugfs_create_file(name, 0400, dentry,
3944				    &hisi_hba->debugfs_cq[index][c],
3945				    &debugfs_cq_v3_hw_fops);
3946	}
3947
3948	/* Create DQ dir and files */
3949	dentry = debugfs_create_dir("dq", dump_dentry);
3950	for (d = 0; d < hisi_hba->queue_count; d++) {
3951		snprintf(name, NAME_BUF_SIZE, "%d", d);
3952
3953		debugfs_create_file(name, 0400, dentry,
3954				    &hisi_hba->debugfs_dq[index][d],
3955				    &debugfs_dq_v3_hw_fops);
3956	}
3957
3958	debugfs_create_file("iost", 0400, dump_dentry,
3959			    &hisi_hba->debugfs_iost[index],
3960			    &debugfs_iost_v3_hw_fops);
3961
3962	debugfs_create_file("iost_cache", 0400, dump_dentry,
3963			    &hisi_hba->debugfs_iost_cache[index],
3964			    &debugfs_iost_cache_v3_hw_fops);
3965
3966	debugfs_create_file("itct", 0400, dump_dentry,
3967			    &hisi_hba->debugfs_itct[index],
3968			    &debugfs_itct_v3_hw_fops);
3969
3970	debugfs_create_file("itct_cache", 0400, dump_dentry,
3971			    &hisi_hba->debugfs_itct_cache[index],
3972			    &debugfs_itct_cache_v3_hw_fops);
3973
3974	debugfs_create_file("axi", 0400, dump_dentry,
3975			    &hisi_hba->debugfs_regs[index][DEBUGFS_AXI],
3976			    &debugfs_axi_v3_hw_fops);
3977
3978	debugfs_create_file("ras", 0400, dump_dentry,
3979			    &hisi_hba->debugfs_regs[index][DEBUGFS_RAS],
3980			    &debugfs_ras_v3_hw_fops);
3981}
3982
3983static ssize_t debugfs_trigger_dump_v3_hw_write(struct file *file,
3984						const char __user *user_buf,
3985						size_t count, loff_t *ppos)
3986{
3987	struct hisi_hba *hisi_hba = file->f_inode->i_private;
3988	char buf[DUMP_BUF_SIZE];
3989
3990	if (count > DUMP_BUF_SIZE)
3991		return -EFAULT;
3992
3993	if (copy_from_user(buf, user_buf, count))
3994		return -EFAULT;
3995
3996	if (buf[0] != '1')
3997		return -EFAULT;
3998
3999	down(&hisi_hba->sem);
4000	if (debugfs_snapshot_regs_v3_hw(hisi_hba)) {
4001		up(&hisi_hba->sem);
4002		return -EFAULT;
4003	}
4004	up(&hisi_hba->sem);
4005
4006	return count;
4007}
4008
4009static const struct file_operations debugfs_trigger_dump_v3_hw_fops = {
4010	.write = &debugfs_trigger_dump_v3_hw_write,
4011	.owner = THIS_MODULE,
4012};
4013
4014enum {
4015	HISI_SAS_BIST_LOOPBACK_MODE_DIGITAL = 0,
4016	HISI_SAS_BIST_LOOPBACK_MODE_SERDES,
4017	HISI_SAS_BIST_LOOPBACK_MODE_REMOTE,
4018};
4019
4020static const struct {
4021	int		value;
4022	char		*name;
4023} debugfs_loop_linkrate_v3_hw[] = {
4024	{ SAS_LINK_RATE_1_5_GBPS, "1.5 Gbit" },
4025	{ SAS_LINK_RATE_3_0_GBPS, "3.0 Gbit" },
4026	{ SAS_LINK_RATE_6_0_GBPS, "6.0 Gbit" },
4027	{ SAS_LINK_RATE_12_0_GBPS, "12.0 Gbit" },
4028};
4029
4030static int debugfs_bist_linkrate_v3_hw_show(struct seq_file *s, void *p)
4031{
4032	struct hisi_hba *hisi_hba = s->private;
4033	int i;
4034
4035	for (i = 0; i < ARRAY_SIZE(debugfs_loop_linkrate_v3_hw); i++) {
4036		int match = (hisi_hba->debugfs_bist_linkrate ==
4037			     debugfs_loop_linkrate_v3_hw[i].value);
4038
4039		seq_printf(s, "%s%s%s ", match ? "[" : "",
4040			   debugfs_loop_linkrate_v3_hw[i].name,
4041			   match ? "]" : "");
4042	}
4043	seq_puts(s, "\n");
4044
4045	return 0;
4046}
4047
4048static ssize_t debugfs_bist_linkrate_v3_hw_write(struct file *filp,
4049						 const char __user *buf,
4050						 size_t count, loff_t *ppos)
4051{
4052	struct seq_file *m = filp->private_data;
4053	struct hisi_hba *hisi_hba = m->private;
4054	char kbuf[BIST_BUF_SIZE] = {}, *pkbuf;
4055	bool found = false;
4056	int i;
4057
4058	if (hisi_hba->debugfs_bist_enable)
4059		return -EPERM;
4060
4061	if (count >= sizeof(kbuf))
4062		return -EOVERFLOW;
4063
4064	if (copy_from_user(kbuf, buf, count))
4065		return -EINVAL;
4066
4067	pkbuf = strstrip(kbuf);
4068
4069	for (i = 0; i < ARRAY_SIZE(debugfs_loop_linkrate_v3_hw); i++) {
4070		if (!strncmp(debugfs_loop_linkrate_v3_hw[i].name,
4071			     pkbuf, BIST_BUF_SIZE)) {
4072			hisi_hba->debugfs_bist_linkrate =
4073				debugfs_loop_linkrate_v3_hw[i].value;
4074			found = true;
4075			break;
4076		}
4077	}
4078
4079	if (!found)
4080		return -EINVAL;
4081
4082	return count;
4083}
4084DEFINE_SHOW_STORE_ATTRIBUTE(debugfs_bist_linkrate_v3_hw);
4085
4086static const struct {
4087	int		value;
4088	char		*name;
4089} debugfs_loop_code_mode_v3_hw[] = {
4090	{ HISI_SAS_BIST_CODE_MODE_PRBS7, "PRBS7" },
4091	{ HISI_SAS_BIST_CODE_MODE_PRBS23, "PRBS23" },
4092	{ HISI_SAS_BIST_CODE_MODE_PRBS31, "PRBS31" },
4093	{ HISI_SAS_BIST_CODE_MODE_JTPAT, "JTPAT" },
4094	{ HISI_SAS_BIST_CODE_MODE_CJTPAT, "CJTPAT" },
4095	{ HISI_SAS_BIST_CODE_MODE_SCRAMBED_0, "SCRAMBED_0" },
4096	{ HISI_SAS_BIST_CODE_MODE_TRAIN, "TRAIN" },
4097	{ HISI_SAS_BIST_CODE_MODE_TRAIN_DONE, "TRAIN_DONE" },
4098	{ HISI_SAS_BIST_CODE_MODE_HFTP, "HFTP" },
4099	{ HISI_SAS_BIST_CODE_MODE_MFTP, "MFTP" },
4100	{ HISI_SAS_BIST_CODE_MODE_LFTP, "LFTP" },
4101	{ HISI_SAS_BIST_CODE_MODE_FIXED_DATA, "FIXED_DATA" },
4102};
4103
4104static int debugfs_bist_code_mode_v3_hw_show(struct seq_file *s, void *p)
4105{
4106	struct hisi_hba *hisi_hba = s->private;
4107	int i;
4108
4109	for (i = 0; i < ARRAY_SIZE(debugfs_loop_code_mode_v3_hw); i++) {
4110		int match = (hisi_hba->debugfs_bist_code_mode ==
4111			     debugfs_loop_code_mode_v3_hw[i].value);
4112
4113		seq_printf(s, "%s%s%s ", match ? "[" : "",
4114			   debugfs_loop_code_mode_v3_hw[i].name,
4115			   match ? "]" : "");
4116	}
4117	seq_puts(s, "\n");
4118
4119	return 0;
4120}
4121
4122static ssize_t debugfs_bist_code_mode_v3_hw_write(struct file *filp,
4123						  const char __user *buf,
4124						  size_t count,
4125						  loff_t *ppos)
4126{
4127	struct seq_file *m = filp->private_data;
4128	struct hisi_hba *hisi_hba = m->private;
4129	char kbuf[BIST_BUF_SIZE] = {}, *pkbuf;
4130	bool found = false;
4131	int i;
4132
4133	if (hisi_hba->debugfs_bist_enable)
4134		return -EPERM;
4135
4136	if (count >= sizeof(kbuf))
4137		return -EINVAL;
4138
4139	if (copy_from_user(kbuf, buf, count))
4140		return -EOVERFLOW;
4141
4142	pkbuf = strstrip(kbuf);
4143
4144	for (i = 0; i < ARRAY_SIZE(debugfs_loop_code_mode_v3_hw); i++) {
4145		if (!strncmp(debugfs_loop_code_mode_v3_hw[i].name,
4146			     pkbuf, BIST_BUF_SIZE)) {
4147			hisi_hba->debugfs_bist_code_mode =
4148				debugfs_loop_code_mode_v3_hw[i].value;
4149			found = true;
4150			break;
4151		}
4152	}
4153
4154	if (!found)
4155		return -EINVAL;
4156
4157	return count;
4158}
4159DEFINE_SHOW_STORE_ATTRIBUTE(debugfs_bist_code_mode_v3_hw);
4160
4161static ssize_t debugfs_bist_phy_v3_hw_write(struct file *filp,
4162					    const char __user *buf,
4163					    size_t count, loff_t *ppos)
4164{
4165	struct seq_file *m = filp->private_data;
4166	struct hisi_hba *hisi_hba = m->private;
4167	unsigned int phy_no;
4168	int val;
4169
4170	if (hisi_hba->debugfs_bist_enable)
4171		return -EPERM;
4172
4173	val = kstrtouint_from_user(buf, count, 0, &phy_no);
4174	if (val)
4175		return val;
4176
4177	if (phy_no >= hisi_hba->n_phy)
4178		return -EINVAL;
4179
4180	hisi_hba->debugfs_bist_phy_no = phy_no;
4181
4182	return count;
4183}
4184
4185static int debugfs_bist_phy_v3_hw_show(struct seq_file *s, void *p)
4186{
4187	struct hisi_hba *hisi_hba = s->private;
4188
4189	seq_printf(s, "%d\n", hisi_hba->debugfs_bist_phy_no);
4190
4191	return 0;
4192}
4193DEFINE_SHOW_STORE_ATTRIBUTE(debugfs_bist_phy_v3_hw);
4194
4195static ssize_t debugfs_bist_cnt_v3_hw_write(struct file *filp,
4196					const char __user *buf,
4197					size_t count, loff_t *ppos)
4198{
4199	struct seq_file *m = filp->private_data;
4200	struct hisi_hba *hisi_hba = m->private;
4201	unsigned int cnt;
4202	int val;
4203
4204	if (hisi_hba->debugfs_bist_enable)
4205		return -EPERM;
4206
4207	val = kstrtouint_from_user(buf, count, 0, &cnt);
4208	if (val)
4209		return val;
4210
4211	if (cnt)
4212		return -EINVAL;
4213
4214	hisi_hba->debugfs_bist_cnt = 0;
4215	return count;
4216}
4217
4218static int debugfs_bist_cnt_v3_hw_show(struct seq_file *s, void *p)
4219{
4220	struct hisi_hba *hisi_hba = s->private;
4221
4222	seq_printf(s, "%u\n", hisi_hba->debugfs_bist_cnt);
4223
4224	return 0;
4225}
4226DEFINE_SHOW_STORE_ATTRIBUTE(debugfs_bist_cnt_v3_hw);
4227
4228static const struct {
4229	int		value;
4230	char		*name;
4231} debugfs_loop_modes_v3_hw[] = {
4232	{ HISI_SAS_BIST_LOOPBACK_MODE_DIGITAL, "digital" },
4233	{ HISI_SAS_BIST_LOOPBACK_MODE_SERDES, "serdes" },
4234	{ HISI_SAS_BIST_LOOPBACK_MODE_REMOTE, "remote" },
4235};
4236
4237static int debugfs_bist_mode_v3_hw_show(struct seq_file *s, void *p)
4238{
4239	struct hisi_hba *hisi_hba = s->private;
4240	int i;
4241
4242	for (i = 0; i < ARRAY_SIZE(debugfs_loop_modes_v3_hw); i++) {
4243		int match = (hisi_hba->debugfs_bist_mode ==
4244			     debugfs_loop_modes_v3_hw[i].value);
4245
4246		seq_printf(s, "%s%s%s ", match ? "[" : "",
4247			   debugfs_loop_modes_v3_hw[i].name,
4248			   match ? "]" : "");
4249	}
4250	seq_puts(s, "\n");
4251
4252	return 0;
4253}
4254
4255static ssize_t debugfs_bist_mode_v3_hw_write(struct file *filp,
4256					     const char __user *buf,
4257					     size_t count, loff_t *ppos)
4258{
4259	struct seq_file *m = filp->private_data;
4260	struct hisi_hba *hisi_hba = m->private;
4261	char kbuf[BIST_BUF_SIZE] = {}, *pkbuf;
4262	bool found = false;
4263	int i;
4264
4265	if (hisi_hba->debugfs_bist_enable)
4266		return -EPERM;
4267
4268	if (count >= sizeof(kbuf))
4269		return -EINVAL;
4270
4271	if (copy_from_user(kbuf, buf, count))
4272		return -EOVERFLOW;
4273
4274	pkbuf = strstrip(kbuf);
4275
4276	for (i = 0; i < ARRAY_SIZE(debugfs_loop_modes_v3_hw); i++) {
4277		if (!strncmp(debugfs_loop_modes_v3_hw[i].name, pkbuf,
4278			     BIST_BUF_SIZE)) {
4279			hisi_hba->debugfs_bist_mode =
4280				debugfs_loop_modes_v3_hw[i].value;
4281			found = true;
4282			break;
4283		}
4284	}
4285
4286	if (!found)
4287		return -EINVAL;
4288
4289	return count;
4290}
4291DEFINE_SHOW_STORE_ATTRIBUTE(debugfs_bist_mode_v3_hw);
4292
4293static ssize_t debugfs_bist_enable_v3_hw_write(struct file *filp,
4294					       const char __user *buf,
4295					       size_t count, loff_t *ppos)
4296{
4297	struct seq_file *m = filp->private_data;
4298	struct hisi_hba *hisi_hba = m->private;
4299	unsigned int enable;
4300	int val;
4301
4302	val = kstrtouint_from_user(buf, count, 0, &enable);
4303	if (val)
4304		return val;
4305
4306	if (enable > 1)
4307		return -EINVAL;
4308
4309	if (enable == hisi_hba->debugfs_bist_enable)
4310		return count;
4311
4312	val = debugfs_set_bist_v3_hw(hisi_hba, enable);
4313	if (val < 0)
4314		return val;
4315
4316	hisi_hba->debugfs_bist_enable = enable;
4317
4318	return count;
4319}
4320
4321static int debugfs_bist_enable_v3_hw_show(struct seq_file *s, void *p)
4322{
4323	struct hisi_hba *hisi_hba = s->private;
4324
4325	seq_printf(s, "%d\n", hisi_hba->debugfs_bist_enable);
4326
4327	return 0;
4328}
4329DEFINE_SHOW_STORE_ATTRIBUTE(debugfs_bist_enable_v3_hw);
4330
4331static const struct {
4332	char *name;
4333} debugfs_ffe_name_v3_hw[FFE_CFG_MAX] = {
4334	{ "SAS_1_5_GBPS" },
4335	{ "SAS_3_0_GBPS" },
4336	{ "SAS_6_0_GBPS" },
4337	{ "SAS_12_0_GBPS" },
4338	{ "FFE_RESV" },
4339	{ "SATA_1_5_GBPS" },
4340	{ "SATA_3_0_GBPS" },
4341	{ "SATA_6_0_GBPS" },
4342};
4343
4344static ssize_t debugfs_v3_hw_write(struct file *filp,
4345				   const char __user *buf,
4346				   size_t count, loff_t *ppos)
4347{
4348	struct seq_file *m = filp->private_data;
4349	u32 *val = m->private;
4350	int res;
4351
4352	res = kstrtouint_from_user(buf, count, 0, val);
4353	if (res)
4354		return res;
4355
4356	return count;
4357}
4358
4359static int debugfs_v3_hw_show(struct seq_file *s, void *p)
4360{
4361	u32 *val = s->private;
4362
4363	seq_printf(s, "0x%x\n", *val);
4364
4365	return 0;
4366}
4367DEFINE_SHOW_STORE_ATTRIBUTE(debugfs_v3_hw);
4368
4369static ssize_t debugfs_phy_down_cnt_v3_hw_write(struct file *filp,
4370						const char __user *buf,
4371						size_t count, loff_t *ppos)
4372{
4373	struct seq_file *s = filp->private_data;
4374	struct hisi_sas_phy *phy = s->private;
4375	unsigned int set_val;
4376	int res;
4377
4378	res = kstrtouint_from_user(buf, count, 0, &set_val);
4379	if (res)
4380		return res;
4381
4382	if (set_val > 0)
4383		return -EINVAL;
4384
4385	atomic_set(&phy->down_cnt, 0);
4386
4387	return count;
4388}
4389
4390static int debugfs_phy_down_cnt_v3_hw_show(struct seq_file *s, void *p)
4391{
4392	struct hisi_sas_phy *phy = s->private;
4393
4394	seq_printf(s, "%d\n", atomic_read(&phy->down_cnt));
4395
4396	return 0;
4397}
4398DEFINE_SHOW_STORE_ATTRIBUTE(debugfs_phy_down_cnt_v3_hw);
4399
4400enum fifo_dump_mode_v3_hw {
4401	FIFO_DUMP_FORVER =		(1U << 0),
4402	FIFO_DUMP_AFTER_TRIGGER =	(1U << 1),
4403	FIFO_DUMP_UNTILL_TRIGGER =	(1U << 2),
4404};
4405
4406enum fifo_trigger_mode_v3_hw {
4407	FIFO_TRIGGER_EDGE =		(1U << 0),
4408	FIFO_TRIGGER_SAME_LEVEL =	(1U << 1),
4409	FIFO_TRIGGER_DIFF_LEVEL =	(1U << 2),
4410};
4411
4412static int debugfs_is_fifo_config_valid_v3_hw(struct hisi_sas_phy *phy)
4413{
4414	struct hisi_hba *hisi_hba = phy->hisi_hba;
4415
4416	if (phy->fifo.signal_sel > 0xf) {
4417		dev_info(hisi_hba->dev, "Invalid signal select: %u\n",
4418			 phy->fifo.signal_sel);
4419		return -EINVAL;
4420	}
4421
4422	switch (phy->fifo.dump_mode) {
4423	case FIFO_DUMP_FORVER:
4424	case FIFO_DUMP_AFTER_TRIGGER:
4425	case FIFO_DUMP_UNTILL_TRIGGER:
4426		break;
4427	default:
4428		dev_info(hisi_hba->dev, "Invalid dump mode: %u\n",
4429			 phy->fifo.dump_mode);
4430		return -EINVAL;
4431	}
4432
4433	/* when FIFO_DUMP_FORVER, no need to check trigger_mode */
4434	if (phy->fifo.dump_mode == FIFO_DUMP_FORVER)
4435		return 0;
4436
4437	switch (phy->fifo.trigger_mode) {
4438	case FIFO_TRIGGER_EDGE:
4439	case FIFO_TRIGGER_SAME_LEVEL:
4440	case FIFO_TRIGGER_DIFF_LEVEL:
4441		break;
4442	default:
4443		dev_info(hisi_hba->dev, "Invalid trigger mode: %u\n",
4444			 phy->fifo.trigger_mode);
4445		return -EINVAL;
4446	}
4447	return 0;
4448}
4449
4450static int debugfs_update_fifo_config_v3_hw(struct hisi_sas_phy *phy)
4451{
4452	u32 trigger_mode = phy->fifo.trigger_mode;
4453	u32 signal_sel = phy->fifo.signal_sel;
4454	u32 dump_mode = phy->fifo.dump_mode;
4455	struct hisi_hba *hisi_hba = phy->hisi_hba;
4456	int phy_no = phy->sas_phy.id;
4457	u32 reg_val;
4458	int res;
4459
4460	/* Check the validity of trace FIFO configuration */
4461	res = debugfs_is_fifo_config_valid_v3_hw(phy);
4462	if (res)
4463		return res;
4464
4465	reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4466	/* Disable trace FIFO before update configuration */
4467	reg_val |= DFX_FIFO_CTRL_DUMP_DISABLE_MSK;
4468
4469	/* Update trace FIFO configuration */
4470	reg_val &= ~(DFX_FIFO_CTRL_DUMP_MODE_MSK |
4471		     DFX_FIFO_CTRL_SIGNAL_SEL_MSK |
4472		     DFX_FIFO_CTRL_TRIGGER_MODE_MSK);
4473
4474	reg_val |= ((trigger_mode << DFX_FIFO_CTRL_TRIGGER_MODE_OFF) |
4475		    (dump_mode << DFX_FIFO_CTRL_DUMP_MODE_OFF) |
4476		    (signal_sel << DFX_FIFO_CTRL_SIGNAL_SEL_OFF));
4477	hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, reg_val);
4478
4479	hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_DUMP_MSK,
4480			     phy->fifo.dump_msk);
4481
4482	hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_TRIGGER,
4483			     phy->fifo.trigger);
4484
4485	hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_TRIGGER_MSK,
4486			     phy->fifo.trigger_msk);
4487
4488	/* Enable trace FIFO after updated configuration */
4489	reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4490	reg_val &= ~DFX_FIFO_CTRL_DUMP_DISABLE_MSK;
4491	hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, reg_val);
4492
4493	return 0;
4494}
4495
4496static ssize_t debugfs_fifo_update_cfg_v3_hw_write(struct file *filp,
4497						   const char __user *buf,
4498						   size_t count, loff_t *ppos)
4499{
4500	struct hisi_sas_phy *phy = filp->private_data;
4501	bool update;
4502	int val;
4503
4504	val = kstrtobool_from_user(buf, count, &update);
4505	if (val)
4506		return val;
4507
4508	if (update != 1)
4509		return -EINVAL;
4510
4511	val = debugfs_update_fifo_config_v3_hw(phy);
4512	if (val)
4513		return val;
4514
4515	return count;
4516}
4517
4518static const struct file_operations debugfs_fifo_update_cfg_v3_hw_fops = {
4519	.open = simple_open,
4520	.write = debugfs_fifo_update_cfg_v3_hw_write,
4521	.owner = THIS_MODULE,
4522};
4523
4524static void debugfs_read_fifo_data_v3_hw(struct hisi_sas_phy *phy)
4525{
4526	struct hisi_hba *hisi_hba = phy->hisi_hba;
4527	u32 *buf = phy->fifo.rd_data;
4528	int phy_no = phy->sas_phy.id;
4529	u32 val;
4530	int i;
4531
4532	memset(buf, 0, sizeof(phy->fifo.rd_data));
4533
4534	/* Disable trace FIFO before read data */
4535	val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4536	val |= DFX_FIFO_CTRL_DUMP_DISABLE_MSK;
4537	hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, val);
4538
4539	for (i = 0; i < HISI_SAS_FIFO_DATA_DW_SIZE; i++) {
4540		val = hisi_sas_phy_read32(hisi_hba, phy_no,
4541					  DFX_FIFO_RD_DATA);
4542		buf[i] = val;
4543	}
4544
4545	/* Enable trace FIFO after read data */
4546	val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4547	val &= ~DFX_FIFO_CTRL_DUMP_DISABLE_MSK;
4548	hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, val);
4549}
4550
4551static int debugfs_fifo_data_v3_hw_show(struct seq_file *s, void *p)
4552{
4553	struct hisi_sas_phy *phy = s->private;
4554
4555	debugfs_read_fifo_data_v3_hw(phy);
4556
4557	debugfs_show_row_32_v3_hw(s, 0,
4558			HISI_SAS_FIFO_DATA_DW_SIZE * HISI_SAS_REG_MEM_SIZE,
4559			(__le32 *)phy->fifo.rd_data);
4560
4561	return 0;
4562}
4563DEFINE_SHOW_ATTRIBUTE(debugfs_fifo_data_v3_hw);
4564
4565static void debugfs_fifo_init_v3_hw(struct hisi_hba *hisi_hba)
4566{
4567	int phy_no;
4568
4569	hisi_hba->debugfs_fifo_dentry =
4570			debugfs_create_dir("fifo", hisi_hba->debugfs_dir);
4571
4572	for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
4573		struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
4574		struct dentry *port_dentry;
4575		char name[256];
4576		u32 val;
4577
4578		/* get default configuration for trace FIFO */
4579		val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4580		val &= DFX_FIFO_CTRL_DUMP_MODE_MSK;
4581		val >>= DFX_FIFO_CTRL_DUMP_MODE_OFF;
4582		phy->fifo.dump_mode = val;
4583
4584		val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4585		val &= DFX_FIFO_CTRL_TRIGGER_MODE_MSK;
4586		val >>= DFX_FIFO_CTRL_TRIGGER_MODE_OFF;
4587		phy->fifo.trigger_mode = val;
4588
4589		val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4590		val &= DFX_FIFO_CTRL_SIGNAL_SEL_MSK;
4591		val >>= DFX_FIFO_CTRL_SIGNAL_SEL_OFF;
4592		phy->fifo.signal_sel = val;
4593
4594		val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_DUMP_MSK);
4595		phy->fifo.dump_msk = val;
4596
4597		val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_TRIGGER);
4598		phy->fifo.trigger = val;
4599		val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_TRIGGER_MSK);
4600		phy->fifo.trigger_msk = val;
4601
4602		snprintf(name, 256, "%d", phy_no);
4603		port_dentry = debugfs_create_dir(name,
4604						 hisi_hba->debugfs_fifo_dentry);
4605
4606		debugfs_create_file("update_config", 0200, port_dentry, phy,
4607				    &debugfs_fifo_update_cfg_v3_hw_fops);
4608
4609		debugfs_create_file("signal_sel", 0600, port_dentry,
4610				    &phy->fifo.signal_sel,
4611				    &debugfs_v3_hw_fops);
4612
4613		debugfs_create_file("dump_msk", 0600, port_dentry,
4614				    &phy->fifo.dump_msk,
4615				    &debugfs_v3_hw_fops);
4616
4617		debugfs_create_file("dump_mode", 0600, port_dentry,
4618				    &phy->fifo.dump_mode,
4619				    &debugfs_v3_hw_fops);
4620
4621		debugfs_create_file("trigger_mode", 0600, port_dentry,
4622				    &phy->fifo.trigger_mode,
4623				    &debugfs_v3_hw_fops);
4624
4625		debugfs_create_file("trigger", 0600, port_dentry,
4626				    &phy->fifo.trigger,
4627				    &debugfs_v3_hw_fops);
4628
4629		debugfs_create_file("trigger_msk", 0600, port_dentry,
4630				    &phy->fifo.trigger_msk,
4631				    &debugfs_v3_hw_fops);
4632
4633		debugfs_create_file("fifo_data", 0400, port_dentry, phy,
4634				    &debugfs_fifo_data_v3_hw_fops);
4635	}
4636}
4637
4638static void debugfs_release_v3_hw(struct hisi_hba *hisi_hba, int dump_index)
4639{
4640	struct device *dev = hisi_hba->dev;
4641	int i;
4642
4643	devm_kfree(dev, hisi_hba->debugfs_iost_cache[dump_index].cache);
4644	hisi_hba->debugfs_iost_cache[dump_index].cache = NULL;
4645	devm_kfree(dev, hisi_hba->debugfs_itct_cache[dump_index].cache);
4646	hisi_hba->debugfs_itct_cache[dump_index].cache = NULL;
4647	devm_kfree(dev, hisi_hba->debugfs_iost[dump_index].iost);
4648	hisi_hba->debugfs_iost[dump_index].iost = NULL;
4649	devm_kfree(dev, hisi_hba->debugfs_itct[dump_index].itct);
4650	hisi_hba->debugfs_itct[dump_index].itct = NULL;
4651
4652	for (i = 0; i < hisi_hba->queue_count; i++) {
4653		devm_kfree(dev, hisi_hba->debugfs_dq[dump_index][i].hdr);
4654		hisi_hba->debugfs_dq[dump_index][i].hdr = NULL;
4655	}
4656
4657	for (i = 0; i < hisi_hba->queue_count; i++) {
4658		devm_kfree(dev,
4659			   hisi_hba->debugfs_cq[dump_index][i].complete_hdr);
4660		hisi_hba->debugfs_cq[dump_index][i].complete_hdr = NULL;
4661	}
4662
4663	for (i = 0; i < DEBUGFS_REGS_NUM; i++) {
4664		devm_kfree(dev, hisi_hba->debugfs_regs[dump_index][i].data);
4665		hisi_hba->debugfs_regs[dump_index][i].data = NULL;
4666	}
4667
4668	for (i = 0; i < hisi_hba->n_phy; i++) {
4669		devm_kfree(dev, hisi_hba->debugfs_port_reg[dump_index][i].data);
4670		hisi_hba->debugfs_port_reg[dump_index][i].data = NULL;
4671	}
4672}
4673
4674static const struct hisi_sas_debugfs_reg *debugfs_reg_array_v3_hw[DEBUGFS_REGS_NUM] = {
4675	[DEBUGFS_GLOBAL] = &debugfs_global_reg,
4676	[DEBUGFS_AXI] = &debugfs_axi_reg,
4677	[DEBUGFS_RAS] = &debugfs_ras_reg,
4678};
4679
4680static int debugfs_alloc_v3_hw(struct hisi_hba *hisi_hba, int dump_index)
4681{
4682	const struct hisi_sas_hw *hw = hisi_hba->hw;
4683	struct device *dev = hisi_hba->dev;
4684	int p, c, d, r;
4685	size_t sz;
4686
4687	for (r = 0; r < DEBUGFS_REGS_NUM; r++) {
4688		struct hisi_sas_debugfs_regs *regs =
4689				&hisi_hba->debugfs_regs[dump_index][r];
4690
4691		sz = debugfs_reg_array_v3_hw[r]->count * HISI_SAS_REG_MEM_SIZE;
4692		regs->data = devm_kmalloc(dev, sz, GFP_KERNEL);
4693		if (!regs->data)
4694			goto fail;
4695		regs->hisi_hba = hisi_hba;
4696	}
4697
4698	sz = debugfs_port_reg.count * HISI_SAS_REG_MEM_SIZE;
4699	for (p = 0; p < hisi_hba->n_phy; p++) {
4700		struct hisi_sas_debugfs_port *port =
4701				&hisi_hba->debugfs_port_reg[dump_index][p];
4702
4703		port->data = devm_kmalloc(dev, sz, GFP_KERNEL);
4704		if (!port->data)
4705			goto fail;
4706		port->phy = &hisi_hba->phy[p];
4707	}
4708
4709	sz = hw->complete_hdr_size * HISI_SAS_QUEUE_SLOTS;
4710	for (c = 0; c < hisi_hba->queue_count; c++) {
4711		struct hisi_sas_debugfs_cq *cq =
4712				&hisi_hba->debugfs_cq[dump_index][c];
4713
4714		cq->complete_hdr = devm_kmalloc(dev, sz, GFP_KERNEL);
4715		if (!cq->complete_hdr)
4716			goto fail;
4717		cq->cq = &hisi_hba->cq[c];
4718	}
4719
4720	sz = sizeof(struct hisi_sas_cmd_hdr) * HISI_SAS_QUEUE_SLOTS;
4721	for (d = 0; d < hisi_hba->queue_count; d++) {
4722		struct hisi_sas_debugfs_dq *dq =
4723				&hisi_hba->debugfs_dq[dump_index][d];
4724
4725		dq->hdr = devm_kmalloc(dev, sz, GFP_KERNEL);
4726		if (!dq->hdr)
4727			goto fail;
4728		dq->dq = &hisi_hba->dq[d];
4729	}
4730
4731	sz = HISI_SAS_MAX_COMMANDS * sizeof(struct hisi_sas_iost);
4732
4733	hisi_hba->debugfs_iost[dump_index].iost =
4734				devm_kmalloc(dev, sz, GFP_KERNEL);
4735	if (!hisi_hba->debugfs_iost[dump_index].iost)
4736		goto fail;
4737
4738	sz = HISI_SAS_IOST_ITCT_CACHE_NUM *
4739	     sizeof(struct hisi_sas_iost_itct_cache);
4740
4741	hisi_hba->debugfs_iost_cache[dump_index].cache =
4742				devm_kmalloc(dev, sz, GFP_KERNEL);
4743	if (!hisi_hba->debugfs_iost_cache[dump_index].cache)
4744		goto fail;
4745
4746	sz = HISI_SAS_IOST_ITCT_CACHE_NUM *
4747	     sizeof(struct hisi_sas_iost_itct_cache);
4748
4749	hisi_hba->debugfs_itct_cache[dump_index].cache =
4750				devm_kmalloc(dev, sz, GFP_KERNEL);
4751	if (!hisi_hba->debugfs_itct_cache[dump_index].cache)
4752		goto fail;
4753
4754	/* New memory allocation must be locate before itct */
4755	sz = HISI_SAS_MAX_ITCT_ENTRIES * sizeof(struct hisi_sas_itct);
4756
4757	hisi_hba->debugfs_itct[dump_index].itct =
4758				devm_kmalloc(dev, sz, GFP_KERNEL);
4759	if (!hisi_hba->debugfs_itct[dump_index].itct)
4760		goto fail;
4761
4762	return 0;
4763fail:
4764	debugfs_release_v3_hw(hisi_hba, dump_index);
4765	return -ENOMEM;
4766}
4767
4768static int debugfs_snapshot_regs_v3_hw(struct hisi_hba *hisi_hba)
4769{
4770	int debugfs_dump_index = hisi_hba->debugfs_dump_index;
4771	struct device *dev = hisi_hba->dev;
4772	u64 timestamp = local_clock();
4773
4774	if (debugfs_dump_index >= hisi_sas_debugfs_dump_count) {
4775		dev_warn(dev, "dump count exceeded!\n");
4776		return -EINVAL;
4777	}
4778
4779	if (debugfs_alloc_v3_hw(hisi_hba, debugfs_dump_index)) {
4780		dev_warn(dev, "failed to alloc memory\n");
4781		return -ENOMEM;
4782	}
4783
4784	do_div(timestamp, NSEC_PER_MSEC);
4785	hisi_hba->debugfs_timestamp[debugfs_dump_index] = timestamp;
4786
4787	debugfs_snapshot_prepare_v3_hw(hisi_hba);
4788
4789	debugfs_snapshot_global_reg_v3_hw(hisi_hba);
4790	debugfs_snapshot_port_reg_v3_hw(hisi_hba);
4791	debugfs_snapshot_axi_reg_v3_hw(hisi_hba);
4792	debugfs_snapshot_ras_reg_v3_hw(hisi_hba);
4793	debugfs_snapshot_cq_reg_v3_hw(hisi_hba);
4794	debugfs_snapshot_dq_reg_v3_hw(hisi_hba);
4795	debugfs_snapshot_itct_reg_v3_hw(hisi_hba);
4796	debugfs_snapshot_iost_reg_v3_hw(hisi_hba);
4797
4798	debugfs_snapshot_restore_v3_hw(hisi_hba);
4799	hisi_hba->debugfs_dump_index++;
4800
4801	return 0;
4802}
4803
4804static void debugfs_phy_down_cnt_init_v3_hw(struct hisi_hba *hisi_hba)
4805{
4806	struct dentry *dir = debugfs_create_dir("phy_down_cnt",
4807						hisi_hba->debugfs_dir);
4808	char name[NAME_BUF_SIZE];
4809	int phy_no;
4810
4811	for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
4812		snprintf(name, NAME_BUF_SIZE, "%d", phy_no);
4813		debugfs_create_file(name, 0600, dir,
4814				    &hisi_hba->phy[phy_no],
4815				    &debugfs_phy_down_cnt_v3_hw_fops);
4816	}
4817}
4818
4819static void debugfs_bist_init_v3_hw(struct hisi_hba *hisi_hba)
4820{
4821	struct dentry *ports_dentry;
4822	int phy_no;
4823
4824	hisi_hba->debugfs_bist_dentry =
4825			debugfs_create_dir("bist", hisi_hba->debugfs_dir);
4826	debugfs_create_file("link_rate", 0600,
4827			    hisi_hba->debugfs_bist_dentry, hisi_hba,
4828			    &debugfs_bist_linkrate_v3_hw_fops);
4829
4830	debugfs_create_file("code_mode", 0600,
4831			    hisi_hba->debugfs_bist_dentry, hisi_hba,
4832			    &debugfs_bist_code_mode_v3_hw_fops);
4833
4834	debugfs_create_file("fixed_code", 0600,
4835			    hisi_hba->debugfs_bist_dentry,
4836			    &hisi_hba->debugfs_bist_fixed_code[0],
4837			    &debugfs_v3_hw_fops);
4838
4839	debugfs_create_file("fixed_code_1", 0600,
4840			    hisi_hba->debugfs_bist_dentry,
4841			    &hisi_hba->debugfs_bist_fixed_code[1],
4842			    &debugfs_v3_hw_fops);
4843
4844	debugfs_create_file("phy_id", 0600, hisi_hba->debugfs_bist_dentry,
4845			    hisi_hba, &debugfs_bist_phy_v3_hw_fops);
4846
4847	debugfs_create_file("cnt", 0600, hisi_hba->debugfs_bist_dentry,
4848			    hisi_hba, &debugfs_bist_cnt_v3_hw_fops);
4849
4850	debugfs_create_file("loopback_mode", 0600,
4851			    hisi_hba->debugfs_bist_dentry,
4852			    hisi_hba, &debugfs_bist_mode_v3_hw_fops);
4853
4854	debugfs_create_file("enable", 0600, hisi_hba->debugfs_bist_dentry,
4855			    hisi_hba, &debugfs_bist_enable_v3_hw_fops);
4856
4857	ports_dentry = debugfs_create_dir("port", hisi_hba->debugfs_bist_dentry);
4858
4859	for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
4860		struct dentry *port_dentry;
4861		struct dentry *ffe_dentry;
4862		char name[256];
4863		int i;
4864
4865		snprintf(name, 256, "%d", phy_no);
4866		port_dentry = debugfs_create_dir(name, ports_dentry);
4867		ffe_dentry = debugfs_create_dir("ffe", port_dentry);
4868		for (i = 0; i < FFE_CFG_MAX; i++) {
4869			if (i == FFE_RESV)
4870				continue;
4871			debugfs_create_file(debugfs_ffe_name_v3_hw[i].name,
4872					    0600, ffe_dentry,
4873					    &hisi_hba->debugfs_bist_ffe[phy_no][i],
4874					    &debugfs_v3_hw_fops);
4875		}
4876	}
4877
4878	hisi_hba->debugfs_bist_linkrate = SAS_LINK_RATE_1_5_GBPS;
4879}
4880
4881static int debugfs_dump_index_v3_hw_show(struct seq_file *s, void *p)
4882{
4883	int *debugfs_dump_index = s->private;
4884
4885	if (*debugfs_dump_index > 0)
4886		seq_printf(s, "%d\n", *debugfs_dump_index - 1);
4887	else
4888		seq_puts(s, "dump not triggered\n");
4889
4890	return 0;
4891}
4892DEFINE_SHOW_ATTRIBUTE(debugfs_dump_index_v3_hw);
4893
4894static void debugfs_dump_init_v3_hw(struct hisi_hba *hisi_hba)
4895{
4896	int i;
4897
4898	hisi_hba->debugfs_dump_dentry =
4899			debugfs_create_dir("dump", hisi_hba->debugfs_dir);
4900
4901	debugfs_create_file("latest_dump", 0400, hisi_hba->debugfs_dump_dentry,
4902			    &hisi_hba->debugfs_dump_index,
4903			    &debugfs_dump_index_v3_hw_fops);
4904
4905	for (i = 0; i < hisi_sas_debugfs_dump_count; i++)
4906		debugfs_create_files_v3_hw(hisi_hba, i);
4907}
4908
4909static void debugfs_exit_v3_hw(struct hisi_hba *hisi_hba)
4910{
4911	debugfs_remove_recursive(hisi_hba->debugfs_dir);
4912	hisi_hba->debugfs_dir = NULL;
4913}
4914
4915static void debugfs_init_v3_hw(struct hisi_hba *hisi_hba)
4916{
4917	struct device *dev = hisi_hba->dev;
4918
4919	hisi_hba->debugfs_dir = debugfs_create_dir(dev_name(dev),
4920						   hisi_sas_debugfs_dir);
4921	/* create bist structures */
4922	debugfs_bist_init_v3_hw(hisi_hba);
4923
4924	debugfs_dump_init_v3_hw(hisi_hba);
4925
4926	debugfs_phy_down_cnt_init_v3_hw(hisi_hba);
4927	debugfs_fifo_init_v3_hw(hisi_hba);
4928	debugfs_create_file("trigger_dump", 0200,
4929			    hisi_hba->debugfs_dir,
4930			    hisi_hba,
4931			    &debugfs_trigger_dump_v3_hw_fops);
4932}
4933
4934static int
4935hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id)
4936{
4937	struct Scsi_Host *shost;
4938	struct hisi_hba *hisi_hba;
4939	struct device *dev = &pdev->dev;
4940	struct asd_sas_phy **arr_phy;
4941	struct asd_sas_port **arr_port;
4942	struct sas_ha_struct *sha;
4943	int rc, phy_nr, port_nr, i;
4944
4945	rc = pcim_enable_device(pdev);
4946	if (rc)
4947		goto err_out;
4948
4949	pci_set_master(pdev);
4950
4951	rc = pcim_iomap_regions(pdev, 1 << BAR_NO_V3_HW, DRV_NAME);
4952	if (rc)
4953		goto err_out;
4954
4955	rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
4956	if (rc) {
4957		dev_err(dev, "No usable DMA addressing method\n");
4958		rc = -ENODEV;
4959		goto err_out;
4960	}
4961
4962	shost = hisi_sas_shost_alloc_pci(pdev);
4963	if (!shost) {
4964		rc = -ENOMEM;
4965		goto err_out;
4966	}
4967
4968	sha = SHOST_TO_SAS_HA(shost);
4969	hisi_hba = shost_priv(shost);
4970	dev_set_drvdata(dev, sha);
4971
4972	hisi_hba->regs = pcim_iomap_table(pdev)[BAR_NO_V3_HW];
4973	if (!hisi_hba->regs) {
4974		dev_err(dev, "cannot map register\n");
4975		rc = -ENOMEM;
4976		goto err_out_free_host;
4977	}
4978
4979	phy_nr = port_nr = hisi_hba->n_phy;
4980
4981	arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
4982	arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
4983	if (!arr_phy || !arr_port) {
4984		rc = -ENOMEM;
4985		goto err_out_free_host;
4986	}
4987
4988	sha->sas_phy = arr_phy;
4989	sha->sas_port = arr_port;
4990	sha->shost = shost;
4991	sha->lldd_ha = hisi_hba;
4992
4993	shost->transportt = hisi_sas_stt;
4994	shost->max_id = HISI_SAS_MAX_DEVICES;
4995	shost->max_lun = ~0;
4996	shost->max_channel = 0;
4997	shost->max_cmd_len = HISI_SAS_MAX_CDB_LEN;
4998	shost->can_queue = HISI_SAS_UNRESERVED_IPTT;
4999	shost->cmd_per_lun = HISI_SAS_UNRESERVED_IPTT;
5000	if (hisi_hba->iopoll_q_cnt)
5001		shost->nr_maps = 3;
5002	else
5003		shost->nr_maps = 1;
5004
5005	sha->sas_ha_name = DRV_NAME;
5006	sha->dev = dev;
5007	sha->sas_addr = &hisi_hba->sas_addr[0];
5008	sha->num_phys = hisi_hba->n_phy;
5009
5010	for (i = 0; i < hisi_hba->n_phy; i++) {
5011		sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy;
5012		sha->sas_port[i] = &hisi_hba->port[i].sas_port;
5013	}
5014
5015	if (hisi_hba->prot_mask) {
5016		dev_info(dev, "Registering for DIF/DIX prot_mask=0x%x\n",
5017			 prot_mask);
5018		scsi_host_set_prot(hisi_hba->shost, prot_mask);
5019		if (hisi_hba->prot_mask & HISI_SAS_DIX_PROT_MASK)
5020			scsi_host_set_guard(hisi_hba->shost,
5021					    SHOST_DIX_GUARD_CRC);
5022	}
5023
5024	rc = interrupt_preinit_v3_hw(hisi_hba);
5025	if (rc)
5026		goto err_out_free_host;
5027
5028	rc = scsi_add_host(shost, dev);
5029	if (rc)
5030		goto err_out_free_host;
5031
5032	rc = sas_register_ha(sha);
5033	if (rc)
5034		goto err_out_remove_host;
5035
5036	rc = hisi_sas_v3_init(hisi_hba);
5037	if (rc)
5038		goto err_out_unregister_ha;
5039
5040	scsi_scan_host(shost);
5041	if (hisi_sas_debugfs_enable)
5042		debugfs_init_v3_hw(hisi_hba);
5043
5044	pm_runtime_set_autosuspend_delay(dev, 5000);
5045	pm_runtime_use_autosuspend(dev);
5046	/*
5047	 * For the situation that there are ATA disks connected with SAS
5048	 * controller, it additionally creates ata_port which will affect the
5049	 * child_count of hisi_hba->dev. Even if suspended all the disks,
5050	 * ata_port is still and the child_count of hisi_hba->dev is not 0.
5051	 * So use pm_suspend_ignore_children() to ignore the effect to
5052	 * hisi_hba->dev.
5053	 */
5054	pm_suspend_ignore_children(dev, true);
5055	pm_runtime_put_noidle(&pdev->dev);
5056
5057	return 0;
5058
5059err_out_unregister_ha:
5060	sas_unregister_ha(sha);
5061err_out_remove_host:
5062	scsi_remove_host(shost);
5063err_out_free_host:
5064	hisi_sas_free(hisi_hba);
5065	scsi_host_put(shost);
5066err_out:
5067	return rc;
5068}
5069
5070static void
5071hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba)
5072{
5073	int i;
5074
5075	devm_free_irq(&pdev->dev, pci_irq_vector(pdev, IRQ_PHY_UP_DOWN_INDEX), hisi_hba);
5076	devm_free_irq(&pdev->dev, pci_irq_vector(pdev, IRQ_CHL_INDEX), hisi_hba);
5077	devm_free_irq(&pdev->dev, pci_irq_vector(pdev, IRQ_AXI_INDEX), hisi_hba);
5078	for (i = 0; i < hisi_hba->cq_nvecs; i++) {
5079		struct hisi_sas_cq *cq = &hisi_hba->cq[i];
5080		int nr = hisi_sas_intr_conv ? BASE_VECTORS_V3_HW :
5081					      BASE_VECTORS_V3_HW + i;
5082
5083		devm_free_irq(&pdev->dev, pci_irq_vector(pdev, nr), cq);
5084	}
5085}
5086
5087static void hisi_sas_v3_remove(struct pci_dev *pdev)
5088{
5089	struct device *dev = &pdev->dev;
5090	struct sas_ha_struct *sha = dev_get_drvdata(dev);
5091	struct hisi_hba *hisi_hba = sha->lldd_ha;
5092	struct Scsi_Host *shost = sha->shost;
5093
5094	pm_runtime_get_noresume(dev);
5095	if (hisi_sas_debugfs_enable)
5096		debugfs_exit_v3_hw(hisi_hba);
5097
5098	sas_unregister_ha(sha);
5099	flush_workqueue(hisi_hba->wq);
5100	sas_remove_host(shost);
5101
5102	hisi_sas_v3_destroy_irqs(pdev, hisi_hba);
5103	hisi_sas_free(hisi_hba);
5104	scsi_host_put(shost);
5105}
5106
5107static void hisi_sas_reset_prepare_v3_hw(struct pci_dev *pdev)
5108{
5109	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
5110	struct hisi_hba *hisi_hba = sha->lldd_ha;
5111	struct Scsi_Host *shost = hisi_hba->shost;
5112	struct device *dev = hisi_hba->dev;
5113	int rc;
5114
5115	wait_event(shost->host_wait, !scsi_host_in_recovery(shost));
5116	dev_info(dev, "FLR prepare\n");
5117	down(&hisi_hba->sem);
5118	set_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags);
5119	hisi_sas_controller_reset_prepare(hisi_hba);
5120
5121	interrupt_disable_v3_hw(hisi_hba);
5122	rc = disable_host_v3_hw(hisi_hba);
5123	if (rc)
5124		dev_err(dev, "FLR: disable host failed rc=%d\n", rc);
5125}
5126
5127static void hisi_sas_reset_done_v3_hw(struct pci_dev *pdev)
5128{
5129	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
5130	struct hisi_hba *hisi_hba = sha->lldd_ha;
5131	struct Scsi_Host *shost = hisi_hba->shost;
5132	struct device *dev = hisi_hba->dev;
5133	int rc;
5134
5135	hisi_sas_init_mem(hisi_hba);
5136
5137	rc = hw_init_v3_hw(hisi_hba);
5138	if (rc) {
5139		dev_err(dev, "FLR: hw init failed rc=%d\n", rc);
5140		clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
5141		scsi_unblock_requests(shost);
5142		clear_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags);
5143		up(&hisi_hba->sem);
5144		return;
5145	}
5146
5147	hisi_sas_controller_reset_done(hisi_hba);
5148	dev_info(dev, "FLR done\n");
5149}
5150
5151enum {
5152	/* instances of the controller */
5153	hip08,
5154};
5155
5156static void enable_host_v3_hw(struct hisi_hba *hisi_hba)
5157{
5158	u32 reg_val;
5159
5160	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
5161			 (u32)((1ULL << hisi_hba->queue_count) - 1));
5162
5163	phys_init_v3_hw(hisi_hba);
5164	reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
5165				  AM_CTRL_GLOBAL);
5166	reg_val &= ~AM_CTRL_SHUTDOWN_REQ_MSK;
5167	hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
5168			 AM_CTRL_GLOBAL, reg_val);
5169}
5170
5171static int _suspend_v3_hw(struct device *device)
5172{
5173	struct pci_dev *pdev = to_pci_dev(device);
5174	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
5175	struct hisi_hba *hisi_hba = sha->lldd_ha;
5176	struct device *dev = hisi_hba->dev;
5177	struct Scsi_Host *shost = hisi_hba->shost;
5178	int rc;
5179
5180	if (!pdev->pm_cap) {
5181		dev_err(dev, "PCI PM not supported\n");
5182		return -ENODEV;
5183	}
5184
5185	if (test_and_set_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags))
5186		return -EPERM;
5187
5188	dev_warn(dev, "entering suspend state\n");
5189
5190	scsi_block_requests(shost);
5191	set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
5192	flush_workqueue(hisi_hba->wq);
5193	interrupt_disable_v3_hw(hisi_hba);
5194
5195#ifdef CONFIG_PM
5196	if ((device->power.runtime_status == RPM_SUSPENDING) &&
5197	    atomic_read(&device->power.usage_count)) {
5198		dev_err(dev, "PM suspend: host status cannot be suspended\n");
5199		rc = -EBUSY;
5200		goto err_out;
5201	}
5202#endif
5203
5204	rc = disable_host_v3_hw(hisi_hba);
5205	if (rc) {
5206		dev_err(dev, "PM suspend: disable host failed rc=%d\n", rc);
5207		goto err_out_recover_host;
5208	}
5209
5210	hisi_sas_init_mem(hisi_hba);
5211
5212	hisi_sas_release_tasks(hisi_hba);
5213
5214	sas_suspend_ha(sha);
5215
5216	dev_warn(dev, "end of suspending controller\n");
5217	return 0;
5218
5219err_out_recover_host:
5220	enable_host_v3_hw(hisi_hba);
5221#ifdef CONFIG_PM
5222err_out:
5223#endif
5224	interrupt_enable_v3_hw(hisi_hba);
5225	clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
5226	clear_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags);
5227	scsi_unblock_requests(shost);
5228	return rc;
5229}
5230
5231static int _resume_v3_hw(struct device *device)
5232{
5233	struct pci_dev *pdev = to_pci_dev(device);
5234	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
5235	struct hisi_hba *hisi_hba = sha->lldd_ha;
5236	struct Scsi_Host *shost = hisi_hba->shost;
5237	struct device *dev = hisi_hba->dev;
5238	unsigned int rc;
5239	pci_power_t device_state = pdev->current_state;
5240
5241	dev_warn(dev, "resuming from operating state [D%d]\n",
5242		 device_state);
5243
5244	scsi_unblock_requests(shost);
5245	clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
5246
5247	sas_prep_resume_ha(sha);
5248	rc = hw_init_v3_hw(hisi_hba);
5249	if (rc) {
5250		scsi_remove_host(shost);
5251		return rc;
5252	}
5253	phys_init_v3_hw(hisi_hba);
5254
5255	/*
5256	 * If a directly-attached disk is removed during suspend, a deadlock
5257	 * may occur, as the PHYE_RESUME_TIMEOUT processing will require the
5258	 * hisi_hba->device to be active, which can only happen when resume
5259	 * completes. So don't wait for the HA event workqueue to drain upon
5260	 * resume.
5261	 */
5262	sas_resume_ha_no_sync(sha);
5263	clear_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags);
5264
5265	dev_warn(dev, "end of resuming controller\n");
5266
5267	return 0;
5268}
5269
5270static int __maybe_unused suspend_v3_hw(struct device *device)
5271{
5272	struct pci_dev *pdev = to_pci_dev(device);
5273	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
5274	struct hisi_hba *hisi_hba = sha->lldd_ha;
5275	int rc;
5276
5277	set_bit(HISI_SAS_PM_BIT, &hisi_hba->flags);
5278
5279	rc = _suspend_v3_hw(device);
5280	if (rc)
5281		clear_bit(HISI_SAS_PM_BIT, &hisi_hba->flags);
5282
5283	return rc;
5284}
5285
5286static int __maybe_unused resume_v3_hw(struct device *device)
5287{
5288	struct pci_dev *pdev = to_pci_dev(device);
5289	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
5290	struct hisi_hba *hisi_hba = sha->lldd_ha;
5291	int rc = _resume_v3_hw(device);
5292
5293	clear_bit(HISI_SAS_PM_BIT, &hisi_hba->flags);
5294
5295	return rc;
5296}
5297
5298static const struct pci_device_id sas_v3_pci_table[] = {
5299	{ PCI_VDEVICE(HUAWEI, 0xa230), hip08 },
5300	{}
5301};
5302MODULE_DEVICE_TABLE(pci, sas_v3_pci_table);
5303
5304static const struct pci_error_handlers hisi_sas_err_handler = {
5305	.reset_prepare	= hisi_sas_reset_prepare_v3_hw,
5306	.reset_done	= hisi_sas_reset_done_v3_hw,
5307};
5308
5309static UNIVERSAL_DEV_PM_OPS(hisi_sas_v3_pm_ops,
5310			    suspend_v3_hw,
5311			    resume_v3_hw,
5312			    NULL);
5313
5314static struct pci_driver sas_v3_pci_driver = {
5315	.name		= DRV_NAME,
5316	.id_table	= sas_v3_pci_table,
5317	.probe		= hisi_sas_v3_probe,
5318	.remove		= hisi_sas_v3_remove,
5319	.err_handler	= &hisi_sas_err_handler,
5320	.driver.pm	= &hisi_sas_v3_pm_ops,
5321};
5322
5323module_pci_driver(sas_v3_pci_driver);
5324module_param_named(intr_conv, hisi_sas_intr_conv, bool, 0444);
5325
5326MODULE_LICENSE("GPL");
5327MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
5328MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device");
5329MODULE_ALIAS("pci:" DRV_NAME);