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hisi_sas_v2_hw.c
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linux-6.19.14/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright (c) 2016 Linaro Ltd. 4 * Copyright (c) 2016 Hisilicon Limited. 5 */ 6 7#include "hisi_sas.h" 8#define DRV_NAME "hisi_sas_v2_hw" 9 10/* global registers need init*/ 11#define DLVRY_QUEUE_ENABLE 0x0 12#define IOST_BASE_ADDR_LO 0x8 13#define IOST_BASE_ADDR_HI 0xc 14#define ITCT_BASE_ADDR_LO 0x10 15#define ITCT_BASE_ADDR_HI 0x14 16#define IO_BROKEN_MSG_ADDR_LO 0x18 17#define IO_BROKEN_MSG_ADDR_HI 0x1c 18#define PHY_CONTEXT 0x20 19#define PHY_STATE 0x24 20#define PHY_PORT_NUM_MA 0x28 21#define PORT_STATE 0x2c 22#define PORT_STATE_PHY8_PORT_NUM_OFF 16 23#define PORT_STATE_PHY8_PORT_NUM_MSK (0xf << PORT_STATE_PHY8_PORT_NUM_OFF) 24#define PORT_STATE_PHY8_CONN_RATE_OFF 20 25#define PORT_STATE_PHY8_CONN_RATE_MSK (0xf << PORT_STATE_PHY8_CONN_RATE_OFF) 26#define PHY_CONN_RATE 0x30 27#define HGC_TRANS_TASK_CNT_LIMIT 0x38 28#define AXI_AHB_CLK_CFG 0x3c 29#define ITCT_CLR 0x44 30#define ITCT_CLR_EN_OFF 16 31#define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF) 32#define ITCT_DEV_OFF 0 33#define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF) 34#define AXI_USER1 0x48 35#define AXI_USER2 0x4c 36#define IO_SATA_BROKEN_MSG_ADDR_LO 0x58 37#define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c 38#define SATA_INITI_D2H_STORE_ADDR_LO 0x60 39#define SATA_INITI_D2H_STORE_ADDR_HI 0x64 40#define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84 41#define HGC_SAS_TXFAIL_RETRY_CTRL 0x88 42#define HGC_GET_ITV_TIME 0x90 43#define DEVICE_MSG_WORK_MODE 0x94 44#define OPENA_WT_CONTI_TIME 0x9c 45#define I_T_NEXUS_LOSS_TIME 0xa0 46#define MAX_CON_TIME_LIMIT_TIME 0xa4 47#define BUS_INACTIVE_LIMIT_TIME 0xa8 48#define REJECT_TO_OPEN_LIMIT_TIME 0xac 49#define CFG_AGING_TIME 0xbc 50#define HGC_DFX_CFG2 0xc0 51#define HGC_IOMB_PROC1_STATUS 0x104 52#define CFG_1US_TIMER_TRSH 0xcc 53#define HGC_LM_DFX_STATUS2 0x128 54#define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0 55#define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \ 56 HGC_LM_DFX_STATUS2_IOSTLIST_OFF) 57#define HGC_LM_DFX_STATUS2_ITCTLIST_OFF 12 58#define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \ 59 HGC_LM_DFX_STATUS2_ITCTLIST_OFF) 60#define HGC_CQE_ECC_ADDR 0x13c 61#define HGC_CQE_ECC_1B_ADDR_OFF 0 62#define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF) 63#define HGC_CQE_ECC_MB_ADDR_OFF 8 64#define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF) 65#define HGC_IOST_ECC_ADDR 0x140 66#define HGC_IOST_ECC_1B_ADDR_OFF 0 67#define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF) 68#define HGC_IOST_ECC_MB_ADDR_OFF 16 69#define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF) 70#define HGC_DQE_ECC_ADDR 0x144 71#define HGC_DQE_ECC_1B_ADDR_OFF 0 72#define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF) 73#define HGC_DQE_ECC_MB_ADDR_OFF 16 74#define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF) 75#define HGC_INVLD_DQE_INFO 0x148 76#define HGC_INVLD_DQE_INFO_FB_CH0_OFF 9 77#define HGC_INVLD_DQE_INFO_FB_CH0_MSK (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF) 78#define HGC_INVLD_DQE_INFO_FB_CH3_OFF 18 79#define HGC_ITCT_ECC_ADDR 0x150 80#define HGC_ITCT_ECC_1B_ADDR_OFF 0 81#define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << \ 82 HGC_ITCT_ECC_1B_ADDR_OFF) 83#define HGC_ITCT_ECC_MB_ADDR_OFF 16 84#define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << \ 85 HGC_ITCT_ECC_MB_ADDR_OFF) 86#define HGC_AXI_FIFO_ERR_INFO 0x154 87#define AXI_ERR_INFO_OFF 0 88#define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF) 89#define FIFO_ERR_INFO_OFF 8 90#define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF) 91#define INT_COAL_EN 0x19c 92#define OQ_INT_COAL_TIME 0x1a0 93#define OQ_INT_COAL_CNT 0x1a4 94#define ENT_INT_COAL_TIME 0x1a8 95#define ENT_INT_COAL_CNT 0x1ac 96#define OQ_INT_SRC 0x1b0 97#define OQ_INT_SRC_MSK 0x1b4 98#define ENT_INT_SRC1 0x1b8 99#define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0 100#define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF) 101#define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8 102#define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF) 103#define ENT_INT_SRC2 0x1bc 104#define ENT_INT_SRC3 0x1c0 105#define ENT_INT_SRC3_WP_DEPTH_OFF 8 106#define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9 107#define ENT_INT_SRC3_RP_DEPTH_OFF 10 108#define ENT_INT_SRC3_AXI_OFF 11 109#define ENT_INT_SRC3_FIFO_OFF 12 110#define ENT_INT_SRC3_LM_OFF 14 111#define ENT_INT_SRC3_ITC_INT_OFF 15 112#define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF) 113#define ENT_INT_SRC3_ABT_OFF 16 114#define ENT_INT_SRC_MSK1 0x1c4 115#define ENT_INT_SRC_MSK2 0x1c8 116#define ENT_INT_SRC_MSK3 0x1cc 117#define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31 118#define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF) 119#define SAS_ECC_INTR 0x1e8 120#define SAS_ECC_INTR_DQE_ECC_1B_OFF 0 121#define SAS_ECC_INTR_DQE_ECC_MB_OFF 1 122#define SAS_ECC_INTR_IOST_ECC_1B_OFF 2 123#define SAS_ECC_INTR_IOST_ECC_MB_OFF 3 124#define SAS_ECC_INTR_ITCT_ECC_MB_OFF 4 125#define SAS_ECC_INTR_ITCT_ECC_1B_OFF 5 126#define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 6 127#define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 7 128#define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 8 129#define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 9 130#define SAS_ECC_INTR_CQE_ECC_1B_OFF 10 131#define SAS_ECC_INTR_CQE_ECC_MB_OFF 11 132#define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 12 133#define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 13 134#define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 14 135#define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 15 136#define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 16 137#define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 17 138#define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 18 139#define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 19 140#define SAS_ECC_INTR_MSK 0x1ec 141#define HGC_ERR_STAT_EN 0x238 142#define CQE_SEND_CNT 0x248 143#define DLVRY_Q_0_BASE_ADDR_LO 0x260 144#define DLVRY_Q_0_BASE_ADDR_HI 0x264 145#define DLVRY_Q_0_DEPTH 0x268 146#define DLVRY_Q_0_WR_PTR 0x26c 147#define DLVRY_Q_0_RD_PTR 0x270 148#define HYPER_STREAM_ID_EN_CFG 0xc80 149#define OQ0_INT_SRC_MSK 0xc90 150#define COMPL_Q_0_BASE_ADDR_LO 0x4e0 151#define COMPL_Q_0_BASE_ADDR_HI 0x4e4 152#define COMPL_Q_0_DEPTH 0x4e8 153#define COMPL_Q_0_WR_PTR 0x4ec 154#define COMPL_Q_0_RD_PTR 0x4f0 155#define HGC_RXM_DFX_STATUS14 0xae8 156#define HGC_RXM_DFX_STATUS14_MEM0_OFF 0 157#define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff << \ 158 HGC_RXM_DFX_STATUS14_MEM0_OFF) 159#define HGC_RXM_DFX_STATUS14_MEM1_OFF 9 160#define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff << \ 161 HGC_RXM_DFX_STATUS14_MEM1_OFF) 162#define HGC_RXM_DFX_STATUS14_MEM2_OFF 18 163#define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff << \ 164 HGC_RXM_DFX_STATUS14_MEM2_OFF) 165#define HGC_RXM_DFX_STATUS15 0xaec 166#define HGC_RXM_DFX_STATUS15_MEM3_OFF 0 167#define HGC_RXM_DFX_STATUS15_MEM3_MSK (0x1ff << \ 168 HGC_RXM_DFX_STATUS15_MEM3_OFF) 169/* phy registers need init */ 170#define PORT_BASE (0x2000) 171 172#define PHY_CFG (PORT_BASE + 0x0) 173#define HARD_PHY_LINKRATE (PORT_BASE + 0x4) 174#define PHY_CFG_ENA_OFF 0 175#define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF) 176#define PHY_CFG_DC_OPT_OFF 2 177#define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF) 178#define PROG_PHY_LINK_RATE (PORT_BASE + 0x8) 179#define PROG_PHY_LINK_RATE_MAX_OFF 0 180#define PROG_PHY_LINK_RATE_MAX_MSK (0xff << PROG_PHY_LINK_RATE_MAX_OFF) 181#define PHY_CTRL (PORT_BASE + 0x14) 182#define PHY_CTRL_RESET_OFF 0 183#define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF) 184#define SAS_PHY_CTRL (PORT_BASE + 0x20) 185#define SL_CFG (PORT_BASE + 0x84) 186#define PHY_PCN (PORT_BASE + 0x44) 187#define SL_TOUT_CFG (PORT_BASE + 0x8c) 188#define SL_CONTROL (PORT_BASE + 0x94) 189#define SL_CONTROL_NOTIFY_EN_OFF 0 190#define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF) 191#define SL_CONTROL_CTA_OFF 17 192#define SL_CONTROL_CTA_MSK (0x1 << SL_CONTROL_CTA_OFF) 193#define RX_PRIMS_STATUS (PORT_BASE + 0x98) 194#define RX_BCAST_CHG_OFF 1 195#define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF) 196#define TX_ID_DWORD0 (PORT_BASE + 0x9c) 197#define TX_ID_DWORD1 (PORT_BASE + 0xa0) 198#define TX_ID_DWORD2 (PORT_BASE + 0xa4) 199#define TX_ID_DWORD3 (PORT_BASE + 0xa8) 200#define TX_ID_DWORD4 (PORT_BASE + 0xaC) 201#define TX_ID_DWORD5 (PORT_BASE + 0xb0) 202#define TX_ID_DWORD6 (PORT_BASE + 0xb4) 203#define TXID_AUTO (PORT_BASE + 0xb8) 204#define TXID_AUTO_CT3_OFF 1 205#define TXID_AUTO_CT3_MSK (0x1 << TXID_AUTO_CT3_OFF) 206#define TXID_AUTO_CTB_OFF 11 207#define TXID_AUTO_CTB_MSK (0x1 << TXID_AUTO_CTB_OFF) 208#define TX_HARDRST_OFF 2 209#define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF) 210#define RX_IDAF_DWORD0 (PORT_BASE + 0xc4) 211#define RX_IDAF_DWORD1 (PORT_BASE + 0xc8) 212#define RX_IDAF_DWORD2 (PORT_BASE + 0xcc) 213#define RX_IDAF_DWORD3 (PORT_BASE + 0xd0) 214#define RX_IDAF_DWORD4 (PORT_BASE + 0xd4) 215#define RX_IDAF_DWORD5 (PORT_BASE + 0xd8) 216#define RX_IDAF_DWORD6 (PORT_BASE + 0xdc) 217#define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) 218#define CON_CONTROL (PORT_BASE + 0x118) 219#define CON_CONTROL_CFG_OPEN_ACC_STP_OFF 0 220#define CON_CONTROL_CFG_OPEN_ACC_STP_MSK \ 221 (0x01 << CON_CONTROL_CFG_OPEN_ACC_STP_OFF) 222#define DONE_RECEIVED_TIME (PORT_BASE + 0x11c) 223#define CHL_INT0 (PORT_BASE + 0x1b4) 224#define CHL_INT0_HOTPLUG_TOUT_OFF 0 225#define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF) 226#define CHL_INT0_SL_RX_BCST_ACK_OFF 1 227#define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF) 228#define CHL_INT0_SL_PHY_ENABLE_OFF 2 229#define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF) 230#define CHL_INT0_NOT_RDY_OFF 4 231#define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF) 232#define CHL_INT0_PHY_RDY_OFF 5 233#define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF) 234#define CHL_INT1 (PORT_BASE + 0x1b8) 235#define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15 236#define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF) 237#define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17 238#define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF) 239#define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19 240#define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20 241#define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21 242#define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22 243#define CHL_INT2 (PORT_BASE + 0x1bc) 244#define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0 245#define CHL_INT0_MSK (PORT_BASE + 0x1c0) 246#define CHL_INT1_MSK (PORT_BASE + 0x1c4) 247#define CHL_INT2_MSK (PORT_BASE + 0x1c8) 248#define CHL_INT_COAL_EN (PORT_BASE + 0x1d0) 249#define DMA_TX_DFX0 (PORT_BASE + 0x200) 250#define DMA_TX_DFX1 (PORT_BASE + 0x204) 251#define DMA_TX_DFX1_IPTT_OFF 0 252#define DMA_TX_DFX1_IPTT_MSK (0xffff << DMA_TX_DFX1_IPTT_OFF) 253#define DMA_TX_FIFO_DFX0 (PORT_BASE + 0x240) 254#define PORT_DFX0 (PORT_BASE + 0x258) 255#define LINK_DFX2 (PORT_BASE + 0X264) 256#define LINK_DFX2_RCVR_HOLD_STS_OFF 9 257#define LINK_DFX2_RCVR_HOLD_STS_MSK (0x1 << LINK_DFX2_RCVR_HOLD_STS_OFF) 258#define LINK_DFX2_SEND_HOLD_STS_OFF 10 259#define LINK_DFX2_SEND_HOLD_STS_MSK (0x1 << LINK_DFX2_SEND_HOLD_STS_OFF) 260#define SAS_ERR_CNT4_REG (PORT_BASE + 0x290) 261#define SAS_ERR_CNT6_REG (PORT_BASE + 0x298) 262#define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0) 263#define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4) 264#define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8) 265#define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc) 266#define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0) 267#define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4) 268#define DMA_TX_STATUS (PORT_BASE + 0x2d0) 269#define DMA_TX_STATUS_BUSY_OFF 0 270#define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF) 271#define DMA_RX_STATUS (PORT_BASE + 0x2e8) 272#define DMA_RX_STATUS_BUSY_OFF 0 273#define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF) 274 275#define AXI_CFG (0x5100) 276#define AM_CFG_MAX_TRANS (0x5010) 277#define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014) 278 279#define AXI_MASTER_CFG_BASE (0x5000) 280#define AM_CTRL_GLOBAL (0x0) 281#define AM_CURR_TRANS_RETURN (0x150) 282 283/* HW dma structures */ 284/* Delivery queue header */ 285/* dw0 */ 286#define CMD_HDR_ABORT_FLAG_OFF 0 287#define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF) 288#define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2 289#define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) 290#define CMD_HDR_RESP_REPORT_OFF 5 291#define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF) 292#define CMD_HDR_TLR_CTRL_OFF 6 293#define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF) 294#define CMD_HDR_PHY_ID_OFF 8 295#define CMD_HDR_PHY_ID_MSK (0x1ff << CMD_HDR_PHY_ID_OFF) 296#define CMD_HDR_FORCE_PHY_OFF 17 297#define CMD_HDR_FORCE_PHY_MSK (0x1 << CMD_HDR_FORCE_PHY_OFF) 298#define CMD_HDR_PORT_OFF 18 299#define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF) 300#define CMD_HDR_PRIORITY_OFF 27 301#define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF) 302#define CMD_HDR_CMD_OFF 29 303#define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF) 304/* dw1 */ 305#define CMD_HDR_DIR_OFF 5 306#define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF) 307#define CMD_HDR_RESET_OFF 7 308#define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF) 309#define CMD_HDR_VDTL_OFF 10 310#define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF) 311#define CMD_HDR_FRAME_TYPE_OFF 11 312#define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF) 313#define CMD_HDR_DEV_ID_OFF 16 314#define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF) 315/* dw2 */ 316#define CMD_HDR_CFL_OFF 0 317#define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF) 318#define CMD_HDR_NCQ_TAG_OFF 10 319#define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF) 320#define CMD_HDR_MRFL_OFF 15 321#define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF) 322#define CMD_HDR_SG_MOD_OFF 24 323#define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF) 324#define CMD_HDR_FIRST_BURST_OFF 26 325#define CMD_HDR_FIRST_BURST_MSK (0x1 << CMD_HDR_SG_MOD_OFF) 326/* dw3 */ 327#define CMD_HDR_IPTT_OFF 0 328#define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF) 329/* dw6 */ 330#define CMD_HDR_DIF_SGL_LEN_OFF 0 331#define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF) 332#define CMD_HDR_DATA_SGL_LEN_OFF 16 333#define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF) 334#define CMD_HDR_ABORT_IPTT_OFF 16 335#define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF) 336 337/* Completion header */ 338/* dw0 */ 339#define CMPLT_HDR_ERR_PHASE_OFF 2 340#define CMPLT_HDR_ERR_PHASE_MSK (0xff << CMPLT_HDR_ERR_PHASE_OFF) 341#define CMPLT_HDR_RSPNS_XFRD_OFF 10 342#define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF) 343#define CMPLT_HDR_ERX_OFF 12 344#define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF) 345#define CMPLT_HDR_ABORT_STAT_OFF 13 346#define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF) 347/* abort_stat */ 348#define STAT_IO_NOT_VALID 0x1 349#define STAT_IO_NO_DEVICE 0x2 350#define STAT_IO_COMPLETE 0x3 351#define STAT_IO_ABORTED 0x4 352/* dw1 */ 353#define CMPLT_HDR_IPTT_OFF 0 354#define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF) 355#define CMPLT_HDR_DEV_ID_OFF 16 356#define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF) 357 358/* ITCT header */ 359/* qw0 */ 360#define ITCT_HDR_DEV_TYPE_OFF 0 361#define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF) 362#define ITCT_HDR_VALID_OFF 2 363#define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF) 364#define ITCT_HDR_MCR_OFF 5 365#define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF) 366#define ITCT_HDR_VLN_OFF 9 367#define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF) 368#define ITCT_HDR_SMP_TIMEOUT_OFF 16 369#define ITCT_HDR_SMP_TIMEOUT_8US 1 370#define ITCT_HDR_SMP_TIMEOUT (ITCT_HDR_SMP_TIMEOUT_8US * \ 371 250) /* 2ms */ 372#define ITCT_HDR_AWT_CONTINUE_OFF 25 373#define ITCT_HDR_PORT_ID_OFF 28 374#define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF) 375/* qw2 */ 376#define ITCT_HDR_INLT_OFF 0 377#define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF) 378#define ITCT_HDR_BITLT_OFF 16 379#define ITCT_HDR_BITLT_MSK (0xffffULL << ITCT_HDR_BITLT_OFF) 380#define ITCT_HDR_MCTLT_OFF 32 381#define ITCT_HDR_MCTLT_MSK (0xffffULL << ITCT_HDR_MCTLT_OFF) 382#define ITCT_HDR_RTOLT_OFF 48 383#define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF) 384 385#define HISI_SAS_FATAL_INT_NR 2 386 387struct hisi_sas_complete_v2_hdr { 388 __le32 dw0; 389 __le32 dw1; 390 __le32 act; 391 __le32 dw3; 392}; 393 394struct hisi_sas_err_record_v2 { 395 /* dw0 */ 396 __le32 trans_tx_fail_type; 397 398 /* dw1 */ 399 __le32 trans_rx_fail_type; 400 401 /* dw2 */ 402 __le16 dma_tx_err_type; 403 __le16 sipc_rx_err_type; 404 405 /* dw3 */ 406 __le32 dma_rx_err_type; 407}; 408 409struct signal_attenuation_s { 410 u32 de_emphasis; 411 u32 preshoot; 412 u32 boost; 413}; 414 415struct sig_atten_lu_s { 416 const struct signal_attenuation_s *att; 417 u32 sas_phy_ctrl; 418}; 419 420static const struct hisi_sas_hw_error one_bit_ecc_errors[] = { 421 { 422 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF), 423 .msk = HGC_DQE_ECC_1B_ADDR_MSK, 424 .shift = HGC_DQE_ECC_1B_ADDR_OFF, 425 .msg = "hgc_dqe_ecc1b_intr", 426 .reg = HGC_DQE_ECC_ADDR, 427 }, 428 { 429 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF), 430 .msk = HGC_IOST_ECC_1B_ADDR_MSK, 431 .shift = HGC_IOST_ECC_1B_ADDR_OFF, 432 .msg = "hgc_iost_ecc1b_intr", 433 .reg = HGC_IOST_ECC_ADDR, 434 }, 435 { 436 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF), 437 .msk = HGC_ITCT_ECC_1B_ADDR_MSK, 438 .shift = HGC_ITCT_ECC_1B_ADDR_OFF, 439 .msg = "hgc_itct_ecc1b_intr", 440 .reg = HGC_ITCT_ECC_ADDR, 441 }, 442 { 443 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF), 444 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK, 445 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF, 446 .msg = "hgc_iostl_ecc1b_intr", 447 .reg = HGC_LM_DFX_STATUS2, 448 }, 449 { 450 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF), 451 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK, 452 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF, 453 .msg = "hgc_itctl_ecc1b_intr", 454 .reg = HGC_LM_DFX_STATUS2, 455 }, 456 { 457 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF), 458 .msk = HGC_CQE_ECC_1B_ADDR_MSK, 459 .shift = HGC_CQE_ECC_1B_ADDR_OFF, 460 .msg = "hgc_cqe_ecc1b_intr", 461 .reg = HGC_CQE_ECC_ADDR, 462 }, 463 { 464 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF), 465 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK, 466 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF, 467 .msg = "rxm_mem0_ecc1b_intr", 468 .reg = HGC_RXM_DFX_STATUS14, 469 }, 470 { 471 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF), 472 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK, 473 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF, 474 .msg = "rxm_mem1_ecc1b_intr", 475 .reg = HGC_RXM_DFX_STATUS14, 476 }, 477 { 478 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF), 479 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK, 480 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF, 481 .msg = "rxm_mem2_ecc1b_intr", 482 .reg = HGC_RXM_DFX_STATUS14, 483 }, 484 { 485 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF), 486 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK, 487 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF, 488 .msg = "rxm_mem3_ecc1b_intr", 489 .reg = HGC_RXM_DFX_STATUS15, 490 }, 491}; 492 493static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = { 494 { 495 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF), 496 .msk = HGC_DQE_ECC_MB_ADDR_MSK, 497 .shift = HGC_DQE_ECC_MB_ADDR_OFF, 498 .msg = "hgc_dqe_eccbad_intr", 499 .reg = HGC_DQE_ECC_ADDR, 500 }, 501 { 502 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF), 503 .msk = HGC_IOST_ECC_MB_ADDR_MSK, 504 .shift = HGC_IOST_ECC_MB_ADDR_OFF, 505 .msg = "hgc_iost_eccbad_intr", 506 .reg = HGC_IOST_ECC_ADDR, 507 }, 508 { 509 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF), 510 .msk = HGC_ITCT_ECC_MB_ADDR_MSK, 511 .shift = HGC_ITCT_ECC_MB_ADDR_OFF, 512 .msg = "hgc_itct_eccbad_intr", 513 .reg = HGC_ITCT_ECC_ADDR, 514 }, 515 { 516 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF), 517 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK, 518 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF, 519 .msg = "hgc_iostl_eccbad_intr", 520 .reg = HGC_LM_DFX_STATUS2, 521 }, 522 { 523 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF), 524 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK, 525 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF, 526 .msg = "hgc_itctl_eccbad_intr", 527 .reg = HGC_LM_DFX_STATUS2, 528 }, 529 { 530 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF), 531 .msk = HGC_CQE_ECC_MB_ADDR_MSK, 532 .shift = HGC_CQE_ECC_MB_ADDR_OFF, 533 .msg = "hgc_cqe_eccbad_intr", 534 .reg = HGC_CQE_ECC_ADDR, 535 }, 536 { 537 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF), 538 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK, 539 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF, 540 .msg = "rxm_mem0_eccbad_intr", 541 .reg = HGC_RXM_DFX_STATUS14, 542 }, 543 { 544 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF), 545 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK, 546 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF, 547 .msg = "rxm_mem1_eccbad_intr", 548 .reg = HGC_RXM_DFX_STATUS14, 549 }, 550 { 551 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF), 552 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK, 553 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF, 554 .msg = "rxm_mem2_eccbad_intr", 555 .reg = HGC_RXM_DFX_STATUS14, 556 }, 557 { 558 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF), 559 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK, 560 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF, 561 .msg = "rxm_mem3_eccbad_intr", 562 .reg = HGC_RXM_DFX_STATUS15, 563 }, 564}; 565 566enum { 567 HISI_SAS_PHY_PHY_UPDOWN, 568 HISI_SAS_PHY_CHNL_INT, 569 HISI_SAS_PHY_INT_NR 570}; 571 572enum { 573 TRANS_TX_FAIL_BASE = 0x0, /* dw0 */ 574 TRANS_RX_FAIL_BASE = 0x20, /* dw1 */ 575 DMA_TX_ERR_BASE = 0x40, /* dw2 bit 15-0 */ 576 SIPC_RX_ERR_BASE = 0x50, /* dw2 bit 31-16*/ 577 DMA_RX_ERR_BASE = 0x60, /* dw3 */ 578 579 /* trans tx*/ 580 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS = TRANS_TX_FAIL_BASE, /* 0x0 */ 581 TRANS_TX_ERR_PHY_NOT_ENABLE, /* 0x1 */ 582 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION, /* 0x2 */ 583 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION, /* 0x3 */ 584 TRANS_TX_OPEN_CNX_ERR_BY_OTHER, /* 0x4 */ 585 RESERVED0, /* 0x5 */ 586 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT, /* 0x6 */ 587 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY, /* 0x7 */ 588 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED, /* 0x8 */ 589 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED, /* 0x9 */ 590 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION, /* 0xa */ 591 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD, /* 0xb */ 592 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER, /* 0xc */ 593 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED, /* 0xd */ 594 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT, /* 0xe */ 595 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION, /* 0xf */ 596 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED, /* 0x10 */ 597 TRANS_TX_ERR_FRAME_TXED, /* 0x11 */ 598 TRANS_TX_ERR_WITH_BREAK_TIMEOUT, /* 0x12 */ 599 TRANS_TX_ERR_WITH_BREAK_REQUEST, /* 0x13 */ 600 TRANS_TX_ERR_WITH_BREAK_RECEVIED, /* 0x14 */ 601 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT, /* 0x15 */ 602 TRANS_TX_ERR_WITH_CLOSE_NORMAL, /* 0x16 for ssp*/ 603 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE, /* 0x17 */ 604 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x18 */ 605 TRANS_TX_ERR_WITH_CLOSE_COMINIT, /* 0x19 */ 606 TRANS_TX_ERR_WITH_NAK_RECEVIED, /* 0x1a for ssp*/ 607 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT, /* 0x1b for ssp*/ 608 /*IO_TX_ERR_WITH_R_ERR_RECEVIED, [> 0x1b for sata/stp<] */ 609 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT, /* 0x1c for ssp */ 610 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST 0x1c for sata/stp */ 611 TRANS_TX_ERR_WITH_IPTT_CONFLICT, /* 0x1d for ssp/smp */ 612 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS, /* 0x1e */ 613 /*IO_TX_ERR_WITH_SYNC_RXD, [> 0x1e <] for sata/stp */ 614 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT, /* 0x1f for sata/stp */ 615 616 /* trans rx */ 617 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x20 */ 618 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR, /* 0x21 for sata/stp */ 619 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM, /* 0x22 for ssp/smp */ 620 /*IO_ERR_WITH_RXFIS_8B10B_CODE_ERR, [> 0x22 <] for sata/stp */ 621 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR, /* 0x23 for sata/stp */ 622 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR, /* 0x24 for sata/stp */ 623 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN, /* 0x25 for smp */ 624 /*IO_ERR_WITH_RXFIS_TX SYNCP, [> 0x25 <] for sata/stp */ 625 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP, /* 0x26 for sata/stp*/ 626 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN, /* 0x27 */ 627 TRANS_RX_ERR_WITH_BREAK_TIMEOUT, /* 0x28 */ 628 TRANS_RX_ERR_WITH_BREAK_REQUEST, /* 0x29 */ 629 TRANS_RX_ERR_WITH_BREAK_RECEVIED, /* 0x2a */ 630 RESERVED1, /* 0x2b */ 631 TRANS_RX_ERR_WITH_CLOSE_NORMAL, /* 0x2c */ 632 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE, /* 0x2d */ 633 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x2e */ 634 TRANS_RX_ERR_WITH_CLOSE_COMINIT, /* 0x2f */ 635 TRANS_RX_ERR_WITH_DATA_LEN0, /* 0x30 for ssp/smp */ 636 TRANS_RX_ERR_WITH_BAD_HASH, /* 0x31 for ssp */ 637 /*IO_RX_ERR_WITH_FIS_TOO_SHORT, [> 0x31 <] for sata/stp */ 638 TRANS_RX_XRDY_WLEN_ZERO_ERR, /* 0x32 for ssp*/ 639 /*IO_RX_ERR_WITH_FIS_TOO_LONG, [> 0x32 <] for sata/stp */ 640 TRANS_RX_SSP_FRM_LEN_ERR, /* 0x33 for ssp */ 641 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST, [> 0x33 <] for sata */ 642 RESERVED2, /* 0x34 */ 643 RESERVED3, /* 0x35 */ 644 RESERVED4, /* 0x36 */ 645 RESERVED5, /* 0x37 */ 646 TRANS_RX_ERR_WITH_BAD_FRM_TYPE, /* 0x38 */ 647 TRANS_RX_SMP_FRM_LEN_ERR, /* 0x39 */ 648 TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x3a */ 649 RESERVED6, /* 0x3b */ 650 RESERVED7, /* 0x3c */ 651 RESERVED8, /* 0x3d */ 652 RESERVED9, /* 0x3e */ 653 TRANS_RX_R_ERR, /* 0x3f */ 654 655 /* dma tx */ 656 DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x40 */ 657 DMA_TX_DIF_APP_ERR, /* 0x41 */ 658 DMA_TX_DIF_RPP_ERR, /* 0x42 */ 659 DMA_TX_DATA_SGL_OVERFLOW, /* 0x43 */ 660 DMA_TX_DIF_SGL_OVERFLOW, /* 0x44 */ 661 DMA_TX_UNEXP_XFER_ERR, /* 0x45 */ 662 DMA_TX_UNEXP_RETRANS_ERR, /* 0x46 */ 663 DMA_TX_XFER_LEN_OVERFLOW, /* 0x47 */ 664 DMA_TX_XFER_OFFSET_ERR, /* 0x48 */ 665 DMA_TX_RAM_ECC_ERR, /* 0x49 */ 666 DMA_TX_DIF_LEN_ALIGN_ERR, /* 0x4a */ 667 DMA_TX_MAX_ERR_CODE, 668 669 /* sipc rx */ 670 SIPC_RX_FIS_STATUS_ERR_BIT_VLD = SIPC_RX_ERR_BASE, /* 0x50 */ 671 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR, /* 0x51 */ 672 SIPC_RX_FIS_STATUS_BSY_BIT_ERR, /* 0x52 */ 673 SIPC_RX_WRSETUP_LEN_ODD_ERR, /* 0x53 */ 674 SIPC_RX_WRSETUP_LEN_ZERO_ERR, /* 0x54 */ 675 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR, /* 0x55 */ 676 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR, /* 0x56 */ 677 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR, /* 0x57 */ 678 SIPC_RX_SATA_UNEXP_FIS_ERR, /* 0x58 */ 679 SIPC_RX_WRSETUP_ESTATUS_ERR, /* 0x59 */ 680 SIPC_RX_DATA_UNDERFLOW_ERR, /* 0x5a */ 681 SIPC_RX_MAX_ERR_CODE, 682 683 /* dma rx */ 684 DMA_RX_DIF_CRC_ERR = DMA_RX_ERR_BASE, /* 0x60 */ 685 DMA_RX_DIF_APP_ERR, /* 0x61 */ 686 DMA_RX_DIF_RPP_ERR, /* 0x62 */ 687 DMA_RX_DATA_SGL_OVERFLOW, /* 0x63 */ 688 DMA_RX_DIF_SGL_OVERFLOW, /* 0x64 */ 689 DMA_RX_DATA_LEN_OVERFLOW, /* 0x65 */ 690 DMA_RX_DATA_LEN_UNDERFLOW, /* 0x66 */ 691 DMA_RX_DATA_OFFSET_ERR, /* 0x67 */ 692 RESERVED10, /* 0x68 */ 693 DMA_RX_SATA_FRAME_TYPE_ERR, /* 0x69 */ 694 DMA_RX_RESP_BUF_OVERFLOW, /* 0x6a */ 695 DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x6b */ 696 DMA_RX_UNEXP_NORM_RESP_ERR, /* 0x6c */ 697 DMA_RX_UNEXP_RDFRAME_ERR, /* 0x6d */ 698 DMA_RX_PIO_DATA_LEN_ERR, /* 0x6e */ 699 DMA_RX_RDSETUP_STATUS_ERR, /* 0x6f */ 700 DMA_RX_RDSETUP_STATUS_DRQ_ERR, /* 0x70 */ 701 DMA_RX_RDSETUP_STATUS_BSY_ERR, /* 0x71 */ 702 DMA_RX_RDSETUP_LEN_ODD_ERR, /* 0x72 */ 703 DMA_RX_RDSETUP_LEN_ZERO_ERR, /* 0x73 */ 704 DMA_RX_RDSETUP_LEN_OVER_ERR, /* 0x74 */ 705 DMA_RX_RDSETUP_OFFSET_ERR, /* 0x75 */ 706 DMA_RX_RDSETUP_ACTIVE_ERR, /* 0x76 */ 707 DMA_RX_RDSETUP_ESTATUS_ERR, /* 0x77 */ 708 DMA_RX_RAM_ECC_ERR, /* 0x78 */ 709 DMA_RX_UNKNOWN_FRM_ERR, /* 0x79 */ 710 DMA_RX_MAX_ERR_CODE, 711}; 712 713#define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096 714#define HISI_MAX_SATA_SUPPORT_V2_HW (HISI_SAS_COMMAND_ENTRIES_V2_HW/64 - 1) 715 716#define DIR_NO_DATA 0 717#define DIR_TO_INI 1 718#define DIR_TO_DEVICE 2 719#define DIR_RESERVED 3 720 721#define ERR_ON_TX_PHASE(err_phase) (err_phase == 0x2 || \ 722 err_phase == 0x4 || err_phase == 0x8 ||\ 723 err_phase == 0x6 || err_phase == 0xa) 724#define ERR_ON_RX_PHASE(err_phase) (err_phase == 0x10 || \ 725 err_phase == 0x20 || err_phase == 0x40) 726 727static void link_timeout_disable_link(struct timer_list *t); 728 729static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) 730{ 731 void __iomem *regs = hisi_hba->regs + off; 732 733 return readl(regs); 734} 735 736static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off) 737{ 738 void __iomem *regs = hisi_hba->regs + off; 739 740 return readl_relaxed(regs); 741} 742 743static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val) 744{ 745 void __iomem *regs = hisi_hba->regs + off; 746 747 writel(val, regs); 748} 749 750static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no, 751 u32 off, u32 val) 752{ 753 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 754 755 writel(val, regs); 756} 757 758static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba, 759 int phy_no, u32 off) 760{ 761 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 762 763 return readl(regs); 764} 765 766/* This function needs to be protected from pre-emption. */ 767static int 768slot_index_alloc_quirk_v2_hw(struct hisi_hba *hisi_hba, 769 struct domain_device *device) 770{ 771 int sata_dev = dev_is_sata(device); 772 void *bitmap = hisi_hba->slot_index_tags; 773 struct hisi_sas_device *sas_dev = device->lldd_dev; 774 int sata_idx = sas_dev->sata_idx; 775 int start, end; 776 777 if (!sata_dev) { 778 /* 779 * STP link SoC bug workaround: index starts from 1. 780 * additionally, we can only allocate odd IPTT(1~4095) 781 * for SAS/SMP device. 782 */ 783 start = 1; 784 end = hisi_hba->slot_index_count; 785 } else { 786 if (sata_idx >= HISI_MAX_SATA_SUPPORT_V2_HW) 787 return -EINVAL; 788 789 /* 790 * For SATA device: allocate even IPTT in this interval 791 * [64*(sata_idx+1), 64*(sata_idx+2)], then each SATA device 792 * own 32 IPTTs. IPTT 0 shall not be used duing to STP link 793 * SoC bug workaround. So we ignore the first 32 even IPTTs. 794 */ 795 start = 64 * (sata_idx + 1); 796 end = 64 * (sata_idx + 2); 797 } 798 799 spin_lock(&hisi_hba->lock); 800 while (1) { 801 start = find_next_zero_bit(bitmap, 802 hisi_hba->slot_index_count, start); 803 if (start >= end) { 804 spin_unlock(&hisi_hba->lock); 805 return -SAS_QUEUE_FULL; 806 } 807 /* 808 * SAS IPTT bit0 should be 1, and SATA IPTT bit0 should be 0. 809 */ 810 if (sata_dev ^ (start & 1)) 811 break; 812 start++; 813 } 814 815 set_bit(start, bitmap); 816 spin_unlock(&hisi_hba->lock); 817 return start; 818} 819 820static bool sata_index_alloc_v2_hw(struct hisi_hba *hisi_hba, int *idx) 821{ 822 unsigned int index; 823 struct device *dev = hisi_hba->dev; 824 void *bitmap = hisi_hba->sata_dev_bitmap; 825 826 index = find_first_zero_bit(bitmap, HISI_MAX_SATA_SUPPORT_V2_HW); 827 if (index >= HISI_MAX_SATA_SUPPORT_V2_HW) { 828 dev_warn(dev, "alloc sata index failed, index=%d\n", index); 829 return false; 830 } 831 832 set_bit(index, bitmap); 833 *idx = index; 834 return true; 835} 836 837 838static struct 839hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device) 840{ 841 struct hisi_hba *hisi_hba = device->port->ha->lldd_ha; 842 struct hisi_sas_device *sas_dev = NULL; 843 int i, sata_dev = dev_is_sata(device); 844 int sata_idx = -1; 845 846 spin_lock(&hisi_hba->lock); 847 848 if (sata_dev) 849 if (!sata_index_alloc_v2_hw(hisi_hba, &sata_idx)) 850 goto out; 851 852 for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) { 853 /* 854 * SATA device id bit0 should be 0 855 */ 856 if (sata_dev && (i & 1)) 857 continue; 858 if (hisi_hba->devices[i].dev_type == SAS_PHY_UNUSED) { 859 int queue = i % hisi_hba->queue_count; 860 struct hisi_sas_dq *dq = &hisi_hba->dq[queue]; 861 862 hisi_hba->devices[i].device_id = i; 863 sas_dev = &hisi_hba->devices[i]; 864 sas_dev->dev_status = HISI_SAS_DEV_INIT; 865 sas_dev->dev_type = device->dev_type; 866 sas_dev->hisi_hba = hisi_hba; 867 sas_dev->sas_device = device; 868 sas_dev->sata_idx = sata_idx; 869 sas_dev->dq = dq; 870 spin_lock_init(&sas_dev->lock); 871 INIT_LIST_HEAD(&hisi_hba->devices[i].list); 872 break; 873 } 874 } 875 876out: 877 spin_unlock(&hisi_hba->lock); 878 879 return sas_dev; 880} 881 882static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 883{ 884 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 885 886 cfg &= ~PHY_CFG_DC_OPT_MSK; 887 cfg |= 1 << PHY_CFG_DC_OPT_OFF; 888 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 889} 890 891static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 892{ 893 struct sas_identify_frame identify_frame; 894 u32 *identify_buffer; 895 896 memset(&identify_frame, 0, sizeof(identify_frame)); 897 identify_frame.dev_type = SAS_END_DEVICE; 898 identify_frame.frame_type = 0; 899 identify_frame._un1 = 1; 900 identify_frame.initiator_bits = SAS_PROTOCOL_ALL; 901 identify_frame.target_bits = SAS_PROTOCOL_NONE; 902 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 903 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 904 identify_frame.phy_id = phy_no; 905 identify_buffer = (u32 *)(&identify_frame); 906 907 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0, 908 __swab32(identify_buffer[0])); 909 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1, 910 __swab32(identify_buffer[1])); 911 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2, 912 __swab32(identify_buffer[2])); 913 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3, 914 __swab32(identify_buffer[3])); 915 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4, 916 __swab32(identify_buffer[4])); 917 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5, 918 __swab32(identify_buffer[5])); 919} 920 921static void setup_itct_v2_hw(struct hisi_hba *hisi_hba, 922 struct hisi_sas_device *sas_dev) 923{ 924 struct domain_device *device = sas_dev->sas_device; 925 struct device *dev = hisi_hba->dev; 926 u64 qw0, device_id = sas_dev->device_id; 927 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id]; 928 struct asd_sas_port *sas_port = device->port; 929 struct hisi_sas_port *port = to_hisi_sas_port(sas_port); 930 u64 sas_addr; 931 932 memset(itct, 0, sizeof(*itct)); 933 934 /* qw0 */ 935 qw0 = 0; 936 switch (sas_dev->dev_type) { 937 case SAS_END_DEVICE: 938 case SAS_EDGE_EXPANDER_DEVICE: 939 case SAS_FANOUT_EXPANDER_DEVICE: 940 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF; 941 break; 942 case SAS_SATA_DEV: 943 case SAS_SATA_PENDING: 944 if (dev_parent_is_expander(device)) 945 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF; 946 else 947 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF; 948 break; 949 default: 950 dev_warn(dev, "setup itct: unsupported dev type (%d)\n", 951 sas_dev->dev_type); 952 } 953 954 qw0 |= ((1 << ITCT_HDR_VALID_OFF) | 955 (device->linkrate << ITCT_HDR_MCR_OFF) | 956 (1 << ITCT_HDR_VLN_OFF) | 957 (ITCT_HDR_SMP_TIMEOUT << ITCT_HDR_SMP_TIMEOUT_OFF) | 958 (1 << ITCT_HDR_AWT_CONTINUE_OFF) | 959 (port->id << ITCT_HDR_PORT_ID_OFF)); 960 itct->qw0 = cpu_to_le64(qw0); 961 962 /* qw1 */ 963 memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE); 964 itct->sas_addr = cpu_to_le64(__swab64(sas_addr)); 965 966 /* qw2 */ 967 if (!dev_is_sata(device)) 968 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) | 969 (0x1ULL << ITCT_HDR_BITLT_OFF) | 970 (0x32ULL << ITCT_HDR_MCTLT_OFF) | 971 (0x1ULL << ITCT_HDR_RTOLT_OFF)); 972} 973 974static int clear_itct_v2_hw(struct hisi_hba *hisi_hba, 975 struct hisi_sas_device *sas_dev) 976{ 977 DECLARE_COMPLETION_ONSTACK(completion); 978 u64 dev_id = sas_dev->device_id; 979 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id]; 980 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 981 struct device *dev = hisi_hba->dev; 982 int i; 983 984 sas_dev->completion = &completion; 985 986 /* clear the itct interrupt state */ 987 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) 988 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 989 ENT_INT_SRC3_ITC_INT_MSK); 990 991 /* need to set register twice to clear ITCT for v2 hw */ 992 for (i = 0; i < 2; i++) { 993 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK); 994 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val); 995 if (!wait_for_completion_timeout(sas_dev->completion, 996 HISI_SAS_CLEAR_ITCT_TIMEOUT)) { 997 dev_warn(dev, "failed to clear ITCT\n"); 998 return -ETIMEDOUT; 999 } 1000 1001 memset(itct, 0, sizeof(struct hisi_sas_itct)); 1002 } 1003 return 0; 1004} 1005 1006static void free_device_v2_hw(struct hisi_sas_device *sas_dev) 1007{ 1008 struct hisi_hba *hisi_hba = sas_dev->hisi_hba; 1009 1010 /* SoC bug workaround */ 1011 if (dev_is_sata(sas_dev->sas_device)) 1012 clear_bit(sas_dev->sata_idx, hisi_hba->sata_dev_bitmap); 1013} 1014 1015static int reset_hw_v2_hw(struct hisi_hba *hisi_hba) 1016{ 1017 int i, reset_val; 1018 u32 val; 1019 unsigned long end_time; 1020 struct device *dev = hisi_hba->dev; 1021 1022 /* The mask needs to be set depending on the number of phys */ 1023 if (hisi_hba->n_phy == 9) 1024 reset_val = 0x1fffff; 1025 else 1026 reset_val = 0x7ffff; 1027 1028 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0); 1029 1030 /* Disable all of the PHYs */ 1031 for (i = 0; i < hisi_hba->n_phy; i++) { 1032 u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG); 1033 1034 phy_cfg &= ~PHY_CTRL_RESET_MSK; 1035 hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg); 1036 } 1037 udelay(50); 1038 1039 /* Ensure DMA tx & rx idle */ 1040 for (i = 0; i < hisi_hba->n_phy; i++) { 1041 u32 dma_tx_status, dma_rx_status; 1042 1043 end_time = jiffies + msecs_to_jiffies(1000); 1044 1045 while (1) { 1046 dma_tx_status = hisi_sas_phy_read32(hisi_hba, i, 1047 DMA_TX_STATUS); 1048 dma_rx_status = hisi_sas_phy_read32(hisi_hba, i, 1049 DMA_RX_STATUS); 1050 1051 if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) && 1052 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK)) 1053 break; 1054 1055 msleep(20); 1056 if (time_after(jiffies, end_time)) 1057 return -EIO; 1058 } 1059 } 1060 1061 /* Ensure axi bus idle */ 1062 end_time = jiffies + msecs_to_jiffies(1000); 1063 while (1) { 1064 u32 axi_status = 1065 hisi_sas_read32(hisi_hba, AXI_CFG); 1066 1067 if (axi_status == 0) 1068 break; 1069 1070 msleep(20); 1071 if (time_after(jiffies, end_time)) 1072 return -EIO; 1073 } 1074 1075 if (ACPI_HANDLE(dev)) { 1076 acpi_status s; 1077 1078 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL); 1079 if (ACPI_FAILURE(s)) { 1080 dev_err(dev, "Reset failed\n"); 1081 return -EIO; 1082 } 1083 } else if (hisi_hba->ctrl) { 1084 /* reset and disable clock*/ 1085 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg, 1086 reset_val); 1087 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4, 1088 reset_val); 1089 msleep(1); 1090 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val); 1091 if (reset_val != (val & reset_val)) { 1092 dev_err(dev, "SAS reset fail.\n"); 1093 return -EIO; 1094 } 1095 1096 /* De-reset and enable clock*/ 1097 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4, 1098 reset_val); 1099 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg, 1100 reset_val); 1101 msleep(1); 1102 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, 1103 &val); 1104 if (val & reset_val) { 1105 dev_err(dev, "SAS de-reset fail.\n"); 1106 return -EIO; 1107 } 1108 } else { 1109 dev_err(dev, "no reset method\n"); 1110 return -EINVAL; 1111 } 1112 1113 return 0; 1114} 1115 1116/* This function needs to be called after resetting SAS controller. */ 1117static void phys_reject_stp_links_v2_hw(struct hisi_hba *hisi_hba) 1118{ 1119 u32 cfg; 1120 int phy_no; 1121 1122 hisi_hba->reject_stp_links_msk = (1 << hisi_hba->n_phy) - 1; 1123 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) { 1124 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, CON_CONTROL); 1125 if (!(cfg & CON_CONTROL_CFG_OPEN_ACC_STP_MSK)) 1126 continue; 1127 1128 cfg &= ~CON_CONTROL_CFG_OPEN_ACC_STP_MSK; 1129 hisi_sas_phy_write32(hisi_hba, phy_no, CON_CONTROL, cfg); 1130 } 1131} 1132 1133static void phys_try_accept_stp_links_v2_hw(struct hisi_hba *hisi_hba) 1134{ 1135 int phy_no; 1136 u32 dma_tx_dfx1; 1137 1138 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) { 1139 if (!(hisi_hba->reject_stp_links_msk & BIT(phy_no))) 1140 continue; 1141 1142 dma_tx_dfx1 = hisi_sas_phy_read32(hisi_hba, phy_no, 1143 DMA_TX_DFX1); 1144 if (dma_tx_dfx1 & DMA_TX_DFX1_IPTT_MSK) { 1145 u32 cfg = hisi_sas_phy_read32(hisi_hba, 1146 phy_no, CON_CONTROL); 1147 1148 cfg |= CON_CONTROL_CFG_OPEN_ACC_STP_MSK; 1149 hisi_sas_phy_write32(hisi_hba, phy_no, 1150 CON_CONTROL, cfg); 1151 clear_bit(phy_no, &hisi_hba->reject_stp_links_msk); 1152 } 1153 } 1154} 1155 1156static const struct signal_attenuation_s x6000 = {9200, 0, 10476}; 1157static const struct sig_atten_lu_s sig_atten_lu[] = { 1158 { &x6000, 0x3016a68 }, 1159}; 1160 1161static void init_reg_v2_hw(struct hisi_hba *hisi_hba) 1162{ 1163 struct device *dev = hisi_hba->dev; 1164 u32 sas_phy_ctrl = 0x30b9908; 1165 u32 signal[3]; 1166 int i; 1167 1168 /* Global registers init */ 1169 1170 /* Deal with am-max-transmissions quirk */ 1171 if (device_property_present(dev, "hip06-sas-v2-quirk-amt")) { 1172 hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020); 1173 hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS, 1174 0x2020); 1175 } /* Else, use defaults -> do nothing */ 1176 1177 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 1178 (u32)((1ULL << hisi_hba->queue_count) - 1)); 1179 hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000); 1180 hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000); 1181 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x0); 1182 hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF); 1183 hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1); 1184 hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4); 1185 hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x32); 1186 hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1); 1187 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1); 1188 hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1); 1189 hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1); 1190 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0xc); 1191 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x60); 1192 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x3); 1193 hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1); 1194 hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1); 1195 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0); 1196 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff); 1197 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff); 1198 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff); 1199 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe); 1200 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe); 1201 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffe20fe); 1202 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfff00c30); 1203 for (i = 0; i < hisi_hba->queue_count; i++) 1204 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0); 1205 1206 hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1); 1207 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1); 1208 1209 /* Get sas_phy_ctrl value to deal with TX FFE issue. */ 1210 if (!device_property_read_u32_array(dev, "hisilicon,signal-attenuation", 1211 signal, ARRAY_SIZE(signal))) { 1212 for (i = 0; i < ARRAY_SIZE(sig_atten_lu); i++) { 1213 const struct sig_atten_lu_s *lookup = &sig_atten_lu[i]; 1214 const struct signal_attenuation_s *att = lookup->att; 1215 1216 if ((signal[0] == att->de_emphasis) && 1217 (signal[1] == att->preshoot) && 1218 (signal[2] == att->boost)) { 1219 sas_phy_ctrl = lookup->sas_phy_ctrl; 1220 break; 1221 } 1222 } 1223 1224 if (i == ARRAY_SIZE(sig_atten_lu)) 1225 dev_warn(dev, "unknown signal attenuation values, using default PHY ctrl config\n"); 1226 } 1227 1228 for (i = 0; i < hisi_hba->n_phy; i++) { 1229 struct hisi_sas_phy *phy = &hisi_hba->phy[i]; 1230 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1231 u32 prog_phy_link_rate = 0x800; 1232 1233 if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate < 1234 SAS_LINK_RATE_1_5_GBPS)) { 1235 prog_phy_link_rate = 0x855; 1236 } else { 1237 enum sas_linkrate max = sas_phy->phy->maximum_linkrate; 1238 1239 prog_phy_link_rate = 1240 hisi_sas_get_prog_phy_linkrate_mask(max) | 1241 0x800; 1242 } 1243 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 1244 prog_phy_link_rate); 1245 hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, sas_phy_ctrl); 1246 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d); 1247 hisi_sas_phy_write32(hisi_hba, i, SL_CONTROL, 0x0); 1248 hisi_sas_phy_write32(hisi_hba, i, TXID_AUTO, 0x2); 1249 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x8); 1250 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff); 1251 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff); 1252 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xfff87fff); 1253 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000); 1254 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xff857fff); 1255 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbfe); 1256 hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x13f801fc); 1257 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0); 1258 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0); 1259 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0); 1260 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0); 1261 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0); 1262 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0); 1263 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0); 1264 if (hisi_hba->refclk_frequency_mhz == 66) 1265 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694); 1266 /* else, do nothing -> leave it how you found it */ 1267 } 1268 1269 for (i = 0; i < hisi_hba->queue_count; i++) { 1270 /* Delivery queue */ 1271 hisi_sas_write32(hisi_hba, 1272 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14), 1273 upper_32_bits(hisi_hba->cmd_hdr_dma[i])); 1274 1275 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14), 1276 lower_32_bits(hisi_hba->cmd_hdr_dma[i])); 1277 1278 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14), 1279 HISI_SAS_QUEUE_SLOTS); 1280 1281 /* Completion queue */ 1282 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14), 1283 upper_32_bits(hisi_hba->complete_hdr_dma[i])); 1284 1285 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14), 1286 lower_32_bits(hisi_hba->complete_hdr_dma[i])); 1287 1288 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14), 1289 HISI_SAS_QUEUE_SLOTS); 1290 } 1291 1292 /* itct */ 1293 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO, 1294 lower_32_bits(hisi_hba->itct_dma)); 1295 1296 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI, 1297 upper_32_bits(hisi_hba->itct_dma)); 1298 1299 /* iost */ 1300 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO, 1301 lower_32_bits(hisi_hba->iost_dma)); 1302 1303 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI, 1304 upper_32_bits(hisi_hba->iost_dma)); 1305 1306 /* breakpoint */ 1307 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO, 1308 lower_32_bits(hisi_hba->breakpoint_dma)); 1309 1310 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI, 1311 upper_32_bits(hisi_hba->breakpoint_dma)); 1312 1313 /* SATA broken msg */ 1314 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO, 1315 lower_32_bits(hisi_hba->sata_breakpoint_dma)); 1316 1317 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI, 1318 upper_32_bits(hisi_hba->sata_breakpoint_dma)); 1319 1320 /* SATA initial fis */ 1321 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO, 1322 lower_32_bits(hisi_hba->initial_fis_dma)); 1323 1324 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI, 1325 upper_32_bits(hisi_hba->initial_fis_dma)); 1326} 1327 1328static void link_timeout_enable_link(struct timer_list *t) 1329{ 1330 struct hisi_hba *hisi_hba = timer_container_of(hisi_hba, t, timer); 1331 int i, reg_val; 1332 1333 for (i = 0; i < hisi_hba->n_phy; i++) { 1334 if (hisi_hba->reject_stp_links_msk & BIT(i)) 1335 continue; 1336 1337 reg_val = hisi_sas_phy_read32(hisi_hba, i, CON_CONTROL); 1338 if (!(reg_val & BIT(0))) { 1339 hisi_sas_phy_write32(hisi_hba, i, 1340 CON_CONTROL, 0x7); 1341 break; 1342 } 1343 } 1344 1345 hisi_hba->timer.function = link_timeout_disable_link; 1346 mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(900)); 1347} 1348 1349static void link_timeout_disable_link(struct timer_list *t) 1350{ 1351 struct hisi_hba *hisi_hba = timer_container_of(hisi_hba, t, timer); 1352 int i, reg_val; 1353 1354 reg_val = hisi_sas_read32(hisi_hba, PHY_STATE); 1355 for (i = 0; i < hisi_hba->n_phy && reg_val; i++) { 1356 if (hisi_hba->reject_stp_links_msk & BIT(i)) 1357 continue; 1358 1359 if (reg_val & BIT(i)) { 1360 hisi_sas_phy_write32(hisi_hba, i, 1361 CON_CONTROL, 0x6); 1362 break; 1363 } 1364 } 1365 1366 hisi_hba->timer.function = link_timeout_enable_link; 1367 mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(100)); 1368} 1369 1370static void set_link_timer_quirk(struct hisi_hba *hisi_hba) 1371{ 1372 hisi_hba->timer.function = link_timeout_disable_link; 1373 hisi_hba->timer.expires = jiffies + msecs_to_jiffies(1000); 1374 add_timer(&hisi_hba->timer); 1375} 1376 1377static int hw_init_v2_hw(struct hisi_hba *hisi_hba) 1378{ 1379 struct device *dev = hisi_hba->dev; 1380 int rc; 1381 1382 rc = reset_hw_v2_hw(hisi_hba); 1383 if (rc) { 1384 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d\n", rc); 1385 return rc; 1386 } 1387 1388 msleep(100); 1389 init_reg_v2_hw(hisi_hba); 1390 1391 return 0; 1392} 1393 1394static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 1395{ 1396 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 1397 1398 cfg |= PHY_CFG_ENA_MSK; 1399 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 1400} 1401 1402static bool is_sata_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 1403{ 1404 u32 context; 1405 1406 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT); 1407 if (context & (1 << phy_no)) 1408 return true; 1409 1410 return false; 1411} 1412 1413static bool tx_fifo_is_empty_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 1414{ 1415 u32 dfx_val; 1416 1417 dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1); 1418 1419 if (dfx_val & BIT(16)) 1420 return false; 1421 1422 return true; 1423} 1424 1425static bool axi_bus_is_idle_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 1426{ 1427 int i, max_loop = 1000; 1428 struct device *dev = hisi_hba->dev; 1429 u32 status, axi_status, dfx_val, dfx_tx_val; 1430 1431 for (i = 0; i < max_loop; i++) { 1432 status = hisi_sas_read32_relaxed(hisi_hba, 1433 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN); 1434 1435 axi_status = hisi_sas_read32(hisi_hba, AXI_CFG); 1436 dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1); 1437 dfx_tx_val = hisi_sas_phy_read32(hisi_hba, 1438 phy_no, DMA_TX_FIFO_DFX0); 1439 1440 if ((status == 0x3) && (axi_status == 0x0) && 1441 (dfx_val & BIT(20)) && (dfx_tx_val & BIT(10))) 1442 return true; 1443 udelay(10); 1444 } 1445 dev_err(dev, "bus is not idle phy%d, axi150:0x%x axi100:0x%x port204:0x%x port240:0x%x\n", 1446 phy_no, status, axi_status, 1447 dfx_val, dfx_tx_val); 1448 return false; 1449} 1450 1451static bool wait_io_done_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 1452{ 1453 int i, max_loop = 1000; 1454 struct device *dev = hisi_hba->dev; 1455 u32 status, tx_dfx0; 1456 1457 for (i = 0; i < max_loop; i++) { 1458 status = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2); 1459 status = (status & 0x3fc0) >> 6; 1460 1461 if (status != 0x1) 1462 return true; 1463 1464 tx_dfx0 = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX0); 1465 if ((tx_dfx0 & 0x1ff) == 0x2) 1466 return true; 1467 udelay(10); 1468 } 1469 dev_err(dev, "IO not done phy%d, port264:0x%x port200:0x%x\n", 1470 phy_no, status, tx_dfx0); 1471 return false; 1472} 1473 1474static bool allowed_disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 1475{ 1476 if (tx_fifo_is_empty_v2_hw(hisi_hba, phy_no)) 1477 return true; 1478 1479 if (!axi_bus_is_idle_v2_hw(hisi_hba, phy_no)) 1480 return false; 1481 1482 if (!wait_io_done_v2_hw(hisi_hba, phy_no)) 1483 return false; 1484 1485 return true; 1486} 1487 1488 1489static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 1490{ 1491 u32 cfg, axi_val, dfx0_val, txid_auto; 1492 struct device *dev = hisi_hba->dev; 1493 1494 /* Close axi bus. */ 1495 axi_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE + 1496 AM_CTRL_GLOBAL); 1497 axi_val |= 0x1; 1498 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + 1499 AM_CTRL_GLOBAL, axi_val); 1500 1501 if (is_sata_phy_v2_hw(hisi_hba, phy_no)) { 1502 if (allowed_disable_phy_v2_hw(hisi_hba, phy_no)) 1503 goto do_disable; 1504 1505 /* Reset host controller. */ 1506 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1507 return; 1508 } 1509 1510 dfx0_val = hisi_sas_phy_read32(hisi_hba, phy_no, PORT_DFX0); 1511 dfx0_val = (dfx0_val & 0x1fc0) >> 6; 1512 if (dfx0_val != 0x4) 1513 goto do_disable; 1514 1515 if (!tx_fifo_is_empty_v2_hw(hisi_hba, phy_no)) { 1516 dev_warn(dev, "phy%d, wait tx fifo need send break\n", 1517 phy_no); 1518 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, 1519 TXID_AUTO); 1520 txid_auto |= TXID_AUTO_CTB_MSK; 1521 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, 1522 txid_auto); 1523 } 1524 1525do_disable: 1526 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 1527 cfg &= ~PHY_CFG_ENA_MSK; 1528 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 1529 1530 /* Open axi bus. */ 1531 axi_val &= ~0x1; 1532 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + 1533 AM_CTRL_GLOBAL, axi_val); 1534} 1535 1536static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 1537{ 1538 config_id_frame_v2_hw(hisi_hba, phy_no); 1539 config_phy_opt_mode_v2_hw(hisi_hba, phy_no); 1540 enable_phy_v2_hw(hisi_hba, phy_no); 1541} 1542 1543static void phy_hard_reset_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 1544{ 1545 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1546 u32 txid_auto; 1547 1548 hisi_sas_phy_enable(hisi_hba, phy_no, 0); 1549 if (phy->identify.device_type == SAS_END_DEVICE) { 1550 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); 1551 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, 1552 txid_auto | TX_HARDRST_MSK); 1553 } 1554 msleep(100); 1555 hisi_sas_phy_enable(hisi_hba, phy_no, 1); 1556} 1557 1558static void phy_get_events_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 1559{ 1560 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1561 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1562 struct sas_phy *sphy = sas_phy->phy; 1563 u32 err4_reg_val, err6_reg_val; 1564 1565 /* loss dword syn, phy reset problem */ 1566 err4_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT4_REG); 1567 1568 /* disparity err, invalid dword */ 1569 err6_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT6_REG); 1570 1571 sphy->loss_of_dword_sync_count += (err4_reg_val >> 16) & 0xFFFF; 1572 sphy->phy_reset_problem_count += err4_reg_val & 0xFFFF; 1573 sphy->invalid_dword_count += (err6_reg_val & 0xFF0000) >> 16; 1574 sphy->running_disparity_error_count += err6_reg_val & 0xFF; 1575} 1576 1577static void phys_init_v2_hw(struct hisi_hba *hisi_hba) 1578{ 1579 int i; 1580 1581 for (i = 0; i < hisi_hba->n_phy; i++) { 1582 struct hisi_sas_phy *phy = &hisi_hba->phy[i]; 1583 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1584 1585 if (!sas_phy->phy->enabled) 1586 continue; 1587 1588 hisi_sas_phy_enable(hisi_hba, i, 1); 1589 } 1590} 1591 1592static void sl_notify_ssp_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 1593{ 1594 u32 sl_control; 1595 1596 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 1597 sl_control |= SL_CONTROL_NOTIFY_EN_MSK; 1598 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 1599 msleep(1); 1600 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 1601 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK; 1602 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 1603} 1604 1605static enum sas_linkrate phy_get_max_linkrate_v2_hw(void) 1606{ 1607 return SAS_LINK_RATE_12_0_GBPS; 1608} 1609 1610static void phy_set_linkrate_v2_hw(struct hisi_hba *hisi_hba, int phy_no, 1611 struct sas_phy_linkrates *r) 1612{ 1613 enum sas_linkrate max = r->maximum_linkrate; 1614 u32 prog_phy_link_rate = 0x800; 1615 1616 prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max); 1617 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, 1618 prog_phy_link_rate); 1619} 1620 1621static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id) 1622{ 1623 int i, bitmap = 0; 1624 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 1625 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1626 1627 for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++) 1628 if (phy_state & 1 << i) 1629 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id) 1630 bitmap |= 1 << i; 1631 1632 if (hisi_hba->n_phy == 9) { 1633 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE); 1634 1635 if (phy_state & 1 << 8) 1636 if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >> 1637 PORT_STATE_PHY8_PORT_NUM_OFF) == port_id) 1638 bitmap |= 1 << 9; 1639 } 1640 1641 return bitmap; 1642} 1643 1644/* DQ lock must be taken here */ 1645static void start_delivery_v2_hw(struct hisi_sas_dq *dq) 1646{ 1647 struct hisi_hba *hisi_hba = dq->hisi_hba; 1648 struct hisi_sas_slot *s, *s1, *s2 = NULL; 1649 int dlvry_queue = dq->id; 1650 int wp; 1651 1652 list_for_each_entry_safe(s, s1, &dq->list, delivery) { 1653 if (!s->ready) 1654 break; 1655 s2 = s; 1656 list_del(&s->delivery); 1657 } 1658 1659 if (!s2) 1660 return; 1661 1662 /* 1663 * Ensure that memories for slots built on other CPUs is observed. 1664 */ 1665 smp_rmb(); 1666 wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS; 1667 1668 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp); 1669} 1670 1671static void prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba, 1672 struct hisi_sas_slot *slot, 1673 struct hisi_sas_cmd_hdr *hdr, 1674 struct scatterlist *scatter, 1675 int n_elem) 1676{ 1677 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot); 1678 struct scatterlist *sg; 1679 int i; 1680 1681 for_each_sg(scatter, sg, n_elem, i) { 1682 struct hisi_sas_sge *entry = &sge_page->sge[i]; 1683 1684 entry->addr = cpu_to_le64(sg_dma_address(sg)); 1685 entry->page_ctrl_0 = entry->page_ctrl_1 = 0; 1686 entry->data_len = cpu_to_le32(sg_dma_len(sg)); 1687 entry->data_off = 0; 1688 } 1689 1690 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot)); 1691 1692 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF); 1693} 1694 1695static void prep_smp_v2_hw(struct hisi_hba *hisi_hba, 1696 struct hisi_sas_slot *slot) 1697{ 1698 struct sas_task *task = slot->task; 1699 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1700 struct domain_device *device = task->dev; 1701 struct hisi_sas_port *port = slot->port; 1702 struct scatterlist *sg_req; 1703 struct hisi_sas_device *sas_dev = device->lldd_dev; 1704 dma_addr_t req_dma_addr; 1705 unsigned int req_len; 1706 1707 /* req */ 1708 sg_req = &task->smp_task.smp_req; 1709 req_dma_addr = sg_dma_address(sg_req); 1710 req_len = sg_dma_len(&task->smp_task.smp_req); 1711 1712 /* create header */ 1713 /* dw0 */ 1714 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) | 1715 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */ 1716 (2 << CMD_HDR_CMD_OFF)); /* smp */ 1717 1718 /* map itct entry */ 1719 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) | 1720 (1 << CMD_HDR_FRAME_TYPE_OFF) | 1721 (DIR_NO_DATA << CMD_HDR_DIR_OFF)); 1722 1723 /* dw2 */ 1724 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) | 1725 (HISI_SAS_MAX_SMP_RESP_SZ / 4 << 1726 CMD_HDR_MRFL_OFF)); 1727 1728 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF); 1729 1730 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr); 1731 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1732} 1733 1734static void prep_ssp_v2_hw(struct hisi_hba *hisi_hba, 1735 struct hisi_sas_slot *slot) 1736{ 1737 struct sas_task *task = slot->task; 1738 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1739 struct domain_device *device = task->dev; 1740 struct hisi_sas_device *sas_dev = device->lldd_dev; 1741 struct hisi_sas_port *port = slot->port; 1742 struct sas_ssp_task *ssp_task = &task->ssp_task; 1743 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd; 1744 struct sas_tmf_task *tmf = slot->tmf; 1745 int has_data = 0, priority = !!tmf; 1746 u8 *buf_cmd; 1747 u32 dw1 = 0, dw2 = 0; 1748 1749 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) | 1750 (2 << CMD_HDR_TLR_CTRL_OFF) | 1751 (port->id << CMD_HDR_PORT_OFF) | 1752 (priority << CMD_HDR_PRIORITY_OFF) | 1753 (1 << CMD_HDR_CMD_OFF)); /* ssp */ 1754 1755 dw1 = 1 << CMD_HDR_VDTL_OFF; 1756 if (tmf) { 1757 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF; 1758 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF; 1759 } else { 1760 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF; 1761 switch (scsi_cmnd->sc_data_direction) { 1762 case DMA_TO_DEVICE: 1763 has_data = 1; 1764 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; 1765 break; 1766 case DMA_FROM_DEVICE: 1767 has_data = 1; 1768 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; 1769 break; 1770 default: 1771 dw1 &= ~CMD_HDR_DIR_MSK; 1772 } 1773 } 1774 1775 /* map itct entry */ 1776 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; 1777 hdr->dw1 = cpu_to_le32(dw1); 1778 1779 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr) 1780 + 3) / 4) << CMD_HDR_CFL_OFF) | 1781 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) | 1782 (2 << CMD_HDR_SG_MOD_OFF); 1783 hdr->dw2 = cpu_to_le32(dw2); 1784 1785 hdr->transfer_tags = cpu_to_le32(slot->idx); 1786 1787 if (has_data) 1788 prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter, 1789 slot->n_elem); 1790 1791 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); 1792 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); 1793 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1794 1795 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) + 1796 sizeof(struct ssp_frame_hdr); 1797 1798 memcpy(buf_cmd, &task->ssp_task.LUN, 8); 1799 if (!tmf) { 1800 buf_cmd[9] = task->ssp_task.task_attr; 1801 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd, 1802 task->ssp_task.cmd->cmd_len); 1803 } else { 1804 buf_cmd[10] = tmf->tmf; 1805 switch (tmf->tmf) { 1806 case TMF_ABORT_TASK: 1807 case TMF_QUERY_TASK: 1808 buf_cmd[12] = 1809 (tmf->tag_of_task_to_be_managed >> 8) & 0xff; 1810 buf_cmd[13] = 1811 tmf->tag_of_task_to_be_managed & 0xff; 1812 break; 1813 default: 1814 break; 1815 } 1816 } 1817} 1818 1819#define TRANS_TX_ERR 0 1820#define TRANS_RX_ERR 1 1821#define DMA_TX_ERR 2 1822#define SIPC_RX_ERR 3 1823#define DMA_RX_ERR 4 1824 1825#define DMA_TX_ERR_OFF 0 1826#define DMA_TX_ERR_MSK (0xffff << DMA_TX_ERR_OFF) 1827#define SIPC_RX_ERR_OFF 16 1828#define SIPC_RX_ERR_MSK (0xffff << SIPC_RX_ERR_OFF) 1829 1830static int parse_trans_tx_err_code_v2_hw(u32 err_msk) 1831{ 1832 static const u8 trans_tx_err_code_prio[] = { 1833 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS, 1834 TRANS_TX_ERR_PHY_NOT_ENABLE, 1835 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION, 1836 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION, 1837 TRANS_TX_OPEN_CNX_ERR_BY_OTHER, 1838 RESERVED0, 1839 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT, 1840 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY, 1841 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED, 1842 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED, 1843 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION, 1844 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD, 1845 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER, 1846 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED, 1847 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT, 1848 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION, 1849 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED, 1850 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE, 1851 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT, 1852 TRANS_TX_ERR_WITH_CLOSE_COMINIT, 1853 TRANS_TX_ERR_WITH_BREAK_TIMEOUT, 1854 TRANS_TX_ERR_WITH_BREAK_REQUEST, 1855 TRANS_TX_ERR_WITH_BREAK_RECEVIED, 1856 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT, 1857 TRANS_TX_ERR_WITH_CLOSE_NORMAL, 1858 TRANS_TX_ERR_WITH_NAK_RECEVIED, 1859 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT, 1860 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT, 1861 TRANS_TX_ERR_WITH_IPTT_CONFLICT, 1862 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS, 1863 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT, 1864 }; 1865 int index, i; 1866 1867 for (i = 0; i < ARRAY_SIZE(trans_tx_err_code_prio); i++) { 1868 index = trans_tx_err_code_prio[i] - TRANS_TX_FAIL_BASE; 1869 if (err_msk & (1 << index)) 1870 return trans_tx_err_code_prio[i]; 1871 } 1872 return -1; 1873} 1874 1875static int parse_trans_rx_err_code_v2_hw(u32 err_msk) 1876{ 1877 static const u8 trans_rx_err_code_prio[] = { 1878 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR, 1879 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR, 1880 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM, 1881 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR, 1882 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR, 1883 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN, 1884 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP, 1885 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN, 1886 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE, 1887 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT, 1888 TRANS_RX_ERR_WITH_CLOSE_COMINIT, 1889 TRANS_RX_ERR_WITH_BREAK_TIMEOUT, 1890 TRANS_RX_ERR_WITH_BREAK_REQUEST, 1891 TRANS_RX_ERR_WITH_BREAK_RECEVIED, 1892 RESERVED1, 1893 TRANS_RX_ERR_WITH_CLOSE_NORMAL, 1894 TRANS_RX_ERR_WITH_DATA_LEN0, 1895 TRANS_RX_ERR_WITH_BAD_HASH, 1896 TRANS_RX_XRDY_WLEN_ZERO_ERR, 1897 TRANS_RX_SSP_FRM_LEN_ERR, 1898 RESERVED2, 1899 RESERVED3, 1900 RESERVED4, 1901 RESERVED5, 1902 TRANS_RX_ERR_WITH_BAD_FRM_TYPE, 1903 TRANS_RX_SMP_FRM_LEN_ERR, 1904 TRANS_RX_SMP_RESP_TIMEOUT_ERR, 1905 RESERVED6, 1906 RESERVED7, 1907 RESERVED8, 1908 RESERVED9, 1909 TRANS_RX_R_ERR, 1910 }; 1911 int index, i; 1912 1913 for (i = 0; i < ARRAY_SIZE(trans_rx_err_code_prio); i++) { 1914 index = trans_rx_err_code_prio[i] - TRANS_RX_FAIL_BASE; 1915 if (err_msk & (1 << index)) 1916 return trans_rx_err_code_prio[i]; 1917 } 1918 return -1; 1919} 1920 1921static int parse_dma_tx_err_code_v2_hw(u32 err_msk) 1922{ 1923 static const u8 dma_tx_err_code_prio[] = { 1924 DMA_TX_UNEXP_XFER_ERR, 1925 DMA_TX_UNEXP_RETRANS_ERR, 1926 DMA_TX_XFER_LEN_OVERFLOW, 1927 DMA_TX_XFER_OFFSET_ERR, 1928 DMA_TX_RAM_ECC_ERR, 1929 DMA_TX_DIF_LEN_ALIGN_ERR, 1930 DMA_TX_DIF_CRC_ERR, 1931 DMA_TX_DIF_APP_ERR, 1932 DMA_TX_DIF_RPP_ERR, 1933 DMA_TX_DATA_SGL_OVERFLOW, 1934 DMA_TX_DIF_SGL_OVERFLOW, 1935 }; 1936 int index, i; 1937 1938 for (i = 0; i < ARRAY_SIZE(dma_tx_err_code_prio); i++) { 1939 index = dma_tx_err_code_prio[i] - DMA_TX_ERR_BASE; 1940 err_msk = err_msk & DMA_TX_ERR_MSK; 1941 if (err_msk & (1 << index)) 1942 return dma_tx_err_code_prio[i]; 1943 } 1944 return -1; 1945} 1946 1947static int parse_sipc_rx_err_code_v2_hw(u32 err_msk) 1948{ 1949 static const u8 sipc_rx_err_code_prio[] = { 1950 SIPC_RX_FIS_STATUS_ERR_BIT_VLD, 1951 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR, 1952 SIPC_RX_FIS_STATUS_BSY_BIT_ERR, 1953 SIPC_RX_WRSETUP_LEN_ODD_ERR, 1954 SIPC_RX_WRSETUP_LEN_ZERO_ERR, 1955 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR, 1956 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR, 1957 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR, 1958 SIPC_RX_SATA_UNEXP_FIS_ERR, 1959 SIPC_RX_WRSETUP_ESTATUS_ERR, 1960 SIPC_RX_DATA_UNDERFLOW_ERR, 1961 }; 1962 int index, i; 1963 1964 for (i = 0; i < ARRAY_SIZE(sipc_rx_err_code_prio); i++) { 1965 index = sipc_rx_err_code_prio[i] - SIPC_RX_ERR_BASE; 1966 err_msk = err_msk & SIPC_RX_ERR_MSK; 1967 if (err_msk & (1 << (index + 0x10))) 1968 return sipc_rx_err_code_prio[i]; 1969 } 1970 return -1; 1971} 1972 1973static int parse_dma_rx_err_code_v2_hw(u32 err_msk) 1974{ 1975 static const u8 dma_rx_err_code_prio[] = { 1976 DMA_RX_UNKNOWN_FRM_ERR, 1977 DMA_RX_DATA_LEN_OVERFLOW, 1978 DMA_RX_DATA_LEN_UNDERFLOW, 1979 DMA_RX_DATA_OFFSET_ERR, 1980 RESERVED10, 1981 DMA_RX_SATA_FRAME_TYPE_ERR, 1982 DMA_RX_RESP_BUF_OVERFLOW, 1983 DMA_RX_UNEXP_RETRANS_RESP_ERR, 1984 DMA_RX_UNEXP_NORM_RESP_ERR, 1985 DMA_RX_UNEXP_RDFRAME_ERR, 1986 DMA_RX_PIO_DATA_LEN_ERR, 1987 DMA_RX_RDSETUP_STATUS_ERR, 1988 DMA_RX_RDSETUP_STATUS_DRQ_ERR, 1989 DMA_RX_RDSETUP_STATUS_BSY_ERR, 1990 DMA_RX_RDSETUP_LEN_ODD_ERR, 1991 DMA_RX_RDSETUP_LEN_ZERO_ERR, 1992 DMA_RX_RDSETUP_LEN_OVER_ERR, 1993 DMA_RX_RDSETUP_OFFSET_ERR, 1994 DMA_RX_RDSETUP_ACTIVE_ERR, 1995 DMA_RX_RDSETUP_ESTATUS_ERR, 1996 DMA_RX_RAM_ECC_ERR, 1997 DMA_RX_DIF_CRC_ERR, 1998 DMA_RX_DIF_APP_ERR, 1999 DMA_RX_DIF_RPP_ERR, 2000 DMA_RX_DATA_SGL_OVERFLOW, 2001 DMA_RX_DIF_SGL_OVERFLOW, 2002 }; 2003 int index, i; 2004 2005 for (i = 0; i < ARRAY_SIZE(dma_rx_err_code_prio); i++) { 2006 index = dma_rx_err_code_prio[i] - DMA_RX_ERR_BASE; 2007 if (err_msk & (1 << index)) 2008 return dma_rx_err_code_prio[i]; 2009 } 2010 return -1; 2011} 2012 2013/* by default, task resp is complete */ 2014static void slot_err_v2_hw(struct hisi_hba *hisi_hba, 2015 struct sas_task *task, 2016 struct hisi_sas_slot *slot, 2017 int err_phase) 2018{ 2019 struct task_status_struct *ts = &task->task_status; 2020 struct hisi_sas_err_record_v2 *err_record = 2021 hisi_sas_status_buf_addr_mem(slot); 2022 u32 trans_tx_fail_type = le32_to_cpu(err_record->trans_tx_fail_type); 2023 u32 trans_rx_fail_type = le32_to_cpu(err_record->trans_rx_fail_type); 2024 u16 dma_tx_err_type = le16_to_cpu(err_record->dma_tx_err_type); 2025 u16 sipc_rx_err_type = le16_to_cpu(err_record->sipc_rx_err_type); 2026 u32 dma_rx_err_type = le32_to_cpu(err_record->dma_rx_err_type); 2027 struct hisi_sas_complete_v2_hdr *complete_queue = 2028 hisi_hba->complete_hdr[slot->cmplt_queue]; 2029 struct hisi_sas_complete_v2_hdr *complete_hdr = 2030 &complete_queue[slot->cmplt_queue_slot]; 2031 u32 dw0 = le32_to_cpu(complete_hdr->dw0); 2032 int error = -1; 2033 2034 if (err_phase == 1) { 2035 /* error in TX phase, the priority of error is: DW2 > DW0 */ 2036 error = parse_dma_tx_err_code_v2_hw(dma_tx_err_type); 2037 if (error == -1) 2038 error = parse_trans_tx_err_code_v2_hw( 2039 trans_tx_fail_type); 2040 } else if (err_phase == 2) { 2041 /* error in RX phase, the priority is: DW1 > DW3 > DW2 */ 2042 error = parse_trans_rx_err_code_v2_hw(trans_rx_fail_type); 2043 if (error == -1) { 2044 error = parse_dma_rx_err_code_v2_hw( 2045 dma_rx_err_type); 2046 if (error == -1) 2047 error = parse_sipc_rx_err_code_v2_hw( 2048 sipc_rx_err_type); 2049 } 2050 } 2051 2052 switch (task->task_proto) { 2053 case SAS_PROTOCOL_SSP: 2054 { 2055 switch (error) { 2056 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION: 2057 { 2058 ts->stat = SAS_OPEN_REJECT; 2059 ts->open_rej_reason = SAS_OREJ_NO_DEST; 2060 break; 2061 } 2062 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED: 2063 { 2064 ts->stat = SAS_OPEN_REJECT; 2065 ts->open_rej_reason = SAS_OREJ_EPROTO; 2066 break; 2067 } 2068 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED: 2069 { 2070 ts->stat = SAS_OPEN_REJECT; 2071 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2072 break; 2073 } 2074 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION: 2075 { 2076 ts->stat = SAS_OPEN_REJECT; 2077 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2078 break; 2079 } 2080 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION: 2081 { 2082 ts->stat = SAS_OPEN_REJECT; 2083 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2084 break; 2085 } 2086 case DMA_RX_UNEXP_NORM_RESP_ERR: 2087 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION: 2088 case DMA_RX_RESP_BUF_OVERFLOW: 2089 { 2090 ts->stat = SAS_OPEN_REJECT; 2091 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2092 break; 2093 } 2094 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER: 2095 { 2096 /* not sure */ 2097 ts->stat = SAS_DEV_NO_RESPONSE; 2098 break; 2099 } 2100 case DMA_RX_DATA_LEN_OVERFLOW: 2101 { 2102 ts->stat = SAS_DATA_OVERRUN; 2103 ts->residual = 0; 2104 break; 2105 } 2106 case DMA_RX_DATA_LEN_UNDERFLOW: 2107 { 2108 ts->residual = trans_tx_fail_type; 2109 ts->stat = SAS_DATA_UNDERRUN; 2110 break; 2111 } 2112 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS: 2113 case TRANS_TX_ERR_PHY_NOT_ENABLE: 2114 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER: 2115 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT: 2116 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD: 2117 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED: 2118 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT: 2119 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED: 2120 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT: 2121 case TRANS_TX_ERR_WITH_BREAK_REQUEST: 2122 case TRANS_TX_ERR_WITH_BREAK_RECEVIED: 2123 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT: 2124 case TRANS_TX_ERR_WITH_CLOSE_NORMAL: 2125 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE: 2126 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT: 2127 case TRANS_TX_ERR_WITH_CLOSE_COMINIT: 2128 case TRANS_TX_ERR_WITH_NAK_RECEVIED: 2129 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT: 2130 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT: 2131 case TRANS_TX_ERR_WITH_IPTT_CONFLICT: 2132 case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR: 2133 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR: 2134 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM: 2135 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN: 2136 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT: 2137 case TRANS_RX_ERR_WITH_BREAK_REQUEST: 2138 case TRANS_RX_ERR_WITH_BREAK_RECEVIED: 2139 case TRANS_RX_ERR_WITH_CLOSE_NORMAL: 2140 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT: 2141 case TRANS_RX_ERR_WITH_CLOSE_COMINIT: 2142 case TRANS_TX_ERR_FRAME_TXED: 2143 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE: 2144 case TRANS_RX_ERR_WITH_DATA_LEN0: 2145 case TRANS_RX_ERR_WITH_BAD_HASH: 2146 case TRANS_RX_XRDY_WLEN_ZERO_ERR: 2147 case TRANS_RX_SSP_FRM_LEN_ERR: 2148 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE: 2149 case DMA_TX_DATA_SGL_OVERFLOW: 2150 case DMA_TX_UNEXP_XFER_ERR: 2151 case DMA_TX_UNEXP_RETRANS_ERR: 2152 case DMA_TX_XFER_LEN_OVERFLOW: 2153 case DMA_TX_XFER_OFFSET_ERR: 2154 case SIPC_RX_DATA_UNDERFLOW_ERR: 2155 case DMA_RX_DATA_SGL_OVERFLOW: 2156 case DMA_RX_DATA_OFFSET_ERR: 2157 case DMA_RX_RDSETUP_LEN_ODD_ERR: 2158 case DMA_RX_RDSETUP_LEN_ZERO_ERR: 2159 case DMA_RX_RDSETUP_LEN_OVER_ERR: 2160 case DMA_RX_SATA_FRAME_TYPE_ERR: 2161 case DMA_RX_UNKNOWN_FRM_ERR: 2162 { 2163 /* This will request a retry */ 2164 ts->stat = SAS_QUEUE_FULL; 2165 slot->abort = 1; 2166 break; 2167 } 2168 default: 2169 break; 2170 } 2171 } 2172 break; 2173 case SAS_PROTOCOL_SMP: 2174 ts->stat = SAS_SAM_STAT_CHECK_CONDITION; 2175 break; 2176 2177 case SAS_PROTOCOL_SATA: 2178 case SAS_PROTOCOL_STP: 2179 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 2180 { 2181 switch (error) { 2182 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION: 2183 { 2184 ts->stat = SAS_OPEN_REJECT; 2185 ts->open_rej_reason = SAS_OREJ_NO_DEST; 2186 break; 2187 } 2188 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER: 2189 { 2190 ts->resp = SAS_TASK_UNDELIVERED; 2191 ts->stat = SAS_DEV_NO_RESPONSE; 2192 break; 2193 } 2194 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED: 2195 { 2196 ts->stat = SAS_OPEN_REJECT; 2197 ts->open_rej_reason = SAS_OREJ_EPROTO; 2198 break; 2199 } 2200 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED: 2201 { 2202 ts->stat = SAS_OPEN_REJECT; 2203 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2204 break; 2205 } 2206 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION: 2207 { 2208 ts->stat = SAS_OPEN_REJECT; 2209 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2210 break; 2211 } 2212 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION: 2213 { 2214 ts->stat = SAS_OPEN_REJECT; 2215 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2216 break; 2217 } 2218 case DMA_RX_RESP_BUF_OVERFLOW: 2219 case DMA_RX_UNEXP_NORM_RESP_ERR: 2220 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION: 2221 { 2222 ts->stat = SAS_OPEN_REJECT; 2223 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2224 break; 2225 } 2226 case DMA_RX_DATA_LEN_OVERFLOW: 2227 { 2228 ts->stat = SAS_DATA_OVERRUN; 2229 ts->residual = 0; 2230 break; 2231 } 2232 case DMA_RX_DATA_LEN_UNDERFLOW: 2233 { 2234 ts->residual = trans_tx_fail_type; 2235 ts->stat = SAS_DATA_UNDERRUN; 2236 break; 2237 } 2238 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS: 2239 case TRANS_TX_ERR_PHY_NOT_ENABLE: 2240 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER: 2241 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT: 2242 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD: 2243 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED: 2244 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT: 2245 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED: 2246 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT: 2247 case TRANS_TX_ERR_WITH_BREAK_REQUEST: 2248 case TRANS_TX_ERR_WITH_BREAK_RECEVIED: 2249 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT: 2250 case TRANS_TX_ERR_WITH_CLOSE_NORMAL: 2251 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE: 2252 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT: 2253 case TRANS_TX_ERR_WITH_CLOSE_COMINIT: 2254 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT: 2255 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT: 2256 case TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS: 2257 case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT: 2258 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM: 2259 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR: 2260 case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR: 2261 case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR: 2262 case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN: 2263 case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP: 2264 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN: 2265 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT: 2266 case TRANS_RX_ERR_WITH_BREAK_REQUEST: 2267 case TRANS_RX_ERR_WITH_BREAK_RECEVIED: 2268 case TRANS_RX_ERR_WITH_CLOSE_NORMAL: 2269 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE: 2270 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT: 2271 case TRANS_RX_ERR_WITH_CLOSE_COMINIT: 2272 case TRANS_RX_ERR_WITH_DATA_LEN0: 2273 case TRANS_RX_ERR_WITH_BAD_HASH: 2274 case TRANS_RX_XRDY_WLEN_ZERO_ERR: 2275 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE: 2276 case DMA_TX_DATA_SGL_OVERFLOW: 2277 case DMA_TX_UNEXP_XFER_ERR: 2278 case DMA_TX_UNEXP_RETRANS_ERR: 2279 case DMA_TX_XFER_LEN_OVERFLOW: 2280 case DMA_TX_XFER_OFFSET_ERR: 2281 case SIPC_RX_FIS_STATUS_ERR_BIT_VLD: 2282 case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR: 2283 case SIPC_RX_FIS_STATUS_BSY_BIT_ERR: 2284 case SIPC_RX_WRSETUP_LEN_ODD_ERR: 2285 case SIPC_RX_WRSETUP_LEN_ZERO_ERR: 2286 case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR: 2287 case SIPC_RX_SATA_UNEXP_FIS_ERR: 2288 case DMA_RX_DATA_SGL_OVERFLOW: 2289 case DMA_RX_DATA_OFFSET_ERR: 2290 case DMA_RX_SATA_FRAME_TYPE_ERR: 2291 case DMA_RX_UNEXP_RDFRAME_ERR: 2292 case DMA_RX_PIO_DATA_LEN_ERR: 2293 case DMA_RX_RDSETUP_STATUS_ERR: 2294 case DMA_RX_RDSETUP_STATUS_DRQ_ERR: 2295 case DMA_RX_RDSETUP_STATUS_BSY_ERR: 2296 case DMA_RX_RDSETUP_LEN_ODD_ERR: 2297 case DMA_RX_RDSETUP_LEN_ZERO_ERR: 2298 case DMA_RX_RDSETUP_LEN_OVER_ERR: 2299 case DMA_RX_RDSETUP_OFFSET_ERR: 2300 case DMA_RX_RDSETUP_ACTIVE_ERR: 2301 case DMA_RX_RDSETUP_ESTATUS_ERR: 2302 case DMA_RX_UNKNOWN_FRM_ERR: 2303 case TRANS_RX_SSP_FRM_LEN_ERR: 2304 case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY: 2305 { 2306 slot->abort = 1; 2307 ts->stat = SAS_PHY_DOWN; 2308 break; 2309 } 2310 default: 2311 { 2312 ts->stat = SAS_PROTO_RESPONSE; 2313 break; 2314 } 2315 } 2316 if (dw0 & CMPLT_HDR_RSPNS_XFRD_MSK) 2317 hisi_sas_sata_done(task, slot); 2318 } 2319 break; 2320 default: 2321 break; 2322 } 2323} 2324 2325static void slot_complete_v2_hw(struct hisi_hba *hisi_hba, 2326 struct hisi_sas_slot *slot) 2327{ 2328 struct sas_task *task = slot->task; 2329 struct hisi_sas_device *sas_dev; 2330 struct device *dev = hisi_hba->dev; 2331 struct task_status_struct *ts; 2332 struct domain_device *device; 2333 struct sas_ha_struct *ha; 2334 struct hisi_sas_complete_v2_hdr *complete_queue = 2335 hisi_hba->complete_hdr[slot->cmplt_queue]; 2336 struct hisi_sas_complete_v2_hdr *complete_hdr = 2337 &complete_queue[slot->cmplt_queue_slot]; 2338 unsigned long flags; 2339 bool is_internal = slot->is_internal; 2340 u32 dw0; 2341 2342 if (unlikely(!task || !task->lldd_task || !task->dev)) 2343 return; 2344 2345 ts = &task->task_status; 2346 device = task->dev; 2347 ha = device->port->ha; 2348 sas_dev = device->lldd_dev; 2349 2350 spin_lock_irqsave(&task->task_state_lock, flags); 2351 task->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2352 spin_unlock_irqrestore(&task->task_state_lock, flags); 2353 2354 memset(ts, 0, sizeof(*ts)); 2355 ts->resp = SAS_TASK_COMPLETE; 2356 2357 if (unlikely(!sas_dev)) { 2358 dev_dbg(dev, "slot complete: port has no device\n"); 2359 ts->stat = SAS_PHY_DOWN; 2360 goto out; 2361 } 2362 2363 /* Use SAS+TMF status codes */ 2364 dw0 = le32_to_cpu(complete_hdr->dw0); 2365 switch ((dw0 & CMPLT_HDR_ABORT_STAT_MSK) >> 2366 CMPLT_HDR_ABORT_STAT_OFF) { 2367 case STAT_IO_ABORTED: 2368 /* this io has been aborted by abort command */ 2369 ts->stat = SAS_ABORTED_TASK; 2370 goto out; 2371 case STAT_IO_COMPLETE: 2372 /* internal abort command complete */ 2373 ts->stat = TMF_RESP_FUNC_SUCC; 2374 timer_delete_sync(&slot->internal_abort_timer); 2375 goto out; 2376 case STAT_IO_NO_DEVICE: 2377 ts->stat = TMF_RESP_FUNC_COMPLETE; 2378 timer_delete_sync(&slot->internal_abort_timer); 2379 goto out; 2380 case STAT_IO_NOT_VALID: 2381 /* abort single io, controller don't find 2382 * the io need to abort 2383 */ 2384 ts->stat = TMF_RESP_FUNC_FAILED; 2385 timer_delete_sync(&slot->internal_abort_timer); 2386 goto out; 2387 default: 2388 break; 2389 } 2390 2391 if ((dw0 & CMPLT_HDR_ERX_MSK) && (!(dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) { 2392 u32 err_phase = (dw0 & CMPLT_HDR_ERR_PHASE_MSK) 2393 >> CMPLT_HDR_ERR_PHASE_OFF; 2394 u32 *error_info = hisi_sas_status_buf_addr_mem(slot); 2395 2396 /* Analyse error happens on which phase TX or RX */ 2397 if (ERR_ON_TX_PHASE(err_phase)) 2398 slot_err_v2_hw(hisi_hba, task, slot, 1); 2399 else if (ERR_ON_RX_PHASE(err_phase)) 2400 slot_err_v2_hw(hisi_hba, task, slot, 2); 2401 2402 if (ts->stat != SAS_DATA_UNDERRUN) 2403 dev_info(dev, "erroneous completion iptt=%d task=%p dev id=%d CQ hdr: 0x%x 0x%x 0x%x 0x%x Error info: 0x%x 0x%x 0x%x 0x%x\n", 2404 slot->idx, task, sas_dev->device_id, 2405 complete_hdr->dw0, complete_hdr->dw1, 2406 complete_hdr->act, complete_hdr->dw3, 2407 error_info[0], error_info[1], 2408 error_info[2], error_info[3]); 2409 2410 if (unlikely(slot->abort)) { 2411 if (dev_is_sata(device) && task->ata_task.use_ncq) 2412 sas_ata_device_link_abort(device, true); 2413 else 2414 sas_task_abort(task); 2415 2416 return; 2417 } 2418 goto out; 2419 } 2420 2421 switch (task->task_proto) { 2422 case SAS_PROTOCOL_SSP: 2423 { 2424 struct hisi_sas_status_buffer *status_buffer = 2425 hisi_sas_status_buf_addr_mem(slot); 2426 struct ssp_response_iu *iu = (struct ssp_response_iu *) 2427 &status_buffer->iu[0]; 2428 2429 sas_ssp_task_response(dev, task, iu); 2430 break; 2431 } 2432 case SAS_PROTOCOL_SMP: 2433 { 2434 struct scatterlist *sg_resp = &task->smp_task.smp_resp; 2435 void *to = page_address(sg_page(sg_resp)); 2436 2437 ts->stat = SAS_SAM_STAT_GOOD; 2438 2439 memcpy(to + sg_resp->offset, 2440 hisi_sas_status_buf_addr_mem(slot) + 2441 sizeof(struct hisi_sas_err_record), 2442 sg_resp->length); 2443 break; 2444 } 2445 case SAS_PROTOCOL_SATA: 2446 case SAS_PROTOCOL_STP: 2447 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 2448 { 2449 ts->stat = SAS_SAM_STAT_GOOD; 2450 if (dw0 & CMPLT_HDR_RSPNS_XFRD_MSK) 2451 hisi_sas_sata_done(task, slot); 2452 break; 2453 } 2454 default: 2455 ts->stat = SAS_SAM_STAT_CHECK_CONDITION; 2456 break; 2457 } 2458 2459 if (!slot->port->port_attached) { 2460 dev_warn(dev, "slot complete: port %d has removed\n", 2461 slot->port->sas_port.id); 2462 ts->stat = SAS_PHY_DOWN; 2463 } 2464 2465out: 2466 spin_lock_irqsave(&task->task_state_lock, flags); 2467 if (task->task_state_flags & SAS_TASK_STATE_ABORTED) { 2468 spin_unlock_irqrestore(&task->task_state_lock, flags); 2469 dev_info(dev, "slot complete: task(%p) aborted\n", task); 2470 return; 2471 } 2472 task->task_state_flags |= SAS_TASK_STATE_DONE; 2473 spin_unlock_irqrestore(&task->task_state_lock, flags); 2474 hisi_sas_slot_task_free(hisi_hba, task, slot, true); 2475 2476 if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) { 2477 spin_lock_irqsave(&device->done_lock, flags); 2478 if (test_bit(SAS_HA_FROZEN, &ha->state)) { 2479 spin_unlock_irqrestore(&device->done_lock, flags); 2480 dev_info(dev, "slot complete: task(%p) ignored\n", 2481 task); 2482 return; 2483 } 2484 spin_unlock_irqrestore(&device->done_lock, flags); 2485 } 2486 2487 if (task->task_done) 2488 task->task_done(task); 2489} 2490 2491static void prep_ata_v2_hw(struct hisi_hba *hisi_hba, 2492 struct hisi_sas_slot *slot) 2493{ 2494 struct sas_task *task = slot->task; 2495 struct domain_device *device = task->dev; 2496 struct hisi_sas_device *sas_dev = device->lldd_dev; 2497 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 2498 struct asd_sas_port *sas_port = device->port; 2499 struct hisi_sas_port *port = to_hisi_sas_port(sas_port); 2500 struct sas_ata_task *ata_task = &task->ata_task; 2501 struct sas_tmf_task *tmf = slot->tmf; 2502 int phy_id; 2503 u8 *buf_cmd; 2504 int has_data = 0, hdr_tag = 0; 2505 u32 dw0, dw1 = 0, dw2 = 0; 2506 2507 /* create header */ 2508 /* dw0 */ 2509 dw0 = port->id << CMD_HDR_PORT_OFF; 2510 if (dev_parent_is_expander(device)) { 2511 dw0 |= 3 << CMD_HDR_CMD_OFF; 2512 } else { 2513 phy_id = device->phy->identify.phy_identifier; 2514 dw0 |= (1U << phy_id) << CMD_HDR_PHY_ID_OFF; 2515 dw0 |= CMD_HDR_FORCE_PHY_MSK; 2516 dw0 |= 4 << CMD_HDR_CMD_OFF; 2517 } 2518 2519 if (tmf && ata_task->force_phy) { 2520 dw0 |= CMD_HDR_FORCE_PHY_MSK; 2521 dw0 |= (1 << ata_task->force_phy_id) << CMD_HDR_PHY_ID_OFF; 2522 } 2523 2524 hdr->dw0 = cpu_to_le32(dw0); 2525 2526 /* dw1 */ 2527 switch (task->data_dir) { 2528 case DMA_TO_DEVICE: 2529 has_data = 1; 2530 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; 2531 break; 2532 case DMA_FROM_DEVICE: 2533 has_data = 1; 2534 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; 2535 break; 2536 default: 2537 dw1 &= ~CMD_HDR_DIR_MSK; 2538 } 2539 2540 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) && 2541 (task->ata_task.fis.control & ATA_SRST)) 2542 dw1 |= 1 << CMD_HDR_RESET_OFF; 2543 2544 dw1 |= (hisi_sas_get_ata_protocol(task)) << CMD_HDR_FRAME_TYPE_OFF; 2545 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; 2546 hdr->dw1 = cpu_to_le32(dw1); 2547 2548 /* dw2 */ 2549 if (task->ata_task.use_ncq) { 2550 struct ata_queued_cmd *qc = task->uldd_task; 2551 2552 hdr_tag = qc->tag; 2553 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); 2554 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF; 2555 } 2556 2557 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF | 2558 2 << CMD_HDR_SG_MOD_OFF; 2559 hdr->dw2 = cpu_to_le32(dw2); 2560 2561 /* dw3 */ 2562 hdr->transfer_tags = cpu_to_le32(slot->idx); 2563 2564 if (has_data) 2565 prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter, 2566 slot->n_elem); 2567 2568 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); 2569 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); 2570 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 2571 2572 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot); 2573 2574 if (likely(!task->ata_task.device_control_reg_update)) 2575 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */ 2576 /* fill in command FIS */ 2577 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis)); 2578} 2579 2580static void hisi_sas_internal_abort_quirk_timeout(struct timer_list *t) 2581{ 2582 struct hisi_sas_slot *slot = timer_container_of(slot, t, 2583 internal_abort_timer); 2584 struct hisi_sas_port *port = slot->port; 2585 struct asd_sas_port *asd_sas_port; 2586 struct asd_sas_phy *sas_phy; 2587 2588 if (!port) 2589 return; 2590 2591 asd_sas_port = &port->sas_port; 2592 2593 /* Kick the hardware - send break command */ 2594 list_for_each_entry(sas_phy, &asd_sas_port->phy_list, port_phy_el) { 2595 struct hisi_sas_phy *phy = sas_phy->lldd_phy; 2596 struct hisi_hba *hisi_hba = phy->hisi_hba; 2597 int phy_no = sas_phy->id; 2598 u32 link_dfx2; 2599 2600 link_dfx2 = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2); 2601 if ((link_dfx2 == LINK_DFX2_RCVR_HOLD_STS_MSK) || 2602 (link_dfx2 & LINK_DFX2_SEND_HOLD_STS_MSK)) { 2603 u32 txid_auto; 2604 2605 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, 2606 TXID_AUTO); 2607 txid_auto |= TXID_AUTO_CTB_MSK; 2608 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, 2609 txid_auto); 2610 return; 2611 } 2612 } 2613} 2614 2615static void prep_abort_v2_hw(struct hisi_hba *hisi_hba, 2616 struct hisi_sas_slot *slot) 2617{ 2618 struct sas_task *task = slot->task; 2619 struct sas_internal_abort_task *abort = &task->abort_task; 2620 struct domain_device *dev = task->dev; 2621 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 2622 struct hisi_sas_port *port = slot->port; 2623 struct timer_list *timer = &slot->internal_abort_timer; 2624 struct hisi_sas_device *sas_dev = dev->lldd_dev; 2625 2626 /* setup the quirk timer */ 2627 timer_setup(timer, hisi_sas_internal_abort_quirk_timeout, 0); 2628 /* Set the timeout to 10ms less than internal abort timeout */ 2629 mod_timer(timer, jiffies + msecs_to_jiffies(100)); 2630 2631 /* dw0 */ 2632 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/ 2633 (port->id << CMD_HDR_PORT_OFF) | 2634 (dev_is_sata(dev) << 2635 CMD_HDR_ABORT_DEVICE_TYPE_OFF) | 2636 (abort->type << CMD_HDR_ABORT_FLAG_OFF)); 2637 2638 /* dw1 */ 2639 hdr->dw1 = cpu_to_le32(sas_dev->device_id << CMD_HDR_DEV_ID_OFF); 2640 2641 /* dw7 */ 2642 hdr->dw7 = cpu_to_le32(abort->tag << CMD_HDR_ABORT_IPTT_OFF); 2643 hdr->transfer_tags = cpu_to_le32(slot->idx); 2644} 2645 2646static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba) 2647{ 2648 int i, res = IRQ_HANDLED; 2649 u32 port_id, link_rate; 2650 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 2651 struct asd_sas_phy *sas_phy = &phy->sas_phy; 2652 struct device *dev = hisi_hba->dev; 2653 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd; 2654 struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd; 2655 2656 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1); 2657 2658 if (is_sata_phy_v2_hw(hisi_hba, phy_no)) 2659 goto end; 2660 2661 timer_delete(&phy->timer); 2662 2663 if (phy_no == 8) { 2664 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE); 2665 2666 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >> 2667 PORT_STATE_PHY8_PORT_NUM_OFF; 2668 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >> 2669 PORT_STATE_PHY8_CONN_RATE_OFF; 2670 } else { 2671 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 2672 port_id = (port_id >> (4 * phy_no)) & 0xf; 2673 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); 2674 link_rate = (link_rate >> (phy_no * 4)) & 0xf; 2675 } 2676 2677 if (port_id == 0xf) { 2678 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no); 2679 res = IRQ_NONE; 2680 goto end; 2681 } 2682 2683 for (i = 0; i < 6; i++) { 2684 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no, 2685 RX_IDAF_DWORD0 + (i * 4)); 2686 frame_rcvd[i] = __swab32(idaf); 2687 } 2688 2689 sas_phy->linkrate = link_rate; 2690 sas_phy->oob_mode = SAS_OOB_MODE; 2691 memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE); 2692 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate); 2693 phy->port_id = port_id; 2694 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); 2695 phy->phy_type |= PORT_TYPE_SAS; 2696 phy->phy_attached = 1; 2697 phy->identify.device_type = id->dev_type; 2698 phy->frame_rcvd_size = sizeof(struct sas_identify_frame); 2699 if (phy->identify.device_type == SAS_END_DEVICE) 2700 phy->identify.target_port_protocols = 2701 SAS_PROTOCOL_SSP; 2702 else if (phy->identify.device_type != SAS_PHY_UNUSED) { 2703 phy->identify.target_port_protocols = 2704 SAS_PROTOCOL_SMP; 2705 if (!timer_pending(&hisi_hba->timer)) 2706 set_link_timer_quirk(hisi_hba); 2707 } 2708 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP); 2709end: 2710 if (phy->reset_completion) 2711 complete(phy->reset_completion); 2712 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 2713 CHL_INT0_SL_PHY_ENABLE_MSK); 2714 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0); 2715 2716 return res; 2717} 2718 2719static bool check_any_wideports_v2_hw(struct hisi_hba *hisi_hba) 2720{ 2721 u32 port_state; 2722 2723 port_state = hisi_sas_read32(hisi_hba, PORT_STATE); 2724 if (port_state & 0x1ff) 2725 return true; 2726 2727 return false; 2728} 2729 2730static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba) 2731{ 2732 u32 phy_state, sl_ctrl, txid_auto; 2733 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 2734 struct hisi_sas_port *port = phy->port; 2735 struct device *dev = hisi_hba->dev; 2736 2737 timer_delete(&phy->timer); 2738 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1); 2739 2740 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 2741 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state); 2742 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0, 2743 GFP_ATOMIC); 2744 2745 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 2746 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, 2747 sl_ctrl & ~SL_CONTROL_CTA_MSK); 2748 if (port && !get_wideport_bitmap_v2_hw(hisi_hba, port->id)) 2749 if (!check_any_wideports_v2_hw(hisi_hba) && 2750 timer_pending(&hisi_hba->timer)) 2751 timer_delete(&hisi_hba->timer); 2752 2753 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); 2754 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, 2755 txid_auto | TXID_AUTO_CT3_MSK); 2756 2757 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK); 2758 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0); 2759 2760 return IRQ_HANDLED; 2761} 2762 2763static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p) 2764{ 2765 struct hisi_hba *hisi_hba = p; 2766 u32 irq_msk; 2767 int phy_no = 0; 2768 irqreturn_t res = IRQ_NONE; 2769 2770 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) 2771 >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff; 2772 while (irq_msk) { 2773 if (irq_msk & 1) { 2774 u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, 2775 CHL_INT0); 2776 2777 switch (reg_value & (CHL_INT0_NOT_RDY_MSK | 2778 CHL_INT0_SL_PHY_ENABLE_MSK)) { 2779 2780 case CHL_INT0_SL_PHY_ENABLE_MSK: 2781 /* phy up */ 2782 if (phy_up_v2_hw(phy_no, hisi_hba) == 2783 IRQ_HANDLED) 2784 res = IRQ_HANDLED; 2785 break; 2786 2787 case CHL_INT0_NOT_RDY_MSK: 2788 /* phy down */ 2789 if (phy_down_v2_hw(phy_no, hisi_hba) == 2790 IRQ_HANDLED) 2791 res = IRQ_HANDLED; 2792 break; 2793 2794 case (CHL_INT0_NOT_RDY_MSK | 2795 CHL_INT0_SL_PHY_ENABLE_MSK): 2796 reg_value = hisi_sas_read32(hisi_hba, 2797 PHY_STATE); 2798 if (reg_value & BIT(phy_no)) { 2799 /* phy up */ 2800 if (phy_up_v2_hw(phy_no, hisi_hba) == 2801 IRQ_HANDLED) 2802 res = IRQ_HANDLED; 2803 } else { 2804 /* phy down */ 2805 if (phy_down_v2_hw(phy_no, hisi_hba) == 2806 IRQ_HANDLED) 2807 res = IRQ_HANDLED; 2808 } 2809 break; 2810 2811 default: 2812 break; 2813 } 2814 2815 } 2816 irq_msk >>= 1; 2817 phy_no++; 2818 } 2819 2820 return res; 2821} 2822 2823static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba) 2824{ 2825 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 2826 u32 bcast_status; 2827 2828 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1); 2829 bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS); 2830 if (bcast_status & RX_BCAST_CHG_MSK) 2831 hisi_sas_phy_bcast(phy); 2832 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 2833 CHL_INT0_SL_RX_BCST_ACK_MSK); 2834 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0); 2835} 2836 2837static const struct hisi_sas_hw_error port_ecc_axi_error[] = { 2838 { 2839 .irq_msk = BIT(CHL_INT1_DMAC_TX_ECC_ERR_OFF), 2840 .msg = "dmac_tx_ecc_bad_err", 2841 }, 2842 { 2843 .irq_msk = BIT(CHL_INT1_DMAC_RX_ECC_ERR_OFF), 2844 .msg = "dmac_rx_ecc_bad_err", 2845 }, 2846 { 2847 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF), 2848 .msg = "dma_tx_axi_wr_err", 2849 }, 2850 { 2851 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF), 2852 .msg = "dma_tx_axi_rd_err", 2853 }, 2854 { 2855 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF), 2856 .msg = "dma_rx_axi_wr_err", 2857 }, 2858 { 2859 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF), 2860 .msg = "dma_rx_axi_rd_err", 2861 }, 2862}; 2863 2864static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p) 2865{ 2866 struct hisi_hba *hisi_hba = p; 2867 struct device *dev = hisi_hba->dev; 2868 u32 ent_msk, ent_tmp, irq_msk; 2869 int phy_no = 0; 2870 2871 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3); 2872 ent_tmp = ent_msk; 2873 ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK; 2874 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk); 2875 2876 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >> 2877 HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff; 2878 2879 while (irq_msk) { 2880 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, 2881 CHL_INT0); 2882 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no, 2883 CHL_INT1); 2884 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no, 2885 CHL_INT2); 2886 2887 if ((irq_msk & (1 << phy_no)) && irq_value1) { 2888 int i; 2889 2890 for (i = 0; i < ARRAY_SIZE(port_ecc_axi_error); i++) { 2891 const struct hisi_sas_hw_error *error = 2892 &port_ecc_axi_error[i]; 2893 2894 if (!(irq_value1 & error->irq_msk)) 2895 continue; 2896 2897 dev_warn(dev, "%s error (phy%d 0x%x) found!\n", 2898 error->msg, phy_no, irq_value1); 2899 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 2900 } 2901 2902 hisi_sas_phy_write32(hisi_hba, phy_no, 2903 CHL_INT1, irq_value1); 2904 } 2905 2906 if ((irq_msk & (1 << phy_no)) && irq_value2) { 2907 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 2908 2909 if (irq_value2 & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) { 2910 dev_warn(dev, "phy%d identify timeout\n", 2911 phy_no); 2912 hisi_sas_notify_phy_event(phy, 2913 HISI_PHYE_LINK_RESET); 2914 } 2915 2916 hisi_sas_phy_write32(hisi_hba, phy_no, 2917 CHL_INT2, irq_value2); 2918 } 2919 2920 if ((irq_msk & (1 << phy_no)) && irq_value0) { 2921 if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK) 2922 phy_bcast_v2_hw(phy_no, hisi_hba); 2923 2924 if (irq_value0 & CHL_INT0_PHY_RDY_MSK) 2925 hisi_sas_phy_oob_ready(hisi_hba, phy_no); 2926 2927 hisi_sas_phy_write32(hisi_hba, phy_no, 2928 CHL_INT0, irq_value0 2929 & (~CHL_INT0_HOTPLUG_TOUT_MSK) 2930 & (~CHL_INT0_SL_PHY_ENABLE_MSK) 2931 & (~CHL_INT0_NOT_RDY_MSK)); 2932 } 2933 irq_msk &= ~(1 << phy_no); 2934 phy_no++; 2935 } 2936 2937 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp); 2938 2939 return IRQ_HANDLED; 2940} 2941 2942static void 2943one_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, u32 irq_value) 2944{ 2945 struct device *dev = hisi_hba->dev; 2946 const struct hisi_sas_hw_error *ecc_error; 2947 u32 val; 2948 int i; 2949 2950 for (i = 0; i < ARRAY_SIZE(one_bit_ecc_errors); i++) { 2951 ecc_error = &one_bit_ecc_errors[i]; 2952 if (irq_value & ecc_error->irq_msk) { 2953 val = hisi_sas_read32(hisi_hba, ecc_error->reg); 2954 val &= ecc_error->msk; 2955 val >>= ecc_error->shift; 2956 dev_warn(dev, "%s found: mem addr is 0x%08X\n", 2957 ecc_error->msg, val); 2958 } 2959 } 2960} 2961 2962static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, 2963 u32 irq_value) 2964{ 2965 struct device *dev = hisi_hba->dev; 2966 const struct hisi_sas_hw_error *ecc_error; 2967 u32 val; 2968 int i; 2969 2970 for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) { 2971 ecc_error = &multi_bit_ecc_errors[i]; 2972 if (irq_value & ecc_error->irq_msk) { 2973 val = hisi_sas_read32(hisi_hba, ecc_error->reg); 2974 val &= ecc_error->msk; 2975 val >>= ecc_error->shift; 2976 dev_err(dev, "%s (0x%x) found: mem addr is 0x%08X\n", 2977 ecc_error->msg, irq_value, val); 2978 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 2979 } 2980 } 2981 2982 return; 2983} 2984 2985static irqreturn_t fatal_ecc_int_v2_hw(int irq_no, void *p) 2986{ 2987 struct hisi_hba *hisi_hba = p; 2988 u32 irq_value, irq_msk; 2989 2990 irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK); 2991 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk | 0xffffffff); 2992 2993 irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR); 2994 if (irq_value) { 2995 one_bit_ecc_error_process_v2_hw(hisi_hba, irq_value); 2996 multi_bit_ecc_error_process_v2_hw(hisi_hba, irq_value); 2997 } 2998 2999 hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value); 3000 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk); 3001 3002 return IRQ_HANDLED; 3003} 3004 3005static const struct hisi_sas_hw_error axi_error[] = { 3006 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" }, 3007 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" }, 3008 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" }, 3009 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" }, 3010 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" }, 3011 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" }, 3012 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" }, 3013 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" }, 3014 {} 3015}; 3016 3017static const struct hisi_sas_hw_error fifo_error[] = { 3018 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" }, 3019 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" }, 3020 { .msk = BIT(10), .msg = "GETDQE_FIFO" }, 3021 { .msk = BIT(11), .msg = "CMDP_FIFO" }, 3022 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" }, 3023 {} 3024}; 3025 3026static const struct hisi_sas_hw_error fatal_axi_errors[] = { 3027 { 3028 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF), 3029 .msg = "write pointer and depth", 3030 }, 3031 { 3032 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF), 3033 .msg = "iptt no match slot", 3034 }, 3035 { 3036 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF), 3037 .msg = "read pointer and depth", 3038 }, 3039 { 3040 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF), 3041 .reg = HGC_AXI_FIFO_ERR_INFO, 3042 .sub = axi_error, 3043 }, 3044 { 3045 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF), 3046 .reg = HGC_AXI_FIFO_ERR_INFO, 3047 .sub = fifo_error, 3048 }, 3049 { 3050 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF), 3051 .msg = "LM add/fetch list", 3052 }, 3053 { 3054 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF), 3055 .msg = "SAS_HGC_ABT fetch LM list", 3056 }, 3057}; 3058 3059static irqreturn_t fatal_axi_int_v2_hw(int irq_no, void *p) 3060{ 3061 struct hisi_hba *hisi_hba = p; 3062 u32 irq_value, irq_msk, err_value; 3063 struct device *dev = hisi_hba->dev; 3064 const struct hisi_sas_hw_error *axi_error; 3065 int i; 3066 3067 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3); 3068 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0xfffffffe); 3069 3070 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 3071 3072 for (i = 0; i < ARRAY_SIZE(fatal_axi_errors); i++) { 3073 axi_error = &fatal_axi_errors[i]; 3074 if (!(irq_value & axi_error->irq_msk)) 3075 continue; 3076 3077 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 3078 1 << axi_error->shift); 3079 if (axi_error->sub) { 3080 const struct hisi_sas_hw_error *sub = axi_error->sub; 3081 3082 err_value = hisi_sas_read32(hisi_hba, axi_error->reg); 3083 for (; sub->msk || sub->msg; sub++) { 3084 if (!(err_value & sub->msk)) 3085 continue; 3086 dev_err(dev, "%s (0x%x) found!\n", 3087 sub->msg, irq_value); 3088 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 3089 } 3090 } else { 3091 dev_err(dev, "%s (0x%x) found!\n", 3092 axi_error->msg, irq_value); 3093 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 3094 } 3095 } 3096 3097 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) { 3098 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR); 3099 u32 dev_id = reg_val & ITCT_DEV_MSK; 3100 struct hisi_sas_device *sas_dev = &hisi_hba->devices[dev_id]; 3101 3102 hisi_sas_write32(hisi_hba, ITCT_CLR, 0); 3103 dev_dbg(dev, "clear ITCT ok\n"); 3104 complete(sas_dev->completion); 3105 } 3106 3107 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value); 3108 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk); 3109 3110 return IRQ_HANDLED; 3111} 3112 3113static irqreturn_t cq_thread_v2_hw(int irq_no, void *p) 3114{ 3115 struct hisi_sas_cq *cq = p; 3116 struct hisi_hba *hisi_hba = cq->hisi_hba; 3117 struct hisi_sas_slot *slot; 3118 struct hisi_sas_itct *itct; 3119 struct hisi_sas_complete_v2_hdr *complete_queue; 3120 u32 rd_point = cq->rd_point, wr_point, dev_id; 3121 int queue = cq->id; 3122 3123 if (unlikely(hisi_hba->reject_stp_links_msk)) 3124 phys_try_accept_stp_links_v2_hw(hisi_hba); 3125 3126 complete_queue = hisi_hba->complete_hdr[queue]; 3127 3128 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR + 3129 (0x14 * queue)); 3130 3131 while (rd_point != wr_point) { 3132 struct hisi_sas_complete_v2_hdr *complete_hdr; 3133 int iptt; 3134 3135 complete_hdr = &complete_queue[rd_point]; 3136 3137 /* Check for NCQ completion */ 3138 if (complete_hdr->act) { 3139 u32 act_tmp = le32_to_cpu(complete_hdr->act); 3140 int ncq_tag_count = ffs(act_tmp); 3141 u32 dw1 = le32_to_cpu(complete_hdr->dw1); 3142 3143 dev_id = (dw1 & CMPLT_HDR_DEV_ID_MSK) >> 3144 CMPLT_HDR_DEV_ID_OFF; 3145 itct = &hisi_hba->itct[dev_id]; 3146 3147 /* The NCQ tags are held in the itct header */ 3148 while (ncq_tag_count) { 3149 __le64 *_ncq_tag = &itct->qw4_15[0], __ncq_tag; 3150 u64 ncq_tag; 3151 3152 ncq_tag_count--; 3153 __ncq_tag = _ncq_tag[ncq_tag_count / 5]; 3154 ncq_tag = le64_to_cpu(__ncq_tag); 3155 iptt = (ncq_tag >> (ncq_tag_count % 5) * 12) & 3156 0xfff; 3157 3158 slot = &hisi_hba->slot_info[iptt]; 3159 slot->cmplt_queue_slot = rd_point; 3160 slot->cmplt_queue = queue; 3161 slot_complete_v2_hw(hisi_hba, slot); 3162 3163 act_tmp &= ~(1 << ncq_tag_count); 3164 ncq_tag_count = ffs(act_tmp); 3165 } 3166 } else { 3167 u32 dw1 = le32_to_cpu(complete_hdr->dw1); 3168 3169 iptt = dw1 & CMPLT_HDR_IPTT_MSK; 3170 slot = &hisi_hba->slot_info[iptt]; 3171 slot->cmplt_queue_slot = rd_point; 3172 slot->cmplt_queue = queue; 3173 slot_complete_v2_hw(hisi_hba, slot); 3174 } 3175 3176 if (++rd_point >= HISI_SAS_QUEUE_SLOTS) 3177 rd_point = 0; 3178 } 3179 3180 /* update rd_point */ 3181 cq->rd_point = rd_point; 3182 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point); 3183 3184 return IRQ_HANDLED; 3185} 3186 3187static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p) 3188{ 3189 struct hisi_sas_cq *cq = p; 3190 struct hisi_hba *hisi_hba = cq->hisi_hba; 3191 int queue = cq->id; 3192 3193 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue); 3194 3195 return IRQ_WAKE_THREAD; 3196} 3197 3198static irqreturn_t sata_int_v2_hw(int irq_no, void *p) 3199{ 3200 struct hisi_sas_phy *phy = p; 3201 struct hisi_hba *hisi_hba = phy->hisi_hba; 3202 struct asd_sas_phy *sas_phy = &phy->sas_phy; 3203 struct device *dev = hisi_hba->dev; 3204 struct hisi_sas_initial_fis *initial_fis; 3205 struct dev_to_host_fis *fis; 3206 u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate; 3207 irqreturn_t res = IRQ_HANDLED; 3208 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0}; 3209 int phy_no, offset; 3210 3211 timer_delete(&phy->timer); 3212 3213 phy_no = sas_phy->id; 3214 initial_fis = &hisi_hba->initial_fis[phy_no]; 3215 fis = &initial_fis->fis; 3216 3217 offset = 4 * (phy_no / 4); 3218 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1 + offset); 3219 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset, 3220 ent_msk | 1 << ((phy_no % 4) * 8)); 3221 3222 ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1 + offset); 3223 ent_tmp = ent_int & (1 << (ENT_INT_SRC1_D2H_FIS_CH1_OFF * 3224 (phy_no % 4))); 3225 ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4); 3226 if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) { 3227 dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no); 3228 res = IRQ_NONE; 3229 goto end; 3230 } 3231 3232 /* check ERR bit of Status Register */ 3233 if (fis->status & ATA_ERR) { 3234 dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", phy_no, 3235 fis->status); 3236 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 3237 res = IRQ_NONE; 3238 goto end; 3239 } 3240 3241 if (unlikely(phy_no == 8)) { 3242 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE); 3243 3244 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >> 3245 PORT_STATE_PHY8_PORT_NUM_OFF; 3246 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >> 3247 PORT_STATE_PHY8_CONN_RATE_OFF; 3248 } else { 3249 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 3250 port_id = (port_id >> (4 * phy_no)) & 0xf; 3251 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); 3252 link_rate = (link_rate >> (phy_no * 4)) & 0xf; 3253 } 3254 3255 if (port_id == 0xf) { 3256 dev_err(dev, "sata int: phy%d invalid portid\n", phy_no); 3257 res = IRQ_NONE; 3258 goto end; 3259 } 3260 3261 sas_phy->linkrate = link_rate; 3262 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no, 3263 HARD_PHY_LINKRATE); 3264 phy->maximum_linkrate = hard_phy_linkrate & 0xf; 3265 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf; 3266 3267 sas_phy->oob_mode = SATA_OOB_MODE; 3268 /* Make up some unique SAS address */ 3269 attached_sas_addr[0] = 0x50; 3270 attached_sas_addr[6] = hisi_hba->shost->host_no; 3271 attached_sas_addr[7] = phy_no; 3272 memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE); 3273 memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis)); 3274 dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate); 3275 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); 3276 phy->port_id = port_id; 3277 phy->phy_type |= PORT_TYPE_SATA; 3278 phy->phy_attached = 1; 3279 phy->identify.device_type = SAS_SATA_DEV; 3280 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 3281 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 3282 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP); 3283 3284 if (phy->reset_completion) 3285 complete(phy->reset_completion); 3286end: 3287 hisi_sas_write32(hisi_hba, ENT_INT_SRC1 + offset, ent_tmp); 3288 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset, ent_msk); 3289 3290 return res; 3291} 3292 3293static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = { 3294 int_phy_updown_v2_hw, 3295 int_chnl_int_v2_hw, 3296}; 3297 3298static irq_handler_t fatal_interrupts[HISI_SAS_FATAL_INT_NR] = { 3299 fatal_ecc_int_v2_hw, 3300 fatal_axi_int_v2_hw 3301}; 3302 3303#define CQ0_IRQ_INDEX (96) 3304 3305static int hisi_sas_v2_interrupt_preinit(struct hisi_hba *hisi_hba) 3306{ 3307 struct platform_device *pdev = hisi_hba->platform_dev; 3308 struct Scsi_Host *shost = hisi_hba->shost; 3309 struct irq_affinity desc = { 3310 .pre_vectors = CQ0_IRQ_INDEX, 3311 .post_vectors = 16, 3312 }; 3313 int resv = desc.pre_vectors + desc.post_vectors, minvec = resv + 1, nvec; 3314 3315 nvec = devm_platform_get_irqs_affinity(pdev, &desc, minvec, 128, 3316 &hisi_hba->irq_map); 3317 if (nvec < 0) 3318 return nvec; 3319 3320 shost->nr_hw_queues = hisi_hba->cq_nvecs = nvec - resv; 3321 3322 return 0; 3323} 3324 3325/* 3326 * There is a limitation in the hip06 chipset that we need 3327 * to map in all mbigen interrupts, even if they are not used. 3328 */ 3329static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba) 3330{ 3331 struct platform_device *pdev = hisi_hba->platform_dev; 3332 struct device *dev = &pdev->dev; 3333 int irq, rc = 0; 3334 int i, phy_no, fatal_no, queue_no; 3335 3336 for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) { 3337 irq = hisi_hba->irq_map[i + 1]; /* Phy up/down is irq1 */ 3338 rc = devm_request_irq(dev, irq, phy_interrupts[i], 0, 3339 DRV_NAME " phy", hisi_hba); 3340 if (rc) { 3341 dev_err(dev, "irq init: could not request phy interrupt %d, rc=%d\n", 3342 irq, rc); 3343 rc = -ENOENT; 3344 goto err_out; 3345 } 3346 } 3347 3348 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) { 3349 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 3350 3351 irq = hisi_hba->irq_map[phy_no + 72]; 3352 rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0, 3353 DRV_NAME " sata", phy); 3354 if (rc) { 3355 dev_err(dev, "irq init: could not request sata interrupt %d, rc=%d\n", 3356 irq, rc); 3357 rc = -ENOENT; 3358 goto err_out; 3359 } 3360 } 3361 3362 for (fatal_no = 0; fatal_no < HISI_SAS_FATAL_INT_NR; fatal_no++) { 3363 irq = hisi_hba->irq_map[fatal_no + 81]; 3364 rc = devm_request_irq(dev, irq, fatal_interrupts[fatal_no], 0, 3365 DRV_NAME " fatal", hisi_hba); 3366 if (rc) { 3367 dev_err(dev, "irq init: could not request fatal interrupt %d, rc=%d\n", 3368 irq, rc); 3369 rc = -ENOENT; 3370 goto err_out; 3371 } 3372 } 3373 3374 for (queue_no = 0; queue_no < hisi_hba->cq_nvecs; queue_no++) { 3375 struct hisi_sas_cq *cq = &hisi_hba->cq[queue_no]; 3376 3377 cq->irq_no = hisi_hba->irq_map[queue_no + 96]; 3378 rc = devm_request_threaded_irq(dev, cq->irq_no, 3379 cq_interrupt_v2_hw, 3380 cq_thread_v2_hw, IRQF_ONESHOT, 3381 DRV_NAME " cq", cq); 3382 if (rc) { 3383 dev_err(dev, "irq init: could not request cq interrupt %d, rc=%d\n", 3384 cq->irq_no, rc); 3385 rc = -ENOENT; 3386 goto err_out; 3387 } 3388 cq->irq_mask = irq_get_affinity_mask(cq->irq_no); 3389 } 3390err_out: 3391 return rc; 3392} 3393 3394static int hisi_sas_v2_init(struct hisi_hba *hisi_hba) 3395{ 3396 int rc; 3397 3398 memset(hisi_hba->sata_dev_bitmap, 0, sizeof(hisi_hba->sata_dev_bitmap)); 3399 3400 rc = hw_init_v2_hw(hisi_hba); 3401 if (rc) 3402 return rc; 3403 3404 rc = interrupt_init_v2_hw(hisi_hba); 3405 if (rc) 3406 return rc; 3407 3408 return 0; 3409} 3410 3411static void interrupt_disable_v2_hw(struct hisi_hba *hisi_hba) 3412{ 3413 struct platform_device *pdev = hisi_hba->platform_dev; 3414 int i; 3415 3416 for (i = 0; i < hisi_hba->queue_count; i++) 3417 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1); 3418 3419 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff); 3420 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff); 3421 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff); 3422 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff); 3423 3424 for (i = 0; i < hisi_hba->n_phy; i++) { 3425 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff); 3426 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff); 3427 } 3428 3429 for (i = 0; i < 128; i++) 3430 synchronize_irq(platform_get_irq(pdev, i)); 3431} 3432 3433 3434static u32 get_phys_state_v2_hw(struct hisi_hba *hisi_hba) 3435{ 3436 return hisi_sas_read32(hisi_hba, PHY_STATE); 3437} 3438 3439static int soft_reset_v2_hw(struct hisi_hba *hisi_hba) 3440{ 3441 struct device *dev = hisi_hba->dev; 3442 int rc, cnt; 3443 3444 interrupt_disable_v2_hw(hisi_hba); 3445 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0); 3446 3447 hisi_sas_stop_phys(hisi_hba); 3448 3449 mdelay(10); 3450 3451 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1); 3452 3453 /* wait until bus idle */ 3454 cnt = 0; 3455 while (1) { 3456 u32 status = hisi_sas_read32_relaxed(hisi_hba, 3457 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN); 3458 3459 if (status == 0x3) 3460 break; 3461 3462 udelay(10); 3463 if (cnt++ > 10) { 3464 dev_err(dev, "wait axi bus state to idle timeout!\n"); 3465 return -1; 3466 } 3467 } 3468 3469 hisi_sas_init_mem(hisi_hba); 3470 3471 rc = hw_init_v2_hw(hisi_hba); 3472 if (rc) 3473 return rc; 3474 3475 phys_reject_stp_links_v2_hw(hisi_hba); 3476 3477 return 0; 3478} 3479 3480static int write_gpio_v2_hw(struct hisi_hba *hisi_hba, u8 reg_type, 3481 u8 reg_index, u8 reg_count, u8 *write_data) 3482{ 3483 struct device *dev = hisi_hba->dev; 3484 int phy_no, count; 3485 3486 if (!hisi_hba->sgpio_regs) 3487 return -EOPNOTSUPP; 3488 3489 switch (reg_type) { 3490 case SAS_GPIO_REG_TX: 3491 count = reg_count * 4; 3492 count = min(count, hisi_hba->n_phy); 3493 3494 for (phy_no = 0; phy_no < count; phy_no++) { 3495 /* 3496 * GPIO_TX[n] register has the highest numbered drive 3497 * of the four in the first byte and the lowest 3498 * numbered drive in the fourth byte. 3499 * See SFF-8485 Rev. 0.7 Table 24. 3500 */ 3501 void __iomem *reg_addr = hisi_hba->sgpio_regs + 3502 reg_index * 4 + phy_no; 3503 int data_idx = phy_no + 3 - (phy_no % 4) * 2; 3504 3505 writeb(write_data[data_idx], reg_addr); 3506 } 3507 3508 break; 3509 default: 3510 dev_err(dev, "write gpio: unsupported or bad reg type %d\n", 3511 reg_type); 3512 return -EINVAL; 3513 } 3514 3515 return 0; 3516} 3517 3518static void wait_cmds_complete_timeout_v2_hw(struct hisi_hba *hisi_hba, 3519 int delay_ms, int timeout_ms) 3520{ 3521 struct device *dev = hisi_hba->dev; 3522 int entries, entries_old = 0, time; 3523 3524 for (time = 0; time < timeout_ms; time += delay_ms) { 3525 entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT); 3526 if (entries == entries_old) 3527 break; 3528 3529 entries_old = entries; 3530 msleep(delay_ms); 3531 } 3532 3533 if (time >= timeout_ms) { 3534 dev_dbg(dev, "Wait commands complete timeout!\n"); 3535 return; 3536 } 3537 3538 dev_dbg(dev, "wait commands complete %dms\n", time); 3539 3540} 3541 3542static struct attribute *host_v2_hw_attrs[] = { 3543 &dev_attr_phy_event_threshold.attr, 3544 NULL 3545}; 3546 3547ATTRIBUTE_GROUPS(host_v2_hw); 3548 3549static const struct attribute_group *sdev_groups_v2_hw[] = { 3550 &sas_ata_sdev_attr_group, 3551 NULL 3552}; 3553 3554static void map_queues_v2_hw(struct Scsi_Host *shost) 3555{ 3556 struct hisi_hba *hisi_hba = shost_priv(shost); 3557 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT]; 3558 const struct cpumask *mask; 3559 unsigned int queue, cpu; 3560 3561 for (queue = 0; queue < qmap->nr_queues; queue++) { 3562 mask = irq_get_affinity_mask(hisi_hba->irq_map[96 + queue]); 3563 if (!mask) 3564 continue; 3565 3566 for_each_cpu(cpu, mask) 3567 qmap->mq_map[cpu] = qmap->queue_offset + queue; 3568 } 3569} 3570 3571static int check_fw_info_v2_hw(struct hisi_hba *hisi_hba) 3572{ 3573 struct device *dev = hisi_hba->dev; 3574 3575 if (hisi_hba->n_phy < 0 || hisi_hba->n_phy > 9) { 3576 dev_err(dev, "invalid phy number from FW\n"); 3577 return -EINVAL; 3578 } 3579 3580 if (hisi_hba->queue_count < 0 || hisi_hba->queue_count > 16) { 3581 dev_err(dev, "invalid queue count from FW\n"); 3582 return -EINVAL; 3583 } 3584 3585 return 0; 3586} 3587 3588static const struct scsi_host_template sht_v2_hw = { 3589 LIBSAS_SHT_BASE_NO_SLAVE_INIT 3590 .sdev_configure = hisi_sas_sdev_configure, 3591 .scan_finished = hisi_sas_scan_finished, 3592 .scan_start = hisi_sas_scan_start, 3593 .sg_tablesize = HISI_SAS_SGE_PAGE_CNT, 3594 .sdev_init = hisi_sas_sdev_init, 3595 .shost_groups = host_v2_hw_groups, 3596 .sdev_groups = sdev_groups_v2_hw, 3597 .host_reset = hisi_sas_host_reset, 3598 .map_queues = map_queues_v2_hw, 3599 .host_tagset = 1, 3600}; 3601 3602static const struct hisi_sas_hw hisi_sas_v2_hw = { 3603 .hw_init = hisi_sas_v2_init, 3604 .fw_info_check = check_fw_info_v2_hw, 3605 .interrupt_preinit = hisi_sas_v2_interrupt_preinit, 3606 .setup_itct = setup_itct_v2_hw, 3607 .slot_index_alloc = slot_index_alloc_quirk_v2_hw, 3608 .alloc_dev = alloc_dev_quirk_v2_hw, 3609 .sl_notify_ssp = sl_notify_ssp_v2_hw, 3610 .get_wideport_bitmap = get_wideport_bitmap_v2_hw, 3611 .clear_itct = clear_itct_v2_hw, 3612 .free_device = free_device_v2_hw, 3613 .prep_smp = prep_smp_v2_hw, 3614 .prep_ssp = prep_ssp_v2_hw, 3615 .prep_stp = prep_ata_v2_hw, 3616 .prep_abort = prep_abort_v2_hw, 3617 .start_delivery = start_delivery_v2_hw, 3618 .phys_init = phys_init_v2_hw, 3619 .phy_start = start_phy_v2_hw, 3620 .phy_disable = disable_phy_v2_hw, 3621 .phy_hard_reset = phy_hard_reset_v2_hw, 3622 .get_events = phy_get_events_v2_hw, 3623 .phy_set_linkrate = phy_set_linkrate_v2_hw, 3624 .phy_get_max_linkrate = phy_get_max_linkrate_v2_hw, 3625 .complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr), 3626 .soft_reset = soft_reset_v2_hw, 3627 .get_phys_state = get_phys_state_v2_hw, 3628 .write_gpio = write_gpio_v2_hw, 3629 .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v2_hw, 3630 .sht = &sht_v2_hw, 3631}; 3632 3633static int hisi_sas_v2_probe(struct platform_device *pdev) 3634{ 3635 return hisi_sas_probe(pdev, &hisi_sas_v2_hw); 3636} 3637 3638static const struct of_device_id sas_v2_of_match[] = { 3639 { .compatible = "hisilicon,hip06-sas-v2",}, 3640 { .compatible = "hisilicon,hip07-sas-v2",}, 3641 {}, 3642}; 3643MODULE_DEVICE_TABLE(of, sas_v2_of_match); 3644 3645static const struct acpi_device_id sas_v2_acpi_match[] = { 3646 { "HISI0162", 0 }, 3647 { } 3648}; 3649 3650MODULE_DEVICE_TABLE(acpi, sas_v2_acpi_match); 3651 3652static struct platform_driver hisi_sas_v2_driver = { 3653 .probe = hisi_sas_v2_probe, 3654 .remove = hisi_sas_remove, 3655 .driver = { 3656 .name = DRV_NAME, 3657 .of_match_table = sas_v2_of_match, 3658 .acpi_match_table = sas_v2_acpi_match, 3659 }, 3660}; 3661 3662module_platform_driver(hisi_sas_v2_driver); 3663 3664MODULE_LICENSE("GPL"); 3665MODULE_AUTHOR("John Garry <john.garry@huawei.com>"); 3666MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver"); 3667MODULE_ALIAS("platform:" DRV_NAME);
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