aic7xxx.reg

   1/*
   2 * Aic7xxx register and scratch ram definitions.
   3 *
   4 * Copyright (c) 1994-2001 Justin T. Gibbs.
   5 * Copyright (c) 2000-2001 Adaptec Inc.
   6 * All rights reserved.
   7 *
   8 * Redistribution and use in source and binary forms, with or without
   9 * modification, are permitted provided that the following conditions
  10 * are met:
  11 * 1. Redistributions of source code must retain the above copyright
  12 *    notice, this list of conditions, and the following disclaimer,
  13 *    without modification.
  14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  15 *    substantially similar to the "NO WARRANTY" disclaimer below
  16 *    ("Disclaimer") and any redistribution must be conditioned upon
  17 *    including a substantially similar Disclaimer requirement for further
  18 *    binary redistribution.
  19 * 3. Neither the names of the above-listed copyright holders nor the names
  20 *    of any contributors may be used to endorse or promote products derived
  21 *    from this software without specific prior written permission.
  22 *
  23 * Alternatively, this software may be distributed under the terms of the
  24 * GNU General Public License ("GPL") version 2 as published by the Free
  25 * Software Foundation.
  26 *
  27 * NO WARRANTY
  28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  38 * POSSIBILITY OF SUCH DAMAGES.
  39 *
  40 * $FreeBSD$
  41 */
  42VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic7xxx.reg#40 $"
  43
  44/*
  45 * This file is processed by the aic7xxx_asm utility for use in assembling
  46 * firmware for the aic7xxx family of SCSI host adapters as well as to generate
  47 * a C header file for use in the kernel portion of the Aic7xxx driver.
  48 *
  49 * All page numbers refer to the Adaptec AIC-7770 Data Book available from
  50 * Adaptec's Technical Documents Department 1-800-934-2766
  51 */
  52
  53/*
  54 * Registers marked "dont_generate_debug_code" are not (yet) referenced
  55 * from the driver code, and this keyword inhibit generation
  56 * of debug code for them.
  57 *
  58 * REG_PRETTY_PRINT config will complain if dont_generate_debug_code
  59 * is added to the register which is referenced in the driver.
  60 * Unreferenced register with no dont_generate_debug_code will result
  61 * in dead code. No warning is issued.
  62 */
  63
  64/*
  65 * SCSI Sequence Control (p. 3-11).
  66 * Each bit, when set starts a specific SCSI sequence on the bus
  67 */
  68register SCSISEQ {
  69	address			0x000
  70	access_mode RW
  71	field	TEMODE		0x80
  72	field	ENSELO		0x40
  73	field	ENSELI		0x20
  74	field	ENRSELI		0x10
  75	field	ENAUTOATNO	0x08
  76	field	ENAUTOATNI	0x04
  77	field	ENAUTOATNP	0x02
  78	field	SCSIRSTO	0x01
  79}
  80
  81/*
  82 * SCSI Transfer Control 0 Register (pp. 3-13).
  83 * Controls the SCSI module data path.
  84 */
  85register SXFRCTL0 {
  86	address			0x001
  87	access_mode RW
  88	field	DFON		0x80
  89	field	DFPEXP		0x40
  90	field	FAST20		0x20
  91	field	CLRSTCNT	0x10
  92	field	SPIOEN		0x08
  93	field	SCAMEN		0x04
  94	field	CLRCHN		0x02
  95}
  96
  97/*
  98 * SCSI Transfer Control 1 Register (pp. 3-14,15).
  99 * Controls the SCSI module data path.
 100 */
 101register SXFRCTL1 {
 102	address			0x002
 103	access_mode RW
 104	field	BITBUCKET	0x80
 105	field	SWRAPEN		0x40
 106	field	ENSPCHK		0x20
 107	mask	STIMESEL	0x18
 108	field	ENSTIMER	0x04
 109	field	ACTNEGEN	0x02
 110	field	STPWEN		0x01	/* Powered Termination */
 111	dont_generate_debug_code
 112}
 113
 114/*
 115 * SCSI Control Signal Read Register (p. 3-15).
 116 * Reads the actual state of the SCSI bus pins
 117 */
 118register SCSISIGI {
 119	address			0x003
 120	access_mode RO
 121	field	CDI		0x80
 122	field	IOI		0x40
 123	field	MSGI		0x20
 124	field	ATNI		0x10
 125	field	SELI		0x08
 126	field	BSYI		0x04
 127	field	REQI		0x02
 128	field	ACKI		0x01
 129/*
 130 * Possible phases in SCSISIGI
 131 */
 132	mask	PHASE_MASK	CDI|IOI|MSGI
 133	mask	P_DATAOUT	0x00
 134	mask	P_DATAIN	IOI
 135	mask	P_DATAOUT_DT	P_DATAOUT|MSGI
 136	mask	P_DATAIN_DT	P_DATAIN|MSGI
 137	mask	P_COMMAND	CDI
 138	mask	P_MESGOUT	CDI|MSGI
 139	mask	P_STATUS	CDI|IOI
 140	mask	P_MESGIN	CDI|IOI|MSGI
 141}
 142
 143/*
 144 * SCSI Control Signal Write Register (p. 3-16).
 145 * Writing to this register modifies the control signals on the bus.  Only
 146 * those signals that are allowed in the current mode (Initiator/Target) are
 147 * asserted.
 148 */
 149register SCSISIGO {
 150	address			0x003
 151	access_mode WO
 152	field	CDO		0x80
 153	field	IOO		0x40
 154	field	MSGO		0x20
 155	field	ATNO		0x10
 156	field	SELO		0x08
 157	field	BSYO		0x04
 158	field	REQO		0x02
 159	field	ACKO		0x01
 160/*
 161 * Possible phases to write into SCSISIG0
 162 */
 163	mask	PHASE_MASK	CDI|IOI|MSGI
 164	mask	P_DATAOUT	0x00
 165	mask	P_DATAIN	IOI
 166	mask	P_COMMAND	CDI
 167	mask	P_MESGOUT	CDI|MSGI
 168	mask	P_STATUS	CDI|IOI
 169	mask	P_MESGIN	CDI|IOI|MSGI
 170	dont_generate_debug_code
 171}
 172
 173/* 
 174 * SCSI Rate Control (p. 3-17).
 175 * Contents of this register determine the Synchronous SCSI data transfer
 176 * rate and the maximum synchronous Req/Ack offset.  An offset of 0 in the
 177 * SOFS (3:0) bits disables synchronous data transfers.  Any offset value
 178 * greater than 0 enables synchronous transfers.
 179 */
 180register SCSIRATE {
 181	address			0x004
 182	access_mode RW
 183	field	WIDEXFER	0x80		/* Wide transfer control */
 184	field	ENABLE_CRC	0x40		/* CRC for D-Phases */
 185	field	SINGLE_EDGE	0x10		/* Disable DT Transfers */
 186	mask	SXFR		0x70		/* Sync transfer rate */
 187	mask	SXFR_ULTRA2	0x0f		/* Sync transfer rate */
 188	mask	SOFS		0x0f		/* Sync offset */
 189}
 190
 191/*
 192 * SCSI ID (p. 3-18).
 193 * Contains the ID of the board and the current target on the
 194 * selected channel.
 195 */
 196register SCSIID	{
 197	address			0x005
 198	access_mode RW
 199	mask	TID		0xf0		/* Target ID mask */
 200	mask	TWIN_TID	0x70
 201	field	TWIN_CHNLB	0x80
 202	mask	OID		0x0f		/* Our ID mask */
 203	/*
 204	 * SCSI Maximum Offset (p. 4-61 aic7890/91 Data Book)
 205	 * The aic7890/91 allow an offset of up to 127 transfers in both wide
 206	 * and narrow mode.
 207	 */
 208	alias	SCSIOFFSET
 209	mask	SOFS_ULTRA2	0x7f		/* Sync offset U2 chips */
 210	dont_generate_debug_code
 211}
 212
 213/*
 214 * SCSI Latched Data (p. 3-19).
 215 * Read/Write latches used to transfer data on the SCSI bus during
 216 * Automatic or Manual PIO mode.  SCSIDATH can be used for the
 217 * upper byte of a 16bit wide asynchronouse data phase transfer.
 218 */
 219register SCSIDATL {
 220	address			0x006
 221	access_mode RW
 222	dont_generate_debug_code
 223}
 224
 225register SCSIDATH {
 226	address			0x007
 227	access_mode RW
 228}
 229
 230/*
 231 * SCSI Transfer Count (pp. 3-19,20)
 232 * These registers count down the number of bytes transferred
 233 * across the SCSI bus.  The counter is decremented only once
 234 * the data has been safely transferred.  SDONE in SSTAT0 is
 235 * set when STCNT goes to 0
 236 */ 
 237register STCNT {
 238	address			0x008
 239	size	3
 240	access_mode RW
 241	dont_generate_debug_code
 242}
 243
 244/* ALT_MODE registers (Ultra2 and Ultra160 chips) */
 245register SXFRCTL2 {
 246	address			0x013
 247	access_mode RW
 248	field	AUTORSTDIS	0x10
 249	field	CMDDMAEN	0x08
 250	mask	ASYNC_SETUP	0x07
 251}
 252
 253/* ALT_MODE register on Ultra160 chips */
 254register OPTIONMODE {
 255	address			0x008
 256	access_mode RW
 257	count		2
 258	field	AUTORATEEN		0x80
 259	field	AUTOACKEN		0x40
 260	field	ATNMGMNTEN		0x20
 261	field	BUSFREEREV		0x10
 262	field	EXPPHASEDIS		0x08
 263	field	SCSIDATL_IMGEN		0x04
 264	field	AUTO_MSGOUT_DE		0x02
 265	field	DIS_MSGIN_DUALEDGE	0x01
 266	mask	OPTIONMODE_DEFAULTS	AUTO_MSGOUT_DE|DIS_MSGIN_DUALEDGE
 267	dont_generate_debug_code
 268}
 269
 270/* ALT_MODE register on Ultra160 chips */
 271register TARGCRCCNT {
 272	address			0x00a
 273	size	2
 274	access_mode RW
 275	count		2
 276	dont_generate_debug_code
 277}
 278
 279/*
 280 * Clear SCSI Interrupt 0 (p. 3-20)
 281 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0.
 282 */
 283register CLRSINT0 {
 284	address			0x00b
 285	access_mode WO
 286	field	CLRSELDO	0x40
 287	field	CLRSELDI	0x20
 288	field	CLRSELINGO	0x10
 289	field	CLRSWRAP	0x08
 290	field	CLRIOERR	0x08	/* Ultra2 Only */
 291	field	CLRSPIORDY	0x02
 292	dont_generate_debug_code
 293}
 294
 295/*
 296 * SCSI Status 0 (p. 3-21)
 297 * Contains one set of SCSI Interrupt codes
 298 * These are most likely of interest to the sequencer
 299 */
 300register SSTAT0	{
 301	address			0x00b
 302	access_mode RO
 303	field	TARGET		0x80	/* Board acting as target */
 304	field	SELDO		0x40	/* Selection Done */
 305	field	SELDI		0x20	/* Board has been selected */
 306	field	SELINGO		0x10	/* Selection In Progress */
 307	field	SWRAP		0x08	/* 24bit counter wrap */
 308	field	IOERR		0x08	/* LVD Tranceiver mode changed */
 309	field	SDONE		0x04	/* STCNT = 0x000000 */
 310	field	SPIORDY		0x02	/* SCSI PIO Ready */
 311	field	DMADONE		0x01	/* DMA transfer completed */
 312}
 313
 314/*
 315 * Clear SCSI Interrupt 1 (p. 3-23)
 316 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1.
 317 */
 318register CLRSINT1 {
 319	address			0x00c
 320	access_mode WO
 321	field	CLRSELTIMEO	0x80
 322	field	CLRATNO		0x40
 323	field	CLRSCSIRSTI	0x20
 324	field	CLRBUSFREE	0x08
 325	field	CLRSCSIPERR	0x04
 326	field	CLRPHASECHG	0x02
 327	field	CLRREQINIT	0x01
 328	dont_generate_debug_code
 329}
 330
 331/*
 332 * SCSI Status 1 (p. 3-24)
 333 */
 334register SSTAT1	{
 335	address			0x00c
 336	access_mode RO
 337	field	SELTO		0x80
 338	field	ATNTARG 	0x40
 339	field	SCSIRSTI	0x20
 340	field	PHASEMIS	0x10
 341	field	BUSFREE		0x08
 342	field	SCSIPERR	0x04
 343	field	PHASECHG	0x02
 344	field	REQINIT		0x01
 345}
 346
 347/*
 348 * SCSI Status 2 (pp. 3-25,26)
 349 */
 350register SSTAT2 {
 351	address			0x00d
 352	access_mode RO
 353	field	OVERRUN		0x80
 354	field	SHVALID		0x40	/* Shadow Layer non-zero */
 355	field	EXP_ACTIVE	0x10	/* SCSI Expander Active */
 356	field	CRCVALERR	0x08	/* CRC doesn't match (U3 only) */
 357	field	CRCENDERR	0x04	/* No terminal CRC packet (U3 only) */
 358	field	CRCREQERR	0x02	/* Illegal CRC packet req (U3 only) */
 359	field	DUAL_EDGE_ERR	0x01	/* Incorrect data phase (U3 only) */
 360	mask	SFCNT		0x1f
 361}
 362
 363/*
 364 * SCSI Status 3 (p. 3-26)
 365 */
 366register SSTAT3 {
 367	address			0x00e
 368	access_mode RO
 369	count		2
 370	mask	SCSICNT		0xf0
 371	mask	OFFCNT		0x0f
 372	mask	U2OFFCNT	0x7f
 373}
 374
 375/*
 376 * SCSI ID for the aic7890/91 chips
 377 */
 378register SCSIID_ULTRA2 {
 379	address			0x00f
 380	access_mode RW
 381	mask	TID		0xf0		/* Target ID mask */
 382	mask	OID		0x0f		/* Our ID mask */
 383	dont_generate_debug_code
 384}
 385
 386/*
 387 * SCSI Interrupt Mode 1 (p. 3-28)
 388 * Setting any bit will enable the corresponding function
 389 * in SIMODE0 to interrupt via the IRQ pin.
 390 */
 391register SIMODE0 {
 392	address			0x010
 393	access_mode RW
 394	count		2
 395	field	ENSELDO		0x40
 396	field	ENSELDI		0x20
 397	field	ENSELINGO	0x10
 398	field	ENSWRAP		0x08
 399	field	ENIOERR		0x08	/* LVD Tranceiver mode changes */
 400	field	ENSDONE		0x04
 401	field	ENSPIORDY	0x02
 402	field	ENDMADONE	0x01
 403}
 404
 405/*
 406 * SCSI Interrupt Mode 1 (pp. 3-28,29)
 407 * Setting any bit will enable the corresponding function
 408 * in SIMODE1 to interrupt via the IRQ pin.
 409 */
 410register SIMODE1 {
 411	address			0x011
 412	access_mode RW
 413	field	ENSELTIMO	0x80
 414	field	ENATNTARG	0x40
 415	field	ENSCSIRST	0x20
 416	field	ENPHASEMIS	0x10
 417	field	ENBUSFREE	0x08
 418	field	ENSCSIPERR	0x04
 419	field	ENPHASECHG	0x02
 420	field	ENREQINIT	0x01
 421}
 422
 423/*
 424 * SCSI Data Bus (High) (p. 3-29)
 425 * This register reads data on the SCSI Data bus directly.
 426 */
 427register SCSIBUSL {
 428	address			0x012
 429	access_mode RW
 430}
 431
 432register SCSIBUSH {
 433	address			0x013
 434	access_mode RW
 435}
 436
 437/*
 438 * SCSI/Host Address (p. 3-30)
 439 * These registers hold the host address for the byte about to be
 440 * transferred on the SCSI bus.  They are counted up in the same
 441 * manner as STCNT is counted down.  SHADDR should always be used
 442 * to determine the address of the last byte transferred since HADDR
 443 * can be skewed by write ahead.
 444 */
 445register SHADDR {
 446	address			0x014
 447	size	4
 448	access_mode RO
 449	dont_generate_debug_code
 450}
 451
 452/*
 453 * Selection Timeout Timer (p. 3-30)
 454 */
 455register SELTIMER {
 456	address			0x018
 457	access_mode RW
 458	count		1
 459	field	STAGE6		0x20
 460	field	STAGE5		0x10
 461	field	STAGE4		0x08
 462	field	STAGE3		0x04
 463	field	STAGE2		0x02
 464	field	STAGE1		0x01
 465	alias	TARGIDIN
 466	dont_generate_debug_code
 467}
 468
 469/*
 470 * Selection/Reselection ID (p. 3-31)
 471 * Upper four bits are the device id.  The ONEBIT is set when the re/selecting
 472 * device did not set its own ID.
 473 */
 474register SELID {
 475	address			0x019
 476	access_mode RW
 477	mask	SELID_MASK	0xf0
 478	field	ONEBIT		0x08
 479	dont_generate_debug_code
 480}
 481
 482register SCAMCTL {
 483	address			0x01a
 484	access_mode RW
 485	field	ENSCAMSELO	0x80
 486	field	CLRSCAMSELID	0x40
 487	field	ALTSTIM		0x20
 488	field	DFLTTID		0x10
 489	mask	SCAMLVL		0x03
 490}
 491
 492/*
 493 * Target Mode Selecting in ID bitmask (aic7890/91/96/97)
 494 */
 495register TARGID {
 496	address			0x01b
 497	size			2
 498	access_mode RW
 499	count		14
 500	dont_generate_debug_code
 501}
 502
 503/*
 504 * Serial Port I/O Cabability register (p. 4-95 aic7860 Data Book)
 505 * Indicates if external logic has been attached to the chip to
 506 * perform the tasks of accessing a serial eeprom, testing termination
 507 * strength, and performing cable detection.  On the aic7860, most of
 508 * these features are handled on chip, but on the aic7855 an attached
 509 * aic3800 does the grunt work.
 510 */
 511register SPIOCAP {
 512	address			0x01b
 513	access_mode RW
 514	count		10
 515	field	SOFT1		0x80
 516	field	SOFT0		0x40
 517	field	SOFTCMDEN	0x20	
 518	field	EXT_BRDCTL	0x10	/* External Board control */
 519	field	SEEPROM		0x08	/* External serial eeprom logic */
 520	field	EEPROM		0x04	/* Writable external BIOS ROM */
 521	field	ROM		0x02	/* Logic for accessing external ROM */
 522	field	SSPIOCPS	0x01	/* Termination and cable detection */
 523	dont_generate_debug_code
 524}
 525
 526register BRDCTL	{
 527	address			0x01d
 528	count		11
 529	field	BRDDAT7		0x80
 530	field	BRDDAT6		0x40
 531	field	BRDDAT5		0x20
 532	field	BRDSTB		0x10
 533	field	BRDCS		0x08
 534	field	BRDRW		0x04
 535	field	BRDCTL1		0x02
 536	field	BRDCTL0		0x01
 537	/* 7890 Definitions */
 538	field	BRDDAT4		0x10
 539	field	BRDDAT3		0x08
 540	field	BRDDAT2		0x04
 541	field	BRDRW_ULTRA2	0x02
 542	field	BRDSTB_ULTRA2	0x01
 543	dont_generate_debug_code
 544}
 545
 546/*
 547 * Serial EEPROM Control (p. 4-92 in 7870 Databook)
 548 * Controls the reading and writing of an external serial 1-bit
 549 * EEPROM Device.  In order to access the serial EEPROM, you must
 550 * first set the SEEMS bit that generates a request to the memory
 551 * port for access to the serial EEPROM device.  When the memory
 552 * port is not busy servicing another request, it reconfigures
 553 * to allow access to the serial EEPROM.  When this happens, SEERDY
 554 * gets set high to verify that the memory port access has been
 555 * granted.  
 556 *
 557 * After successful arbitration for the memory port, the SEECS bit of 
 558 * the SEECTL register is connected to the chip select.  The SEECK, 
 559 * SEEDO, and SEEDI are connected to the clock, data out, and data in 
 560 * lines respectively.  The SEERDY bit of SEECTL is useful in that it 
 561 * gives us an 800 nsec timer.  After a write to the SEECTL register, 
 562 * the SEERDY goes high 800 nsec later.  The one exception to this is 
 563 * when we first request access to the memory port.  The SEERDY goes 
 564 * high to signify that access has been granted and, for this case, has 
 565 * no implied timing.
 566 *
 567 * See 93cx6.c for detailed information on the protocol necessary to 
 568 * read the serial EEPROM.
 569 */
 570register SEECTL {
 571	address			0x01e
 572	count		11
 573	field	EXTARBACK	0x80
 574	field	EXTARBREQ	0x40
 575	field	SEEMS		0x20
 576	field	SEERDY		0x10
 577	field	SEECS		0x08
 578	field	SEECK		0x04
 579	field	SEEDO		0x02
 580	field	SEEDI		0x01
 581	dont_generate_debug_code
 582}
 583/*
 584 * SCSI Block Control (p. 3-32)
 585 * Controls Bus type and channel selection.  In a twin channel configuration
 586 * addresses 0x00-0x1e are gated to the appropriate channel based on this
 587 * register.  SELWIDE allows for the coexistence of 8bit and 16bit devices
 588 * on a wide bus.
 589 */
 590register SBLKCTL {
 591	address			0x01f
 592	access_mode RW
 593	field	DIAGLEDEN	0x80	/* Aic78X0 only */
 594	field	DIAGLEDON	0x40	/* Aic78X0 only */
 595	field	AUTOFLUSHDIS	0x20
 596	field	SELBUSB		0x08
 597	field	ENAB40		0x08	/* LVD transceiver active */
 598	field	ENAB20		0x04	/* SE/HVD transceiver active */
 599	field	SELWIDE		0x02
 600	field	XCVR		0x01	/* External transceiver active */
 601}
 602
 603/*
 604 * Sequencer Control (p. 3-33)
 605 * Error detection mode and speed configuration
 606 */
 607register SEQCTL {
 608	address			0x060
 609	access_mode RW
 610	count		15
 611	field	PERRORDIS	0x80
 612	field	PAUSEDIS	0x40
 613	field	FAILDIS		0x20
 614	field	FASTMODE	0x10
 615	field	BRKADRINTEN	0x08
 616	field	STEP		0x04
 617	field	SEQRESET	0x02
 618	field	LOADRAM		0x01
 619}
 620
 621/*
 622 * Sequencer RAM Data (p. 3-34)
 623 * Single byte window into the Scratch Ram area starting at the address
 624 * specified by SEQADDR0 and SEQADDR1.  To write a full word, simply write
 625 * four bytes in succession.  The SEQADDRs will increment after the most
 626 * significant byte is written
 627 */
 628register SEQRAM {
 629	address			0x061
 630	access_mode RW
 631	count		2
 632	dont_generate_debug_code
 633}
 634
 635/*
 636 * Sequencer Address Registers (p. 3-35)
 637 * Only the first bit of SEQADDR1 holds addressing information
 638 */
 639register SEQADDR0 {
 640	address			0x062
 641	access_mode RW
 642	dont_generate_debug_code
 643}
 644
 645register SEQADDR1 {
 646	address			0x063
 647	access_mode RW
 648	count		8
 649	mask	SEQADDR1_MASK	0x01
 650	dont_generate_debug_code
 651}
 652
 653/*
 654 * Accumulator
 655 * We cheat by passing arguments in the Accumulator up to the kernel driver
 656 */
 657register ACCUM {
 658	address			0x064
 659	access_mode RW
 660	accumulator
 661	dont_generate_debug_code
 662}
 663
 664register SINDEX	{
 665	address			0x065
 666	access_mode RW
 667	sindex
 668	dont_generate_debug_code
 669}
 670
 671register DINDEX {
 672	address			0x066
 673	access_mode RW
 674	dont_generate_debug_code
 675}
 676
 677register ALLONES {
 678	address			0x069
 679	access_mode RO
 680	allones
 681	dont_generate_debug_code
 682}
 683
 684register ALLZEROS {
 685	address			0x06a
 686	access_mode RO
 687	allzeros
 688	dont_generate_debug_code
 689}
 690
 691register NONE {
 692	address			0x06a
 693	access_mode WO
 694	none
 695	dont_generate_debug_code
 696}
 697
 698register FLAGS {
 699	address			0x06b
 700	access_mode RO
 701	count		18
 702	field	ZERO		0x02
 703	field	CARRY		0x01
 704	dont_generate_debug_code
 705}
 706
 707register SINDIR	{
 708	address			0x06c
 709	access_mode RO
 710	dont_generate_debug_code
 711}
 712
 713register DINDIR	 {
 714	address			0x06d
 715	access_mode WO
 716	dont_generate_debug_code
 717}
 718
 719register FUNCTION1 {
 720	address			0x06e
 721	access_mode RW
 722}
 723
 724register STACK {
 725	address			0x06f
 726	access_mode RO
 727	count		5
 728	dont_generate_debug_code
 729}
 730
 731const	STACK_SIZE	4
 732
 733/*
 734 * Board Control (p. 3-43)
 735 */
 736register BCTL {
 737	address			0x084
 738	access_mode RW
 739	field	ACE		0x08
 740	field	ENABLE		0x01
 741}
 742
 743/*
 744 * On the aic78X0 chips, Board Control is replaced by the DSCommand
 745 * register (p. 4-64)
 746 */
 747register DSCOMMAND0 {
 748	address			0x084
 749	access_mode RW
 750	count		7
 751	field	CACHETHEN	0x80	/* Cache Threshold enable */
 752	field	DPARCKEN	0x40	/* Data Parity Check Enable */
 753	field	MPARCKEN	0x20	/* Memory Parity Check Enable */
 754	field	EXTREQLCK	0x10	/* External Request Lock */
 755	/* aic7890/91/96/97 only */
 756	field	INTSCBRAMSEL	0x08	/* Internal SCB RAM Select */
 757	field	RAMPS		0x04	/* External SCB RAM Present */
 758	field	USCBSIZE32	0x02	/* Use 32byte SCB Page Size */
 759	field	CIOPARCKEN	0x01	/* Internal bus parity error enable */
 760	dont_generate_debug_code
 761}
 762
 763register DSCOMMAND1 {
 764	address			0x085
 765	access_mode RW
 766	mask	DSLATT		0xfc	/* PCI latency timer (non-ultra2) */
 767	field	HADDLDSEL1	0x02	/* Host Address Load Select Bits */
 768	field	HADDLDSEL0	0x01
 769	dont_generate_debug_code
 770}
 771
 772/*
 773 * Bus On/Off Time (p. 3-44) aic7770 only
 774 */
 775register BUSTIME {
 776	address			0x085
 777	access_mode RW
 778	count		2
 779	mask	BOFF		0xf0
 780	mask	BON		0x0f
 781	dont_generate_debug_code
 782}
 783
 784/*
 785 * Bus Speed (p. 3-45) aic7770 only
 786 */
 787register BUSSPD {
 788	address			0x086
 789	access_mode RW
 790	count		2
 791	mask	DFTHRSH		0xc0
 792	mask	STBOFF		0x38
 793	mask	STBON		0x07
 794	mask	DFTHRSH_100	0xc0
 795	mask	DFTHRSH_75	0x80
 796	dont_generate_debug_code
 797}
 798
 799/* aic7850/55/60/70/80/95 only */
 800register DSPCISTATUS {
 801	address			0x086
 802	count		4
 803	mask	DFTHRSH_100	0xc0
 804	dont_generate_debug_code
 805}
 806
 807/* aic7890/91/96/97 only */
 808register HS_MAILBOX {
 809	address			0x086
 810	mask	HOST_MAILBOX	0xF0
 811	mask	SEQ_MAILBOX	0x0F
 812	mask	HOST_TQINPOS	0x80	/* Boundary at either 0 or 128 */
 813	dont_generate_debug_code
 814}
 815
 816const	HOST_MAILBOX_SHIFT	4
 817const	SEQ_MAILBOX_SHIFT	0
 818
 819/*
 820 * Host Control (p. 3-47) R/W
 821 * Overall host control of the device.
 822 */
 823register HCNTRL {
 824	address			0x087
 825	access_mode RW
 826	count		14
 827	field	POWRDN		0x40
 828	field	SWINT		0x10
 829	field	IRQMS		0x08
 830	field	PAUSE		0x04
 831	field	INTEN		0x02
 832	field	CHIPRST		0x01
 833	field	CHIPRSTACK	0x01
 834	dont_generate_debug_code
 835}
 836
 837/*
 838 * Host Address (p. 3-48)
 839 * This register contains the address of the byte about
 840 * to be transferred across the host bus.
 841 */
 842register HADDR {
 843	address			0x088
 844	size	4
 845	access_mode RW
 846	dont_generate_debug_code
 847}
 848
 849register HCNT {
 850	address			0x08c
 851	size	3
 852	access_mode RW
 853	dont_generate_debug_code
 854}
 855
 856/*
 857 * SCB Pointer (p. 3-49)
 858 * Gate one of the SCBs into the SCBARRAY window.
 859 */
 860register SCBPTR {
 861	address			0x090
 862	access_mode RW
 863	dont_generate_debug_code
 864}
 865
 866/*
 867 * Interrupt Status (p. 3-50)
 868 * Status for system interrupts
 869 */
 870register INTSTAT {
 871	address			0x091
 872	access_mode RW
 873	field	BRKADRINT 0x08
 874	field	SCSIINT	  0x04
 875	field	CMDCMPLT  0x02
 876	field	SEQINT    0x01
 877	mask	BAD_PHASE	SEQINT		/* unknown scsi bus phase */
 878	mask	SEND_REJECT	0x10|SEQINT	/* sending a message reject */
 879	mask	PROTO_VIOLATION	0x20|SEQINT	/* SCSI protocol violation */ 
 880	mask	NO_MATCH	0x30|SEQINT	/* no cmd match for reconnect */
 881	mask	IGN_WIDE_RES	0x40|SEQINT	/* Complex IGN Wide Res Msg */
 882	mask	PDATA_REINIT	0x50|SEQINT	/*
 883						 * Returned to data phase
 884						 * that requires data
 885						 * transfer pointers to be
 886						 * recalculated from the
 887						 * transfer residual.
 888						 */
 889	mask	HOST_MSG_LOOP	0x60|SEQINT	/*
 890						 * The bus is ready for the
 891						 * host to perform another
 892						 * message transaction.  This
 893						 * mechanism is used for things
 894						 * like sync/wide negotiation
 895						 * that require a kernel based
 896						 * message state engine.
 897						 */
 898	mask	BAD_STATUS	0x70|SEQINT	/* Bad status from target */
 899	mask	PERR_DETECTED	0x80|SEQINT	/*
 900						 * Either the phase_lock
 901						 * or inb_next routine has
 902						 * noticed a parity error.
 903						 */
 904	mask	DATA_OVERRUN	0x90|SEQINT	/*
 905						 * Target attempted to write
 906						 * beyond the bounds of its
 907						 * command.
 908						 */
 909	mask	MKMSG_FAILED	0xa0|SEQINT	/*
 910						 * Target completed command
 911						 * without honoring our ATN
 912						 * request to issue a message. 
 913						 */
 914	mask	MISSED_BUSFREE	0xb0|SEQINT	/*
 915						 * The sequencer never saw
 916						 * the bus go free after
 917						 * either a command complete
 918						 * or disconnect message.
 919						 */
 920	mask	SCB_MISMATCH	0xc0|SEQINT	/*
 921						 * Downloaded SCB's tag does
 922						 * not match the entry we
 923						 * intended to download.
 924						 */
 925	mask	NO_FREE_SCB	0xd0|SEQINT	/*
 926						 * get_free_or_disc_scb failed.
 927						 */
 928	mask	OUT_OF_RANGE	0xe0|SEQINT
 929
 930	mask	SEQINT_MASK	0xf0|SEQINT	/* SEQINT Status Codes */
 931	mask	INT_PEND  (BRKADRINT|SEQINT|SCSIINT|CMDCMPLT)
 932	dont_generate_debug_code
 933}
 934
 935/*
 936 * Hard Error (p. 3-53)
 937 * Reporting of catastrophic errors.  You usually cannot recover from
 938 * these without a full board reset.
 939 */
 940register ERROR {
 941	address			0x092
 942	access_mode RO
 943	count		26
 944	field	CIOPARERR	0x80	/* Ultra2 only */
 945	field	PCIERRSTAT	0x40	/* PCI only */
 946	field	MPARERR		0x20	/* PCI only */
 947	field	DPARERR		0x10	/* PCI only */
 948	field	SQPARERR	0x08
 949	field	ILLOPCODE	0x04
 950	field	ILLSADDR	0x02
 951	field	ILLHADDR	0x01
 952}
 953
 954/*
 955 * Clear Interrupt Status (p. 3-52)
 956 */
 957register CLRINT {
 958	address			0x092
 959	access_mode WO
 960	count		24
 961	field	CLRPARERR	0x10	/* PCI only */
 962	field	CLRBRKADRINT	0x08
 963	field	CLRSCSIINT      0x04
 964	field	CLRCMDINT 	0x02
 965	field	CLRSEQINT 	0x01
 966	dont_generate_debug_code
 967}
 968
 969register DFCNTRL {
 970	address			0x093
 971	access_mode RW
 972	field	PRELOADEN	0x80	/* aic7890 only */
 973	field	WIDEODD		0x40
 974	field	SCSIEN		0x20
 975	field	SDMAEN		0x10
 976	field	SDMAENACK	0x10
 977	field	HDMAEN		0x08
 978	field	HDMAENACK	0x08
 979	field	DIRECTION	0x04
 980	field	FIFOFLUSH	0x02
 981	field	FIFORESET	0x01
 982}
 983
 984register DFSTATUS {
 985	address			0x094
 986	access_mode RO
 987	field	PRELOAD_AVAIL	0x80
 988	field	DFCACHETH	0x40
 989	field	FIFOQWDEMP	0x20
 990	field	MREQPEND	0x10
 991	field	HDONE		0x08
 992	field	DFTHRESH	0x04
 993	field	FIFOFULL	0x02
 994	field	FIFOEMP		0x01
 995}
 996
 997register DFWADDR {
 998	address			0x95
 999	access_mode RW
1000	dont_generate_debug_code
1001}
1002
1003register DFRADDR {
1004	address			0x97
1005	access_mode RW
1006}
1007
1008register DFDAT {
1009	address			0x099
1010	access_mode RW
1011	dont_generate_debug_code
1012}
1013
1014/*
1015 * SCB Auto Increment (p. 3-59)
1016 * Byte offset into the SCB Array and an optional bit to allow auto
1017 * incrementing of the address during download and upload operations
1018 */
1019register SCBCNT {
1020	address			0x09a
1021	access_mode RW
1022	count		1
1023	field	SCBAUTO		0x80
1024	mask	SCBCNT_MASK	0x1f
1025	dont_generate_debug_code
1026}
1027
1028/*
1029 * Queue In FIFO (p. 3-60)
1030 * Input queue for queued SCBs (commands that the seqencer has yet to start)
1031 */
1032register QINFIFO {
1033	address			0x09b
1034	access_mode RW
1035	count		12
1036	dont_generate_debug_code
1037}
1038
1039/*
1040 * Queue In Count (p. 3-60)
1041 * Number of queued SCBs
1042 */
1043register QINCNT	{
1044	address			0x09c
1045	access_mode RO
1046}
1047
1048/*
1049 * Queue Out FIFO (p. 3-61)
1050 * Queue of SCBs that have completed and await the host
1051 */
1052register QOUTFIFO {
1053	address			0x09d
1054	access_mode WO
1055	count		7
1056	dont_generate_debug_code
1057}
1058
1059register CRCCONTROL1 {
1060	address			0x09d
1061	access_mode RW
1062	count		3
1063	field	CRCONSEEN		0x80
1064	field	CRCVALCHKEN		0x40
1065	field	CRCENDCHKEN		0x20
1066	field	CRCREQCHKEN		0x10
1067	field	TARGCRCENDEN		0x08
1068	field	TARGCRCCNTEN		0x04
1069	dont_generate_debug_code
1070}
1071
1072
1073/*
1074 * Queue Out Count (p. 3-61)
1075 * Number of queued SCBs in the Out FIFO
1076 */
1077register QOUTCNT {
1078	address			0x09e
1079	access_mode RO
1080}
1081
1082register SCSIPHASE {
1083	address			0x09e
1084	access_mode RO
1085	field	STATUS_PHASE	0x20
1086	field	COMMAND_PHASE	0x10
1087	field	MSG_IN_PHASE	0x08
1088	field	MSG_OUT_PHASE	0x04
1089	field	DATA_IN_PHASE	0x02
1090	field	DATA_OUT_PHASE	0x01
1091	mask	DATA_PHASE_MASK	0x03
1092}
1093
1094/*
1095 * Special Function
1096 */
1097register SFUNCT {
1098	address			0x09f
1099	access_mode RW
1100	count	    4
1101	field	ALT_MODE	0x80
1102	dont_generate_debug_code
1103}
1104
1105/*
1106 * SCB Definition (p. 5-4)
1107 */
1108scb {
1109	address		0x0a0
1110	size		64
1111
1112	SCB_CDB_PTR {
1113		size	4
1114		alias	SCB_RESIDUAL_DATACNT
1115		alias	SCB_CDB_STORE
1116		dont_generate_debug_code
1117	}
1118	SCB_RESIDUAL_SGPTR {
1119		size	4
1120		dont_generate_debug_code
1121	}
1122	SCB_SCSI_STATUS {
1123		size	1
1124		dont_generate_debug_code
1125	}
1126	SCB_TARGET_PHASES {
1127		size	1
1128		dont_generate_debug_code
1129	}
1130	SCB_TARGET_DATA_DIR {
1131		size	1
1132		dont_generate_debug_code
1133	}
1134	SCB_TARGET_ITAG {
1135		size	1
1136		dont_generate_debug_code
1137	}
1138	SCB_DATAPTR {
1139		size	4
1140		dont_generate_debug_code
1141	}
1142	SCB_DATACNT {
1143		/*
1144		 * The last byte is really the high address bits for
1145		 * the data address.
1146		 */
1147		size	4
1148		field	SG_LAST_SEG		0x80	/* In the fourth byte */
1149		mask	SG_HIGH_ADDR_BITS	0x7F	/* In the fourth byte */
1150		dont_generate_debug_code
1151	}
1152	SCB_SGPTR {
1153		size	4
1154		field	SG_RESID_VALID	0x04	/* In the first byte */
1155		field	SG_FULL_RESID	0x02	/* In the first byte */
1156		field	SG_LIST_NULL	0x01	/* In the first byte */
1157		dont_generate_debug_code
1158	}
1159	SCB_CONTROL {
1160		size	1
1161		field	TARGET_SCB			0x80
1162		field	STATUS_RCVD			0x80
1163		field	DISCENB				0x40
1164		field	TAG_ENB				0x20
1165		field	MK_MESSAGE			0x10
1166		field	ULTRAENB			0x08
1167		field	DISCONNECTED			0x04
1168		mask	SCB_TAG_TYPE			0x03
1169	}
1170	SCB_SCSIID {
1171		size	1
1172		field	TWIN_CHNLB			0x80
1173		mask	TWIN_TID			0x70
1174		mask	TID				0xf0
1175		mask	OID				0x0f
1176	}
1177	SCB_LUN {
1178		field	SCB_XFERLEN_ODD			0x80
1179		mask	LID				0x3f
1180		size	1
1181	}
1182	SCB_TAG {
1183		size	1
1184	}
1185	SCB_CDB_LEN {
1186		size	1
1187		dont_generate_debug_code
1188	}
1189	SCB_SCSIRATE {
1190		size	1
1191		dont_generate_debug_code
1192	}
1193	SCB_SCSIOFFSET {
1194		size	1
1195		count	1
1196		dont_generate_debug_code
1197	}
1198	SCB_NEXT {
1199		size	1
1200		dont_generate_debug_code
1201	}
1202	SCB_64_SPARE {
1203		size	16
1204	}
1205	SCB_64_BTT {
1206		size	16
1207		dont_generate_debug_code
1208	}
1209}
1210
1211const	SCB_UPLOAD_SIZE		32
1212const	SCB_DOWNLOAD_SIZE	32
1213const	SCB_DOWNLOAD_SIZE_64	48
1214
1215const	SG_SIZEOF	0x08		/* sizeof(struct ahc_dma) */
1216
1217/* --------------------- AHA-2840-only definitions -------------------- */
1218
1219register SEECTL_2840 {
1220	address			0x0c0
1221	access_mode RW
1222	count		2
1223	field	CS_2840		0x04
1224	field	CK_2840		0x02
1225	field	DO_2840		0x01
1226	dont_generate_debug_code
1227}
1228
1229register STATUS_2840 {
1230	address			0x0c1
1231	access_mode RW
1232	count		4
1233	field	EEPROM_TF	0x80
1234	mask	BIOS_SEL	0x60
1235	mask	ADSEL		0x1e
1236	field	DI_2840		0x01
1237	dont_generate_debug_code
1238}
1239
1240/* --------------------- AIC-7870-only definitions -------------------- */
1241
1242register CCHADDR {
1243	address			0x0E0
1244	size 8
1245	dont_generate_debug_code
1246}
1247
1248register CCHCNT {
1249	address			0x0E8
1250	dont_generate_debug_code
1251}
1252
1253register CCSGRAM {
1254	address			0x0E9
1255	dont_generate_debug_code
1256}
1257
1258register CCSGADDR {
1259	address			0x0EA
1260	dont_generate_debug_code
1261}
1262
1263register CCSGCTL {
1264	address			0x0EB
1265	field	CCSGDONE	0x80
1266	field	CCSGEN		0x08
1267	field	SG_FETCH_NEEDED 0x02	/* Bit used for software state */
1268	field	CCSGRESET	0x01
1269	dont_generate_debug_code
1270}
1271
1272register CCSCBCNT {
1273	address			0xEF
1274	count		1
1275	dont_generate_debug_code
1276}
1277
1278register CCSCBCTL {
1279	address			0x0EE
1280	field	CCSCBDONE	0x80
1281	field	ARRDONE		0x40	/* SCB Array prefetch done */
1282	field	CCARREN		0x10
1283	field	CCSCBEN		0x08
1284	field	CCSCBDIR	0x04
1285	field	CCSCBRESET	0x01
1286	dont_generate_debug_code
1287}
1288
1289register CCSCBADDR {
1290	address			0x0ED
1291	dont_generate_debug_code
1292}
1293
1294register CCSCBRAM {
1295	address			0xEC
1296	dont_generate_debug_code
1297}
1298
1299/*
1300 * SCB bank address (7895/7896/97 only)
1301 */
1302register SCBBADDR {
1303	address			0x0F0
1304	access_mode RW
1305	count		3
1306	dont_generate_debug_code
1307}
1308
1309register CCSCBPTR {
1310	address			0x0F1
1311	dont_generate_debug_code
1312}
1313
1314register HNSCB_QOFF {
1315	address			0x0F4
1316	count		4
1317	dont_generate_debug_code
1318}
1319
1320register SNSCB_QOFF {
1321	address			0x0F6
1322	dont_generate_debug_code
1323}
1324
1325register SDSCB_QOFF {
1326	address			0x0F8
1327	dont_generate_debug_code
1328}
1329
1330register QOFF_CTLSTA {
1331	address			0x0FA
1332	field	SCB_AVAIL	0x40
1333	field	SNSCB_ROLLOVER	0x20
1334	field	SDSCB_ROLLOVER	0x10
1335	mask	SCB_QSIZE	0x07
1336	mask	SCB_QSIZE_256	0x06
1337	dont_generate_debug_code
1338}
1339
1340register DFF_THRSH {
1341	address			0x0FB
1342	mask	WR_DFTHRSH	0x70
1343	mask	RD_DFTHRSH	0x07
1344	mask	RD_DFTHRSH_MIN	0x00
1345	mask	RD_DFTHRSH_25	0x01
1346	mask	RD_DFTHRSH_50	0x02
1347	mask	RD_DFTHRSH_63	0x03
1348	mask	RD_DFTHRSH_75	0x04
1349	mask	RD_DFTHRSH_85	0x05
1350	mask	RD_DFTHRSH_90	0x06
1351	mask	RD_DFTHRSH_MAX	0x07
1352	mask	WR_DFTHRSH_MIN	0x00
1353	mask	WR_DFTHRSH_25	0x10
1354	mask	WR_DFTHRSH_50	0x20
1355	mask	WR_DFTHRSH_63	0x30
1356	mask	WR_DFTHRSH_75	0x40
1357	mask	WR_DFTHRSH_85	0x50
1358	mask	WR_DFTHRSH_90	0x60
1359	mask	WR_DFTHRSH_MAX	0x70
1360	count	4
1361	dont_generate_debug_code
1362}
1363
1364register SG_CACHE_PRE {
1365	access_mode WO
1366	address			0x0fc
1367	mask	SG_ADDR_MASK	0xf8
1368	field	LAST_SEG	0x02
1369	field	LAST_SEG_DONE	0x01
1370	dont_generate_debug_code
1371}
1372
1373register SG_CACHE_SHADOW {
1374	access_mode RO
1375	address			0x0fc
1376	mask	SG_ADDR_MASK	0xf8
1377	field	LAST_SEG	0x02
1378	field	LAST_SEG_DONE	0x01
1379	dont_generate_debug_code
1380}
1381/* ---------------------- Scratch RAM Offsets ------------------------- */
1382/* These offsets are either to values that are initialized by the board's
1383 * BIOS or are specified by the sequencer code.
1384 *
1385 * The host adapter card (at least the BIOS) uses 20-2f for SCSI
1386 * device information, 32-33 and 5a-5f as well. As it turns out, the
1387 * BIOS trashes 20-2f, writing the synchronous negotiation results
1388 * on top of the BIOS values, so we re-use those for our per-target
1389 * scratchspace (actually a value that can be copied directly into
1390 * SCSIRATE).  The kernel driver will enable synchronous negotiation
1391 * for all targets that have a value other than 0 in the lower four
1392 * bits of the target scratch space.  This should work regardless of
1393 * whether the bios has been installed.
1394 */
1395
1396scratch_ram {
1397	address		0x020
1398	size		58
1399
1400	/*
1401	 * 1 byte per target starting at this address for configuration values
1402	 */
1403	BUSY_TARGETS {
1404		alias		TARG_SCSIRATE
1405		size		16
1406		dont_generate_debug_code
1407	}
1408	/*
1409	 * Bit vector of targets that have ULTRA enabled as set by
1410	 * the BIOS.  The Sequencer relies on a per-SCB field to
1411	 * control whether to enable Ultra transfers or not.  During
1412	 * initialization, we read this field and reuse it for 2
1413	 * entries in the busy target table.
1414	 */
1415	ULTRA_ENB {
1416		alias		CMDSIZE_TABLE
1417		size		2
1418		count		2
1419		dont_generate_debug_code
1420	}
1421	/*
1422	 * Bit vector of targets that have disconnection disabled as set by
1423	 * the BIOS.  The Sequencer relies in a per-SCB field to control the
1424	 * disconnect priveldge.  During initialization, we read this field
1425	 * and reuse it for 2 entries in the busy target table.
1426	 */
1427	DISC_DSB {
1428		size		2
1429		count		6
1430		dont_generate_debug_code
1431	}
1432	CMDSIZE_TABLE_TAIL {
1433		size		4
1434	}
1435	/*
1436	 * Partial transfer past cacheline end to be
1437	 * transferred using an extra S/G.
1438	 */
1439	MWI_RESIDUAL {
1440		size		1
1441		dont_generate_debug_code
1442	}
1443	/*
1444	 * SCBID of the next SCB to be started by the controller.
1445	 */
1446	NEXT_QUEUED_SCB {
1447		size		1
1448		dont_generate_debug_code
1449	}
1450	/*
1451	 * Single byte buffer used to designate the type or message
1452	 * to send to a target.
1453	 */
1454	MSG_OUT {
1455		size		1
1456		dont_generate_debug_code
1457	}
1458	/* Parameters for DMA Logic */
1459	DMAPARAMS {
1460		size		1
1461		count		12
1462		field	PRELOADEN	0x80
1463		field	WIDEODD		0x40
1464		field	SCSIEN		0x20
1465		field	SDMAEN		0x10
1466		field	SDMAENACK	0x10
1467		field	HDMAEN		0x08
1468		field	HDMAENACK	0x08
1469		field	DIRECTION	0x04	/* Set indicates PCI->SCSI */
1470		field	FIFOFLUSH	0x02
1471		field	FIFORESET	0x01
1472		dont_generate_debug_code
1473	}
1474	SEQ_FLAGS {
1475		size		1
1476		field	NOT_IDENTIFIED		0x80
1477		field	NO_CDB_SENT		0x40
1478		field	TARGET_CMD_IS_TAGGED	0x40
1479		field	DPHASE			0x20
1480		/* Target flags */
1481		field	TARG_CMD_PENDING	0x10
1482		field	CMDPHASE_PENDING	0x08
1483		field	DPHASE_PENDING		0x04
1484		field	SPHASE_PENDING		0x02
1485		field	NO_DISCONNECT		0x01
1486	}
1487	/*
1488	 * Temporary storage for the
1489	 * target/channel/lun of a
1490	 * reconnecting target
1491	 */
1492	SAVED_SCSIID {
1493		size		1
1494		dont_generate_debug_code
1495	}
1496	SAVED_LUN {
1497		size		1
1498		dont_generate_debug_code
1499	}
1500	/*
1501	 * The last bus phase as seen by the sequencer. 
1502	 */
1503	LASTPHASE {
1504		size		1
1505		field	CDI		0x80
1506		field	IOI		0x40
1507		field	MSGI		0x20
1508		mask	PHASE_MASK	CDI|IOI|MSGI
1509		mask	P_DATAOUT	0x00
1510		mask	P_DATAIN	IOI
1511		mask	P_COMMAND	CDI
1512		mask	P_MESGOUT	CDI|MSGI
1513		mask	P_STATUS	CDI|IOI
1514		mask	P_MESGIN	CDI|IOI|MSGI
1515		mask	P_BUSFREE	0x01
1516	}
1517	/*
1518	 * head of list of SCBs awaiting
1519	 * selection
1520	 */
1521	WAITING_SCBH {
1522		size		1
1523		dont_generate_debug_code
1524	}
1525	/*
1526	 * head of list of SCBs that are
1527	 * disconnected.  Used for SCB
1528	 * paging.
1529	 */
1530	DISCONNECTED_SCBH {
1531		size		1
1532		dont_generate_debug_code
1533	}
1534	/*
1535	 * head of list of SCBs that are
1536	 * not in use.  Used for SCB paging.
1537	 */
1538	FREE_SCBH {
1539		size		1
1540		dont_generate_debug_code
1541	}
1542	/*
1543	 * head of list of SCBs that have
1544	 * completed but have not been
1545	 * put into the qoutfifo.
1546	 */
1547	COMPLETE_SCBH {
1548		size		1
1549	}
1550	/*
1551	 * Address of the hardware scb array in the host.
1552	 */
1553	HSCB_ADDR {
1554		size		4
1555		dont_generate_debug_code
1556	}
1557	/*
1558	 * Base address of our shared data with the kernel driver in host
1559	 * memory.  This includes the qoutfifo and target mode
1560	 * incoming command queue.
1561	 */
1562	SHARED_DATA_ADDR {
1563		size		4
1564		dont_generate_debug_code
1565	}
1566	KERNEL_QINPOS {
1567		size		1
1568		dont_generate_debug_code
1569	}
1570	QINPOS {
1571		size		1
1572		dont_generate_debug_code
1573	}
1574	QOUTPOS {
1575		size		1
1576		dont_generate_debug_code
1577	}
1578	/*
1579	 * Kernel and sequencer offsets into the queue of
1580	 * incoming target mode command descriptors.  The
1581	 * queue is full when the KERNEL_TQINPOS == TQINPOS.
1582	 */
1583	KERNEL_TQINPOS {
1584		size		1
1585		dont_generate_debug_code
1586	}
1587	TQINPOS {
1588		size		1
1589		dont_generate_debug_code
1590	}
1591	ARG_1 {
1592		size		1
1593		count		1
1594		mask	SEND_MSG		0x80
1595		mask	SEND_SENSE		0x40
1596		mask	SEND_REJ		0x20
1597		mask	MSGOUT_PHASEMIS		0x10
1598		mask	EXIT_MSG_LOOP		0x08
1599		mask	CONT_MSG_LOOP		0x04
1600		mask	CONT_TARG_SESSION	0x02
1601		alias	RETURN_1
1602		dont_generate_debug_code
1603	}
1604	ARG_2 {
1605		size		1
1606		alias	RETURN_2
1607		dont_generate_debug_code
1608	}
1609
1610	/*
1611	 * Snapshot of MSG_OUT taken after each message is sent.
1612	 */
1613	LAST_MSG {
1614		size		1
1615		alias	TARG_IMMEDIATE_SCB
1616		dont_generate_debug_code
1617	}
1618
1619	/*
1620	 * Sequences the kernel driver has okayed for us.  This allows
1621	 * the driver to do things like prevent initiator or target
1622	 * operations.
1623	 */
1624	SCSISEQ_TEMPLATE {
1625		size		1
1626		field	ENSELO		0x40
1627		field	ENSELI		0x20
1628		field	ENRSELI		0x10
1629		field	ENAUTOATNO	0x08
1630		field	ENAUTOATNI	0x04
1631		field	ENAUTOATNP	0x02
1632		dont_generate_debug_code
1633	}
1634}
1635
1636scratch_ram {
1637	address		0x056
1638	size		4
1639	/*
1640	 * These scratch ram locations are initialized by the 274X BIOS.
1641	 * We reuse them after capturing the BIOS settings during
1642	 * initialization.
1643	 */
1644
1645	/*
1646	 * The initiator specified tag for this target mode transaction.
1647	 */
1648	HA_274_BIOSGLOBAL {
1649		size	1
1650		field	HA_274_EXTENDED_TRANS	0x01
1651		alias	INITIATOR_TAG
1652		count		1
1653		dont_generate_debug_code
1654	}
1655
1656	SEQ_FLAGS2 {
1657		size	1
1658		field	SCB_DMA			0x01
1659		field	TARGET_MSG_PENDING	0x02
1660		dont_generate_debug_code
1661	}
1662}
1663
1664scratch_ram {
1665	address		0x05a
1666	size		6
1667	/*
1668	 * These are reserved registers in the card's scratch ram on the 2742.
1669	 * The EISA configuration chip is mapped here.  On Rev E. of the
1670	 * aic7770, the sequencer can use this area for scratch, but the
1671	 * host cannot directly access these registers.  On later chips, this
1672	 * area can be read and written by both the host and the sequencer.
1673	 * Even on later chips, many of these locations are initialized by
1674	 * the BIOS.
1675	 */
1676	SCSICONF {
1677		size		1
1678		count		12
1679		field	TERM_ENB	0x80
1680		field	RESET_SCSI	0x40
1681		field	ENSPCHK		0x20
1682		mask	HSCSIID		0x07	/* our SCSI ID */
1683		mask	HWSCSIID	0x0f	/* our SCSI ID if Wide Bus */
1684		dont_generate_debug_code
1685	}
1686	INTDEF {
1687		address		0x05c
1688		size		1
1689		count		1
1690		field	EDGE_TRIG	0x80
1691		mask	VECTOR		0x0f
1692		dont_generate_debug_code
1693	}
1694	HOSTCONF {
1695		address		0x05d
1696		size		1
1697		count		1
1698		dont_generate_debug_code
1699	}
1700	HA_274_BIOSCTRL	{
1701		address		0x05f
1702		size		1
1703		count		1
1704		mask	BIOSMODE		0x30
1705		mask	BIOSDISABLED		0x30	
1706		field	CHANNEL_B_PRIMARY	0x08
1707		dont_generate_debug_code
1708	}
1709}
1710
1711scratch_ram {
1712	address		0x070
1713	size		16
1714
1715	/*
1716	 * Per target SCSI offset values for Ultra2 controllers.
1717	 */
1718	TARG_OFFSET {
1719		size		16
1720		count		1
1721		dont_generate_debug_code
1722	}
1723}
1724
1725const TID_SHIFT		4
1726const SCB_LIST_NULL	0xff
1727const TARGET_CMD_CMPLT	0xfe
1728
1729const CCSGADDR_MAX	0x80
1730const CCSGRAM_MAXSEGS	16
1731
1732/* WDTR Message values */
1733const BUS_8_BIT			0x00
1734const BUS_16_BIT		0x01
1735const BUS_32_BIT		0x02
1736
1737/* Offset maximums */
1738const MAX_OFFSET_8BIT		0x0f
1739const MAX_OFFSET_16BIT		0x08
1740const MAX_OFFSET_ULTRA2		0x7f
1741const MAX_OFFSET		0x7f
1742const HOST_MSG			0xff
1743
1744/* Target mode command processing constants */
1745const CMD_GROUP_CODE_SHIFT	0x05
1746
1747const STATUS_BUSY		0x08
1748const STATUS_QUEUE_FULL	0x28
1749const TARGET_DATA_IN		1
1750
1751/*
1752 * Downloaded (kernel inserted) constants
1753 */
1754/* Offsets into the SCBID array where different data is stored */
1755const QOUTFIFO_OFFSET download
1756const QINFIFO_OFFSET download
1757const CACHESIZE_MASK download
1758const INVERTED_CACHESIZE_MASK download
1759const SG_PREFETCH_CNT download
1760const SG_PREFETCH_ALIGN_MASK download
1761const SG_PREFETCH_ADDR_MASK download