aic79xx.reg

   1/*
   2 * Aic79xx register and scratch ram definitions.
   3 *
   4 * Copyright (c) 1994-2001, 2004 Justin T. Gibbs.
   5 * Copyright (c) 2000-2002 Adaptec Inc.
   6 * All rights reserved.
   7 *
   8 * Redistribution and use in source and binary forms, with or without
   9 * modification, are permitted provided that the following conditions
  10 * are met:
  11 * 1. Redistributions of source code must retain the above copyright
  12 *    notice, this list of conditions, and the following disclaimer,
  13 *    without modification.
  14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  15 *    substantially similar to the "NO WARRANTY" disclaimer below
  16 *    ("Disclaimer") and any redistribution must be conditioned upon
  17 *    including a substantially similar Disclaimer requirement for further
  18 *    binary redistribution.
  19 * 3. Neither the names of the above-listed copyright holders nor the names
  20 *    of any contributors may be used to endorse or promote products derived
  21 *    from this software without specific prior written permission.
  22 *
  23 * Alternatively, this software may be distributed under the terms of the
  24 * GNU General Public License ("GPL") version 2 as published by the Free
  25 * Software Foundation.
  26 *
  27 * NO WARRANTY
  28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  38 * POSSIBILITY OF SUCH DAMAGES.
  39 *
  40 * $FreeBSD$
  41 */
  42VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#77 $"
  43
  44/*
  45 * This file is processed by the aic7xxx_asm utility for use in assembling
  46 * firmware for the aic79xx family of SCSI host adapters as well as to generate
  47 * a C header file for use in the kernel portion of the Aic79xx driver.
  48 */
  49
  50/* Register window Modes */
  51#define M_DFF0		0
  52#define M_DFF1		1
  53#define M_CCHAN		2
  54#define M_SCSI		3
  55#define M_CFG		4
  56#define M_DST_SHIFT	4
  57
  58#define MK_MODE(src, dst) ((src) | ((dst) << M_DST_SHIFT))
  59#define SET_MODE(src, dst)						\
  60	SET_SRC_MODE	src;						\
  61	SET_DST_MODE	dst;						\
  62	if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) {			\
  63		mvi	MK_MODE(src, dst) call set_mode_work_around;	\
  64	} else {							\
  65		mvi	MODE_PTR, MK_MODE(src, dst);			\
  66	}
  67
  68#define RESTORE_MODE(mode)						\
  69	if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) {			\
  70		mov	mode call set_mode_work_around;			\
  71	} else {							\
  72		mov	MODE_PTR, mode;					\
  73	}
  74
  75#define SET_SEQINTCODE(code)						\
  76	if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {			\
  77		mvi	code call set_seqint_work_around;		\
  78	} else {							\
  79		mvi	SEQINTCODE, code;				\
  80	}
  81
  82/*
  83 * Registers marked "dont_generate_debug_code" are not (yet) referenced
  84 * from the driver code, and this keyword inhibit generation
  85 * of debug code for them.
  86 *
  87 * REG_PRETTY_PRINT config will complain if dont_generate_debug_code
  88 * is added to the register which is referenced in the driver.
  89 * Unreferenced register with no dont_generate_debug_code will result
  90 * in dead code. No warning is issued.
  91 */
  92
  93/*
  94 * Mode Pointer
  95 * Controls which of the 5, 512byte, address spaces should be used
  96 * as the source and destination of any register accesses in our
  97 * register window.
  98 */
  99register MODE_PTR {
 100	address			0x000
 101	access_mode	RW
 102	field	DST_MODE	0x70
 103	field	SRC_MODE	0x07
 104	mode_pointer
 105	dont_generate_debug_code
 106}
 107
 108const SRC_MODE_SHIFT	0
 109const DST_MODE_SHIFT	4
 110
 111/*
 112 * Host Interrupt Status
 113 */
 114register INTSTAT {
 115	address			0x001
 116	access_mode	RW
 117	field	HWERRINT	0x80
 118	field	BRKADRINT	0x40
 119	field	SWTMINT		0x20
 120	field	PCIINT		0x10
 121	field	SCSIINT		0x08
 122	field	SEQINT		0x04
 123	field	CMDCMPLT	0x02
 124	field	SPLTINT		0x01
 125	mask	INT_PEND 0xFF
 126}
 127
 128/*
 129 * Sequencer Interrupt Code
 130 */
 131register SEQINTCODE {
 132	address			0x002
 133	access_mode	RW
 134	field {
 135		NO_SEQINT,			/* No seqint pending. */
 136		BAD_PHASE,			/* unknown scsi bus phase */
 137		SEND_REJECT,			/* sending a message reject */
 138		PROTO_VIOLATION, 		/* Protocol Violation */
 139		NO_MATCH,			/* no cmd match for reconnect */
 140		IGN_WIDE_RES,			/* Complex IGN Wide Res Msg */
 141		PDATA_REINIT,			/*
 142						 * Returned to data phase
 143						 * that requires data
 144						 * transfer pointers to be
 145						 * recalculated from the
 146						 * transfer residual.
 147						 */
 148		HOST_MSG_LOOP,			/*
 149						 * The bus is ready for the
 150						 * host to perform another
 151						 * message transaction.  This
 152						 * mechanism is used for things
 153						 * like sync/wide negotiation
 154						 * that require a kernel based
 155						 * message state engine.
 156						 */
 157		BAD_STATUS,			/* Bad status from target */
 158		DATA_OVERRUN,			/*
 159						 * Target attempted to write
 160						 * beyond the bounds of its
 161						 * command.
 162						 */
 163		MKMSG_FAILED,			/*
 164						 * Target completed command
 165						 * without honoring our ATN
 166						 * request to issue a message. 
 167						 */
 168		MISSED_BUSFREE,			/*
 169						 * The sequencer never saw
 170						 * the bus go free after
 171						 * either a command complete
 172						 * or disconnect message.
 173						 */
 174		DUMP_CARD_STATE,
 175		ILLEGAL_PHASE,
 176		INVALID_SEQINT,
 177		CFG4ISTAT_INTR,
 178		STATUS_OVERRUN,
 179		CFG4OVERRUN,
 180		ENTERING_NONPACK,
 181		TASKMGMT_FUNC_COMPLETE,		/*
 182						 * Task management function
 183						 * request completed with
 184						 * an expected busfree.
 185						 */
 186		TASKMGMT_CMD_CMPLT_OKAY,	/*
 187						 * A command with a non-zero
 188						 * task management function
 189						 * has completed via the normal
 190						 * command completion method
 191						 * for commands with a zero
 192						 * task management function.
 193						 * This happens when an attempt
 194						 * to abort a command loses
 195						 * the race for the command to
 196						 * complete normally.
 197						 */
 198		TRACEPOINT0,
 199		TRACEPOINT1,
 200		TRACEPOINT2,
 201		TRACEPOINT3,
 202		SAW_HWERR,
 203		BAD_SCB_STATUS
 204	}
 205	dont_generate_debug_code
 206}
 207
 208/*
 209 * Clear Host Interrupt
 210 */
 211register CLRINT {
 212	address			0x003
 213	access_mode	WO
 214	count		19
 215	field	CLRHWERRINT	0x80 /* Rev B or greater */
 216	field	CLRBRKADRINT	0x40
 217	field	CLRSWTMINT	0x20
 218	field	CLRPCIINT	0x10
 219	field	CLRSCSIINT	0x08
 220	field	CLRSEQINT	0x04
 221	field	CLRCMDINT	0x02
 222	field	CLRSPLTINT	0x01
 223	dont_generate_debug_code
 224}
 225
 226/*
 227 * Error Register
 228 */
 229register ERROR {
 230	address			0x004
 231	access_mode	RO
 232	field	CIOPARERR	0x80
 233	field	CIOACCESFAIL	0x40 /* Rev B or greater */
 234	field	MPARERR		0x20
 235	field	DPARERR		0x10
 236	field	SQPARERR	0x08
 237	field	ILLOPCODE	0x04
 238	field	DSCTMOUT	0x02
 239	dont_generate_debug_code
 240}
 241
 242/*
 243 * Clear Error
 244 */
 245register CLRERR {
 246	address			0x004
 247	access_mode 	WO
 248	field	CLRCIOPARERR	0x80
 249	field	CLRCIOACCESFAIL	0x40 /* Rev B or greater */
 250	field	CLRMPARERR	0x20
 251	field	CLRDPARERR	0x10
 252	field	CLRSQPARERR	0x08
 253	field	CLRILLOPCODE	0x04
 254	field	CLRDSCTMOUT	0x02
 255}
 256
 257/*
 258 * Host Control Register
 259 * Overall host control of the device.
 260 */
 261register HCNTRL {
 262	address			0x005
 263	access_mode	RW
 264	count		12
 265	field	SEQ_RESET	0x80 /* Rev B or greater */
 266	field	POWRDN		0x40
 267	field	SWINT		0x10
 268	field	SWTIMER_START_B	0x08 /* Rev B or greater */
 269	field	PAUSE		0x04
 270	field	INTEN		0x02
 271	field	CHIPRST		0x01
 272	field	CHIPRSTACK	0x01
 273	dont_generate_debug_code
 274}
 275
 276/*
 277 * Host New SCB Queue Offset
 278 */
 279register HNSCB_QOFF {
 280	address			0x006
 281	access_mode	RW
 282	size		2
 283	count		2
 284	dont_generate_debug_code
 285}
 286
 287/*
 288 * Host Empty SCB Queue Offset
 289 */
 290register HESCB_QOFF {
 291	address			0x008
 292	access_mode	RW
 293	count		2
 294	dont_generate_debug_code
 295}
 296
 297/*
 298 * Host Mailbox
 299 */
 300register HS_MAILBOX {
 301	address			0x00B
 302	access_mode	RW
 303	mask	HOST_TQINPOS	0x80	/* Boundary at either 0 or 128 */
 304	mask	ENINT_COALESCE	0x40	/* Perform interrupt coalescing */
 305}
 306
 307/*
 308 * Sequencer Interrupt Status
 309 */
 310register SEQINTSTAT {
 311	address			0x00C
 312	count		1
 313	access_mode	RO
 314	field	SEQ_SWTMRTO	0x10
 315	field	SEQ_SEQINT	0x08
 316	field	SEQ_SCSIINT	0x04
 317	field	SEQ_PCIINT	0x02
 318	field	SEQ_SPLTINT	0x01
 319}
 320
 321/*
 322 * Clear SEQ Interrupt
 323 */
 324register CLRSEQINTSTAT {
 325	address			0x00C
 326	access_mode	WO
 327	field	CLRSEQ_SWTMRTO	0x10
 328	field	CLRSEQ_SEQINT	0x08
 329	field	CLRSEQ_SCSIINT	0x04
 330	field	CLRSEQ_PCIINT	0x02
 331	field	CLRSEQ_SPLTINT	0x01
 332	dont_generate_debug_code
 333}
 334
 335/*
 336 * Software Timer
 337 */
 338register SWTIMER {
 339	address			0x00E
 340	access_mode	RW
 341	size		2
 342	dont_generate_debug_code
 343}
 344
 345/*
 346 * SEQ New SCB Queue Offset
 347 */
 348register SNSCB_QOFF {
 349	address			0x010
 350	access_mode	RW
 351	size		2
 352	modes		M_CCHAN
 353	dont_generate_debug_code
 354}
 355
 356/*
 357 * SEQ Empty SCB Queue Offset
 358 */
 359register SESCB_QOFF {
 360	address			0x012
 361	count		2
 362	access_mode	RW
 363	modes		M_CCHAN
 364	dont_generate_debug_code
 365}
 366
 367/*
 368 * SEQ Done SCB Queue Offset
 369 */
 370register SDSCB_QOFF {
 371	address			0x014
 372	access_mode	RW
 373	modes		M_CCHAN
 374	size		2
 375	dont_generate_debug_code
 376}
 377
 378/*
 379 * Queue Offset Control & Status
 380 */
 381register QOFF_CTLSTA {
 382	address			0x016
 383	access_mode	RW
 384	modes		M_CCHAN
 385	field	EMPTY_SCB_AVAIL	0x80
 386	field	NEW_SCB_AVAIL	0x40
 387	field	SDSCB_ROLLOVR	0x20
 388	field	HS_MAILBOX_ACT	0x10
 389	field	SCB_QSIZE	0x0F {
 390		SCB_QSIZE_4,
 391		SCB_QSIZE_8,
 392		SCB_QSIZE_16,
 393		SCB_QSIZE_32,
 394		SCB_QSIZE_64,
 395		SCB_QSIZE_128,
 396		SCB_QSIZE_256,
 397		SCB_QSIZE_512,
 398		SCB_QSIZE_1024,
 399		SCB_QSIZE_2048,
 400		SCB_QSIZE_4096,
 401		SCB_QSIZE_8192,
 402		SCB_QSIZE_16384
 403	}
 404	dont_generate_debug_code
 405}
 406
 407/*
 408 * Interrupt Control
 409 */
 410register INTCTL {
 411	address			0x018
 412	access_mode	RW
 413	field	SWTMINTMASK	0x80
 414	field	SWTMINTEN	0x40
 415	field	SWTIMER_START	0x20
 416	field	AUTOCLRCMDINT	0x10
 417	field	PCIINTEN	0x08
 418	field	SCSIINTEN	0x04
 419	field	SEQINTEN	0x02
 420	field	SPLTINTEN	0x01
 421}
 422
 423/*
 424 * Data FIFO Control
 425 */
 426register DFCNTRL {
 427	address			0x019
 428	access_mode	RW
 429	modes		M_DFF0, M_DFF1
 430	count		11
 431	field	PRELOADEN	0x80
 432	field	SCSIENWRDIS	0x40	/* Rev B only. */
 433	field	SCSIEN		0x20
 434	field	SCSIENACK	0x20
 435	field	HDMAEN		0x08
 436	field	HDMAENACK	0x08
 437	field	DIRECTION	0x04
 438	field	DIRECTIONACK	0x04
 439	field	FIFOFLUSH	0x02
 440	field	FIFOFLUSHACK	0x02
 441	field	DIRECTIONEN	0x01
 442}
 443
 444/*
 445 * Device Space Command 0
 446 */
 447register DSCOMMAND0 {
 448	address			0x019
 449	count		1
 450	access_mode	RW
 451	modes		M_CFG
 452	field	CACHETHEN	0x80	/* Cache Threshold enable */
 453	field	DPARCKEN	0x40	/* Data Parity Check Enable */
 454	field	MPARCKEN	0x20	/* Memory Parity Check Enable */
 455	field	EXTREQLCK	0x10	/* External Request Lock */
 456	field	DISABLE_TWATE	0x02	/* Rev B or greater */
 457	field	CIOPARCKEN	0x01	/* Internal bus parity error enable */
 458	dont_generate_debug_code
 459}
 460
 461/*
 462 * Data FIFO Status
 463 */
 464register DFSTATUS {
 465	address			0x01A
 466	access_mode	RO
 467	modes		M_DFF0, M_DFF1
 468	field	PRELOAD_AVAIL		0x80
 469	field	PKT_PRELOAD_AVAIL	0x40
 470	field	MREQPEND		0x10
 471	field	HDONE			0x08
 472	field	DFTHRESH		0x04
 473	field	FIFOFULL		0x02
 474	field	FIFOEMP			0x01
 475}
 476
 477/*
 478 * S/G Cache Pointer
 479 */
 480register SG_CACHE_PRE {
 481	address			0x01B
 482	access_mode	WO
 483	modes		M_DFF0, M_DFF1
 484	field	SG_ADDR_MASK	0xf8
 485	field	ODD_SEG		0x04
 486	field	LAST_SEG	0x02
 487	dont_generate_debug_code
 488}
 489
 490register SG_CACHE_SHADOW {
 491	address			0x01B
 492	access_mode	RO
 493	modes		M_DFF0, M_DFF1
 494	field	SG_ADDR_MASK	0xf8
 495	field	ODD_SEG		0x04
 496	field	LAST_SEG	0x02
 497	field	LAST_SEG_DONE	0x01
 498}
 499
 500/*
 501 * Arbiter Control
 502 */
 503register ARBCTL {
 504	address			0x01B
 505	access_mode	RW
 506	modes		M_CFG
 507	field	RESET_HARB	0x80
 508	field	RETRY_SWEN	0x08
 509	field	USE_TIME	0x07
 510}
 511
 512/*
 513 * Data Channel Host Address
 514 */
 515register HADDR {
 516	address			0x070
 517	access_mode	RW
 518	size		8
 519	modes		M_DFF0, M_DFF1
 520	dont_generate_debug_code
 521}
 522
 523/*
 524 * Host Overlay DMA Address
 525 */
 526register HODMAADR {
 527	address			0x070
 528	access_mode	RW
 529	size		8
 530	modes		M_SCSI
 531}
 532
 533/*
 534 * PCI PLL Delay.
 535 */
 536register PLLDELAY {
 537	address			0x070
 538	access_mode	RW
 539	size		1
 540	modes		M_CFG
 541	field	SPLIT_DROP_REQ	0x80
 542}
 543
 544/*
 545 * Data Channel Host Count
 546 */
 547register HCNT {
 548	address			0x078
 549	access_mode	RW
 550	size		3
 551	modes		M_DFF0, M_DFF1
 552	dont_generate_debug_code
 553}
 554
 555/*
 556 * Host Overlay DMA Count
 557 */
 558register HODMACNT {
 559	address			0x078
 560	access_mode	RW
 561	size		2
 562	modes		M_SCSI
 563}
 564
 565/*
 566 * Host Overlay DMA Enable
 567 */
 568register HODMAEN {
 569	address			0x07A
 570	access_mode	RW
 571	modes		M_SCSI
 572}
 573
 574/*
 575 * Scatter/Gather Host Address
 576 */
 577register SGHADDR {
 578	address			0x07C
 579	access_mode	RW
 580	size		8
 581	modes		M_DFF0, M_DFF1
 582	dont_generate_debug_code
 583}
 584
 585/*
 586 * SCB Host Address
 587 */
 588register SCBHADDR {
 589	address			0x07C
 590	access_mode	RW
 591	size		8
 592	modes		M_CCHAN
 593	dont_generate_debug_code
 594}
 595
 596/*
 597 * Scatter/Gather Host Count
 598 */
 599register SGHCNT {
 600	address			0x084
 601	access_mode	RW
 602	modes		M_DFF0, M_DFF1
 603	dont_generate_debug_code
 604}
 605
 606/*
 607 * SCB Host Count
 608 */
 609register SCBHCNT {
 610	address			0x084
 611	access_mode	RW
 612	modes		M_CCHAN
 613	dont_generate_debug_code
 614}
 615
 616/*
 617 * Data FIFO Threshold
 618 */
 619register DFF_THRSH {
 620	address			0x088
 621	access_mode	RW
 622	modes		M_CFG
 623	count		1
 624	field	WR_DFTHRSH	0x70 {
 625		WR_DFTHRSH_MIN,
 626		WR_DFTHRSH_25,
 627		WR_DFTHRSH_50,
 628		WR_DFTHRSH_63,
 629		WR_DFTHRSH_75,
 630		WR_DFTHRSH_85,
 631		WR_DFTHRSH_90,
 632		WR_DFTHRSH_MAX
 633	}
 634	field	RD_DFTHRSH	0x07 {
 635		RD_DFTHRSH_MIN,
 636		RD_DFTHRSH_25,
 637		RD_DFTHRSH_50,
 638		RD_DFTHRSH_63,
 639		RD_DFTHRSH_75,
 640		RD_DFTHRSH_85,
 641		RD_DFTHRSH_90,
 642		RD_DFTHRSH_MAX
 643	}
 644	dont_generate_debug_code
 645}
 646
 647/*
 648 * ROM Address
 649 */
 650register ROMADDR {
 651	address			0x08A
 652	access_mode	RW
 653	size		3
 654}
 655
 656/*
 657 * ROM Control
 658 */
 659register ROMCNTRL {
 660	address			0x08D
 661	access_mode	RW
 662	field	ROMOP		0xE0
 663	field	ROMSPD		0x18
 664	field	REPEAT		0x02
 665	field	RDY		0x01
 666}
 667
 668/*
 669 * ROM Data
 670 */
 671register ROMDATA {
 672	address			0x08E
 673	access_mode	RW
 674}
 675
 676/*
 677 * Data Channel Receive Message 0
 678 */
 679register DCHRXMSG0 {
 680	address			0x090
 681	access_mode	RO
 682	modes		M_DFF0, M_DFF1
 683	field		CDNUM	0xF8
 684	field		CFNUM	0x07
 685}
 686
 687/*
 688 * CMC Receive Message 0
 689 */
 690register CMCRXMSG0 {
 691	address			0x090
 692	access_mode	RO
 693	modes		M_CCHAN
 694	field		CDNUM	0xF8
 695	field		CFNUM	0x07
 696}
 697
 698/*
 699 * Overlay Receive Message 0
 700 */
 701register OVLYRXMSG0 {
 702	address			0x090
 703	access_mode	RO
 704	modes		M_SCSI
 705	field		CDNUM	0xF8
 706	field		CFNUM	0x07
 707}
 708
 709/*
 710 * Relaxed Order Enable
 711 */
 712register ROENABLE {
 713	address			0x090
 714	access_mode	RW
 715	modes		M_CFG
 716	field	MSIROEN		0x20
 717	field	OVLYROEN	0x10
 718	field	CMCROEN		0x08
 719	field	SGROEN		0x04
 720	field	DCH1ROEN	0x02
 721	field	DCH0ROEN	0x01
 722}
 723
 724/*
 725 * Data Channel Receive Message 1
 726 */
 727register DCHRXMSG1 {
 728	address			0x091
 729	access_mode	RO
 730	modes		M_DFF0, M_DFF1
 731	field	CBNUM		0xFF
 732}
 733
 734/*
 735 * CMC Receive Message 1
 736 */
 737register CMCRXMSG1 {
 738	address			0x091
 739	access_mode	RO
 740	modes		M_CCHAN
 741	field	CBNUM		0xFF
 742}
 743
 744/*
 745 * Overlay Receive Message 1
 746 */
 747register OVLYRXMSG1 {
 748	address			0x091
 749	access_mode	RO
 750	modes		M_SCSI
 751	field	CBNUM		0xFF
 752}
 753
 754/*
 755 * No Snoop Enable
 756 */
 757register NSENABLE {
 758	address			0x091
 759	access_mode	RW
 760	modes		M_CFG
 761	field	MSINSEN		0x20
 762	field	OVLYNSEN	0x10
 763	field	CMCNSEN		0x08
 764	field	SGNSEN		0x04
 765	field	DCH1NSEN	0x02
 766	field	DCH0NSEN	0x01
 767}
 768
 769/*
 770 * Data Channel Receive Message 2
 771 */
 772register DCHRXMSG2 {
 773	address			0x092
 774	access_mode	RO
 775	modes		M_DFF0, M_DFF1
 776	field	MINDEX		0xFF
 777}
 778
 779/*
 780 * CMC Receive Message 2
 781 */
 782register CMCRXMSG2 {
 783	address			0x092
 784	access_mode	RO
 785	modes		M_CCHAN
 786	field	MINDEX		0xFF
 787}
 788
 789/*
 790 * Overlay Receive Message 2
 791 */
 792register OVLYRXMSG2 {
 793	address			0x092
 794	access_mode	RO
 795	modes		M_SCSI
 796	field	MINDEX		0xFF
 797}
 798
 799/*
 800 * Outstanding Split Transactions
 801 */
 802register OST {
 803	address			0x092
 804	access_mode	RW
 805	modes		M_CFG
 806}
 807
 808/*
 809 * Data Channel Receive Message 3
 810 */
 811register DCHRXMSG3 {
 812	address			0x093
 813	access_mode	RO
 814	modes		M_DFF0, M_DFF1
 815	field	MCLASS		0x0F
 816}
 817
 818/*
 819 * CMC Receive Message 3
 820 */
 821register CMCRXMSG3 {
 822	address			0x093
 823	access_mode	RO
 824	modes		M_CCHAN
 825	field	MCLASS		0x0F
 826}
 827
 828/*
 829 * Overlay Receive Message 3
 830 */
 831register OVLYRXMSG3 {
 832	address			0x093
 833	access_mode	RO
 834	modes		M_SCSI
 835	field	MCLASS		0x0F
 836}
 837
 838/*
 839 * PCI-X Control
 840 */
 841register PCIXCTL {
 842	address			0x093
 843	access_mode	RW
 844	modes		M_CFG
 845	count		1
 846	field	SERRPULSE	0x80
 847	field	UNEXPSCIEN	0x20
 848	field	SPLTSMADIS	0x10
 849	field	SPLTSTADIS	0x08
 850	field	SRSPDPEEN	0x04
 851	field	TSCSERREN	0x02
 852	field	CMPABCDIS	0x01
 853	dont_generate_debug_code
 854}
 855
 856/*
 857 * CMC Sequencer Byte Count
 858 */
 859register CMCSEQBCNT {
 860	address			0x094
 861	access_mode	RO
 862	modes		M_CCHAN
 863}
 864
 865/*
 866 * Overlay Sequencer Byte Count
 867 */
 868register OVLYSEQBCNT {
 869	address			0x094
 870	access_mode	RO
 871	modes		M_SCSI
 872}
 873
 874/*
 875 * Data Channel Sequencer Byte Count
 876 */
 877register DCHSEQBCNT {
 878	address			0x094
 879	access_mode	RO
 880	size		2
 881	modes		M_DFF0, M_DFF1
 882}
 883
 884/*
 885 * Data Channel Split Status 0
 886 */
 887register DCHSPLTSTAT0 {
 888	address			0x096
 889	access_mode	RW
 890	modes		M_DFF0, M_DFF1
 891	count		2
 892	field	STAETERM	0x80
 893	field	SCBCERR		0x40
 894	field	SCADERR		0x20
 895	field	SCDATBUCKET	0x10
 896	field	CNTNOTCMPLT	0x08
 897	field	RXOVRUN		0x04
 898	field	RXSCEMSG	0x02
 899	field	RXSPLTRSP	0x01
 900	dont_generate_debug_code
 901}
 902
 903/*
 904 * CMC Split Status 0
 905 */
 906register CMCSPLTSTAT0 {
 907	address			0x096
 908	access_mode	RW
 909	modes		M_CCHAN
 910	field	STAETERM	0x80
 911	field	SCBCERR		0x40
 912	field	SCADERR		0x20
 913	field	SCDATBUCKET	0x10
 914	field	CNTNOTCMPLT	0x08
 915	field	RXOVRUN		0x04
 916	field	RXSCEMSG	0x02
 917	field	RXSPLTRSP	0x01
 918}
 919
 920/*
 921 * Overlay Split Status 0
 922 */
 923register OVLYSPLTSTAT0 {
 924	address			0x096
 925	access_mode	RW
 926	modes		M_SCSI
 927	field	STAETERM	0x80
 928	field	SCBCERR		0x40
 929	field	SCADERR		0x20
 930	field	SCDATBUCKET	0x10
 931	field	CNTNOTCMPLT	0x08
 932	field	RXOVRUN		0x04
 933	field	RXSCEMSG	0x02
 934	field	RXSPLTRSP	0x01
 935}
 936
 937/*
 938 * Data Channel Split Status 1
 939 */
 940register DCHSPLTSTAT1 {
 941	address			0x097
 942	access_mode	RW
 943	modes		M_DFF0, M_DFF1
 944	count		2
 945	field	RXDATABUCKET	0x01
 946	dont_generate_debug_code
 947}
 948
 949/*
 950 * CMC Split Status 1
 951 */
 952register CMCSPLTSTAT1 {
 953	address			0x097
 954	access_mode	RW
 955	modes		M_CCHAN
 956	field	RXDATABUCKET	0x01
 957}
 958
 959/*
 960 * Overlay Split Status 1
 961 */
 962register OVLYSPLTSTAT1 {
 963	address			0x097
 964	access_mode	RW
 965	modes		M_SCSI
 966	field	RXDATABUCKET	0x01
 967}
 968
 969/*
 970 * S/G Receive Message 0
 971 */
 972register SGRXMSG0 {
 973	address			0x098
 974	access_mode	RO
 975	modes		M_DFF0, M_DFF1
 976	field		CDNUM	0xF8
 977	field		CFNUM	0x07
 978}
 979
 980/*
 981 * S/G Receive Message 1
 982 */
 983register SGRXMSG1 {
 984	address			0x099
 985	access_mode	RO
 986	modes		M_DFF0, M_DFF1
 987	field	CBNUM		0xFF
 988}
 989
 990/*
 991 * S/G Receive Message 2
 992 */
 993register SGRXMSG2 {
 994	address			0x09A
 995	access_mode	RO
 996	modes		M_DFF0, M_DFF1
 997	field	MINDEX		0xFF
 998}
 999
1000/*
1001 * S/G Receive Message 3
1002 */
1003register SGRXMSG3 {
1004	address			0x09B
1005	access_mode	RO
1006	modes		M_DFF0, M_DFF1
1007	field	MCLASS		0x0F
1008}
1009
1010/*
1011 * Slave Split Out Address 0
1012 */
1013register SLVSPLTOUTADR0 {
1014	address			0x098
1015	access_mode	RO
1016	modes		M_SCSI
1017	field	LOWER_ADDR	0x7F
1018}
1019
1020/*
1021 * Slave Split Out Address 1
1022 */
1023register SLVSPLTOUTADR1 {
1024	address			0x099
1025	access_mode	RO
1026	modes		M_SCSI
1027	field	REQ_DNUM	0xF8
1028	field	REQ_FNUM	0x07
1029}
1030
1031/*
1032 * Slave Split Out Address 2
1033 */
1034register SLVSPLTOUTADR2 {
1035	address			0x09A
1036	access_mode	RO
1037	modes		M_SCSI
1038	field	REQ_BNUM	0xFF
1039}
1040
1041/*
1042 * Slave Split Out Address 3
1043 */
1044register SLVSPLTOUTADR3 {
1045	address			0x09B
1046	access_mode	RO
1047	modes		M_SCSI
1048	field	RLXORD		020
1049	field	TAG_NUM		0x1F
1050}
1051
1052/*
1053 * SG Sequencer Byte Count
1054 */
1055register SGSEQBCNT {
1056	address			0x09C
1057	access_mode	RO
1058	modes		M_DFF0, M_DFF1
1059}
1060
1061/*
1062 * Slave Split Out Attribute 0
1063 */
1064register SLVSPLTOUTATTR0 {
1065	address			0x09C
1066	access_mode	RO
1067	modes		M_SCSI
1068	field	LOWER_BCNT	0xFF
1069}
1070
1071/*
1072 * Slave Split Out Attribute 1
1073 */
1074register SLVSPLTOUTATTR1 {
1075	address			0x09D
1076	access_mode	RO
1077	modes		M_SCSI
1078	field	CMPLT_DNUM	0xF8
1079	field	CMPLT_FNUM	0x07
1080}
1081
1082/*
1083 * Slave Split Out Attribute 2
1084 */
1085register SLVSPLTOUTATTR2 {
1086	address			0x09E
1087	access_mode	RO
1088	size		2
1089	modes		M_SCSI
1090	field	CMPLT_BNUM	0xFF
1091}
1092/*
1093 * S/G Split Status 0
1094 */
1095register SGSPLTSTAT0 {
1096	address			0x09E
1097	access_mode	RW
1098	modes		M_DFF0, M_DFF1
1099	count		2
1100	field	STAETERM	0x80
1101	field	SCBCERR		0x40
1102	field	SCADERR		0x20
1103	field	SCDATBUCKET	0x10
1104	field	CNTNOTCMPLT	0x08
1105	field	RXOVRUN		0x04
1106	field	RXSCEMSG	0x02
1107	field	RXSPLTRSP	0x01
1108	dont_generate_debug_code
1109}
1110
1111/*
1112 * S/G Split Status 1
1113 */
1114register SGSPLTSTAT1 {
1115	address			0x09F
1116	access_mode	RW
1117	modes		M_DFF0, M_DFF1
1118	count		2
1119	field	RXDATABUCKET	0x01
1120	dont_generate_debug_code
1121}
1122
1123/*
1124 * Special Function
1125 */
1126register SFUNCT {
1127	address			0x09f
1128	access_mode	RW
1129	modes		M_CFG
1130	field	TEST_GROUP	0xF0
1131	field	TEST_NUM	0x0F
1132	dont_generate_debug_code
1133}
1134
1135/*
1136 * Data FIFO 0 PCI Status 
1137 */
1138register DF0PCISTAT {
1139	address			0x0A0
1140	access_mode	RW
1141	modes		M_CFG
1142	count		1
1143	field	DPE		0x80
1144	field	SSE		0x40
1145	field	RMA		0x20
1146	field	RTA		0x10
1147	field	SCAAPERR	0x08
1148	field	RDPERR		0x04
1149	field	TWATERR		0x02
1150	field	DPR		0x01
1151	dont_generate_debug_code
1152}
1153
1154/*
1155 * Data FIFO 1 PCI Status 
1156 */
1157register DF1PCISTAT {
1158	address			0x0A1
1159	access_mode	RW
1160	modes		M_CFG
1161	field	DPE		0x80
1162	field	SSE		0x40
1163	field	RMA		0x20
1164	field	RTA		0x10
1165	field	SCAAPERR	0x08
1166	field	RDPERR		0x04
1167	field	TWATERR		0x02
1168	field	DPR		0x01
1169}
1170
1171/*
1172 * S/G PCI Status 
1173 */
1174register SGPCISTAT {
1175	address			0x0A2
1176	access_mode	RW
1177	modes		M_CFG
1178	field	DPE		0x80
1179	field	SSE		0x40
1180	field	RMA		0x20
1181	field	RTA		0x10
1182	field	SCAAPERR	0x08
1183	field	RDPERR		0x04
1184	field	DPR		0x01
1185}
1186
1187/*
1188 * CMC PCI Status 
1189 */
1190register CMCPCISTAT {
1191	address			0x0A3
1192	access_mode	RW
1193	modes		M_CFG
1194	field	DPE		0x80
1195	field	SSE		0x40
1196	field	RMA		0x20
1197	field	RTA		0x10
1198	field	SCAAPERR	0x08
1199	field	RDPERR		0x04
1200	field	TWATERR		0x02
1201	field	DPR		0x01
1202}
1203
1204/*
1205 * Overlay PCI Status 
1206 */
1207register OVLYPCISTAT {
1208	address			0x0A4
1209	access_mode	RW
1210	modes		M_CFG
1211	field	DPE		0x80
1212	field	SSE		0x40
1213	field	RMA		0x20
1214	field	RTA		0x10
1215	field	SCAAPERR	0x08
1216	field	RDPERR		0x04
1217	field	DPR		0x01
1218}
1219
1220/*
1221 * PCI Status for MSI Master DMA Transfer
1222 */
1223register MSIPCISTAT {
1224	address			0x0A6
1225	access_mode	RW
1226	modes		M_CFG
1227	field	SSE		0x40
1228	field	RMA		0x20
1229	field	RTA		0x10
1230	field	CLRPENDMSI	0x08
1231	field	TWATERR		0x02
1232	field	DPR		0x01
1233}
1234
1235/*
1236 * PCI Status for Target
1237 */
1238register TARGPCISTAT {
1239	address			0x0A7
1240	access_mode	RW
1241	modes		M_CFG
1242	count		5
1243	field	DPE		0x80
1244	field	SSE		0x40
1245	field	STA		0x08
1246	field	TWATERR		0x02
1247	dont_generate_debug_code
1248}
1249
1250/*
1251 * LQ Packet In
1252 * The last LQ Packet received
1253 */
1254register LQIN {
1255	address			0x020
1256	access_mode	RW
1257	size		20
1258	count		2
1259	modes		M_DFF0, M_DFF1, M_SCSI
1260	dont_generate_debug_code
1261}
1262
1263/*
1264 * SCB Type Pointer
1265 * SCB offset for Target Mode SCB type information
1266 */
1267register TYPEPTR {
1268	address			0x020
1269	access_mode	RW
1270	modes		M_CFG
1271}
1272
1273/*
1274 * Queue Tag Pointer
1275 * SCB offset to the Two Byte tag identifier used for target mode.
1276 */
1277register TAGPTR {
1278	address			0x021
1279	access_mode	RW
1280	modes		M_CFG
1281}
1282
1283/*
1284 * Logical Unit Number Pointer
1285 * SCB offset to the LSB (little endian) of the lun field.
1286 */
1287register LUNPTR {
1288	address			0x022
1289	access_mode	RW
1290	modes		M_CFG
1291	count		2
1292	dont_generate_debug_code
1293}
1294
1295/*
1296 * Data Length Pointer
1297 * SCB offset for the 4 byte data length field in target mode.
1298 */
1299register DATALENPTR {
1300	address			0x023
1301	access_mode	RW
1302	modes		M_CFG
1303}
1304
1305/*
1306 * Status Length Pointer
1307 * SCB offset to the two byte status field in target SCBs.
1308 */
1309register STATLENPTR {
1310	address			0x024
1311	access_mode	RW
1312	modes		M_CFG
1313}
1314
1315/*
1316 * Command Length Pointer
1317 * Scb offset for the CDB length field in initiator SCBs.
1318 */
1319register CMDLENPTR {
1320	address			0x025
1321	access_mode	RW
1322	modes		M_CFG
1323	count		1
1324	dont_generate_debug_code
1325}
1326
1327/*
1328 * Task Attribute Pointer
1329 * Scb offset for the byte field specifying the attribute byte
1330 * to be used in command packets.
1331 */ 
1332register ATTRPTR {
1333	address			0x026
1334	access_mode	RW
1335	modes		M_CFG
1336	count		1
1337	dont_generate_debug_code
1338}
1339
1340/*
1341 * Task Management Flags Pointer
1342 * Scb offset for the byte field specifying the attribute flags
1343 * byte to be used in command packets.
1344 */ 
1345register FLAGPTR {
1346	address			0x027
1347	access_mode	RW
1348	modes		M_CFG
1349	count		1
1350	dont_generate_debug_code
1351}
1352
1353/*
1354 * Command Pointer
1355 * Scb offset for the first byte in the CDB for initiator SCBs.
1356 */
1357register CMDPTR {
1358	address			0x028
1359	access_mode	RW
1360	modes		M_CFG
1361	count		1
1362	dont_generate_debug_code
1363}
1364
1365/*
1366 * Queue Next Pointer
1367 * Scb offset for the 2 byte "next scb link".
1368 */
1369register QNEXTPTR {
1370	address			0x029
1371	access_mode	RW
1372	modes		M_CFG
1373	count		1
1374	dont_generate_debug_code
1375}
1376
1377/*
1378 * SCSI ID Pointer
1379 * Scb offset to the value to place in the SCSIID register
1380 * during target mode connections.
1381 */
1382register IDPTR {
1383	address			0x02A
1384	access_mode	RW
1385	modes		M_CFG
1386}
1387
1388/*
1389 * Command Aborted Byte Pointer
1390 * Offset to the SCB flags field that includes the
1391 * "SCB aborted" status bit.
1392 */
1393register ABRTBYTEPTR {
1394	address			0x02B
1395	access_mode	RW
1396	modes		M_CFG
1397	count		1
1398	dont_generate_debug_code
1399}
1400
1401/*
1402 * Command Aborted Bit Pointer
1403 * Bit offset in the SCB flags field for "SCB aborted" status.
1404 */
1405register ABRTBITPTR {
1406	address			0x02C
1407	access_mode	RW
1408	modes		M_CFG
1409	count		1
1410	dont_generate_debug_code
1411}
1412
1413/*
1414 * Rev B or greater.
1415 */
1416register MAXCMDBYTES {
1417	address			0x02D
1418	access_mode	RW
1419	modes		M_CFG
1420}
1421
1422/*
1423 * Rev B or greater.
1424 */
1425register MAXCMD2RCV {
1426	address			0x02E
1427	access_mode	RW
1428	modes		M_CFG
1429}
1430
1431/*
1432 * Rev B or greater.
1433 */
1434register SHORTTHRESH {
1435	address			0x02F
1436	access_mode	RW
1437	modes		M_CFG
1438}
1439
1440/*
1441 * Logical Unit Number Length
1442 * The length, in bytes, of the SCB lun field.
1443 */
1444register LUNLEN {
1445	address			0x030
1446	access_mode	RW
1447	modes		M_CFG
1448	count		2
1449	mask		ILUNLEN	0x0F
1450	mask		TLUNLEN	0xF0
1451	dont_generate_debug_code
1452}
1453const LUNLEN_SINGLE_LEVEL_LUN 0xF
1454
1455/*
1456 * CDB Limit
1457 * The size, in bytes, of the embedded CDB field in initator SCBs.
1458 */
1459register CDBLIMIT {
1460	address			0x031
1461	access_mode	RW
1462	modes		M_CFG
1463	count		1
1464	dont_generate_debug_code
1465}
1466
1467/*
1468 * Maximum Commands
1469 * The maximum number of commands to issue during a
1470 * single packetized connection.
1471 */
1472register MAXCMD {
1473	address			0x032
1474	access_mode	RW
1475	modes		M_CFG
1476	count		9
1477	dont_generate_debug_code
1478}
1479
1480/*
1481 * Maximum Command Counter
1482 * The number of commands already sent during this connection
1483 */
1484register MAXCMDCNT {
1485	address			0x033
1486	access_mode	RW
1487	modes		M_CFG
1488	dont_generate_debug_code
1489}
1490
1491/*
1492 * LQ Packet Reserved Bytes
1493 * The bytes to be sent in the currently reserved fileds
1494 * of all LQ packets.
1495 */
1496register LQRSVD01 {
1497	address			0x034
1498	access_mode	RW
1499	modes		M_SCSI
1500}
1501register LQRSVD16 {
1502	address			0x035
1503	access_mode	RW
1504	modes		M_SCSI
1505}
1506register LQRSVD17 {
1507	address			0x036
1508	access_mode	RW
1509	modes		M_SCSI
1510}
1511
1512/*
1513 * Command Reserved 0
1514 * The byte to be sent for the reserved byte 0 of
1515 * outgoing command packets.
1516 */
1517register CMDRSVD0 {
1518	address			0x037
1519	access_mode	RW
1520	modes		M_CFG
1521}
1522
1523/*
1524 * LQ Manager Control 0
1525 */
1526register LQCTL0 {
1527	address			0x038
1528	access_mode	RW
1529	modes		M_CFG
1530	field	LQITARGCLT	0xC0
1531	field	LQIINITGCLT	0x30
1532	field	LQ0TARGCLT	0x0C
1533	field	LQ0INITGCLT	0x03
1534}
1535
1536/*
1537 * LQ Manager Control 1
1538 */
1539register LQCTL1 {
1540	address			0x038
1541	access_mode	RW
1542	modes		M_DFF0, M_DFF1, M_SCSI
1543	count		2
1544	field	PCI2PCI		0x04
1545	field	SINGLECMD	0x02
1546	field	ABORTPENDING	0x01
1547	dont_generate_debug_code
1548}
1549
1550/*
1551 * LQ Manager Control 2
1552 */
1553register LQCTL2 {
1554	address			0x039
1555	access_mode	RW
1556	modes		M_DFF0, M_DFF1, M_SCSI
1557	count		5
1558	field	LQIRETRY	0x80
1559	field	LQICONTINUE	0x40
1560	field	LQITOIDLE	0x20
1561	field	LQIPAUSE	0x10
1562	field	LQORETRY	0x08
1563	field	LQOCONTINUE	0x04
1564	field	LQOTOIDLE	0x02
1565	field	LQOPAUSE	0x01
1566	dont_generate_debug_code
1567}
1568
1569/*
1570 * SCSI RAM BIST0
1571 */
1572register SCSBIST0 {
1573	address			0x039
1574	access_mode	RW
1575	modes		M_CFG
1576	field	GSBISTERR	0x40
1577	field	GSBISTDONE	0x20
1578	field	GSBISTRUN	0x10
1579	field	OSBISTERR	0x04
1580	field	OSBISTDONE	0x02
1581	field	OSBISTRUN	0x01
1582}
1583
1584/*
1585 * SCSI Sequence Control0
1586 */
1587register SCSISEQ0 {
1588	address			0x03A
1589	access_mode	RW
1590	modes		M_DFF0, M_DFF1, M_SCSI
1591	field	TEMODEO		0x80
1592	field	ENSELO		0x40
1593	field	ENARBO		0x20
1594	field	FORCEBUSFREE	0x10
1595	field	SCSIRSTO	0x01
1596}
1597
1598/*
1599 * SCSI RAM BIST 1
1600 */
1601register SCSBIST1 {
1602	address			0x03A
1603	access_mode	RW
1604	modes		M_CFG
1605	field	NTBISTERR	0x04
1606	field	NTBISTDONE	0x02
1607	field	NTBISTRUN	0x01
1608}
1609
1610/*
1611 * SCSI Sequence Control 1
1612 */
1613register SCSISEQ1 {
1614	address			0x03B
1615	access_mode	RW
1616	modes		M_DFF0, M_DFF1, M_SCSI
1617	count		8
1618	field	MANUALCTL	0x40
1619	field	ENSELI		0x20
1620	field	ENRSELI		0x10
1621	field	MANUALP		0x0C
1622	field	ENAUTOATNP	0x02
1623	field	ALTSTIM		0x01
1624}
1625
1626/*
1627 * SCSI Transfer Control 0
1628 */
1629register SXFRCTL0 {
1630	address			0x03C
1631	access_mode	RW
1632	modes		M_SCSI
1633	field	DFON		0x80
1634	field	DFPEXP		0x40
1635	field	BIOSCANCELEN	0x10
1636	field	SPIOEN		0x08
1637	dont_generate_debug_code
1638}
1639
1640/*
1641 * SCSI Transfer Control 1
1642 */
1643register SXFRCTL1 {
1644	address			0x03D
1645	access_mode	RW
1646	modes		M_SCSI
1647	field	BITBUCKET	0x80
1648	field	ENSACHK		0x40
1649	field	ENSPCHK		0x20
1650	field	STIMESEL	0x18
1651	field	ENSTIMER	0x04
1652	field	ACTNEGEN	0x02
1653	field	STPWEN		0x01
1654	dont_generate_debug_code
1655}
1656
1657/*
1658 * SCSI Transfer Control 2
1659 */
1660register SXFRCTL2 {
1661	address			0x03E
1662	access_mode	RW
1663	modes		M_SCSI
1664	field	AUTORSTDIS	0x10
1665	field	CMDDMAEN	0x08
1666	field	ASU		0x07
1667}
1668
1669/*
1670 * SCSI Bus Initiator IDs
1671 * Bitmask of observed initiators on the bus.
1672 */
1673register BUSINITID {
1674	address			0x03C
1675	access_mode	RW
1676	modes		M_CFG
1677	size		2
1678}
1679
1680/*
1681 * Data Length Counters
1682 * Packet byte counter.
1683 */
1684register DLCOUNT {
1685	address			0x03C
1686	access_mode	RW
1687	modes		M_DFF0, M_DFF1
1688	size		3
1689}
1690
1691/*
1692 * Data FIFO Status
1693 */
1694register DFFSTAT {
1695	address			0x03F
1696	access_mode	RW
1697	modes		M_SCSI
1698	field	FIFO1FREE	0x20
1699	field	FIFO0FREE	0x10
1700	/*
1701	 * On the B, this enum only works
1702	 * in the read direction.  For writes,
1703	 * you must use the B version of the
1704	 * CURRFIFO_0 definition which is defined
1705	 * as a constant outside of this register
1706	 * definition to avoid confusing the
1707	 * register pretty printing code.
1708	 */
1709	enum	CURRFIFO	0x03 {
1710		CURRFIFO_0,
1711		CURRFIFO_1,
1712		CURRFIFO_NONE	0x3
1713	}
1714}
1715
1716const B_CURRFIFO_0 0x2
1717
1718/*
1719 * SCSI Bus Target IDs
1720 * Bitmask of observed targets on the bus.
1721 */
1722register BUSTARGID {
1723	address			0x03E
1724	access_mode	RW
1725	modes		M_CFG
1726	size		2
1727}
1728
1729/*
1730 * SCSI Control Signal Out
1731 */
1732register SCSISIGO {
1733	address			0x040
1734	access_mode	RW
1735	modes		M_DFF0, M_DFF1, M_SCSI
1736	field	CDO		0x80
1737	field	IOO		0x40
1738	field	MSGO		0x20
1739	field	ATNO		0x10
1740	field	SELO		0x08
1741	field	BSYO		0x04
1742	field	REQO		0x02
1743	field	ACKO		0x01
1744/*
1745 * Possible phases to write into SCSISIG0
1746 */
1747	enum	PHASE_MASK  CDO|IOO|MSGO {
1748		P_DATAOUT	0x0,
1749		P_DATAIN	IOO,
1750		P_DATAOUT_DT	P_DATAOUT|MSGO,
1751		P_DATAIN_DT	P_DATAIN|MSGO,
1752		P_COMMAND	CDO,
1753		P_MESGOUT	CDO|MSGO,
1754		P_STATUS	CDO|IOO,
1755		P_MESGIN	CDO|IOO|MSGO
1756	}
1757	dont_generate_debug_code
1758}
1759
1760/*
1761 * SCSI Control Signal In
1762 */
1763register SCSISIGI {
1764	address			0x041
1765	access_mode	RO
1766	modes		M_DFF0, M_DFF1, M_SCSI
1767	field	CDI		0x80
1768	field	IOI		0x40
1769	field	MSGI		0x20
1770	field	ATNI		0x10
1771	field	SELI		0x08
1772	field	BSYI		0x04
1773	field	REQI		0x02
1774	field	ACKI		0x01
1775/*
1776 * Possible phases in SCSISIGI
1777 */
1778	enum	PHASE_MASK  CDO|IOO|MSGO {
1779		P_DATAOUT	0x0,
1780		P_DATAIN	IOO,
1781		P_DATAOUT_DT	P_DATAOUT|MSGO,
1782		P_DATAIN_DT	P_DATAIN|MSGO,
1783		P_COMMAND	CDO,
1784		P_MESGOUT	CDO|MSGO,
1785		P_STATUS	CDO|IOO,
1786		P_MESGIN	CDO|IOO|MSGO
1787	}
1788}
1789
1790/*
1791 * Multiple Target IDs
1792 * Bitmask of ids to respond as a target.
1793 */
1794register MULTARGID {
1795	address			0x040
1796	access_mode	RW
1797	modes		M_CFG
1798	size		2
1799	count		2
1800	dont_generate_debug_code
1801}
1802
1803/*
1804 * SCSI Phase
1805 */
1806register SCSIPHASE {
1807	address			0x042
1808	access_mode	RO
1809	modes		M_DFF0, M_DFF1, M_SCSI
1810	field	STATUS_PHASE	0x20
1811	field	COMMAND_PHASE	0x10
1812	field	MSG_IN_PHASE	0x08
1813	field	MSG_OUT_PHASE	0x04
1814	field	DATA_PHASE_MASK	0x03 {
1815		DATA_OUT_PHASE	0x01,
1816		DATA_IN_PHASE	0x02
1817	}
1818}
1819
1820/*
1821 * SCSI Data 0 Image
1822 */
1823register SCSIDAT0_IMG {
1824	address			0x043
1825	access_mode	RW
1826	modes		M_DFF0, M_DFF1, M_SCSI
1827}
1828
1829/*
1830 * SCSI Latched Data
1831 */
1832register SCSIDAT {
1833	address			0x044
1834	access_mode	RW
1835	modes		M_DFF0, M_DFF1, M_SCSI
1836	size		2
1837	dont_generate_debug_code
1838}
1839
1840/*
1841 * SCSI Data Bus
1842 */
1843register SCSIBUS {
1844	address			0x046
1845	access_mode	RW
1846	modes		M_DFF0, M_DFF1, M_SCSI
1847	size		2
1848}
1849
1850/*
1851 * Target ID In
1852 */
1853register TARGIDIN {
1854	address			0x048
1855	access_mode	RO
1856	modes		M_DFF0, M_DFF1, M_SCSI
1857	count		2
1858	field	CLKOUT		0x80
1859	field	TARGID		0x0F
1860	dont_generate_debug_code
1861}
1862
1863/*
1864 * Selection/Reselection ID
1865 * Upper four bits are the device id.  The ONEBIT is set when the re/selecting
1866 * device did not set its own ID.
1867 */
1868register SELID {
1869	address			0x049
1870	access_mode	RW
1871	modes		M_DFF0, M_DFF1, M_SCSI
1872	field	SELID_MASK	0xf0
1873	field	ONEBIT		0x08
1874}
1875
1876/*
1877 * SCSI Block Control
1878 * Controls Bus type and channel selection.  SELWIDE allows for the
1879 * coexistence of 8bit and 16bit devices on a wide bus.
1880 */
1881register SBLKCTL {
1882	address			0x04A
1883	access_mode	RW
1884	modes		M_DFF0, M_DFF1, M_SCSI
1885	field	DIAGLEDEN	0x80
1886	field	DIAGLEDON	0x40
1887	field	ENAB40		0x08	/* LVD transceiver active */
1888	field	ENAB20		0x04	/* SE/HVD transceiver active */
1889	field	SELWIDE		0x02
1890	dont_generate_debug_code
1891}
1892
1893/*
1894 * Option Mode
1895 */
1896register OPTIONMODE {
1897	address			0x04A
1898	access_mode	RW
1899	modes		M_CFG
1900	count		4
1901	field	BIOSCANCTL		0x80
1902	field	AUTOACKEN		0x40
1903	field	BIASCANCTL		0x20
1904	field	BUSFREEREV		0x10
1905	field	ENDGFORMCHK		0x04
1906	field	AUTO_MSGOUT_DE		0x02
1907	mask	OPTIONMODE_DEFAULTS	AUTO_MSGOUT_DE
1908	dont_generate_debug_code
1909}
1910
1911/*
1912 * SCSI Status 0
1913 */
1914register SSTAT0	{
1915	address			0x04B
1916	access_mode	RO
1917	modes		M_DFF0, M_DFF1, M_SCSI
1918	field	TARGET		0x80	/* Board acting as target */
1919	field	SELDO		0x40	/* Selection Done */
1920	field	SELDI		0x20	/* Board has been selected */
1921	field	SELINGO		0x10	/* Selection In Progress */
1922	field	IOERR		0x08	/* LVD Tranceiver mode changed */
1923	field	OVERRUN		0x04	/* SCSI Offset overrun detected */
1924	field	SPIORDY		0x02	/* SCSI PIO Ready */
1925	field	ARBDO		0x01	/* Arbitration Done Out */
1926}
1927
1928/*
1929 * Clear SCSI Interrupt 0
1930 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0.
1931 */
1932register CLRSINT0 {
1933	address			0x04B
1934	access_mode	WO
1935	modes		M_DFF0, M_DFF1, M_SCSI
1936	field	CLRSELDO	0x40
1937	field	CLRSELDI	0x20
1938	field	CLRSELINGO	0x10
1939	field	CLRIOERR	0x08
1940	field	CLROVERRUN	0x04
1941	field	CLRSPIORDY	0x02
1942	field	CLRARBDO	0x01
1943	dont_generate_debug_code
1944}
1945
1946/*
1947 * SCSI Interrupt Mode 0
1948 * Setting any bit will enable the corresponding function
1949 * in SIMODE0 to interrupt via the IRQ pin.
1950 */
1951register SIMODE0 {
1952	address			0x04B
1953	access_mode	RW
1954	modes		M_CFG
1955	count		8
1956	field	ENSELDO		0x40
1957	field	ENSELDI		0x20
1958	field	ENSELINGO	0x10
1959	field	ENIOERR		0x08
1960	field	ENOVERRUN	0x04
1961	field	ENSPIORDY	0x02
1962	field	ENARBDO		0x01
1963}
1964
1965/*
1966 * SCSI Status 1
1967 */
1968register SSTAT1 {
1969	address			0x04C
1970	access_mode	RO
1971	modes		M_DFF0, M_DFF1, M_SCSI
1972	field	SELTO		0x80
1973	field	ATNTARG 	0x40
1974	field	SCSIRSTI	0x20
1975	field	PHASEMIS	0x10
1976	field	BUSFREE		0x08
1977	field	SCSIPERR	0x04
1978	field	STRB2FAST	0x02
1979	field	REQINIT		0x01
1980}
1981
1982/*
1983 * Clear SCSI Interrupt 1
1984 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1.
1985 */
1986register CLRSINT1 {
1987	address			0x04C
1988	access_mode	WO
1989	modes		M_DFF0, M_DFF1, M_SCSI
1990	field	CLRSELTIMEO	0x80
1991	field	CLRATNO		0x40
1992	field	CLRSCSIRSTI	0x20
1993	field	CLRBUSFREE	0x08
1994	field	CLRSCSIPERR	0x04
1995	field	CLRSTRB2FAST	0x02
1996	field	CLRREQINIT	0x01
1997	dont_generate_debug_code
1998}
1999
2000/*
2001 * SCSI Status 2
2002 */
2003register SSTAT2 {
2004	address			0x04d
2005	access_mode	RO
2006	modes		M_DFF0, M_DFF1, M_SCSI
2007	field	BUSFREETIME	0xc0 {
2008		BUSFREE_LQO	0x40,
2009		BUSFREE_DFF0	0x80,
2010		BUSFREE_DFF1	0xC0
2011	}
2012	field	NONPACKREQ	0x20
2013	field	EXP_ACTIVE	0x10	/* SCSI Expander Active */
2014	field	BSYX		0x08	/* Busy Expander */
2015	field	WIDE_RES	0x04	/* Modes 0 and 1 only */
2016	field	SDONE		0x02	/* Modes 0 and 1 only */
2017	field	DMADONE		0x01	/* Modes 0 and 1 only */
2018}
2019
2020/*
2021 * Clear SCSI Interrupt 2
2022 */
2023register CLRSINT2 {
2024	address			0x04D
2025	access_mode	WO
2026	modes		M_DFF0, M_DFF1, M_SCSI
2027	field	CLRNONPACKREQ	0x20
2028	field	CLRWIDE_RES	0x04	/* Modes 0 and 1 only */
2029	field	CLRSDONE	0x02	/* Modes 0 and 1 only */
2030	field	CLRDMADONE	0x01	/* Modes 0 and 1 only */
2031	dont_generate_debug_code
2032}
2033
2034/*
2035 * SCSI Interrupt Mode 2
2036 */
2037register SIMODE2 {
2038	address			0x04D
2039	access_mode	RW
2040	modes		M_CFG
2041	field	ENWIDE_RES	0x04
2042	field	ENSDONE		0x02
2043	field	ENDMADONE	0x01
2044}
2045
2046/*
2047 * Physical Error Diagnosis
2048 */
2049register PERRDIAG {
2050	address			0x04E
2051	access_mode	RO
2052	modes		M_DFF0, M_DFF1, M_SCSI
2053	count		3
2054	field	HIZERO		0x80
2055	field	HIPERR		0x40
2056	field	PREVPHASE	0x20
2057	field	PARITYERR	0x10
2058	field	AIPERR		0x08
2059	field	CRCERR		0x04
2060	field	DGFORMERR	0x02
2061	field	DTERR		0x01
2062}
2063
2064/*
2065 * LQI Manager Current State
2066 */
2067register LQISTATE {
2068	address			0x04E
2069	access_mode	RO
2070	modes		M_CFG
2071	count		6
2072	dont_generate_debug_code
2073}
2074
2075/*
2076 * SCSI Offset Count
2077 */
2078register SOFFCNT {
2079	address			0x04F
2080	access_mode	RO
2081	modes		M_DFF0, M_DFF1, M_SCSI
2082	count		1
2083}
2084
2085/*
2086 * LQO Manager Current State
2087 */
2088register LQOSTATE {
2089	address			0x04F
2090	access_mode	RO
2091	modes		M_CFG
2092	count		2
2093	dont_generate_debug_code
2094}
2095
2096/*
2097 * LQI Manager Status
2098 */
2099register LQISTAT0 {
2100	address			0x050
2101	access_mode	RO
2102	modes		M_DFF0, M_DFF1, M_SCSI
2103	count		2
2104	field	LQIATNQAS	0x20
2105	field	LQICRCT1	0x10
2106	field	LQICRCT2	0x08
2107	field	LQIBADLQT	0x04
2108	field	LQIATNLQ	0x02
2109	field	LQIATNCMD	0x01
2110}
2111
2112/*
2113 * Clear LQI Interrupts 0
2114 */
2115register CLRLQIINT0 {
2116	address			0x050
2117	access_mode	WO
2118	modes		M_DFF0, M_DFF1, M_SCSI
2119	count		1
2120	field	CLRLQIATNQAS	0x20
2121	field	CLRLQICRCT1	0x10
2122	field	CLRLQICRCT2	0x08
2123	field	CLRLQIBADLQT	0x04
2124	field	CLRLQIATNLQ	0x02
2125	field	CLRLQIATNCMD	0x01
2126	dont_generate_debug_code
2127}
2128
2129/*
2130 * LQI Manager Interrupt Mode 0
2131 */
2132register LQIMODE0 {
2133	address			0x050
2134	access_mode	RW
2135	modes		M_CFG
2136	count		3
2137	field	ENLQIATNQASK	0x20
2138	field	ENLQICRCT1	0x10
2139	field	ENLQICRCT2	0x08
2140	field	ENLQIBADLQT	0x04
2141	field	ENLQIATNLQ	0x02
2142	field	ENLQIATNCMD	0x01
2143	dont_generate_debug_code
2144}
2145
2146/*
2147 * LQI Manager Status 1
2148 */
2149register LQISTAT1 {
2150	address			0x051
2151	access_mode	RO
2152	modes		M_DFF0, M_DFF1, M_SCSI
2153	count		3
2154	field	LQIPHASE_LQ	0x80
2155	field	LQIPHASE_NLQ	0x40
2156	field	LQIABORT	0x20
2157	field	LQICRCI_LQ	0x10
2158	field	LQICRCI_NLQ	0x08
2159	field	LQIBADLQI	0x04
2160	field	LQIOVERI_LQ	0x02
2161	field	LQIOVERI_NLQ	0x01
2162}
2163
2164/*
2165 * Clear LQI Manager Interrupts1
2166 */
2167register CLRLQIINT1 {
2168	address			0x051
2169	access_mode	WO
2170	modes		M_DFF0, M_DFF1, M_SCSI
2171	count		4
2172	field	CLRLQIPHASE_LQ	0x80
2173	field	CLRLQIPHASE_NLQ	0x40
2174	field	CLRLIQABORT	0x20
2175	field	CLRLQICRCI_LQ	0x10
2176	field	CLRLQICRCI_NLQ	0x08
2177	field	CLRLQIBADLQI	0x04
2178	field	CLRLQIOVERI_LQ	0x02
2179	field	CLRLQIOVERI_NLQ	0x01
2180	dont_generate_debug_code
2181}
2182
2183/*
2184 * LQI Manager Interrupt Mode 1
2185 */
2186register LQIMODE1 {
2187	address			0x051
2188	access_mode	RW
2189	modes		M_CFG
2190	count		4
2191	field	ENLQIPHASE_LQ	0x80	/* LQIPHASE1 */
2192	field	ENLQIPHASE_NLQ	0x40	/* LQIPHASE2 */
2193	field	ENLIQABORT	0x20
2194	field	ENLQICRCI_LQ	0x10	/* LQICRCI1 */
2195	field	ENLQICRCI_NLQ	0x08	/* LQICRCI2 */
2196	field	ENLQIBADLQI	0x04
2197	field	ENLQIOVERI_LQ	0x02	/* LQIOVERI1 */
2198	field	ENLQIOVERI_NLQ	0x01	/* LQIOVERI2 */
2199	dont_generate_debug_code
2200}
2201
2202/*
2203 * LQI Manager Status 2
2204 */
2205register LQISTAT2 {
2206	address			0x052
2207	access_mode	RO
2208	modes		M_DFF0, M_DFF1, M_SCSI
2209	field	PACKETIZED	0x80
2210	field	LQIPHASE_OUTPKT	0x40
2211	field	LQIWORKONLQ	0x20
2212	field	LQIWAITFIFO	0x10
2213	field	LQISTOPPKT	0x08
2214	field	LQISTOPLQ	0x04
2215	field	LQISTOPCMD	0x02
2216	field	LQIGSAVAIL	0x01
2217}
2218
2219/*
2220 * SCSI Status 3
2221 */
2222register SSTAT3 {
2223	address			0x053
2224	access_mode	RO
2225	modes		M_DFF0, M_DFF1, M_SCSI
2226	count		3
2227	field	NTRAMPERR	0x02
2228	field	OSRAMPERR	0x01
2229}
2230
2231/*
2232 * Clear SCSI Status 3
2233 */
2234register CLRSINT3 {
2235	address			0x053
2236	access_mode	WO
2237	modes		M_DFF0, M_DFF1, M_SCSI
2238	count		3
2239	field	CLRNTRAMPERR	0x02
2240	field	CLROSRAMPERR	0x01
2241	dont_generate_debug_code
2242}
2243
2244/*
2245 * SCSI Interrupt Mode 3
2246 */
2247register SIMODE3 {
2248	address			0x053
2249	access_mode	RW
2250	modes		M_CFG
2251	count		4
2252	field	ENNTRAMPERR	0x02
2253	field	ENOSRAMPERR	0x01
2254	dont_generate_debug_code
2255}
2256
2257/*
2258 * LQO Manager Status 0
2259 */
2260register LQOSTAT0 {
2261	address			0x054
2262	access_mode	RO
2263	modes		M_DFF0, M_DFF1, M_SCSI
2264	count		2
2265	field	LQOTARGSCBPERR	0x10
2266	field	LQOSTOPT2	0x08
2267	field	LQOATNLQ	0x04
2268	field	LQOATNPKT	0x02
2269	field	LQOTCRC		0x01
2270}
2271
2272/*
2273 * Clear LQO Manager interrupt 0
2274 */
2275register CLRLQOINT0 {
2276	address			0x054
2277	access_mode	WO
2278	modes		M_DFF0, M_DFF1, M_SCSI
2279	count		3
2280	field	CLRLQOTARGSCBPERR	0x10
2281	field	CLRLQOSTOPT2		0x08
2282	field	CLRLQOATNLQ		0x04
2283	field	CLRLQOATNPKT		0x02
2284	field	CLRLQOTCRC		0x01
2285	dont_generate_debug_code
2286}
2287
2288/*
2289 * LQO Manager Interrupt Mode 0
2290 */
2291register LQOMODE0 {
2292	address			0x054
2293	access_mode	RW
2294	modes		M_CFG
2295	count		4
2296	field	ENLQOTARGSCBPERR	0x10
2297	field	ENLQOSTOPT2		0x08
2298	field	ENLQOATNLQ		0x04
2299	field	ENLQOATNPKT		0x02
2300	field	ENLQOTCRC		0x01
2301	dont_generate_debug_code
2302}
2303
2304/*
2305 * LQO Manager Status 1
2306 */
2307register LQOSTAT1 {
2308	address			0x055
2309	access_mode	RO
2310	modes		M_DFF0, M_DFF1, M_SCSI
2311	field	LQOINITSCBPERR	0x10
2312	field	LQOSTOPI2	0x08
2313	field	LQOBADQAS	0x04
2314	field	LQOBUSFREE	0x02
2315	field	LQOPHACHGINPKT	0x01
2316}
2317
2318/*
2319 * Clear LOQ Interrupt 1
2320 */
2321register CLRLQOINT1 {
2322	address			0x055
2323	access_mode	WO
2324	modes		M_DFF0, M_DFF1, M_SCSI
2325	count		7
2326	field	CLRLQOINITSCBPERR	0x10
2327	field	CLRLQOSTOPI2		0x08
2328	field	CLRLQOBADQAS		0x04
2329	field	CLRLQOBUSFREE		0x02
2330	field	CLRLQOPHACHGINPKT	0x01
2331	dont_generate_debug_code
2332}
2333
2334/*
2335 * LQO Manager Interrupt Mode 1
2336 */
2337register LQOMODE1 {
2338	address			0x055
2339	access_mode	RW
2340	modes		M_CFG
2341	count		4
2342	field	ENLQOINITSCBPERR	0x10
2343	field	ENLQOSTOPI2		0x08
2344	field	ENLQOBADQAS		0x04
2345	field	ENLQOBUSFREE		0x02
2346	field	ENLQOPHACHGINPKT	0x01
2347	dont_generate_debug_code
2348}
2349
2350/*
2351 * LQO Manager Status 2
2352 */
2353register LQOSTAT2 {
2354	address			0x056
2355	access_mode	RO
2356	modes		M_DFF0, M_DFF1, M_SCSI
2357	field	LQOPKT		0xE0
2358	field	LQOWAITFIFO	0x10
2359	field	LQOPHACHGOUTPKT	0x02	/* outside of packet boundaries. */
2360	field	LQOSTOP0	0x01	/* Stopped after sending all packets */
2361}
2362
2363/*
2364 * Output Synchronizer Space Count
2365 */
2366register OS_SPACE_CNT {
2367	address			0x056
2368	access_mode	RO
2369	modes		M_CFG
2370	count		2
2371	dont_generate_debug_code
2372}
2373
2374/*
2375 * SCSI Interrupt Mode 1
2376 * Setting any bit will enable the corresponding function
2377 * in SIMODE1 to interrupt via the IRQ pin.
2378 */
2379register SIMODE1 {
2380	address			0x057
2381	access_mode	RW
2382	modes		M_DFF0, M_DFF1, M_SCSI
2383	field	ENSELTIMO	0x80
2384	field	ENATNTARG	0x40
2385	field	ENSCSIRST	0x20
2386	field	ENPHASEMIS	0x10
2387	field	ENBUSFREE	0x08
2388	field	ENSCSIPERR	0x04
2389	field	ENSTRB2FAST	0x02
2390	field	ENREQINIT	0x01
2391}
2392
2393/*
2394 * Good Status FIFO
2395 */
2396register GSFIFO {
2397	address			0x058
2398	access_mode	RO
2399	size		2
2400	modes		M_DFF0, M_DFF1, M_SCSI
2401	dont_generate_debug_code
2402}
2403
2404/*
2405 * Data FIFO SCSI Transfer Control
2406 */
2407register DFFSXFRCTL {
2408	address			0x05A
2409	access_mode	RW
2410	modes		M_DFF0, M_DFF1
2411	field	DFFBITBUCKET	0x08
2412	field	CLRSHCNT	0x04
2413	field	CLRCHN		0x02
2414	field	RSTCHN		0x01
2415}
2416
2417/*
2418 * Next SCSI Control Block
2419 */
2420register NEXTSCB {
2421	address			0x05A
2422	access_mode	RW
2423	size		2
2424	modes		M_SCSI
2425	dont_generate_debug_code
2426}
2427
2428/*
2429 * LQO SCSI Control
2430 * (Rev B only.)
2431 */
2432register LQOSCSCTL {
2433	address			0x05A
2434	access_mode	RW
2435	size		1
2436	modes		M_CFG
2437	count		1
2438	field		LQOH2A_VERSION	0x80
2439	field		LQOBUSETDLY	0x40
2440	field		LQONOHOLDLACK	0x02
2441	field		LQONOCHKOVER	0x01
2442	dont_generate_debug_code
2443}
2444
2445/*
2446 * SEQ Interrupts
2447 */
2448register SEQINTSRC {
2449	address			0x05B
2450	access_mode	RO
2451	modes		M_DFF0, M_DFF1
2452	field	CTXTDONE	0x40
2453	field	SAVEPTRS	0x20
2454	field	CFG4DATA	0x10
2455	field	CFG4ISTAT	0x08
2456	field	CFG4TSTAT	0x04
2457	field	CFG4ICMD	0x02
2458	field	CFG4TCMD	0x01
2459}
2460
2461/*
2462 * Clear Arp Interrupts
2463 */
2464register CLRSEQINTSRC {
2465	address			0x05B
2466	access_mode	WO
2467	modes		M_DFF0, M_DFF1
2468	field	CLRCTXTDONE	0x40
2469	field	CLRSAVEPTRS	0x20
2470	field	CLRCFG4DATA	0x10
2471	field	CLRCFG4ISTAT	0x08
2472	field	CLRCFG4TSTAT	0x04
2473	field	CLRCFG4ICMD	0x02
2474	field	CLRCFG4TCMD	0x01
2475	dont_generate_debug_code
2476}
2477
2478/*
2479 * SEQ Interrupt Enabled (Shared)
2480 */
2481register SEQIMODE {
2482	address			0x05C
2483	access_mode	RW
2484	modes		M_DFF0, M_DFF1
2485	field	ENCTXTDONE	0x40
2486	field	ENSAVEPTRS	0x20
2487	field	ENCFG4DATA	0x10
2488	field	ENCFG4ISTAT	0x08
2489	field	ENCFG4TSTAT	0x04
2490	field	ENCFG4ICMD	0x02
2491	field	ENCFG4TCMD	0x01
2492}
2493
2494/*
2495 * Current SCSI Control Block
2496 */
2497register CURRSCB {
2498	address			0x05C
2499	access_mode	RW
2500	size		2
2501	modes		M_SCSI
2502	dont_generate_debug_code
2503}
2504
2505/*
2506 * Data FIFO Status
2507 */
2508register MDFFSTAT {
2509	address			0x05D
2510	access_mode	RO
2511	modes		M_DFF0, M_DFF1
2512	field	SHCNTNEGATIVE	0x40 /* Rev B or higher */
2513	field	SHCNTMINUS1	0x20 /* Rev B or higher */
2514	field	LASTSDONE	0x10
2515	field	SHVALID		0x08
2516	field	DLZERO		0x04 /* FIFO data ends on packet boundary. */
2517	field	DATAINFIFO	0x02
2518	field	FIFOFREE	0x01
2519}
2520
2521/*
2522 * CRC Control
2523 */
2524register CRCCONTROL {
2525	address			0x05d
2526	access_mode	RW
2527	modes		M_CFG
2528	field	CRCVALCHKEN		0x40
2529}
2530
2531/*
2532 * SCSI Test Control
2533 */
2534register SCSITEST {
2535	address			0x05E
2536	access_mode	RW
2537	modes		M_CFG
2538	field	CNTRTEST	0x08
2539	field	SEL_TXPLL_DEBUG	0x04
2540}
2541
2542/*
2543 * Data FIFO Queue Tag
2544 */
2545register DFFTAG {
2546	address			0x05E
2547	access_mode	RW
2548	size		2
2549	modes		M_DFF0, M_DFF1
2550}
2551
2552/*
2553 * Last SCSI Control Block
2554 */
2555register LASTSCB {
2556	address			0x05E
2557	access_mode	RW
2558	size		2
2559	modes		M_SCSI
2560	dont_generate_debug_code
2561}
2562
2563/*
2564 * SCSI I/O Cell Power-down Control
2565 */
2566register IOPDNCTL {
2567	address			0x05F
2568	access_mode	RW
2569	modes		M_CFG
2570	field	DISABLE_OE	0x80
2571	field	PDN_IDIST	0x04
2572	field	PDN_DIFFSENSE	0x01
2573}
2574
2575/*
2576 * Shadow Host Address.
2577 */
2578register SHADDR {
2579	address			0x060
2580	access_mode	RO
2581	size		8
2582	modes		M_DFF0, M_DFF1
2583	dont_generate_debug_code
2584}
2585
2586/*
2587 * Data Group CRC Interval.
2588 */
2589register DGRPCRCI {
2590	address			0x060
2591	access_mode	RW
2592	size		2
2593	modes		M_CFG
2594}
2595
2596/*
2597 * Data Transfer Negotiation Address
2598 */
2599register NEGOADDR {
2600	address			0x060
2601	access_mode	RW
2602	modes		M_SCSI
2603	dont_generate_debug_code
2604}
2605
2606/*
2607 * Data Transfer Negotiation Data - Period Byte
2608 */
2609register NEGPERIOD {
2610	address			0x061
2611	access_mode	RW
2612	modes		M_SCSI
2613	count		1
2614	dont_generate_debug_code
2615}
2616
2617/*
2618 * Packetized CRC Interval
2619 */
2620register PACKCRCI {
2621	address			0x062
2622	access_mode	RW
2623	size		2
2624	modes		M_CFG
2625}
2626
2627/*
2628 * Data Transfer Negotiation Data - Offset Byte
2629 */
2630register NEGOFFSET {
2631	address			0x062
2632	access_mode	RW
2633	modes		M_SCSI
2634	count		1
2635	dont_generate_debug_code
2636}
2637
2638/*
2639 * Data Transfer Negotiation Data - PPR Options
2640 */
2641register NEGPPROPTS {
2642	address			0x063
2643	access_mode	RW
2644	modes		M_SCSI
2645	count		1
2646	field	PPROPT_PACE	0x08
2647	field	PPROPT_QAS	0x04
2648	field	PPROPT_DT	0x02
2649	field	PPROPT_IUT	0x01
2650	dont_generate_debug_code
2651}
2652
2653/*
2654 * Data Transfer Negotiation Data -  Connection Options
2655 */
2656register NEGCONOPTS {
2657	address			0x064
2658	access_mode	RW
2659	modes		M_SCSI
2660	field	ENSNAPSHOT	0x40
2661	field	RTI_WRTDIS	0x20
2662	field	RTI_OVRDTRN	0x10
2663	field	ENSLOWCRC	0x08
2664	field	ENAUTOATNI	0x04
2665	field	ENAUTOATNO	0x02
2666	field	WIDEXFER	0x01
2667	dont_generate_debug_code
2668}
2669
2670/*
2671 * Negotiation Table Annex Column Index.
2672 */
2673register ANNEXCOL {
2674	address			0x065
2675	access_mode	RW
2676	modes		M_SCSI
2677	count		7
2678	dont_generate_debug_code
2679}
2680
2681/*
2682 * SCSI Check
2683 * (Rev. B only)
2684 */
2685register SCSCHKN {
2686	address			0x066
2687	access_mode	RW
2688	modes		M_CFG
2689	count		1
2690	field	BIDICHKDIS	0x80
2691	field	STSELSKIDDIS	0x40
2692	field	CURRFIFODEF	0x20
2693	field	WIDERESEN	0x10
2694	field	SDONEMSKDIS	0x08
2695	field	DFFACTCLR	0x04
2696	field	SHVALIDSTDIS	0x02
2697	field	LSTSGCLRDIS	0x01
2698	dont_generate_debug_code
2699}
2700
2701const AHD_ANNEXCOL_PER_DEV0	4
2702const AHD_NUM_PER_DEV_ANNEXCOLS	4
2703const AHD_ANNEXCOL_PRECOMP_SLEW	4
2704const	AHD_PRECOMP_MASK	0x07
2705const	AHD_PRECOMP_SHIFT	0
2706const	AHD_PRECOMP_CUTBACK_17	0x04
2707const	AHD_PRECOMP_CUTBACK_29	0x06
2708const	AHD_PRECOMP_CUTBACK_37	0x07
2709const	AHD_SLEWRATE_MASK	0x78
2710const	AHD_SLEWRATE_SHIFT	3
2711/*
2712 * Rev A has only a single bit (high bit of field) of slew adjustment.
2713 * Rev B has 4 bits.  The current default happens to be the same for both.
2714 */
2715const	AHD_SLEWRATE_DEF_REVA	0x08
2716const	AHD_SLEWRATE_DEF_REVB	0x08
2717
2718/* Rev A does not have any amplitude setting. */
2719const AHD_ANNEXCOL_AMPLITUDE	6
2720const	AHD_AMPLITUDE_MASK	0x7
2721const	AHD_AMPLITUDE_SHIFT	0
2722const	AHD_AMPLITUDE_DEF	0x7
2723
2724/*
2725 * Negotiation Table Annex Data Port.
2726 */
2727register ANNEXDAT {
2728	address			0x066
2729	access_mode	RW
2730	modes		M_SCSI
2731	count		3
2732	dont_generate_debug_code
2733}
2734
2735/*
2736 * Initiator's Own Id.
2737 * The SCSI ID to use for Selection Out and seen during a reselection..
2738 */
2739register IOWNID {
2740	address			0x067
2741	access_mode	RW
2742	modes		M_SCSI
2743	dont_generate_debug_code
2744}
2745
2746/*
2747 * 960MHz Phase-Locked Loop Control 0
2748 */
2749register PLL960CTL0 {
2750	address			0x068
2751	access_mode	RW
2752	modes		M_CFG
2753	field	PLL_VCOSEL	0x80
2754	field	PLL_PWDN	0x40
2755	field	PLL_NS		0x30
2756	field	PLL_ENLUD	0x08
2757	field	PLL_ENLPF	0x04
2758	field	PLL_DLPF	0x02
2759	field	PLL_ENFBM	0x01
2760}
2761
2762/*
2763 * Target Own Id
2764 */
2765register TOWNID {
2766	address			0x069
2767	access_mode	RW
2768	modes		M_SCSI
2769	count		2
2770	dont_generate_debug_code
2771}
2772
2773/*
2774 * 960MHz Phase-Locked Loop Control 1
2775 */
2776register PLL960CTL1 {
2777	address			0x069
2778	access_mode	RW
2779	modes		M_CFG
2780	field	PLL_CNTEN	0x80
2781	field	PLL_CNTCLR	0x40
2782	field	PLL_RST		0x01
2783}
2784
2785/*
2786 * Expander Signature
2787 */
2788register XSIG {
2789	address			0x06A
2790	access_mode	RW
2791	modes		M_SCSI
2792}
2793
2794/*
2795 * Shadow Byte Count
2796 */
2797register SHCNT {
2798	address			0x068
2799	access_mode	RW
2800	size		3
2801	modes		M_DFF0, M_DFF1
2802	dont_generate_debug_code
2803}
2804
2805/*
2806 * Selection Out ID
2807 */
2808register SELOID {
2809	address			0x06B
2810	access_mode	RW
2811	modes		M_SCSI
2812}
2813
2814/*
2815 * 960-MHz Phase-Locked Loop Test Count
2816 */
2817register PLL960CNT0 {
2818	address			0x06A
2819	access_mode	RO
2820	size		2
2821	modes		M_CFG
2822}
2823
2824/*
2825 * 400-MHz Phase-Locked Loop Control 0
2826 */
2827register PLL400CTL0 {
2828	address			0x06C
2829	access_mode	RW
2830	modes		M_CFG
2831	field	PLL_VCOSEL	0x80
2832	field	PLL_PWDN	0x40
2833	field	PLL_NS		0x30
2834	field	PLL_ENLUD	0x08
2835	field	PLL_ENLPF	0x04
2836	field	PLL_DLPF	0x02
2837	field	PLL_ENFBM	0x01
2838}
2839
2840/*
2841 * Arbitration Fairness
2842 */
2843register FAIRNESS {
2844	address			0x06C
2845	access_mode	RW
2846	size		2
2847	modes		M_SCSI
2848}
2849
2850/*
2851 * 400-MHz Phase-Locked Loop Control 1
2852 */
2853register PLL400CTL1 {
2854	address			0x06D
2855	access_mode	RW
2856	modes		M_CFG
2857	field	PLL_CNTEN	0x80
2858	field	PLL_CNTCLR	0x40
2859	field	PLL_RST		0x01
2860}
2861
2862/*
2863 * Arbitration Unfairness
2864 */
2865register UNFAIRNESS {
2866	address			0x06E
2867	access_mode	RW
2868	size		2
2869	modes		M_SCSI
2870}
2871
2872/*
2873 * 400-MHz Phase-Locked Loop Test Count
2874 */
2875register PLL400CNT0 {
2876	address			0x06E
2877	access_mode	RO
2878	size		2
2879	modes		M_CFG
2880}
2881
2882/*
2883 * SCB Page Pointer
2884 */
2885register SCBPTR {
2886	address			0x0A8
2887	access_mode	RW
2888	size		2
2889	modes		M_DFF0, M_DFF1, M_CCHAN, M_SCSI
2890	dont_generate_debug_code
2891}
2892
2893/*
2894 * CMC SCB Array Count
2895 * Number of bytes to transfer between CMC SCB memory and SCBRAM.
2896 * Transfers must be 8byte aligned and sized.
2897 */
2898register CCSCBACNT {
2899	address			0x0AB
2900	access_mode	RW
2901	modes		M_CCHAN
2902}
2903
2904/*
2905 * SCB Autopointer
2906 * SCB-Next Address Snooping logic.  When an SCB is transferred to
2907 * the card, the next SCB address to be used by the CMC array can
2908 * be autoloaded from that transfer.
2909 */
2910register SCBAUTOPTR {
2911	address			0x0AB
2912	access_mode	RW
2913	modes		M_CFG
2914	count		1
2915	field	AUSCBPTR_EN	0x80
2916	field	SCBPTR_ADDR	0x38
2917	field	SCBPTR_OFF	0x07
2918	dont_generate_debug_code
2919}
2920
2921/*
2922 * CMC SG Ram Address Pointer
2923 */
2924register CCSGADDR {
2925	address			0x0AC
2926	access_mode	RW
2927	modes		M_DFF0, M_DFF1
2928	dont_generate_debug_code
2929}
2930
2931/*
2932 * CMC SCB RAM Address Pointer
2933 */
2934register CCSCBADDR {
2935	address			0x0AC
2936	access_mode	RW
2937	modes		M_CCHAN
2938	dont_generate_debug_code
2939}
2940
2941/*
2942 * CMC SCB Ram Back-up Address Pointer
2943 * Indicates the true stop location of transfers halted prior
2944 * to SCBHCNT going to 0.
2945 */
2946register CCSCBADR_BK {
2947	address			0x0AC
2948	access_mode	RO
2949	modes		M_CFG
2950}
2951
2952/*
2953 * CMC SG Control
2954 */
2955register CCSGCTL {
2956	address			0x0AD
2957	access_mode	RW
2958	modes		M_DFF0, M_DFF1
2959	field	CCSGDONE	0x80
2960	field	SG_CACHE_AVAIL	0x10
2961	field	CCSGENACK	0x08
2962	mask	CCSGEN		0x0C
2963	field	SG_FETCH_REQ	0x02
2964	field	CCSGRESET	0x01
2965}
2966
2967/*
2968 * CMD SCB Control
2969 */
2970register CCSCBCTL {
2971	address			0x0AD
2972	access_mode	RW
2973	modes		M_CCHAN
2974	field	CCSCBDONE	0x80
2975	field	ARRDONE		0x40
2976	field	CCARREN		0x10
2977	field	CCSCBEN		0x08
2978	field	CCSCBDIR	0x04
2979	field	CCSCBRESET	0x01
2980}
2981
2982/*
2983 * CMC Ram BIST
2984 */
2985register CMC_RAMBIST {
2986	address			0x0AD
2987	access_mode	RW
2988	modes		M_CFG
2989	field	SG_ELEMENT_SIZE		0x80
2990	field	SCBRAMBIST_FAIL		0x40
2991	field	SG_BIST_FAIL		0x20
2992	field	SG_BIST_EN		0x10
2993	field	CMC_BUFFER_BIST_FAIL	0x02
2994	field	CMC_BUFFER_BIST_EN	0x01
2995}
2996
2997/*
2998 * CMC SG RAM Data Port
2999 */
3000register CCSGRAM {
3001	address			0x0B0
3002	access_mode	RW
3003	modes		M_DFF0, M_DFF1
3004	dont_generate_debug_code
3005}
3006
3007/*
3008 * CMC SCB RAM Data Port
3009 */
3010register CCSCBRAM {
3011	address			0x0B0
3012	access_mode	RW
3013	modes		M_CCHAN
3014	dont_generate_debug_code
3015}
3016
3017/*
3018 * Flex DMA Address.
3019 */
3020register FLEXADR {
3021	address			0x0B0
3022	access_mode	RW
3023	size		3
3024	modes		M_SCSI
3025}
3026
3027/*
3028 * Flex DMA Byte Count
3029 */
3030register FLEXCNT {
3031	address			0x0B3
3032	access_mode	RW
3033	size		2
3034	modes		M_SCSI
3035}
3036
3037/*
3038 * Flex DMA Status
3039 */
3040register FLEXDMASTAT {
3041	address			0x0B5
3042	access_mode	RW
3043	modes		M_SCSI
3044	field	FLEXDMAERR	0x02
3045	field	FLEXDMADONE	0x01
3046}
3047
3048/*
3049 * Flex DMA Data Port
3050 */
3051register FLEXDATA {
3052	address			0x0B6
3053	access_mode	RW
3054	modes		M_SCSI
3055}
3056
3057/*
3058 * Board Data
3059 */
3060register BRDDAT {
3061	address			0x0B8
3062	access_mode	RW
3063	modes		M_SCSI
3064	count		2
3065	dont_generate_debug_code
3066}
3067
3068/*
3069 * Board Control
3070 */
3071register BRDCTL {
3072	address			0x0B9
3073	access_mode	RW
3074	modes		M_SCSI
3075	count		7
3076	field	FLXARBACK	0x80
3077	field	FLXARBREQ	0x40
3078	field	BRDADDR		0x38
3079	field	BRDEN		0x04
3080	field	BRDRW		0x02
3081	field	BRDSTB		0x01
3082	dont_generate_debug_code
3083}
3084
3085/*
3086 * Serial EEPROM Address
3087 */
3088register SEEADR {
3089	address			0x0BA
3090	access_mode	RW
3091	modes		M_SCSI
3092	count		4
3093	dont_generate_debug_code
3094}
3095
3096/*
3097 * Serial EEPROM Data
3098 */
3099register SEEDAT {
3100	address			0x0BC
3101	access_mode	RW
3102	size		2
3103	modes		M_SCSI
3104	count		4
3105	dont_generate_debug_code
3106}
3107
3108/*
3109 * Serial EEPROM Status
3110 */
3111register SEESTAT {
3112	address			0x0BE
3113	access_mode	RO
3114	modes		M_SCSI
3115	count		1
3116	field	INIT_DONE	0x80
3117	field	SEEOPCODE	0x70
3118	field	LDALTID_L	0x08
3119	field	SEEARBACK	0x04
3120	field	SEEBUSY		0x02
3121	field	SEESTART	0x01
3122	dont_generate_debug_code
3123}
3124
3125/*
3126 * Serial EEPROM Control
3127 */
3128register SEECTL {
3129	address			0x0BE
3130	access_mode	RW
3131	modes		M_SCSI
3132	count		4
3133	field	SEEOPCODE	0x70 {
3134		SEEOP_ERASE	0x70,
3135		SEEOP_READ	0x60,
3136		SEEOP_WRITE	0x50,
3137	/*
3138	 * The following four commands use special
3139	 * addresses for differentiation.
3140	 */
3141		SEEOP_ERAL	0x40
3142	}
3143	mask	SEEOP_EWEN	0x40
3144	mask	SEEOP_WALL	0x40
3145	mask	SEEOP_EWDS	0x40
3146	field	SEERST		0x02
3147	field	SEESTART	0x01
3148	dont_generate_debug_code
3149}
3150
3151const SEEOP_ERAL_ADDR	0x80
3152const SEEOP_EWEN_ADDR	0xC0
3153const SEEOP_WRAL_ADDR	0x40
3154const SEEOP_EWDS_ADDR	0x00
3155
3156/*
3157 * SCB Counter
3158 */
3159register SCBCNT {
3160	address			0x0BF
3161	access_mode	RW
3162	modes		M_SCSI
3163	dont_generate_debug_code
3164}
3165
3166/*
3167 * Data FIFO Write Address
3168 * Pointer to the next QWD location to be written to the data FIFO.
3169 */
3170register DFWADDR {
3171	address			0x0C0
3172	access_mode	RW
3173	size		2
3174	modes		M_DFF0, M_DFF1
3175	dont_generate_debug_code
3176}
3177
3178/*
3179 * DSP Filter Control
3180 */
3181register DSPFLTRCTL {
3182	address			0x0C0
3183	access_mode	RW
3184	modes		M_CFG
3185	field	FLTRDISABLE	0x20
3186	field	EDGESENSE	0x10
3187	field	DSPFCNTSEL	0x0F
3188}
3189
3190/*
3191 * DSP Data Channel Control
3192 */
3193register DSPDATACTL {
3194	address			0x0C1
3195	access_mode	RW
3196	modes		M_CFG
3197	count		3
3198	field	BYPASSENAB	0x80
3199	field	DESQDIS		0x10
3200	field	RCVROFFSTDIS	0x04
3201	field	XMITOFFSTDIS	0x02
3202	dont_generate_debug_code
3203}
3204
3205/*
3206 * Data FIFO Read Address
3207 * Pointer to the next QWD location to be read from the data FIFO.
3208 */
3209register DFRADDR {
3210	address			0x0C2
3211	access_mode	RW
3212	size		2
3213	modes		M_DFF0, M_DFF1
3214}
3215
3216/*
3217 * DSP REQ Control
3218 */
3219register DSPREQCTL {
3220	address			0x0C2
3221	access_mode	RW
3222	modes		M_CFG
3223	field	MANREQCTL	0xC0
3224	field	MANREQDLY	0x3F
3225}
3226
3227/*
3228 * DSP ACK Control
3229 */
3230register DSPACKCTL {
3231	address			0x0C3
3232	access_mode	RW
3233	modes		M_CFG
3234	field	MANACKCTL	0xC0
3235	field	MANACKDLY	0x3F
3236}
3237
3238/*
3239 * Data FIFO Data
3240 * Read/Write byte port into the data FIFO.  The read and write
3241 * FIFO pointers increment with each read and write respectively
3242 * to this port.
3243 */
3244register DFDAT {
3245	address			0x0C4
3246	access_mode	RW
3247	modes		M_DFF0, M_DFF1
3248	dont_generate_debug_code
3249}
3250
3251/*
3252 * DSP Channel Select
3253 */
3254register DSPSELECT {
3255	address			0x0C4
3256	access_mode	RW
3257	modes		M_CFG
3258	count		1
3259	field	AUTOINCEN	0x80
3260	field	DSPSEL		0x1F
3261	dont_generate_debug_code
3262}
3263
3264const NUMDSPS 0x14
3265
3266/*
3267 * Write Bias Control
3268 */
3269register WRTBIASCTL {
3270	address			0x0C5
3271	access_mode	WO
3272	modes		M_CFG
3273	count		3
3274	field	AUTOXBCDIS	0x80
3275	field	XMITMANVAL	0x3F
3276	dont_generate_debug_code
3277}
3278
3279/*
3280 * Currently the WRTBIASCTL is the same as the default.
3281 */
3282const WRTBIASCTL_HP_DEFAULT 0x0
3283
3284/*
3285 * Receiver Bias Control
3286 */
3287register RCVRBIOSCTL {
3288	address			0x0C6
3289	access_mode	WO
3290	modes		M_CFG
3291	field	AUTORBCDIS	0x80
3292	field	RCVRMANVAL	0x3F
3293}
3294
3295/*
3296 * Write Bias Calculator
3297 */
3298register WRTBIASCALC {
3299	address			0x0C7
3300	access_mode	RO
3301	modes		M_CFG
3302}
3303
3304/*
3305 * Data FIFO Pointers
3306 * Contains the byte offset from DFWADDR and DWRADDR to the current
3307 * FIFO write/read locations.
3308 */
3309register DFPTRS {
3310	address			0x0C8
3311	access_mode	RW
3312	modes		M_DFF0, M_DFF1
3313}
3314
3315/*
3316 * Receiver Bias Calculator
3317 */
3318register RCVRBIASCALC {
3319	address			0x0C8
3320	access_mode	RO
3321	modes		M_CFG
3322}
3323
3324/*
3325 * Data FIFO Backup Read Pointer
3326 * Contains the data FIFO address to be restored if the last
3327 * data accessed from the data FIFO was not transferred successfully.
3328 */
3329register DFBKPTR {
3330	address			0x0C9
3331	access_mode	RW
3332	size		2
3333	modes		M_DFF0, M_DFF1
3334}
3335
3336/*
3337 * Skew Calculator
3338 */
3339register SKEWCALC {
3340	address			0x0C9
3341	access_mode	RO
3342	modes		M_CFG
3343}
3344
3345/*
3346 * Data FIFO Debug Control
3347 */
3348register DFDBCTL {
3349	address				0x0CB
3350	access_mode	RW
3351	modes		M_DFF0, M_DFF1
3352	field	DFF_CIO_WR_RDY		0x20
3353	field	DFF_CIO_RD_RDY		0x10
3354	field	DFF_DIR_ERR		0x08
3355	field	DFF_RAMBIST_FAIL	0x04
3356	field	DFF_RAMBIST_DONE	0x02
3357	field	DFF_RAMBIST_EN		0x01
3358}
3359
3360/*
3361 * Data FIFO Space Count
3362 * Number of FIFO locations that are free.
3363 */
3364register DFSCNT {
3365	address			0x0CC
3366	access_mode	RO
3367	size		2
3368	modes		M_DFF0, M_DFF1
3369}
3370
3371/*
3372 * Data FIFO Byte Count
3373 * Number of filled FIFO locations.
3374 */
3375register DFBCNT {
3376	address			0x0CE
3377	access_mode	RO
3378	size		2
3379	modes		M_DFF0, M_DFF1
3380}
3381
3382/*
3383 * Sequencer Program Overlay Address.
3384 * Low address must be written prior to high address.
3385 */
3386register OVLYADDR {
3387	address			0x0D4
3388	modes		M_SCSI
3389	size		2
3390	access_mode	RW
3391}
3392
3393/*
3394 * Sequencer Control 0
3395 * Error detection mode, speed configuration,
3396 * single step, breakpoints and program load.
3397 */
3398register SEQCTL0 {
3399	address			0x0D6
3400	access_mode	RW
3401	count		11
3402	field	PERRORDIS	0x80
3403	field	PAUSEDIS	0x40
3404	field	FAILDIS		0x20
3405	field	FASTMODE	0x10
3406	field	BRKADRINTEN	0x08
3407	field	STEP		0x04
3408	field	SEQRESET	0x02
3409	field	LOADRAM		0x01
3410}
3411
3412/*
3413 * Sequencer Control 1
3414 * Instruction RAM Diagnostics
3415 */
3416register SEQCTL1 {
3417	address			0x0D7
3418	access_mode RW
3419	field	OVRLAY_DATA_CHK	0x08
3420	field	RAMBIST_DONE	0x04
3421	field	RAMBIST_FAIL	0x02
3422	field	RAMBIST_EN	0x01
3423}
3424
3425/*
3426 * Sequencer Flags
3427 * Zero and Carry state of the ALU.
3428 */
3429register FLAGS {
3430	address			0x0D8
3431	access_mode 	RO
3432	count		23
3433	field	ZERO		0x02
3434	field	CARRY		0x01
3435	dont_generate_debug_code
3436}
3437
3438/*
3439 * Sequencer Interrupt Control
3440 */ 
3441register SEQINTCTL {
3442	address			0x0D9
3443	access_mode RW
3444	field	INTVEC1DSL	0x80
3445	field	INT1_CONTEXT	0x20
3446	field	SCS_SEQ_INT1M1	0x10
3447	field	SCS_SEQ_INT1M0	0x08
3448	field	INTMASK2	0x04
3449	field	INTMASK1	0x02
3450	field	IRET		0x01
3451}
3452
3453/*
3454 * Sequencer RAM Data Port
3455 * Single byte window into the Sequencer Instruction Ram area starting
3456 * at the address specified by OVLYADDR.  To write a full instruction word,
3457 * simply write four bytes in succession.  OVLYADDR will increment after the
3458 * most significant instrution byte (the byte with the parity bit) is written.
3459 */
3460register SEQRAM {
3461	address			0x0DA
3462	access_mode 	RW
3463	count		2
3464	dont_generate_debug_code
3465}
3466
3467/*
3468 * Sequencer Program Counter
3469 * Low byte must be written prior to high byte.
3470 */
3471register PRGMCNT {
3472	address			0x0DE
3473	access_mode	RW
3474	size		2
3475	count		5
3476	dont_generate_debug_code
3477}
3478
3479/*
3480 * Accumulator
3481 */
3482register ACCUM {
3483	address			0x0E0
3484	access_mode 	RW
3485	accumulator
3486	dont_generate_debug_code
3487}
3488
3489/*
3490 * Source Index Register
3491 * Incrementing index for reads of SINDIR and the destination (low byte only)
3492 * for any immediate operands passed in jmp, jc, jnc, call instructions.
3493 * Example:
3494 *		mvi	0xFF	call some_routine;
3495 *
3496 *  Will set SINDEX[0] to 0xFF and call the routine "some_routine.
3497 */
3498register SINDEX	{
3499	address			0x0E2
3500	access_mode	RW
3501	size		2
3502	sindex
3503	dont_generate_debug_code
3504}
3505
3506/*
3507 * Destination Index Register
3508 * Incrementing index for writes to DINDIR.  Can be used as a scratch register.
3509 */
3510register DINDEX {
3511	address			0x0E4
3512	access_mode	RW
3513	size		2
3514	dont_generate_debug_code
3515}
3516
3517/*
3518 * Break Address
3519 * Sequencer instruction breakpoint address address.
3520 */
3521register BRKADDR0 {
3522	address			0x0E6
3523	access_mode	RW
3524}
3525
3526register BRKADDR1 {
3527	address			0x0E6
3528	access_mode	RW
3529	field	BRKDIS		0x80	/* Disable Breakpoint */
3530}
3531
3532/*
3533 * All Ones
3534 * All reads to this register return the value 0xFF.
3535 */
3536register ALLONES {
3537	address			0x0E8
3538	access_mode RO
3539	allones
3540	dont_generate_debug_code
3541}
3542
3543/*
3544 * All Zeros
3545 * All reads to this register return the value 0.
3546 */
3547register ALLZEROS {
3548	address			0x0EA
3549	access_mode RO
3550	allzeros
3551	dont_generate_debug_code
3552}
3553
3554/*
3555 * No Destination
3556 * Writes to this register have no effect.
3557 */
3558register NONE {
3559	address			0x0EA
3560	access_mode WO
3561	none
3562	dont_generate_debug_code
3563}
3564
3565/*
3566 * Source Index Indirect
3567 * Reading this register is equivalent to reading (register_base + SINDEX) and
3568 * incrementing SINDEX by 1.
3569 */
3570register SINDIR	{
3571	address			0x0EC
3572	access_mode RO
3573	dont_generate_debug_code
3574}
3575
3576/*
3577 * Destination Index Indirect
3578 * Writing this register is equivalent to writing to (register_base + DINDEX)
3579 * and incrementing DINDEX by 1.
3580 */
3581register DINDIR	 {
3582	address			0x0ED
3583	access_mode WO
3584	dont_generate_debug_code
3585}
3586
3587/*
3588 * Function One
3589 * 2's complement to bit value conversion.  Write the 2's complement value
3590 * (0-7 only) to the top nibble and retrieve the bit indexed by that value
3591 * on the next read of this register. 
3592 * Example:
3593 *	Write	0x60
3594 *	Read	0x40
3595 */
3596register FUNCTION1 {
3597	address			0x0F0
3598	access_mode RW
3599}
3600
3601/*
3602 * Stack
3603 * Window into the stack.  Each stack location is 10 bits wide reported
3604 * low byte followed by high byte.  There are 8 stack locations.
3605 */
3606register STACK {
3607	address			0x0F2
3608	access_mode RW
3609	dont_generate_debug_code
3610}
3611
3612/*
3613 * Interrupt Vector 1 Address
3614 * Interrupt branch address for SCS SEQ_INT1 mode 0 and 1 interrupts.
3615 */
3616register INTVEC1_ADDR {
3617	address			0x0F4
3618	access_mode	RW
3619	size		2
3620	modes		M_CFG
3621	count		1
3622	dont_generate_debug_code
3623}
3624
3625/*
3626 * Current Address
3627 * Address of the SEQRAM instruction currently executing instruction.
3628 */
3629register CURADDR {
3630	address			0x0F4
3631	access_mode	RW
3632	size		2
3633	modes		M_SCSI
3634	count		2
3635	dont_generate_debug_code
3636}
3637
3638/*
3639 * Interrupt Vector 2 Address
3640 * Interrupt branch address for HST_SEQ_INT2 interrupts.
3641 */
3642register INTVEC2_ADDR {
3643	address			0x0F6
3644	access_mode	RW
3645	size		2
3646	modes		M_CFG
3647	count		1
3648	dont_generate_debug_code
3649}
3650
3651/*
3652 * Last Address
3653 * Address of the SEQRAM instruction executed prior to the current instruction.
3654 */
3655register LASTADDR {
3656	address			0x0F6
3657	access_mode	RW
3658	size		2
3659	modes		M_SCSI
3660}
3661
3662register AHD_PCI_CONFIG_BASE {
3663	address			0x100
3664	access_mode	RW
3665	size		256
3666	modes		M_CFG
3667}
3668
3669/* ---------------------- Scratch RAM Offsets ------------------------- */
3670scratch_ram {
3671	/* Mode Specific */
3672	address			0x0A0
3673	size	8
3674	modes	0, 1, 2, 3
3675	REG0 {
3676		size		2
3677		dont_generate_debug_code
3678	}
3679	REG1 {
3680		size		2
3681	}
3682	REG_ISR {
3683		size		2
3684		dont_generate_debug_code
3685	}
3686	SG_STATE {
3687		size		1
3688		field	SEGS_AVAIL	0x01
3689		field	LOADING_NEEDED	0x02
3690		field	FETCH_INPROG	0x04
3691	}
3692	/*
3693	 * Track whether the transfer byte count for
3694	 * the current data phase is odd.
3695	 */
3696	DATA_COUNT_ODD {
3697		size		1
3698	}
3699}
3700
3701scratch_ram {
3702	/* Mode Specific */
3703	address			0x0F8
3704	size	8
3705	modes	0, 1, 2, 3
3706	LONGJMP_ADDR {
3707		size		2
3708		dont_generate_debug_code
3709	}
3710	ACCUM_SAVE {
3711		size		1
3712		dont_generate_debug_code
3713	}
3714}
3715
3716
3717scratch_ram {
3718	address			0x100
3719	size	128
3720	modes	0, 1, 2, 3
3721	/*
3722	 * Per "other-id" execution queues.  We use an array of
3723	 * tail pointers into lists of SCBs sorted by "other-id".
3724	 * The execution head pointer threads the head SCBs for
3725	 * each list.
3726	 */
3727	WAITING_SCB_TAILS {
3728		size		32
3729		dont_generate_debug_code
3730	}
3731	WAITING_TID_HEAD {
3732		size		2
3733		dont_generate_debug_code
3734	}
3735	WAITING_TID_TAIL {
3736		size		2
3737		dont_generate_debug_code
3738	}
3739	/*
3740	 * SCBID of the next SCB in the new SCB queue.
3741	 */
3742	NEXT_QUEUED_SCB_ADDR {
3743		size		4
3744		dont_generate_debug_code
3745	}
3746	/*
3747	 * head of list of SCBs that have
3748	 * completed but have not been
3749	 * put into the qoutfifo.
3750	 */
3751	COMPLETE_SCB_HEAD {
3752		size		2
3753		dont_generate_debug_code
3754	}
3755	/*
3756	 * The list of completed SCBs in
3757	 * the active DMA.
3758	 */
3759	COMPLETE_SCB_DMAINPROG_HEAD {
3760		size		2
3761		dont_generate_debug_code
3762	}
3763	/*
3764	 * head of list of SCBs that have
3765	 * completed but need to be uploaded
3766	 * to the host prior to being completed.
3767	 */
3768	COMPLETE_DMA_SCB_HEAD {
3769		size		2
3770		dont_generate_debug_code
3771	}
3772	/*
3773	 * tail of list of SCBs that have
3774	 * completed but need to be uploaded
3775	 * to the host prior to being completed.
3776	 */
3777	COMPLETE_DMA_SCB_TAIL {
3778		size		2
3779		dont_generate_debug_code
3780	}
3781	/*
3782	 * head of list of SCBs that have
3783	 * been uploaded to the host, but cannot
3784	 * be completed until the QFREEZE is in
3785	 * full effect (i.e. no selections pending).
3786	 */
3787	COMPLETE_ON_QFREEZE_HEAD {
3788		size		2
3789		dont_generate_debug_code
3790	}
3791	/*
3792	 * Counting semaphore to prevent new select-outs
3793	 * The queue is frozen so long as the sequencer
3794	 * and kernel freeze counts differ.
3795	 */
3796	QFREEZE_COUNT {
3797		size		2
3798	}
3799	KERNEL_QFREEZE_COUNT {
3800		size		2
3801	}
3802	/*
3803	 * Mode to restore on legacy idle loop exit.
3804	 */
3805	SAVED_MODE {
3806		size		1
3807	}
3808	/*
3809	 * Single byte buffer used to designate the type or message
3810	 * to send to a target.
3811	 */
3812	MSG_OUT {
3813		size		1
3814		dont_generate_debug_code
3815	}
3816	/* Parameters for DMA Logic */
3817	DMAPARAMS {
3818		size		1
3819		count		8
3820		field	PRELOADEN	0x80
3821		field	WIDEODD		0x40
3822		field	SCSIEN		0x20
3823		field	SDMAEN		0x10
3824		field	SDMAENACK	0x10
3825		field	HDMAEN		0x08
3826		field	HDMAENACK	0x08
3827		field	DIRECTION	0x04	/* Set indicates PCI->SCSI */
3828		field	FIFOFLUSH	0x02
3829		field	FIFORESET	0x01
3830		dont_generate_debug_code
3831	}
3832	SEQ_FLAGS {
3833		size		1
3834		field	NOT_IDENTIFIED		0x80
3835		field	NO_CDB_SENT		0x40
3836		field	TARGET_CMD_IS_TAGGED	0x40
3837		field	DPHASE			0x20
3838		/* Target flags */
3839		field	TARG_CMD_PENDING	0x10
3840		field	CMDPHASE_PENDING	0x08
3841		field	DPHASE_PENDING		0x04
3842		field	SPHASE_PENDING		0x02
3843		field	NO_DISCONNECT		0x01
3844	}
3845	/*
3846	 * Temporary storage for the
3847	 * target/channel/lun of a
3848	 * reconnecting target
3849	 */
3850	SAVED_SCSIID {
3851		size		1
3852		dont_generate_debug_code
3853	}
3854	SAVED_LUN {
3855		size		1
3856		dont_generate_debug_code
3857	}
3858	/*
3859	 * The last bus phase as seen by the sequencer. 
3860	 */
3861	LASTPHASE {
3862		size		1
3863		field	CDI		0x80
3864		field	IOI		0x40
3865		field	MSGI		0x20
3866		field	P_BUSFREE	0x01
3867		enum	PHASE_MASK  CDO|IOO|MSGO {
3868			P_DATAOUT	0x0,
3869			P_DATAIN	IOO,
3870			P_DATAOUT_DT	P_DATAOUT|MSGO,
3871			P_DATAIN_DT	P_DATAIN|MSGO,
3872			P_COMMAND	CDO,
3873			P_MESGOUT	CDO|MSGO,
3874			P_STATUS	CDO|IOO,
3875			P_MESGIN	CDO|IOO|MSGO
3876		}
3877	}
3878	/*
3879	 * Value to "or" into the SCBPTR[1] value to
3880	 * indicate that an entry in the QINFIFO is valid.
3881	 */
3882	QOUTFIFO_ENTRY_VALID_TAG {
3883		size		1
3884		dont_generate_debug_code
3885	}
3886	/*
3887	 * Kernel and sequencer offsets into the queue of
3888	 * incoming target mode command descriptors.  The
3889	 * queue is full when the KERNEL_TQINPOS == TQINPOS.
3890	 */
3891	KERNEL_TQINPOS {
3892		size		1
3893		count		1
3894		dont_generate_debug_code
3895	}
3896	TQINPOS {
3897		size		1
3898		count		8
3899		dont_generate_debug_code
3900	}
3901	/*
3902	 * Base address of our shared data with the kernel driver in host
3903	 * memory.  This includes the qoutfifo and target mode
3904	 * incoming command queue.
3905	 */
3906	SHARED_DATA_ADDR {
3907		size		4
3908		dont_generate_debug_code
3909	}
3910	/*
3911	 * Pointer to location in host memory for next
3912	 * position in the qoutfifo.
3913	 */
3914	QOUTFIFO_NEXT_ADDR {
3915		size		4
3916		dont_generate_debug_code
3917	}
3918	ARG_1 {
3919		size		1
3920		mask	SEND_MSG		0x80
3921		mask	SEND_SENSE		0x40
3922		mask	SEND_REJ		0x20
3923		mask	MSGOUT_PHASEMIS		0x10
3924		mask	EXIT_MSG_LOOP		0x08
3925		mask	CONT_MSG_LOOP_WRITE	0x04
3926		mask	CONT_MSG_LOOP_READ	0x03
3927		mask	CONT_MSG_LOOP_TARG	0x02
3928		alias	RETURN_1
3929		dont_generate_debug_code
3930	}
3931	ARG_2 {
3932		size		1
3933		count		1
3934		alias	RETURN_2
3935		dont_generate_debug_code
3936	}
3937
3938	/*
3939	 * Snapshot of MSG_OUT taken after each message is sent.
3940	 */
3941	LAST_MSG {
3942		size		1
3943		dont_generate_debug_code
3944	}
3945
3946	/*
3947	 * Sequences the kernel driver has okayed for us.  This allows
3948	 * the driver to do things like prevent initiator or target
3949	 * operations.
3950	 */
3951	SCSISEQ_TEMPLATE {
3952		size		1
3953		count		7
3954		field	MANUALCTL	0x40
3955		field	ENSELI		0x20
3956		field	ENRSELI		0x10
3957		field	MANUALP		0x0C
3958		field	ENAUTOATNP	0x02
3959		field	ALTSTIM		0x01
3960		dont_generate_debug_code
3961	}
3962
3963	/*
3964	 * The initiator specified tag for this target mode transaction.
3965	 */
3966	INITIATOR_TAG {
3967		size		1
3968		count		1
3969		dont_generate_debug_code
3970	}
3971
3972	SEQ_FLAGS2 {
3973		size		1
3974		field	PENDING_MK_MESSAGE	0x01
3975		field	TARGET_MSG_PENDING	0x02
3976		field	SELECTOUT_QFROZEN	0x04
3977	}
3978
3979	ALLOCFIFO_SCBPTR {
3980		size		2
3981		dont_generate_debug_code
3982	}
3983
3984	/*
3985	 * The maximum amount of time to wait, when interrupt coalescing
3986	 * is enabled, before issuing a CMDCMPLT interrupt for a completed
3987	 * command.
3988	 */
3989	INT_COALESCING_TIMER {
3990		size		2
3991		dont_generate_debug_code
3992	}
3993
3994	/*
3995	 * The maximum number of commands to coalesce into a single interrupt.
3996	 * Actually the 2's complement of that value to simplify sequencer
3997	 * code.
3998	 */
3999	INT_COALESCING_MAXCMDS {
4000		size		1
4001		dont_generate_debug_code
4002	}
4003
4004	/*
4005	 * The minimum number of commands still outstanding required
4006	 * to continue coalescing (2's complement of value).
4007	 */
4008	INT_COALESCING_MINCMDS {
4009		size		1
4010		dont_generate_debug_code
4011	}
4012
4013	/*
4014	 * Number of commands "in-flight".
4015	 */
4016	CMDS_PENDING {
4017		size		2
4018		dont_generate_debug_code
4019	}
4020
4021	/*
4022	 * The count of commands that have been coalesced.
4023	 */
4024	INT_COALESCING_CMDCOUNT {
4025		size		1
4026		dont_generate_debug_code
4027	}
4028
4029	/*
4030	 * Since the HS_MAIBOX is self clearing, copy its contents to
4031	 * this position in scratch ram every time it changes.
4032	 */
4033	LOCAL_HS_MAILBOX {
4034		size		1
4035		dont_generate_debug_code
4036	}
4037	/*
4038	 * Target-mode CDB type to CDB length table used
4039	 * in non-packetized operation.
4040	 */
4041	CMDSIZE_TABLE {
4042		size		8
4043		count		8
4044		dont_generate_debug_code
4045	}
4046	/*
4047	 * When an SCB with the MK_MESSAGE flag is
4048	 * queued to the controller, it cannot enter
4049	 * the waiting for selection list until the
4050	 * selections for any previously queued
4051	 * commands to that target complete.  During
4052	 * the wait, the MK_MESSAGE SCB is queued
4053	 * here.
4054	 */
4055	MK_MESSAGE_SCB {
4056		size		2
4057	}
4058	/*
4059	 * Saved SCSIID of MK_MESSAGE_SCB to avoid
4060	 * an extra SCBPTR operation when deciding
4061	 * if the MK_MESSAGE_SCB can be run.
4062	 */
4063	MK_MESSAGE_SCSIID {
4064		size		1
4065	}
4066}
4067
4068/************************* Hardware SCB Definition ****************************/
4069scb {
4070	address			0x180
4071	size		64
4072	modes		0, 1, 2, 3
4073	SCB_RESIDUAL_DATACNT {
4074		size	4
4075		alias	SCB_CDB_STORE
4076		alias	SCB_HOST_CDB_PTR
4077		dont_generate_debug_code
4078	}
4079	SCB_RESIDUAL_SGPTR {
4080		size	4
4081		field	SG_ADDR_MASK		0xf8	/* In the last byte */
4082		field	SG_OVERRUN_RESID	0x02	/* In the first byte */
4083		field	SG_LIST_NULL		0x01	/* In the first byte */
4084		dont_generate_debug_code
4085	}
4086	SCB_SCSI_STATUS {
4087		size	1
4088		alias	SCB_HOST_CDB_LEN
4089		dont_generate_debug_code
4090	}
4091	SCB_TARGET_PHASES {
4092		size	1
4093		dont_generate_debug_code
4094	}
4095	SCB_TARGET_DATA_DIR {
4096		size	1
4097		dont_generate_debug_code
4098	}
4099	SCB_TARGET_ITAG {
4100		size	1
4101		dont_generate_debug_code
4102	}
4103	SCB_SENSE_BUSADDR {
4104		/*
4105		 * Only valid if CDB length is less than 13 bytes or
4106		 * we are using a CDB pointer.  Otherwise contains
4107		 * the last 4 bytes of embedded cdb information.
4108		 */
4109		size	4
4110		alias	SCB_NEXT_COMPLETE
4111		dont_generate_debug_code
4112	}
4113	SCB_TAG {
4114		alias	SCB_FIFO_USE_COUNT
4115		size	2
4116		dont_generate_debug_code
4117	}
4118	SCB_CONTROL {
4119		size	1
4120		field	TARGET_SCB	0x80
4121		field	DISCENB		0x40
4122		field	TAG_ENB		0x20
4123		field	MK_MESSAGE	0x10
4124		field	STATUS_RCVD	0x08
4125		field	DISCONNECTED	0x04
4126		field	SCB_TAG_TYPE	0x03
4127	}
4128	SCB_SCSIID {
4129		size	1
4130		field	TID	0xF0
4131		field	OID	0x0F
4132	}
4133	SCB_LUN {
4134		size	1
4135		field	LID	0xff
4136		dont_generate_debug_code
4137	}
4138	SCB_TASK_ATTRIBUTE {
4139		size	1
4140		/*
4141		 * Overloaded field for non-packetized 
4142		 * ignore wide residue message handling.
4143		 */
4144		field	SCB_XFERLEN_ODD	0x01
4145		dont_generate_debug_code
4146	}
4147	SCB_CDB_LEN {
4148		size	1
4149		field	SCB_CDB_LEN_PTR	0x80	/* CDB in host memory */
4150		dont_generate_debug_code
4151	}
4152	SCB_TASK_MANAGEMENT {
4153		size	1
4154		dont_generate_debug_code
4155	}
4156	SCB_DATAPTR {
4157		size	8
4158		dont_generate_debug_code
4159	}
4160	SCB_DATACNT {
4161		/*
4162		 * The last byte is really the high address bits for
4163		 * the data address.
4164		 */
4165		size	4
4166		field	SG_LAST_SEG		0x80	/* In the fourth byte */
4167		field	SG_HIGH_ADDR_BITS	0x7F	/* In the fourth byte */
4168		dont_generate_debug_code
4169	}
4170	SCB_SGPTR {
4171		size	4
4172		field	SG_STATUS_VALID	0x04	/* In the first byte */
4173		field	SG_FULL_RESID	0x02	/* In the first byte */
4174		field	SG_LIST_NULL	0x01	/* In the first byte */
4175		dont_generate_debug_code
4176	}
4177	SCB_BUSADDR {
4178		size	4
4179		dont_generate_debug_code
4180	}
4181	SCB_NEXT {
4182		alias	SCB_NEXT_SCB_BUSADDR
4183		size	2
4184		dont_generate_debug_code
4185	}
4186	SCB_NEXT2 {
4187		size	2
4188		dont_generate_debug_code
4189	}
4190	SCB_SPARE {
4191		size	8
4192		alias	SCB_PKT_LUN
4193	}
4194	SCB_DISCONNECTED_LISTS {
4195		size	8
4196		dont_generate_debug_code
4197	}
4198}
4199
4200/*********************************** Constants ********************************/
4201const MK_MESSAGE_BIT_OFFSET	4
4202const TID_SHIFT		4
4203const TARGET_CMD_CMPLT	0xfe
4204const INVALID_ADDR	0x80
4205#define SCB_LIST_NULL	0xff
4206#define QOUTFIFO_ENTRY_VALID_TOGGLE	0x80
4207
4208const CCSGADDR_MAX	0x80
4209const CCSCBADDR_MAX	0x80
4210const CCSGRAM_MAXSEGS	16
4211
4212/* Selection Timeout Timer Constants */
4213const STIMESEL_SHIFT	3
4214const STIMESEL_MIN	0x18
4215const STIMESEL_BUG_ADJ	0x8
4216
4217/* WDTR Message values */
4218const BUS_8_BIT			0x00
4219const BUS_16_BIT		0x01
4220const BUS_32_BIT		0x02
4221
4222/* Offset maximums */
4223const MAX_OFFSET		0xfe
4224const MAX_OFFSET_PACED		0xfe
4225const MAX_OFFSET_PACED_BUG	0x7f
4226/*
4227 * Some 160 devices incorrectly accept 0xfe as a
4228 * sync offset, but will overrun this value.  Limit
4229 * to 0x7f for speed lower than U320 which will
4230 * avoid the persistent sync offset overruns.
4231 */
4232const MAX_OFFSET_NON_PACED	0x7f
4233const HOST_MSG			0xff
4234
4235/*
4236 * The size of our sense buffers.
4237 * Sense buffer mapping can be handled in either of two ways.
4238 * The first is to allocate a dmamap for each transaction.
4239 * Depending on the architecture, dmamaps can be costly. The
4240 * alternative is to statically map the buffers in much the same
4241 * way we handle our scatter gather lists.  The driver implements
4242 * the later.
4243 */
4244const AHD_SENSE_BUFSIZE		256
4245
4246/* Target mode command processing constants */
4247const CMD_GROUP_CODE_SHIFT	0x05
4248
4249const STATUS_BUSY		0x08
4250const STATUS_QUEUE_FULL		0x28
4251const STATUS_PKT_SENSE		0xFF
4252const TARGET_DATA_IN		1
4253
4254const SCB_TRANSFER_SIZE_FULL_LUN	56
4255const SCB_TRANSFER_SIZE_1BYTE_LUN	48
4256/* PKT_OVERRUN_BUFSIZE must be a multiple of 256 less than 64K */
4257const PKT_OVERRUN_BUFSIZE	512
4258
4259/*
4260 * Timer parameters.
4261 */
4262const AHD_TIMER_US_PER_TICK	25
4263const AHD_TIMER_MAX_TICKS	0xFFFF
4264const AHD_TIMER_MAX_US		(AHD_TIMER_MAX_TICKS * AHD_TIMER_US_PER_TICK)
4265
4266/*
4267 * Downloaded (kernel inserted) constants
4268 */
4269const SG_PREFETCH_CNT download
4270const SG_PREFETCH_CNT_LIMIT download
4271const SG_PREFETCH_ALIGN_MASK download
4272const SG_PREFETCH_ADDR_MASK download
4273const SG_SIZEOF download
4274const PKT_OVERRUN_BUFOFFSET download
4275const SCB_TRANSFER_SIZE	download
4276const CACHELINE_MASK download
4277
4278/*
4279 * BIOS SCB offsets
4280 */
4281const NVRAM_SCB_OFFSET	0x2C