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aacraid.h
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linux-6.19.14/drivers/scsi/aacraid/aacraid.h
1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * Adaptec AAC series RAID controller driver 4 * (c) Copyright 2001 Red Hat Inc. <alan@redhat.com> 5 * 6 * based on the old aacraid driver that is.. 7 * Adaptec aacraid device driver for Linux. 8 * 9 * Copyright (c) 2000-2010 Adaptec, Inc. 10 * 2010-2015 PMC-Sierra, Inc. (aacraid@pmc-sierra.com) 11 * 2016-2017 Microsemi Corp. (aacraid@microsemi.com) 12 * 13 * Module Name: 14 * aacraid.h 15 * 16 * Abstract: Contains all routines for control of the aacraid driver 17 */ 18 19#ifndef _AACRAID_H_ 20#define _AACRAID_H_ 21#ifndef dprintk 22# define dprintk(x) 23#endif 24/* eg: if (nblank(dprintk(x))) */ 25#define _nblank(x) #x 26#define nblank(x) _nblank(x)[0] 27 28#include <linux/interrupt.h> 29#include <linux/completion.h> 30#include <linux/pci.h> 31#include <scsi/scsi_host.h> 32#include <scsi/scsi_cmnd.h> 33 34/*------------------------------------------------------------------------------ 35 * D E F I N E S 36 *----------------------------------------------------------------------------*/ 37 38#define AAC_MAX_MSIX 32 /* vectors */ 39#define AAC_PCI_MSI_ENABLE 0x8000 40 41enum { 42 AAC_ENABLE_INTERRUPT = 0x0, 43 AAC_DISABLE_INTERRUPT, 44 AAC_ENABLE_MSIX, 45 AAC_DISABLE_MSIX, 46 AAC_CLEAR_AIF_BIT, 47 AAC_CLEAR_SYNC_BIT, 48 AAC_ENABLE_INTX 49}; 50 51#define AAC_INT_MODE_INTX (1<<0) 52#define AAC_INT_MODE_MSI (1<<1) 53#define AAC_INT_MODE_AIF (1<<2) 54#define AAC_INT_MODE_SYNC (1<<3) 55#define AAC_INT_MODE_MSIX (1<<16) 56 57#define AAC_INT_ENABLE_TYPE1_INTX 0xfffffffb 58#define AAC_INT_ENABLE_TYPE1_MSIX 0xfffffffa 59#define AAC_INT_DISABLE_ALL 0xffffffff 60 61/* Bit definitions in IOA->Host Interrupt Register */ 62#define PMC_TRANSITION_TO_OPERATIONAL (1<<31) 63#define PMC_IOARCB_TRANSFER_FAILED (1<<28) 64#define PMC_IOA_UNIT_CHECK (1<<27) 65#define PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE (1<<26) 66#define PMC_CRITICAL_IOA_OP_IN_PROGRESS (1<<25) 67#define PMC_IOARRIN_LOST (1<<4) 68#define PMC_SYSTEM_BUS_MMIO_ERROR (1<<3) 69#define PMC_IOA_PROCESSOR_IN_ERROR_STATE (1<<2) 70#define PMC_HOST_RRQ_VALID (1<<1) 71#define PMC_OPERATIONAL_STATUS (1<<31) 72#define PMC_ALLOW_MSIX_VECTOR0 (1<<0) 73 74#define PMC_IOA_ERROR_INTERRUPTS (PMC_IOARCB_TRANSFER_FAILED | \ 75 PMC_IOA_UNIT_CHECK | \ 76 PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE | \ 77 PMC_IOARRIN_LOST | \ 78 PMC_SYSTEM_BUS_MMIO_ERROR | \ 79 PMC_IOA_PROCESSOR_IN_ERROR_STATE) 80 81#define PMC_ALL_INTERRUPT_BITS (PMC_IOA_ERROR_INTERRUPTS | \ 82 PMC_HOST_RRQ_VALID | \ 83 PMC_TRANSITION_TO_OPERATIONAL | \ 84 PMC_ALLOW_MSIX_VECTOR0) 85#define PMC_GLOBAL_INT_BIT2 0x00000004 86#define PMC_GLOBAL_INT_BIT0 0x00000001 87 88#ifndef AAC_DRIVER_BUILD 89# define AAC_DRIVER_BUILD 50983 90# define AAC_DRIVER_BRANCH "-custom" 91#endif 92#define MAXIMUM_NUM_CONTAINERS 32 93 94#define AAC_NUM_MGT_FIB 8 95#define AAC_NUM_IO_FIB (1024 - AAC_NUM_MGT_FIB) 96 97#define AAC_MAX_LUN 256 98 99#define AAC_MAX_HOSTPHYSMEMPAGES (0xfffff) 100#define AAC_MAX_32BIT_SGBCOUNT ((unsigned short)256) 101 102#define AAC_DEBUG_INSTRUMENT_AIF_DELETE 103 104#define AAC_MAX_NATIVE_TARGETS 1024 105/* Thor: 5 phys. buses: #0: empty, 1-4: 256 targets each */ 106#define AAC_MAX_BUSES 5 107#define AAC_MAX_TARGETS 256 108#define AAC_BUS_TARGET_LOOP (AAC_MAX_BUSES * AAC_MAX_TARGETS) 109#define AAC_MAX_NATIVE_SIZE 2048 110#define FW_ERROR_BUFFER_SIZE 512 111#define AAC_SA_TIMEOUT 180 112#define AAC_ARC_TIMEOUT 60 113 114#define get_bus_number(x) (x/AAC_MAX_TARGETS) 115#define get_target_number(x) (x%AAC_MAX_TARGETS) 116 117/* Thor AIF events */ 118#define SA_AIF_HOTPLUG (1<<1) 119#define SA_AIF_HARDWARE (1<<2) 120#define SA_AIF_PDEV_CHANGE (1<<4) 121#define SA_AIF_LDEV_CHANGE (1<<5) 122#define SA_AIF_BPSTAT_CHANGE (1<<30) 123#define SA_AIF_BPCFG_CHANGE (1U<<31) 124 125#define HBA_MAX_SG_EMBEDDED 28 126#define HBA_MAX_SG_SEPARATE 90 127#define HBA_SENSE_DATA_LEN_MAX 32 128#define HBA_REQUEST_TAG_ERROR_FLAG 0x00000002 129#define HBA_SGL_FLAGS_EXT 0x80000000UL 130 131struct aac_hba_sgl { 132 u32 addr_lo; /* Lower 32-bits of SGL element address */ 133 u32 addr_hi; /* Upper 32-bits of SGL element address */ 134 u32 len; /* Length of SGL element in bytes */ 135 u32 flags; /* SGL element flags */ 136}; 137 138enum { 139 HBA_IU_TYPE_SCSI_CMD_REQ = 0x40, 140 HBA_IU_TYPE_SCSI_TM_REQ = 0x41, 141 HBA_IU_TYPE_SATA_REQ = 0x42, 142 HBA_IU_TYPE_RESP = 0x60, 143 HBA_IU_TYPE_COALESCED_RESP = 0x61, 144 HBA_IU_TYPE_INT_COALESCING_CFG_REQ = 0x70 145}; 146 147enum { 148 HBA_CMD_BYTE1_DATA_DIR_IN = 0x1, 149 HBA_CMD_BYTE1_DATA_DIR_OUT = 0x2, 150 HBA_CMD_BYTE1_DATA_TYPE_DDR = 0x4, 151 HBA_CMD_BYTE1_CRYPTO_ENABLE = 0x8 152}; 153 154enum { 155 HBA_CMD_BYTE1_BITOFF_DATA_DIR_IN = 0x0, 156 HBA_CMD_BYTE1_BITOFF_DATA_DIR_OUT, 157 HBA_CMD_BYTE1_BITOFF_DATA_TYPE_DDR, 158 HBA_CMD_BYTE1_BITOFF_CRYPTO_ENABLE 159}; 160 161enum { 162 HBA_RESP_DATAPRES_NO_DATA = 0x0, 163 HBA_RESP_DATAPRES_RESPONSE_DATA, 164 HBA_RESP_DATAPRES_SENSE_DATA 165}; 166 167enum { 168 HBA_RESP_SVCRES_TASK_COMPLETE = 0x0, 169 HBA_RESP_SVCRES_FAILURE, 170 HBA_RESP_SVCRES_TMF_COMPLETE, 171 HBA_RESP_SVCRES_TMF_SUCCEEDED, 172 HBA_RESP_SVCRES_TMF_REJECTED, 173 HBA_RESP_SVCRES_TMF_LUN_INVALID 174}; 175 176enum { 177 HBA_RESP_STAT_IO_ERROR = 0x1, 178 HBA_RESP_STAT_IO_ABORTED, 179 HBA_RESP_STAT_NO_PATH_TO_DEVICE, 180 HBA_RESP_STAT_INVALID_DEVICE, 181 HBA_RESP_STAT_HBAMODE_DISABLED = 0xE, 182 HBA_RESP_STAT_UNDERRUN = 0x51, 183 HBA_RESP_STAT_OVERRUN = 0x75 184}; 185 186struct aac_hba_cmd_req { 187 u8 iu_type; /* HBA information unit type */ 188 /* 189 * byte1: 190 * [1:0] DIR - 0=No data, 0x1 = IN, 0x2 = OUT 191 * [2] TYPE - 0=PCI, 1=DDR 192 * [3] CRYPTO_ENABLE - 0=Crypto disabled, 1=Crypto enabled 193 */ 194 u8 byte1; 195 u8 reply_qid; /* Host reply queue to post response to */ 196 u8 reserved1; 197 __le32 it_nexus; /* Device handle for the request */ 198 __le32 request_id; /* Sender context */ 199 /* Lower 32-bits of tweak value for crypto enabled IOs */ 200 __le32 tweak_value_lo; 201 u8 cdb[16]; /* SCSI CDB of the command */ 202 u8 lun[8]; /* SCSI LUN of the command */ 203 204 /* Total data length in bytes to be read/written (if any) */ 205 __le32 data_length; 206 207 /* [2:0] Task Attribute, [6:3] Command Priority */ 208 u8 attr_prio; 209 210 /* Number of SGL elements embedded in the HBA req */ 211 u8 emb_data_desc_count; 212 213 __le16 dek_index; /* DEK index for crypto enabled IOs */ 214 215 /* Lower 32-bits of reserved error data target location on the host */ 216 __le32 error_ptr_lo; 217 218 /* Upper 32-bits of reserved error data target location on the host */ 219 __le32 error_ptr_hi; 220 221 /* Length of reserved error data area on the host in bytes */ 222 __le32 error_length; 223 224 /* Upper 32-bits of tweak value for crypto enabled IOs */ 225 __le32 tweak_value_hi; 226 227 struct aac_hba_sgl sge[HBA_MAX_SG_SEPARATE+2]; /* SG list space */ 228 229 /* 230 * structure must not exceed 231 * AAC_MAX_NATIVE_SIZE-FW_ERROR_BUFFER_SIZE 232 */ 233}; 234 235/* Task Management Functions (TMF) */ 236#define HBA_TMF_ABORT_TASK 0x01 237#define HBA_TMF_LUN_RESET 0x08 238 239struct aac_hba_tm_req { 240 u8 iu_type; /* HBA information unit type */ 241 u8 reply_qid; /* Host reply queue to post response to */ 242 u8 tmf; /* Task management function */ 243 u8 reserved1; 244 245 __le32 it_nexus; /* Device handle for the command */ 246 247 u8 lun[8]; /* SCSI LUN */ 248 249 /* Used to hold sender context. */ 250 __le32 request_id; /* Sender context */ 251 __le32 reserved2; 252 253 /* Request identifier of managed task */ 254 __le32 managed_request_id; /* Sender context being managed */ 255 __le32 reserved3; 256 257 /* Lower 32-bits of reserved error data target location on the host */ 258 __le32 error_ptr_lo; 259 /* Upper 32-bits of reserved error data target location on the host */ 260 __le32 error_ptr_hi; 261 /* Length of reserved error data area on the host in bytes */ 262 __le32 error_length; 263}; 264 265struct aac_hba_reset_req { 266 u8 iu_type; /* HBA information unit type */ 267 /* 0 - reset specified device, 1 - reset all devices */ 268 u8 reset_type; 269 u8 reply_qid; /* Host reply queue to post response to */ 270 u8 reserved1; 271 272 __le32 it_nexus; /* Device handle for the command */ 273 __le32 request_id; /* Sender context */ 274 /* Lower 32-bits of reserved error data target location on the host */ 275 __le32 error_ptr_lo; 276 /* Upper 32-bits of reserved error data target location on the host */ 277 __le32 error_ptr_hi; 278 /* Length of reserved error data area on the host in bytes */ 279 __le32 error_length; 280}; 281 282struct aac_hba_resp { 283 u8 iu_type; /* HBA information unit type */ 284 u8 reserved1[3]; 285 __le32 request_identifier; /* sender context */ 286 __le32 reserved2; 287 u8 service_response; /* SCSI service response */ 288 u8 status; /* SCSI status */ 289 u8 datapres; /* [1:0] - data present, [7:2] - reserved */ 290 u8 sense_response_data_len; /* Sense/response data length */ 291 __le32 residual_count; /* Residual data length in bytes */ 292 /* Sense/response data */ 293 u8 sense_response_buf[HBA_SENSE_DATA_LEN_MAX]; 294}; 295 296struct aac_native_hba { 297 union { 298 struct aac_hba_cmd_req cmd; 299 struct aac_hba_tm_req tmr; 300 u8 cmd_bytes[AAC_MAX_NATIVE_SIZE-FW_ERROR_BUFFER_SIZE]; 301 } cmd; 302 union { 303 struct aac_hba_resp err; 304 u8 resp_bytes[FW_ERROR_BUFFER_SIZE]; 305 } resp; 306}; 307 308#define CISS_REPORT_PHYSICAL_LUNS 0xc3 309#define WRITE_HOST_WELLNESS 0xa5 310#define CISS_IDENTIFY_PHYSICAL_DEVICE 0x15 311#define BMIC_IN 0x26 312#define BMIC_OUT 0x27 313 314struct aac_ciss_phys_luns_resp { 315 u8 list_length[4]; /* LUN list length (N-7, big endian) */ 316 u8 resp_flag; /* extended response_flag */ 317 u8 reserved[3]; 318 struct _ciss_lun { 319 u8 tid[3]; /* Target ID */ 320 u8 bus; /* Bus, flag (bits 6,7) */ 321 u8 level3[2]; 322 u8 level2[2]; 323 u8 node_ident[16]; /* phys. node identifier */ 324 } lun[]; /* List of phys. devices */ 325}; 326 327/* 328 * Interrupts 329 */ 330#define AAC_MAX_HRRQ 64 331 332struct aac_ciss_identify_pd { 333 u8 scsi_bus; /* SCSI Bus number on controller */ 334 u8 scsi_id; /* SCSI ID on this bus */ 335 u16 block_size; /* sector size in bytes */ 336 u32 total_blocks; /* number for sectors on drive */ 337 u32 reserved_blocks; /* controller reserved (RIS) */ 338 u8 model[40]; /* Physical Drive Model */ 339 u8 serial_number[40]; /* Drive Serial Number */ 340 u8 firmware_revision[8]; /* drive firmware revision */ 341 u8 scsi_inquiry_bits; /* inquiry byte 7 bits */ 342 u8 compaq_drive_stamp; /* 0 means drive not stamped */ 343 u8 last_failure_reason; 344 345 u8 flags; 346 u8 more_flags; 347 u8 scsi_lun; /* SCSI LUN for phys drive */ 348 u8 yet_more_flags; 349 u8 even_more_flags; 350 u32 spi_speed_rules; /* SPI Speed :Ultra disable diagnose */ 351 u8 phys_connector[2]; /* connector number on controller */ 352 u8 phys_box_on_bus; /* phys enclosure this drive resides */ 353 u8 phys_bay_in_box; /* phys drv bay this drive resides */ 354 u32 rpm; /* Drive rotational speed in rpm */ 355 u8 device_type; /* type of drive */ 356 u8 sata_version; /* only valid when drive_type is SATA */ 357 u64 big_total_block_count; 358 u64 ris_starting_lba; 359 u32 ris_size; 360 u8 wwid[20]; 361 u8 controller_phy_map[32]; 362 u16 phy_count; 363 u8 phy_connected_dev_type[256]; 364 u8 phy_to_drive_bay_num[256]; 365 u16 phy_to_attached_dev_index[256]; 366 u8 box_index; 367 u8 spitfire_support; 368 u16 extra_physical_drive_flags; 369 u8 negotiated_link_rate[256]; 370 u8 phy_to_phy_map[256]; 371 u8 redundant_path_present_map; 372 u8 redundant_path_failure_map; 373 u8 active_path_number; 374 u16 alternate_paths_phys_connector[8]; 375 u8 alternate_paths_phys_box_on_port[8]; 376 u8 multi_lun_device_lun_count; 377 u8 minimum_good_fw_revision[8]; 378 u8 unique_inquiry_bytes[20]; 379 u8 current_temperature_degreesC; 380 u8 temperature_threshold_degreesC; 381 u8 max_temperature_degreesC; 382 u8 logical_blocks_per_phys_block_exp; /* phyblocksize = 512 * 2^exp */ 383 u16 current_queue_depth_limit; 384 u8 switch_name[10]; 385 u16 switch_port; 386 u8 alternate_paths_switch_name[40]; 387 u8 alternate_paths_switch_port[8]; 388 u16 power_on_hours; /* valid only if gas gauge supported */ 389 u16 percent_endurance_used; /* valid only if gas gauge supported. */ 390 u8 drive_authentication; 391 u8 smart_carrier_authentication; 392 u8 smart_carrier_app_fw_version; 393 u8 smart_carrier_bootloader_fw_version; 394 u8 SanitizeSecureEraseSupport; 395 u8 DriveKeyFlags; 396 u8 encryption_key_name[64]; 397 u32 misc_drive_flags; 398 u16 dek_index; 399 u16 drive_encryption_flags; 400 u8 sanitize_maximum_time[6]; 401 u8 connector_info_mode; 402 u8 connector_info_number[4]; 403 u8 long_connector_name[64]; 404 u8 device_unique_identifier[16]; 405 u8 padto_2K[17]; 406} __packed; 407 408/* 409 * These macros convert from physical channels to virtual channels 410 */ 411#define CONTAINER_CHANNEL (0) 412#define NATIVE_CHANNEL (1) 413#define CONTAINER_TO_CHANNEL(cont) (CONTAINER_CHANNEL) 414#define CONTAINER_TO_ID(cont) (cont) 415#define CONTAINER_TO_LUN(cont) (0) 416#define ENCLOSURE_CHANNEL (3) 417 418#define PMC_DEVICE_S6 0x28b 419#define PMC_DEVICE_S7 0x28c 420#define PMC_DEVICE_S8 0x28d 421 422#define aac_phys_to_logical(x) ((x)+1) 423#define aac_logical_to_phys(x) ((x)?(x)-1:0) 424 425/* 426 * These macros are for keeping track of 427 * character device state. 428 */ 429#define AAC_CHARDEV_UNREGISTERED (-1) 430#define AAC_CHARDEV_NEEDS_REINIT (-2) 431 432/* #define AAC_DETAILED_STATUS_INFO */ 433 434struct diskparm 435{ 436 int heads; 437 int sectors; 438 int cylinders; 439}; 440 441 442/* 443 * Firmware constants 444 */ 445 446#define CT_NONE 0 447#define CT_OK 218 448#define FT_FILESYS 8 /* ADAPTEC's "FSA"(tm) filesystem */ 449#define FT_DRIVE 9 /* physical disk - addressable in scsi by bus/id/lun */ 450 451/* 452 * Host side memory scatter gather list 453 * Used by the adapter for read, write, and readdirplus operations 454 * We have separate 32 and 64 bit version because even 455 * on 64 bit systems not all cards support the 64 bit version 456 */ 457struct sgentry { 458 __le32 addr; /* 32-bit address. */ 459 __le32 count; /* Length. */ 460}; 461 462struct user_sgentry { 463 u32 addr; /* 32-bit address. */ 464 u32 count; /* Length. */ 465}; 466 467struct sgentry64 { 468 __le32 addr[2]; /* 64-bit addr. 2 pieces for data alignment */ 469 __le32 count; /* Length. */ 470}; 471 472struct user_sgentry64 { 473 u32 addr[2]; /* 64-bit addr. 2 pieces for data alignment */ 474 u32 count; /* Length. */ 475}; 476 477struct sgentryraw { 478 __le32 next; /* reserved for F/W use */ 479 __le32 prev; /* reserved for F/W use */ 480 __le32 addr[2]; 481 __le32 count; 482 __le32 flags; /* reserved for F/W use */ 483}; 484 485struct user_sgentryraw { 486 u32 next; /* reserved for F/W use */ 487 u32 prev; /* reserved for F/W use */ 488 u32 addr[2]; 489 u32 count; 490 u32 flags; /* reserved for F/W use */ 491}; 492 493struct sge_ieee1212 { 494 u32 addrLow; 495 u32 addrHigh; 496 u32 length; 497 u32 flags; 498}; 499 500/* 501 * SGMAP 502 * 503 * This is the SGMAP structure for all commands that use 504 * 32-bit addressing. 505 */ 506 507struct sgmap { 508 __le32 count; 509 struct sgentry sg[]; 510}; 511 512struct user_sgmap { 513 u32 count; 514 struct user_sgentry sg[]; 515}; 516 517struct sgmap64 { 518 __le32 count; 519 struct sgentry64 sg[]; 520}; 521 522struct user_sgmap64 { 523 u32 count; 524 struct user_sgentry64 sg[]; 525}; 526 527struct sgmapraw { 528 __le32 count; 529 struct sgentryraw sg[]; 530}; 531 532struct creation_info 533{ 534 u8 buildnum; /* e.g., 588 */ 535 u8 usec; /* e.g., 588 */ 536 u8 via; /* e.g., 1 = FSU, 537 * 2 = API 538 */ 539 u8 year; /* e.g., 1997 = 97 */ 540 __le32 date; /* 541 * unsigned Month :4; // 1 - 12 542 * unsigned Day :6; // 1 - 32 543 * unsigned Hour :6; // 0 - 23 544 * unsigned Minute :6; // 0 - 60 545 * unsigned Second :6; // 0 - 60 546 */ 547 __le32 serial[2]; /* e.g., 0x1DEADB0BFAFAF001 */ 548}; 549 550 551/* 552 * Define all the constants needed for the communication interface 553 */ 554 555/* 556 * Define how many queue entries each queue will have and the total 557 * number of entries for the entire communication interface. Also define 558 * how many queues we support. 559 * 560 * This has to match the controller 561 */ 562 563#define NUMBER_OF_COMM_QUEUES 8 // 4 command; 4 response 564#define HOST_HIGH_CMD_ENTRIES 4 565#define HOST_NORM_CMD_ENTRIES 8 566#define ADAP_HIGH_CMD_ENTRIES 4 567#define ADAP_NORM_CMD_ENTRIES 512 568#define HOST_HIGH_RESP_ENTRIES 4 569#define HOST_NORM_RESP_ENTRIES 512 570#define ADAP_HIGH_RESP_ENTRIES 4 571#define ADAP_NORM_RESP_ENTRIES 8 572 573#define TOTAL_QUEUE_ENTRIES \ 574 (HOST_NORM_CMD_ENTRIES + HOST_HIGH_CMD_ENTRIES + ADAP_NORM_CMD_ENTRIES + ADAP_HIGH_CMD_ENTRIES + \ 575 HOST_NORM_RESP_ENTRIES + HOST_HIGH_RESP_ENTRIES + ADAP_NORM_RESP_ENTRIES + ADAP_HIGH_RESP_ENTRIES) 576 577 578/* 579 * Set the queues on a 16 byte alignment 580 */ 581 582#define QUEUE_ALIGNMENT 16 583 584/* 585 * The queue headers define the Communication Region queues. These 586 * are physically contiguous and accessible by both the adapter and the 587 * host. Even though all queue headers are in the same contiguous block 588 * they will be represented as individual units in the data structures. 589 */ 590 591struct aac_entry { 592 __le32 size; /* Size in bytes of Fib which this QE points to */ 593 __le32 addr; /* Receiver address of the FIB */ 594}; 595 596/* 597 * The adapter assumes the ProducerIndex and ConsumerIndex are grouped 598 * adjacently and in that order. 599 */ 600 601struct aac_qhdr { 602 __le64 header_addr;/* Address to hand the adapter to access 603 to this queue head */ 604 __le32 *producer; /* The producer index for this queue (host address) */ 605 __le32 *consumer; /* The consumer index for this queue (host address) */ 606}; 607 608/* 609 * Define all the events which the adapter would like to notify 610 * the host of. 611 */ 612 613#define HostNormCmdQue 1 /* Change in host normal priority command queue */ 614#define HostHighCmdQue 2 /* Change in host high priority command queue */ 615#define HostNormRespQue 3 /* Change in host normal priority response queue */ 616#define HostHighRespQue 4 /* Change in host high priority response queue */ 617#define AdapNormRespNotFull 5 618#define AdapHighRespNotFull 6 619#define AdapNormCmdNotFull 7 620#define AdapHighCmdNotFull 8 621#define SynchCommandComplete 9 622#define AdapInternalError 0xfe /* The adapter detected an internal error shutting down */ 623 624/* 625 * Define all the events the host wishes to notify the 626 * adapter of. The first four values much match the Qid the 627 * corresponding queue. 628 */ 629 630#define AdapNormCmdQue 2 631#define AdapHighCmdQue 3 632#define AdapNormRespQue 6 633#define AdapHighRespQue 7 634#define HostShutdown 8 635#define HostPowerFail 9 636#define FatalCommError 10 637#define HostNormRespNotFull 11 638#define HostHighRespNotFull 12 639#define HostNormCmdNotFull 13 640#define HostHighCmdNotFull 14 641#define FastIo 15 642#define AdapPrintfDone 16 643 644/* 645 * Define all the queues that the adapter and host use to communicate 646 * Number them to match the physical queue layout. 647 */ 648 649enum aac_queue_types { 650 HostNormCmdQueue = 0, /* Adapter to host normal priority command traffic */ 651 HostHighCmdQueue, /* Adapter to host high priority command traffic */ 652 AdapNormCmdQueue, /* Host to adapter normal priority command traffic */ 653 AdapHighCmdQueue, /* Host to adapter high priority command traffic */ 654 HostNormRespQueue, /* Adapter to host normal priority response traffic */ 655 HostHighRespQueue, /* Adapter to host high priority response traffic */ 656 AdapNormRespQueue, /* Host to adapter normal priority response traffic */ 657 AdapHighRespQueue /* Host to adapter high priority response traffic */ 658}; 659 660/* 661 * Assign type values to the FSA communication data structures 662 */ 663 664#define FIB_MAGIC 0x0001 665#define FIB_MAGIC2 0x0004 666#define FIB_MAGIC2_64 0x0005 667 668/* 669 * Define the priority levels the FSA communication routines support. 670 */ 671 672#define FsaNormal 1 673 674/* transport FIB header (PMC) */ 675struct aac_fib_xporthdr { 676 __le64 HostAddress; /* FIB host address w/o xport header */ 677 __le32 Size; /* FIB size excluding xport header */ 678 __le32 Handle; /* driver handle to reference the FIB */ 679 __le64 Reserved[2]; 680}; 681 682#define ALIGN32 32 683 684/* 685 * Define the FIB. The FIB is the where all the requested data and 686 * command information are put to the application on the FSA adapter. 687 */ 688 689struct aac_fibhdr { 690 __le32 XferState; /* Current transfer state for this CCB */ 691 __le16 Command; /* Routing information for the destination */ 692 u8 StructType; /* Type FIB */ 693 u8 Unused; /* Unused */ 694 __le16 Size; /* Size of this FIB in bytes */ 695 __le16 SenderSize; /* Size of the FIB in the sender 696 (for response sizing) */ 697 __le32 SenderFibAddress; /* Host defined data in the FIB */ 698 union { 699 __le32 ReceiverFibAddress;/* Logical address of this FIB for 700 the adapter (old) */ 701 __le32 SenderFibAddressHigh;/* upper 32bit of phys. FIB address */ 702 __le32 TimeStamp; /* otherwise timestamp for FW internal use */ 703 } u; 704 __le32 Handle; /* FIB handle used for MSGU commnunication */ 705 u32 Previous; /* FW internal use */ 706 u32 Next; /* FW internal use */ 707}; 708 709struct hw_fib { 710 struct aac_fibhdr header; 711 u8 data[512-sizeof(struct aac_fibhdr)]; // Command specific data 712}; 713 714/* 715 * FIB commands 716 */ 717 718#define TestCommandResponse 1 719#define TestAdapterCommand 2 720/* 721 * Lowlevel and comm commands 722 */ 723#define LastTestCommand 100 724#define ReinitHostNormCommandQueue 101 725#define ReinitHostHighCommandQueue 102 726#define ReinitHostHighRespQueue 103 727#define ReinitHostNormRespQueue 104 728#define ReinitAdapNormCommandQueue 105 729#define ReinitAdapHighCommandQueue 107 730#define ReinitAdapHighRespQueue 108 731#define ReinitAdapNormRespQueue 109 732#define InterfaceShutdown 110 733#define DmaCommandFib 120 734#define StartProfile 121 735#define TermProfile 122 736#define SpeedTest 123 737#define TakeABreakPt 124 738#define RequestPerfData 125 739#define SetInterruptDefTimer 126 740#define SetInterruptDefCount 127 741#define GetInterruptDefStatus 128 742#define LastCommCommand 129 743/* 744 * Filesystem commands 745 */ 746#define NuFileSystem 300 747#define UFS 301 748#define HostFileSystem 302 749#define LastFileSystemCommand 303 750/* 751 * Container Commands 752 */ 753#define ContainerCommand 500 754#define ContainerCommand64 501 755#define ContainerRawIo 502 756#define ContainerRawIo2 503 757/* 758 * Scsi Port commands (scsi passthrough) 759 */ 760#define ScsiPortCommand 600 761#define ScsiPortCommand64 601 762/* 763 * Misc house keeping and generic adapter initiated commands 764 */ 765#define AifRequest 700 766#define CheckRevision 701 767#define FsaHostShutdown 702 768#define RequestAdapterInfo 703 769#define IsAdapterPaused 704 770#define SendHostTime 705 771#define RequestSupplementAdapterInfo 706 772#define LastMiscCommand 707 773 774/* 775 * Commands that will target the failover level on the FSA adapter 776 */ 777 778enum fib_xfer_state { 779 HostOwned = (1<<0), 780 AdapterOwned = (1<<1), 781 FibInitialized = (1<<2), 782 FibEmpty = (1<<3), 783 AllocatedFromPool = (1<<4), 784 SentFromHost = (1<<5), 785 SentFromAdapter = (1<<6), 786 ResponseExpected = (1<<7), 787 NoResponseExpected = (1<<8), 788 AdapterProcessed = (1<<9), 789 HostProcessed = (1<<10), 790 HighPriority = (1<<11), 791 NormalPriority = (1<<12), 792 Async = (1<<13), 793 AsyncIo = (1<<13), // rpbfix: remove with new regime 794 PageFileIo = (1<<14), // rpbfix: remove with new regime 795 ShutdownRequest = (1<<15), 796 LazyWrite = (1<<16), // rpbfix: remove with new regime 797 AdapterMicroFib = (1<<17), 798 BIOSFibPath = (1<<18), 799 FastResponseCapable = (1<<19), 800 ApiFib = (1<<20), /* Its an API Fib */ 801 /* PMC NEW COMM: There is no more AIF data pending */ 802 NoMoreAifDataAvailable = (1<<21) 803}; 804 805/* 806 * The following defines needs to be updated any time there is an 807 * incompatible change made to the aac_init structure. 808 */ 809 810#define ADAPTER_INIT_STRUCT_REVISION 3 811#define ADAPTER_INIT_STRUCT_REVISION_4 4 // rocket science 812#define ADAPTER_INIT_STRUCT_REVISION_6 6 /* PMC src */ 813#define ADAPTER_INIT_STRUCT_REVISION_7 7 /* Denali */ 814#define ADAPTER_INIT_STRUCT_REVISION_8 8 // Thor 815 816union aac_init 817{ 818 struct _r7 { 819 __le32 init_struct_revision; 820 __le32 no_of_msix_vectors; 821 __le32 fsrev; 822 __le32 comm_header_address; 823 __le32 fast_io_comm_area_address; 824 __le32 adapter_fibs_physical_address; 825 __le32 adapter_fibs_virtual_address; 826 __le32 adapter_fibs_size; 827 __le32 adapter_fib_align; 828 __le32 printfbuf; 829 __le32 printfbufsiz; 830 /* number of 4k pages of host phys. mem. */ 831 __le32 host_phys_mem_pages; 832 /* number of seconds since 1970. */ 833 __le32 host_elapsed_seconds; 834 /* ADAPTER_INIT_STRUCT_REVISION_4 begins here */ 835 __le32 init_flags; /* flags for supported features */ 836#define INITFLAGS_NEW_COMM_SUPPORTED 0x00000001 837#define INITFLAGS_DRIVER_USES_UTC_TIME 0x00000010 838#define INITFLAGS_DRIVER_SUPPORTS_PM 0x00000020 839#define INITFLAGS_NEW_COMM_TYPE1_SUPPORTED 0x00000040 840#define INITFLAGS_FAST_JBOD_SUPPORTED 0x00000080 841#define INITFLAGS_NEW_COMM_TYPE2_SUPPORTED 0x00000100 842#define INITFLAGS_DRIVER_SUPPORTS_HBA_MODE 0x00000400 843 __le32 max_io_commands; /* max outstanding commands */ 844 __le32 max_io_size; /* largest I/O command */ 845 __le32 max_fib_size; /* largest FIB to adapter */ 846 /* ADAPTER_INIT_STRUCT_REVISION_5 begins here */ 847 __le32 max_num_aif; /* max number of aif */ 848 /* ADAPTER_INIT_STRUCT_REVISION_6 begins here */ 849 /* Host RRQ (response queue) for SRC */ 850 __le32 host_rrq_addr_low; 851 __le32 host_rrq_addr_high; 852 } r7; 853 struct _r8 { 854 /* ADAPTER_INIT_STRUCT_REVISION_8 */ 855 __le32 init_struct_revision; 856 __le32 rr_queue_count; 857 __le32 host_elapsed_seconds; /* number of secs since 1970. */ 858 __le32 init_flags; 859 __le32 max_io_size; /* largest I/O command */ 860 __le32 max_num_aif; /* max number of aif */ 861 __le32 reserved1; 862 __le32 reserved2; 863 struct _rrq { 864 __le32 host_addr_low; 865 __le32 host_addr_high; 866 __le16 msix_id; 867 __le16 element_count; 868 __le16 comp_thresh; 869 __le16 unused; 870 } rrq[] __counted_by_le(rr_queue_count); /* up to 64 RRQ addresses */ 871 } r8; 872}; 873 874enum aac_log_level { 875 LOG_AAC_INIT = 10, 876 LOG_AAC_INFORMATIONAL = 20, 877 LOG_AAC_WARNING = 30, 878 LOG_AAC_LOW_ERROR = 40, 879 LOG_AAC_MEDIUM_ERROR = 50, 880 LOG_AAC_HIGH_ERROR = 60, 881 LOG_AAC_PANIC = 70, 882 LOG_AAC_DEBUG = 80, 883 LOG_AAC_WINDBG_PRINT = 90 884}; 885 886#define FSAFS_NTC_GET_ADAPTER_FIB_CONTEXT 0x030b 887#define FSAFS_NTC_FIB_CONTEXT 0x030c 888 889struct aac_dev; 890struct fib; 891struct scsi_cmnd; 892 893struct adapter_ops 894{ 895 /* Low level operations */ 896 void (*adapter_interrupt)(struct aac_dev *dev); 897 void (*adapter_notify)(struct aac_dev *dev, u32 event); 898 void (*adapter_disable_int)(struct aac_dev *dev); 899 void (*adapter_enable_int)(struct aac_dev *dev); 900 int (*adapter_sync_cmd)(struct aac_dev *dev, u32 command, u32 p1, u32 p2, u32 p3, u32 p4, u32 p5, u32 p6, u32 *status, u32 *r1, u32 *r2, u32 *r3, u32 *r4); 901 int (*adapter_check_health)(struct aac_dev *dev); 902 int (*adapter_restart)(struct aac_dev *dev, int bled, u8 reset_type); 903 void (*adapter_start)(struct aac_dev *dev); 904 /* Transport operations */ 905 int (*adapter_ioremap)(struct aac_dev * dev, u32 size); 906 irq_handler_t adapter_intr; 907 /* Packet operations */ 908 int (*adapter_deliver)(struct fib * fib); 909 int (*adapter_bounds)(struct aac_dev * dev, struct scsi_cmnd * cmd, u64 lba); 910 int (*adapter_read)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count); 911 int (*adapter_write)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count, int fua); 912 int (*adapter_scsi)(struct fib * fib, struct scsi_cmnd * cmd); 913 /* Administrative operations */ 914 int (*adapter_comm)(struct aac_dev * dev, int comm); 915}; 916 917/* 918 * Define which interrupt handler needs to be installed 919 */ 920 921struct aac_driver_ident 922{ 923 int (*init)(struct aac_dev *dev); 924 char * name; 925 char * vname; 926 char * model; 927 u16 channels; 928 int quirks; 929}; 930/* 931 * Some adapter firmware needs communication memory 932 * below 2gig. This tells the init function to set the 933 * dma mask such that fib memory will be allocated where the 934 * adapter firmware can get to it. 935 */ 936#define AAC_QUIRK_31BIT 0x0001 937 938/* 939 * Some adapter firmware, when the raid card's cache is turned off, can not 940 * split up scatter gathers in order to deal with the limits of the 941 * underlying CHIM. This limit is 34 scatter gather elements. 942 */ 943#define AAC_QUIRK_34SG 0x0002 944 945/* 946 * This adapter is a slave (no Firmware) 947 */ 948#define AAC_QUIRK_SLAVE 0x0004 949 950/* 951 * This adapter is a master. 952 */ 953#define AAC_QUIRK_MASTER 0x0008 954 955/* 956 * Some adapter firmware perform poorly when it must split up scatter gathers 957 * in order to deal with the limits of the underlying CHIM. This limit in this 958 * class of adapters is 17 scatter gather elements. 959 */ 960#define AAC_QUIRK_17SG 0x0010 961 962/* 963 * Some adapter firmware does not support 64 bit scsi passthrough 964 * commands. 965 */ 966#define AAC_QUIRK_SCSI_32 0x0020 967 968/* 969 * SRC based adapters support the AifReqEvent functions 970 */ 971#define AAC_QUIRK_SRC 0x0040 972 973/* 974 * The adapter interface specs all queues to be located in the same 975 * physically contiguous block. The host structure that defines the 976 * commuication queues will assume they are each a separate physically 977 * contiguous memory region that will support them all being one big 978 * contiguous block. 979 * There is a command and response queue for each level and direction of 980 * commuication. These regions are accessed by both the host and adapter. 981 */ 982 983struct aac_queue { 984 u64 logical; /*address we give the adapter */ 985 struct aac_entry *base; /*system virtual address */ 986 struct aac_qhdr headers; /*producer,consumer q headers*/ 987 u32 entries; /*Number of queue entries */ 988 wait_queue_head_t qfull; /*Event to wait on if q full */ 989 wait_queue_head_t cmdready; /*Cmd ready from the adapter */ 990 /* This is only valid for adapter to host command queues. */ 991 spinlock_t *lock; /* Spinlock for this queue must take this lock before accessing the lock */ 992 spinlock_t lockdata; /* Actual lock (used only on one side of the lock) */ 993 struct list_head cmdq; /* A queue of FIBs which need to be prcessed by the FS thread. This is */ 994 /* only valid for command queues which receive entries from the adapter. */ 995 /* Number of entries on outstanding queue. */ 996 atomic_t numpending; 997 struct aac_dev * dev; /* Back pointer to adapter structure */ 998}; 999 1000/* 1001 * Message queues. The order here is important, see also the 1002 * queue type ordering 1003 */ 1004 1005struct aac_queue_block 1006{ 1007 struct aac_queue queue[8]; 1008}; 1009 1010/* 1011 * SaP1 Message Unit Registers 1012 */ 1013 1014struct sa_drawbridge_CSR { 1015 /* Offset | Name */ 1016 __le32 reserved[10]; /* 00h-27h | Reserved */ 1017 u8 LUT_Offset; /* 28h | Lookup Table Offset */ 1018 u8 reserved1[3]; /* 29h-2bh | Reserved */ 1019 __le32 LUT_Data; /* 2ch | Looup Table Data */ 1020 __le32 reserved2[26]; /* 30h-97h | Reserved */ 1021 __le16 PRICLEARIRQ; /* 98h | Primary Clear Irq */ 1022 __le16 SECCLEARIRQ; /* 9ah | Secondary Clear Irq */ 1023 __le16 PRISETIRQ; /* 9ch | Primary Set Irq */ 1024 __le16 SECSETIRQ; /* 9eh | Secondary Set Irq */ 1025 __le16 PRICLEARIRQMASK;/* a0h | Primary Clear Irq Mask */ 1026 __le16 SECCLEARIRQMASK;/* a2h | Secondary Clear Irq Mask */ 1027 __le16 PRISETIRQMASK; /* a4h | Primary Set Irq Mask */ 1028 __le16 SECSETIRQMASK; /* a6h | Secondary Set Irq Mask */ 1029 __le32 MAILBOX0; /* a8h | Scratchpad 0 */ 1030 __le32 MAILBOX1; /* ach | Scratchpad 1 */ 1031 __le32 MAILBOX2; /* b0h | Scratchpad 2 */ 1032 __le32 MAILBOX3; /* b4h | Scratchpad 3 */ 1033 __le32 MAILBOX4; /* b8h | Scratchpad 4 */ 1034 __le32 MAILBOX5; /* bch | Scratchpad 5 */ 1035 __le32 MAILBOX6; /* c0h | Scratchpad 6 */ 1036 __le32 MAILBOX7; /* c4h | Scratchpad 7 */ 1037 __le32 ROM_Setup_Data; /* c8h | Rom Setup and Data */ 1038 __le32 ROM_Control_Addr;/* cch | Rom Control and Address */ 1039 __le32 reserved3[12]; /* d0h-ffh | reserved */ 1040 __le32 LUT[64]; /* 100h-1ffh | Lookup Table Entries */ 1041}; 1042 1043#define Mailbox0 SaDbCSR.MAILBOX0 1044#define Mailbox1 SaDbCSR.MAILBOX1 1045#define Mailbox2 SaDbCSR.MAILBOX2 1046#define Mailbox3 SaDbCSR.MAILBOX3 1047#define Mailbox4 SaDbCSR.MAILBOX4 1048#define Mailbox5 SaDbCSR.MAILBOX5 1049#define Mailbox6 SaDbCSR.MAILBOX6 1050#define Mailbox7 SaDbCSR.MAILBOX7 1051 1052#define DoorbellReg_p SaDbCSR.PRISETIRQ 1053#define DoorbellReg_s SaDbCSR.SECSETIRQ 1054#define DoorbellClrReg_p SaDbCSR.PRICLEARIRQ 1055 1056 1057#define DOORBELL_0 0x0001 1058#define DOORBELL_1 0x0002 1059#define DOORBELL_2 0x0004 1060#define DOORBELL_3 0x0008 1061#define DOORBELL_4 0x0010 1062#define DOORBELL_5 0x0020 1063#define DOORBELL_6 0x0040 1064 1065 1066#define PrintfReady DOORBELL_5 1067#define PrintfDone DOORBELL_5 1068 1069struct sa_registers { 1070 struct sa_drawbridge_CSR SaDbCSR; /* 98h - c4h */ 1071}; 1072 1073 1074#define SA_INIT_NUM_MSIXVECTORS 1 1075#define SA_MINIPORT_REVISION SA_INIT_NUM_MSIXVECTORS 1076 1077#define sa_readw(AEP, CSR) readl(&((AEP)->regs.sa->CSR)) 1078#define sa_readl(AEP, CSR) readl(&((AEP)->regs.sa->CSR)) 1079#define sa_writew(AEP, CSR, value) writew(value, &((AEP)->regs.sa->CSR)) 1080#define sa_writel(AEP, CSR, value) writel(value, &((AEP)->regs.sa->CSR)) 1081 1082/* 1083 * Rx Message Unit Registers 1084 */ 1085 1086struct rx_mu_registers { 1087 /* Local | PCI*| Name */ 1088 __le32 ARSR; /* 1300h | 00h | APIC Register Select Register */ 1089 __le32 reserved0; /* 1304h | 04h | Reserved */ 1090 __le32 AWR; /* 1308h | 08h | APIC Window Register */ 1091 __le32 reserved1; /* 130Ch | 0Ch | Reserved */ 1092 __le32 IMRx[2]; /* 1310h | 10h | Inbound Message Registers */ 1093 __le32 OMRx[2]; /* 1318h | 18h | Outbound Message Registers */ 1094 __le32 IDR; /* 1320h | 20h | Inbound Doorbell Register */ 1095 __le32 IISR; /* 1324h | 24h | Inbound Interrupt 1096 Status Register */ 1097 __le32 IIMR; /* 1328h | 28h | Inbound Interrupt 1098 Mask Register */ 1099 __le32 ODR; /* 132Ch | 2Ch | Outbound Doorbell Register */ 1100 __le32 OISR; /* 1330h | 30h | Outbound Interrupt 1101 Status Register */ 1102 __le32 OIMR; /* 1334h | 34h | Outbound Interrupt 1103 Mask Register */ 1104 __le32 reserved2; /* 1338h | 38h | Reserved */ 1105 __le32 reserved3; /* 133Ch | 3Ch | Reserved */ 1106 __le32 InboundQueue;/* 1340h | 40h | Inbound Queue Port relative to firmware */ 1107 __le32 OutboundQueue;/*1344h | 44h | Outbound Queue Port relative to firmware */ 1108 /* * Must access through ATU Inbound 1109 Translation Window */ 1110}; 1111 1112struct rx_inbound { 1113 __le32 Mailbox[8]; 1114}; 1115 1116#define INBOUNDDOORBELL_0 0x00000001 1117#define INBOUNDDOORBELL_1 0x00000002 1118#define INBOUNDDOORBELL_2 0x00000004 1119#define INBOUNDDOORBELL_3 0x00000008 1120#define INBOUNDDOORBELL_4 0x00000010 1121#define INBOUNDDOORBELL_5 0x00000020 1122#define INBOUNDDOORBELL_6 0x00000040 1123 1124#define OUTBOUNDDOORBELL_0 0x00000001 1125#define OUTBOUNDDOORBELL_1 0x00000002 1126#define OUTBOUNDDOORBELL_2 0x00000004 1127#define OUTBOUNDDOORBELL_3 0x00000008 1128#define OUTBOUNDDOORBELL_4 0x00000010 1129 1130#define InboundDoorbellReg MUnit.IDR 1131#define OutboundDoorbellReg MUnit.ODR 1132 1133struct rx_registers { 1134 struct rx_mu_registers MUnit; /* 1300h - 1347h */ 1135 __le32 reserved1[2]; /* 1348h - 134ch */ 1136 struct rx_inbound IndexRegs; 1137}; 1138 1139#define rx_readb(AEP, CSR) readb(&((AEP)->regs.rx->CSR)) 1140#define rx_readl(AEP, CSR) readl(&((AEP)->regs.rx->CSR)) 1141#define rx_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rx->CSR)) 1142#define rx_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rx->CSR)) 1143 1144/* 1145 * Rkt Message Unit Registers (same as Rx, except a larger reserve region) 1146 */ 1147 1148#define rkt_mu_registers rx_mu_registers 1149#define rkt_inbound rx_inbound 1150 1151struct rkt_registers { 1152 struct rkt_mu_registers MUnit; /* 1300h - 1347h */ 1153 __le32 reserved1[1006]; /* 1348h - 22fch */ 1154 struct rkt_inbound IndexRegs; /* 2300h - */ 1155}; 1156 1157#define rkt_readb(AEP, CSR) readb(&((AEP)->regs.rkt->CSR)) 1158#define rkt_readl(AEP, CSR) readl(&((AEP)->regs.rkt->CSR)) 1159#define rkt_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rkt->CSR)) 1160#define rkt_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rkt->CSR)) 1161 1162/* 1163 * PMC SRC message unit registers 1164 */ 1165 1166#define src_inbound rx_inbound 1167 1168struct src_mu_registers { 1169 /* PCI*| Name */ 1170 __le32 reserved0[6]; /* 00h | Reserved */ 1171 __le32 IOAR[2]; /* 18h | IOA->host interrupt register */ 1172 __le32 IDR; /* 20h | Inbound Doorbell Register */ 1173 __le32 IISR; /* 24h | Inbound Int. Status Register */ 1174 __le32 reserved1[3]; /* 28h | Reserved */ 1175 __le32 OIMR; /* 34h | Outbound Int. Mask Register */ 1176 __le32 reserved2[25]; /* 38h | Reserved */ 1177 __le32 ODR_R; /* 9ch | Outbound Doorbell Read */ 1178 __le32 ODR_C; /* a0h | Outbound Doorbell Clear */ 1179 __le32 reserved3[3]; /* a4h | Reserved */ 1180 __le32 SCR0; /* b0h | Scratchpad 0 */ 1181 __le32 reserved4[2]; /* b4h | Reserved */ 1182 __le32 OMR; /* bch | Outbound Message Register */ 1183 __le32 IQ_L; /* c0h | Inbound Queue (Low address) */ 1184 __le32 IQ_H; /* c4h | Inbound Queue (High address) */ 1185 __le32 ODR_MSI; /* c8h | MSI register for sync./AIF */ 1186 __le32 reserved5; /* cch | Reserved */ 1187 __le32 IQN_L; /* d0h | Inbound (native cmd) low */ 1188 __le32 IQN_H; /* d4h | Inbound (native cmd) high */ 1189}; 1190 1191struct src_registers { 1192 struct src_mu_registers MUnit; /* 00h - cbh */ 1193 union { 1194 struct { 1195 __le32 reserved1[130786]; /* d8h - 7fc5fh */ 1196 struct src_inbound IndexRegs; /* 7fc60h */ 1197 } tupelo; 1198 struct { 1199 __le32 reserved1[970]; /* d8h - fffh */ 1200 struct src_inbound IndexRegs; /* 1000h */ 1201 } denali; 1202 } u; 1203}; 1204 1205#define src_readb(AEP, CSR) readb(&((AEP)->regs.src.bar0->CSR)) 1206#define src_readl(AEP, CSR) readl(&((AEP)->regs.src.bar0->CSR)) 1207#define src_writeb(AEP, CSR, value) writeb(value, \ 1208 &((AEP)->regs.src.bar0->CSR)) 1209#define src_writel(AEP, CSR, value) writel(value, \ 1210 &((AEP)->regs.src.bar0->CSR)) 1211#if defined(writeq) 1212#define src_writeq(AEP, CSR, value) writeq(value, \ 1213 &((AEP)->regs.src.bar0->CSR)) 1214#endif 1215 1216#define SRC_ODR_SHIFT 12 1217#define SRC_IDR_SHIFT 9 1218#define SRC_MSI_READ_MASK 0x1000 1219 1220typedef void (*fib_callback)(void *ctxt, struct fib *fibctx); 1221 1222struct aac_fib_context { 1223 s16 type; // used for verification of structure 1224 s16 size; 1225 u32 unique; // unique value representing this context 1226 ulong jiffies; // used for cleanup - dmb changed to ulong 1227 struct list_head next; // used to link context's into a linked list 1228 struct completion completion; // this is used to wait for the next fib to arrive. 1229 int wait; // Set to true when thread is in WaitForSingleObject 1230 unsigned long count; // total number of FIBs on FibList 1231 struct list_head fib_list; // this holds fibs and their attachd hw_fibs 1232}; 1233 1234struct sense_data { 1235 u8 error_code; /* 70h (current errors), 71h(deferred errors) */ 1236 u8 valid:1; /* A valid bit of one indicates that the information */ 1237 /* field contains valid information as defined in the 1238 * SCSI-2 Standard. 1239 */ 1240 u8 segment_number; /* Only used for COPY, COMPARE, or COPY AND VERIFY Commands */ 1241 u8 sense_key:4; /* Sense Key */ 1242 u8 reserved:1; 1243 u8 ILI:1; /* Incorrect Length Indicator */ 1244 u8 EOM:1; /* End Of Medium - reserved for random access devices */ 1245 u8 filemark:1; /* Filemark - reserved for random access devices */ 1246 1247 u8 information[4]; /* for direct-access devices, contains the unsigned 1248 * logical block address or residue associated with 1249 * the sense key 1250 */ 1251 u8 add_sense_len; /* number of additional sense bytes to follow this field */ 1252 u8 cmnd_info[4]; /* not used */ 1253 u8 ASC; /* Additional Sense Code */ 1254 u8 ASCQ; /* Additional Sense Code Qualifier */ 1255 u8 FRUC; /* Field Replaceable Unit Code - not used */ 1256 u8 bit_ptr:3; /* indicates which byte of the CDB or parameter data 1257 * was in error 1258 */ 1259 u8 BPV:1; /* bit pointer valid (BPV): 1- indicates that 1260 * the bit_ptr field has valid value 1261 */ 1262 u8 reserved2:2; 1263 u8 CD:1; /* command data bit: 1- illegal parameter in CDB. 1264 * 0- illegal parameter in data. 1265 */ 1266 u8 SKSV:1; 1267 u8 field_ptr[2]; /* byte of the CDB or parameter data in error */ 1268}; 1269 1270struct fsa_dev_info { 1271 u64 last; 1272 u64 size; 1273 u32 type; 1274 u32 config_waiting_on; 1275 unsigned long config_waiting_stamp; 1276 u16 queue_depth; 1277 u8 config_needed; 1278 u8 valid; 1279 u8 ro; 1280 u8 locked; 1281 u8 deleted; 1282 char devname[8]; 1283 struct sense_data sense_data; 1284 u32 block_size; 1285 u8 identifier[16]; 1286}; 1287 1288struct fib { 1289 void *next; /* this is used by the allocator */ 1290 s16 type; 1291 s16 size; 1292 /* 1293 * The Adapter that this I/O is destined for. 1294 */ 1295 struct aac_dev *dev; 1296 /* 1297 * This is the event the sendfib routine will wait on if the 1298 * caller did not pass one and this is synch io. 1299 */ 1300 struct completion event_wait; 1301 spinlock_t event_lock; 1302 1303 u32 done; /* gets set to 1 when fib is complete */ 1304 fib_callback callback; 1305 void *callback_data; 1306 u32 flags; // u32 dmb was ulong 1307 /* 1308 * And for the internal issue/reply queues (we may be able 1309 * to merge these two) 1310 */ 1311 struct list_head fiblink; 1312 void *data; 1313 u32 vector_no; 1314 struct hw_fib *hw_fib_va; /* also used for native */ 1315 dma_addr_t hw_fib_pa; /* physical address of hw_fib*/ 1316 dma_addr_t hw_sgl_pa; /* extra sgl for native */ 1317 dma_addr_t hw_error_pa; /* error buffer for native */ 1318 u32 hbacmd_size; /* cmd size for native */ 1319}; 1320 1321#define AAC_INIT 0 1322#define AAC_RESCAN 1 1323 1324#define AAC_DEVTYPE_RAID_MEMBER 1 1325#define AAC_DEVTYPE_ARC_RAW 2 1326#define AAC_DEVTYPE_NATIVE_RAW 3 1327 1328#define AAC_RESCAN_DELAY (10 * HZ) 1329 1330struct aac_hba_map_info { 1331 __le32 rmw_nexus; /* nexus for native HBA devices */ 1332 u8 devtype; /* device type */ 1333 s8 reset_state; /* 0 - no reset, 1..x - */ 1334 /* after xth TM LUN reset */ 1335 u16 qd_limit; 1336 u32 scan_counter; 1337 struct aac_ciss_identify_pd *safw_identify_resp; 1338}; 1339 1340/* 1341 * Adapter Information Block 1342 * 1343 * This is returned by the RequestAdapterInfo block 1344 */ 1345 1346struct aac_adapter_info 1347{ 1348 __le32 platform; 1349 __le32 cpu; 1350 __le32 subcpu; 1351 __le32 clock; 1352 __le32 execmem; 1353 __le32 buffermem; 1354 __le32 totalmem; 1355 __le32 kernelrev; 1356 __le32 kernelbuild; 1357 __le32 monitorrev; 1358 __le32 monitorbuild; 1359 __le32 hwrev; 1360 __le32 hwbuild; 1361 __le32 biosrev; 1362 __le32 biosbuild; 1363 __le32 cluster; 1364 __le32 clusterchannelmask; 1365 __le32 serial[2]; 1366 __le32 battery; 1367 __le32 options; 1368 __le32 OEM; 1369}; 1370 1371struct aac_supplement_adapter_info 1372{ 1373 u8 adapter_type_text[17+1]; 1374 u8 pad[2]; 1375 __le32 flash_memory_byte_size; 1376 __le32 flash_image_id; 1377 __le32 max_number_ports; 1378 __le32 version; 1379 __le32 feature_bits; 1380 u8 slot_number; 1381 u8 reserved_pad0[3]; 1382 u8 build_date[12]; 1383 __le32 current_number_ports; 1384 struct { 1385 u8 assembly_pn[8]; 1386 u8 fru_pn[8]; 1387 u8 battery_fru_pn[8]; 1388 u8 ec_version_string[8]; 1389 u8 tsid[12]; 1390 } vpd_info; 1391 __le32 flash_firmware_revision; 1392 __le32 flash_firmware_build; 1393 __le32 raid_type_morph_options; 1394 __le32 flash_firmware_boot_revision; 1395 __le32 flash_firmware_boot_build; 1396 u8 mfg_pcba_serial_no[12]; 1397 u8 mfg_wwn_name[8]; 1398 __le32 supported_options2; 1399 __le32 struct_expansion; 1400 /* StructExpansion == 1 */ 1401 __le32 feature_bits3; 1402 __le32 supported_performance_modes; 1403 u8 host_bus_type; /* uses HOST_BUS_TYPE_xxx defines */ 1404 u8 host_bus_width; /* actual width in bits or links */ 1405 u16 host_bus_speed; /* actual bus speed/link rate in MHz */ 1406 u8 max_rrc_drives; /* max. number of ITP-RRC drives/pool */ 1407 u8 max_disk_xtasks; /* max. possible num of DiskX Tasks */ 1408 1409 u8 cpld_ver_loaded; 1410 u8 cpld_ver_in_flash; 1411 1412 __le64 max_rrc_capacity; 1413 __le32 compiled_max_hist_log_level; 1414 u8 custom_board_name[12]; 1415 u16 supported_cntlr_mode; /* identify supported controller mode */ 1416 u16 reserved_for_future16; 1417 __le32 supported_options3; /* reserved for future options */ 1418 1419 __le16 virt_device_bus; /* virt. SCSI device for Thor */ 1420 __le16 virt_device_target; 1421 __le16 virt_device_lun; 1422 __le16 unused; 1423 __le32 reserved_for_future_growth[68]; 1424 1425}; 1426#define AAC_FEATURE_FALCON cpu_to_le32(0x00000010) 1427#define AAC_FEATURE_JBOD cpu_to_le32(0x08000000) 1428/* SupportedOptions2 */ 1429#define AAC_OPTION_MU_RESET cpu_to_le32(0x00000001) 1430#define AAC_OPTION_IGNORE_RESET cpu_to_le32(0x00000002) 1431#define AAC_OPTION_POWER_MANAGEMENT cpu_to_le32(0x00000004) 1432#define AAC_OPTION_DOORBELL_RESET cpu_to_le32(0x00004000) 1433/* 4KB sector size */ 1434#define AAC_OPTION_VARIABLE_BLOCK_SIZE cpu_to_le32(0x00040000) 1435/* 240 simple volume support */ 1436#define AAC_OPTION_SUPPORTED_240_VOLUMES cpu_to_le32(0x10000000) 1437/* 1438 * Supports FIB dump sync command send prior to IOP_RESET 1439 */ 1440#define AAC_OPTION_SUPPORTED3_IOP_RESET_FIB_DUMP cpu_to_le32(0x00004000) 1441#define AAC_SIS_VERSION_V3 3 1442#define AAC_SIS_SLOT_UNKNOWN 0xFF 1443 1444#define GetBusInfo 0x00000009 1445struct aac_bus_info { 1446 __le32 Command; /* VM_Ioctl */ 1447 __le32 ObjType; /* FT_DRIVE */ 1448 __le32 MethodId; /* 1 = SCSI Layer */ 1449 __le32 ObjectId; /* Handle */ 1450 __le32 CtlCmd; /* GetBusInfo */ 1451}; 1452 1453struct aac_bus_info_response { 1454 __le32 Status; /* ST_OK */ 1455 __le32 ObjType; 1456 __le32 MethodId; /* unused */ 1457 __le32 ObjectId; /* unused */ 1458 __le32 CtlCmd; /* unused */ 1459 __le32 ProbeComplete; 1460 __le32 BusCount; 1461 __le32 TargetsPerBus; 1462 u8 InitiatorBusId[10]; 1463 u8 BusValid[10]; 1464}; 1465 1466/* 1467 * Battery platforms 1468 */ 1469#define AAC_BAT_REQ_PRESENT (1) 1470#define AAC_BAT_REQ_NOTPRESENT (2) 1471#define AAC_BAT_OPT_PRESENT (3) 1472#define AAC_BAT_OPT_NOTPRESENT (4) 1473#define AAC_BAT_NOT_SUPPORTED (5) 1474/* 1475 * cpu types 1476 */ 1477#define AAC_CPU_SIMULATOR (1) 1478#define AAC_CPU_I960 (2) 1479#define AAC_CPU_STRONGARM (3) 1480 1481/* 1482 * Supported Options 1483 */ 1484#define AAC_OPT_SNAPSHOT cpu_to_le32(1) 1485#define AAC_OPT_CLUSTERS cpu_to_le32(1<<1) 1486#define AAC_OPT_WRITE_CACHE cpu_to_le32(1<<2) 1487#define AAC_OPT_64BIT_DATA cpu_to_le32(1<<3) 1488#define AAC_OPT_HOST_TIME_FIB cpu_to_le32(1<<4) 1489#define AAC_OPT_RAID50 cpu_to_le32(1<<5) 1490#define AAC_OPT_4GB_WINDOW cpu_to_le32(1<<6) 1491#define AAC_OPT_SCSI_UPGRADEABLE cpu_to_le32(1<<7) 1492#define AAC_OPT_SOFT_ERR_REPORT cpu_to_le32(1<<8) 1493#define AAC_OPT_SUPPORTED_RECONDITION cpu_to_le32(1<<9) 1494#define AAC_OPT_SGMAP_HOST64 cpu_to_le32(1<<10) 1495#define AAC_OPT_ALARM cpu_to_le32(1<<11) 1496#define AAC_OPT_NONDASD cpu_to_le32(1<<12) 1497#define AAC_OPT_SCSI_MANAGED cpu_to_le32(1<<13) 1498#define AAC_OPT_RAID_SCSI_MODE cpu_to_le32(1<<14) 1499#define AAC_OPT_SUPPLEMENT_ADAPTER_INFO cpu_to_le32(1<<16) 1500#define AAC_OPT_NEW_COMM cpu_to_le32(1<<17) 1501#define AAC_OPT_NEW_COMM_64 cpu_to_le32(1<<18) 1502#define AAC_OPT_EXTENDED cpu_to_le32(1<<23) 1503#define AAC_OPT_NATIVE_HBA cpu_to_le32(1<<25) 1504#define AAC_OPT_NEW_COMM_TYPE1 cpu_to_le32(1<<28) 1505#define AAC_OPT_NEW_COMM_TYPE2 cpu_to_le32(1<<29) 1506#define AAC_OPT_NEW_COMM_TYPE3 cpu_to_le32(1<<30) 1507#define AAC_OPT_NEW_COMM_TYPE4 cpu_to_le32(1<<31) 1508 1509#define AAC_COMM_PRODUCER 0 1510#define AAC_COMM_MESSAGE 1 1511#define AAC_COMM_MESSAGE_TYPE1 3 1512#define AAC_COMM_MESSAGE_TYPE2 4 1513#define AAC_COMM_MESSAGE_TYPE3 5 1514 1515#define AAC_EXTOPT_SA_FIRMWARE cpu_to_le32(1<<1) 1516#define AAC_EXTOPT_SOFT_RESET cpu_to_le32(1<<16) 1517 1518/* MSIX context */ 1519struct aac_msix_ctx { 1520 int vector_no; 1521 struct aac_dev *dev; 1522}; 1523 1524struct aac_dev 1525{ 1526 struct list_head entry; 1527 const char *name; 1528 int id; 1529 1530 /* 1531 * negotiated FIB settings 1532 */ 1533 unsigned int max_fib_size; 1534 unsigned int sg_tablesize; 1535 unsigned int max_num_aif; 1536 1537 unsigned int max_cmd_size; /* max_fib_size or MAX_NATIVE */ 1538 1539 /* 1540 * Map for 128 fib objects (64k) 1541 */ 1542 dma_addr_t hw_fib_pa; /* also used for native cmd */ 1543 struct hw_fib *hw_fib_va; /* also used for native cmd */ 1544 struct hw_fib *aif_base_va; 1545 /* 1546 * Fib Headers 1547 */ 1548 struct fib *fibs; 1549 1550 struct fib *free_fib; 1551 spinlock_t fib_lock; 1552 1553 struct mutex ioctl_mutex; 1554 struct mutex scan_mutex; 1555 struct aac_queue_block *queues; 1556 /* 1557 * The user API will use an IOCTL to register itself to receive 1558 * FIBs from the adapter. The following list is used to keep 1559 * track of all the threads that have requested these FIBs. The 1560 * mutex is used to synchronize access to all data associated 1561 * with the adapter fibs. 1562 */ 1563 struct list_head fib_list; 1564 1565 struct adapter_ops a_ops; 1566 unsigned long fsrev; /* Main driver's revision number */ 1567 1568 resource_size_t base_start; /* main IO base */ 1569 resource_size_t dbg_base; /* address of UART 1570 * debug buffer */ 1571 1572 resource_size_t base_size, dbg_size; /* Size of 1573 * mapped in region */ 1574 /* 1575 * Holds initialization info 1576 * to communicate with adapter 1577 */ 1578 union aac_init *init; 1579 dma_addr_t init_pa; /* Holds physical address of the init struct */ 1580 /* response queue (if AAC_COMM_MESSAGE_TYPE1) */ 1581 __le32 *host_rrq; 1582 dma_addr_t host_rrq_pa; /* phys. address */ 1583 /* index into rrq buffer */ 1584 u32 host_rrq_idx[AAC_MAX_MSIX]; 1585 atomic_t rrq_outstanding[AAC_MAX_MSIX]; 1586 u32 fibs_pushed_no; 1587 struct pci_dev *pdev; /* Our PCI interface */ 1588 /* pointer to buffer used for printf's from the adapter */ 1589 void *printfbuf; 1590 void *comm_addr; /* Base address of Comm area */ 1591 dma_addr_t comm_phys; /* Physical Address of Comm area */ 1592 size_t comm_size; 1593 1594 struct Scsi_Host *scsi_host_ptr; 1595 int maximum_num_containers; 1596 int maximum_num_physicals; 1597 int maximum_num_channels; 1598 struct fsa_dev_info *fsa_dev; 1599 struct task_struct *thread; 1600 struct delayed_work safw_rescan_work; 1601 struct delayed_work src_reinit_aif_worker; 1602 int cardtype; 1603 /* 1604 *This lock will protect the two 32-bit 1605 *writes to the Inbound Queue 1606 */ 1607 spinlock_t iq_lock; 1608 1609 /* 1610 * The following is the device specific extension. 1611 */ 1612#ifndef AAC_MIN_FOOTPRINT_SIZE 1613# define AAC_MIN_FOOTPRINT_SIZE 8192 1614# define AAC_MIN_SRC_BAR0_SIZE 0x400000 1615# define AAC_MIN_SRC_BAR1_SIZE 0x800 1616# define AAC_MIN_SRCV_BAR0_SIZE 0x100000 1617# define AAC_MIN_SRCV_BAR1_SIZE 0x400 1618#endif 1619 union 1620 { 1621 struct sa_registers __iomem *sa; 1622 struct rx_registers __iomem *rx; 1623 struct rkt_registers __iomem *rkt; 1624 struct { 1625 struct src_registers __iomem *bar0; 1626 char __iomem *bar1; 1627 } src; 1628 } regs; 1629 volatile void __iomem *base, *dbg_base_mapped; 1630 volatile struct rx_inbound __iomem *IndexRegs; 1631 u32 OIMR; /* Mask Register Cache */ 1632 /* 1633 * AIF thread states 1634 */ 1635 u32 aif_thread; 1636 struct aac_adapter_info adapter_info; 1637 struct aac_supplement_adapter_info supplement_adapter_info; 1638 /* These are in adapter info but they are in the io flow so 1639 * lets break them out so we don't have to do an AND to check them 1640 */ 1641 u8 nondasd_support; 1642 u8 jbod; 1643 u8 cache_protected; 1644 u8 dac_support; 1645 u8 needs_dac; 1646 u8 raid_scsi_mode; 1647 u8 comm_interface; 1648 u8 raw_io_interface; 1649 u8 raw_io_64; 1650 u8 printf_enabled; 1651 u8 in_reset; 1652 u8 in_soft_reset; 1653 u8 msi; 1654 u8 sa_firmware; 1655 int management_fib_count; 1656 spinlock_t manage_lock; 1657 spinlock_t sync_lock; 1658 int sync_mode; 1659 struct fib *sync_fib; 1660 struct list_head sync_fib_list; 1661 u32 doorbell_mask; 1662 u32 max_msix; /* max. MSI-X vectors */ 1663 u32 vector_cap; /* MSI-X vector capab.*/ 1664 int msi_enabled; /* MSI/MSI-X enabled */ 1665 atomic_t msix_counter; 1666 u32 scan_counter; 1667 struct msix_entry msixentry[AAC_MAX_MSIX]; 1668 struct aac_msix_ctx aac_msix[AAC_MAX_MSIX]; /* context */ 1669 struct aac_hba_map_info hba_map[AAC_MAX_BUSES][AAC_MAX_TARGETS]; 1670 struct aac_ciss_phys_luns_resp *safw_phys_luns; 1671 u8 adapter_shutdown; 1672 u32 handle_pci_error; 1673 bool init_reset; 1674 u8 soft_reset_support; 1675}; 1676 1677#define aac_adapter_interrupt(dev) \ 1678 (dev)->a_ops.adapter_interrupt(dev) 1679 1680#define aac_adapter_notify(dev, event) \ 1681 (dev)->a_ops.adapter_notify(dev, event) 1682 1683#define aac_adapter_disable_int(dev) \ 1684 (dev)->a_ops.adapter_disable_int(dev) 1685 1686#define aac_adapter_enable_int(dev) \ 1687 (dev)->a_ops.adapter_enable_int(dev) 1688 1689#define aac_adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4) \ 1690 (dev)->a_ops.adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4) 1691 1692#define aac_adapter_restart(dev, bled, reset_type) \ 1693 ((dev)->a_ops.adapter_restart(dev, bled, reset_type)) 1694 1695#define aac_adapter_start(dev) \ 1696 ((dev)->a_ops.adapter_start(dev)) 1697 1698#define aac_adapter_ioremap(dev, size) \ 1699 (dev)->a_ops.adapter_ioremap(dev, size) 1700 1701#define aac_adapter_deliver(fib) \ 1702 ((fib)->dev)->a_ops.adapter_deliver(fib) 1703 1704#define aac_adapter_bounds(dev,cmd,lba) \ 1705 dev->a_ops.adapter_bounds(dev,cmd,lba) 1706 1707#define aac_adapter_read(fib,cmd,lba,count) \ 1708 ((fib)->dev)->a_ops.adapter_read(fib,cmd,lba,count) 1709 1710#define aac_adapter_write(fib,cmd,lba,count,fua) \ 1711 ((fib)->dev)->a_ops.adapter_write(fib,cmd,lba,count,fua) 1712 1713#define aac_adapter_scsi(fib,cmd) \ 1714 ((fib)->dev)->a_ops.adapter_scsi(fib,cmd) 1715 1716#define aac_adapter_comm(dev,comm) \ 1717 (dev)->a_ops.adapter_comm(dev, comm) 1718 1719#define FIB_CONTEXT_FLAG_TIMED_OUT (0x00000001) 1720#define FIB_CONTEXT_FLAG (0x00000002) 1721#define FIB_CONTEXT_FLAG_WAIT (0x00000004) 1722#define FIB_CONTEXT_FLAG_FASTRESP (0x00000008) 1723#define FIB_CONTEXT_FLAG_NATIVE_HBA (0x00000010) 1724#define FIB_CONTEXT_FLAG_NATIVE_HBA_TMF (0x00000020) 1725#define FIB_CONTEXT_FLAG_SCSI_CMD (0x00000040) 1726#define FIB_CONTEXT_FLAG_EH_RESET (0x00000080) 1727 1728/* 1729 * Define the command values 1730 */ 1731 1732#define Null 0 1733#define GetAttributes 1 1734#define SetAttributes 2 1735#define Lookup 3 1736#define ReadLink 4 1737#define Read 5 1738#define Write 6 1739#define Create 7 1740#define MakeDirectory 8 1741#define SymbolicLink 9 1742#define MakeNode 10 1743#define Removex 11 1744#define RemoveDirectoryx 12 1745#define Rename 13 1746#define Link 14 1747#define ReadDirectory 15 1748#define ReadDirectoryPlus 16 1749#define FileSystemStatus 17 1750#define FileSystemInfo 18 1751#define PathConfigure 19 1752#define Commit 20 1753#define Mount 21 1754#define UnMount 22 1755#define Newfs 23 1756#define FsCheck 24 1757#define FsSync 25 1758#define SimReadWrite 26 1759#define SetFileSystemStatus 27 1760#define BlockRead 28 1761#define BlockWrite 29 1762#define NvramIoctl 30 1763#define FsSyncWait 31 1764#define ClearArchiveBit 32 1765#define SetAcl 33 1766#define GetAcl 34 1767#define AssignAcl 35 1768#define FaultInsertion 36 /* Fault Insertion Command */ 1769#define CrazyCache 37 /* Crazycache */ 1770 1771#define MAX_FSACOMMAND_NUM 38 1772 1773 1774/* 1775 * Define the status returns. These are very unixlike although 1776 * most are not in fact used 1777 */ 1778 1779#define ST_OK 0 1780#define ST_PERM 1 1781#define ST_NOENT 2 1782#define ST_IO 5 1783#define ST_NXIO 6 1784#define ST_E2BIG 7 1785#define ST_MEDERR 8 1786#define ST_ACCES 13 1787#define ST_EXIST 17 1788#define ST_XDEV 18 1789#define ST_NODEV 19 1790#define ST_NOTDIR 20 1791#define ST_ISDIR 21 1792#define ST_INVAL 22 1793#define ST_FBIG 27 1794#define ST_NOSPC 28 1795#define ST_ROFS 30 1796#define ST_MLINK 31 1797#define ST_WOULDBLOCK 35 1798#define ST_NAMETOOLONG 63 1799#define ST_NOTEMPTY 66 1800#define ST_DQUOT 69 1801#define ST_STALE 70 1802#define ST_REMOTE 71 1803#define ST_NOT_READY 72 1804#define ST_BADHANDLE 10001 1805#define ST_NOT_SYNC 10002 1806#define ST_BAD_COOKIE 10003 1807#define ST_NOTSUPP 10004 1808#define ST_TOOSMALL 10005 1809#define ST_SERVERFAULT 10006 1810#define ST_BADTYPE 10007 1811#define ST_JUKEBOX 10008 1812#define ST_NOTMOUNTED 10009 1813#define ST_MAINTMODE 10010 1814#define ST_STALEACL 10011 1815 1816/* 1817 * On writes how does the client want the data written. 1818 */ 1819 1820#define CACHE_CSTABLE 1 1821#define CACHE_UNSTABLE 2 1822 1823/* 1824 * Lets the client know at which level the data was committed on 1825 * a write request 1826 */ 1827 1828#define CMFILE_SYNCH_NVRAM 1 1829#define CMDATA_SYNCH_NVRAM 2 1830#define CMFILE_SYNCH 3 1831#define CMDATA_SYNCH 4 1832#define CMUNSTABLE 5 1833 1834#define RIO_TYPE_WRITE 0x0000 1835#define RIO_TYPE_READ 0x0001 1836#define RIO_SUREWRITE 0x0008 1837 1838#define RIO2_IO_TYPE 0x0003 1839#define RIO2_IO_TYPE_WRITE 0x0000 1840#define RIO2_IO_TYPE_READ 0x0001 1841#define RIO2_IO_TYPE_VERIFY 0x0002 1842#define RIO2_IO_ERROR 0x0004 1843#define RIO2_IO_SUREWRITE 0x0008 1844#define RIO2_SGL_CONFORMANT 0x0010 1845#define RIO2_SG_FORMAT 0xF000 1846#define RIO2_SG_FORMAT_ARC 0x0000 1847#define RIO2_SG_FORMAT_SRL 0x1000 1848#define RIO2_SG_FORMAT_IEEE1212 0x2000 1849 1850struct aac_read 1851{ 1852 __le32 command; 1853 __le32 cid; 1854 __le32 block; 1855 __le32 count; 1856 struct sgmap sg; // Must be last in struct because it is variable 1857}; 1858 1859struct aac_read64 1860{ 1861 __le32 command; 1862 __le16 cid; 1863 __le16 sector_count; 1864 __le32 block; 1865 __le16 pad; 1866 __le16 flags; 1867 struct sgmap64 sg; // Must be last in struct because it is variable 1868}; 1869 1870struct aac_read_reply 1871{ 1872 __le32 status; 1873 __le32 count; 1874}; 1875 1876struct aac_write 1877{ 1878 __le32 command; 1879 __le32 cid; 1880 __le32 block; 1881 __le32 count; 1882 __le32 stable; // Not used 1883 struct sgmap sg; // Must be last in struct because it is variable 1884}; 1885 1886struct aac_write64 1887{ 1888 __le32 command; 1889 __le16 cid; 1890 __le16 sector_count; 1891 __le32 block; 1892 __le16 pad; 1893 __le16 flags; 1894 struct sgmap64 sg; // Must be last in struct because it is variable 1895}; 1896struct aac_write_reply 1897{ 1898 __le32 status; 1899 __le32 count; 1900 __le32 committed; 1901}; 1902 1903struct aac_raw_io 1904{ 1905 __le32 block[2]; 1906 __le32 count; 1907 __le16 cid; 1908 __le16 flags; /* 00 W, 01 R */ 1909 __le16 bpTotal; /* reserved for F/W use */ 1910 __le16 bpComplete; /* reserved for F/W use */ 1911 struct sgmapraw sg; 1912}; 1913 1914struct aac_raw_io2 { 1915 __le32 blockLow; 1916 __le32 blockHigh; 1917 __le32 byteCount; 1918 __le16 cid; 1919 __le16 flags; /* RIO2 flags */ 1920 __le32 sgeFirstSize; /* size of first sge el. */ 1921 __le32 sgeNominalSize; /* size of 2nd sge el. (if conformant) */ 1922 u8 sgeCnt; /* only 8 bits required */ 1923 u8 bpTotal; /* reserved for F/W use */ 1924 u8 bpComplete; /* reserved for F/W use */ 1925 u8 sgeFirstIndex; /* reserved for F/W use */ 1926 u8 unused[4]; 1927 struct sge_ieee1212 sge[]; 1928}; 1929 1930#define CT_FLUSH_CACHE 129 1931struct aac_synchronize { 1932 __le32 command; /* VM_ContainerConfig */ 1933 __le32 type; /* CT_FLUSH_CACHE */ 1934 __le32 cid; 1935 __le32 parm1; 1936 __le32 parm2; 1937 __le32 parm3; 1938 __le32 parm4; 1939 __le32 count; /* sizeof(((struct aac_synchronize_reply *)NULL)->data) */ 1940}; 1941 1942struct aac_synchronize_reply { 1943 __le32 dummy0; 1944 __le32 dummy1; 1945 __le32 status; /* CT_OK */ 1946 __le32 parm1; 1947 __le32 parm2; 1948 __le32 parm3; 1949 __le32 parm4; 1950 __le32 parm5; 1951 u8 data[16]; 1952}; 1953 1954#define CT_POWER_MANAGEMENT 245 1955#define CT_PM_START_UNIT 2 1956#define CT_PM_STOP_UNIT 3 1957#define CT_PM_UNIT_IMMEDIATE 1 1958struct aac_power_management { 1959 __le32 command; /* VM_ContainerConfig */ 1960 __le32 type; /* CT_POWER_MANAGEMENT */ 1961 __le32 sub; /* CT_PM_* */ 1962 __le32 cid; 1963 __le32 parm; /* CT_PM_sub_* */ 1964}; 1965 1966#define CT_PAUSE_IO 65 1967#define CT_RELEASE_IO 66 1968struct aac_pause { 1969 __le32 command; /* VM_ContainerConfig */ 1970 __le32 type; /* CT_PAUSE_IO */ 1971 __le32 timeout; /* 10ms ticks */ 1972 __le32 min; 1973 __le32 noRescan; 1974 __le32 parm3; 1975 __le32 parm4; 1976 __le32 count; /* sizeof(((struct aac_pause_reply *)NULL)->data) */ 1977}; 1978 1979struct aac_srb 1980{ 1981 __le32 function; 1982 __le32 channel; 1983 __le32 id; 1984 __le32 lun; 1985 __le32 timeout; 1986 __le32 flags; 1987 __le32 count; // Data xfer size 1988 __le32 retry_limit; 1989 __le32 cdb_size; 1990 u8 cdb[16]; 1991 struct sgmap sg; 1992}; 1993 1994/* 1995 * This and associated data structs are used by the 1996 * ioctl caller and are in cpu order. 1997 */ 1998struct user_aac_srb 1999{ 2000 u32 function; 2001 u32 channel; 2002 u32 id; 2003 u32 lun; 2004 u32 timeout; 2005 u32 flags; 2006 u32 count; // Data xfer size 2007 u32 retry_limit; 2008 u32 cdb_size; 2009 u8 cdb[16]; 2010 struct user_sgmap sg; 2011}; 2012 2013#define AAC_SENSE_BUFFERSIZE 30 2014 2015struct aac_srb_reply 2016{ 2017 __le32 status; 2018 __le32 srb_status; 2019 __le32 scsi_status; 2020 __le32 data_xfer_length; 2021 __le32 sense_data_size; 2022 u8 sense_data[AAC_SENSE_BUFFERSIZE]; // Can this be SCSI_SENSE_BUFFERSIZE 2023}; 2024 2025struct aac_srb_unit { 2026 struct aac_srb_reply srb_reply; 2027 struct aac_srb srb; 2028}; 2029 2030/* 2031 * SRB Flags 2032 */ 2033#define SRB_NoDataXfer 0x0000 2034#define SRB_DisableDisconnect 0x0004 2035#define SRB_DisableSynchTransfer 0x0008 2036#define SRB_BypassFrozenQueue 0x0010 2037#define SRB_DisableAutosense 0x0020 2038#define SRB_DataIn 0x0040 2039#define SRB_DataOut 0x0080 2040 2041/* 2042 * SRB Functions - set in aac_srb->function 2043 */ 2044#define SRBF_ExecuteScsi 0x0000 2045#define SRBF_ClaimDevice 0x0001 2046#define SRBF_IO_Control 0x0002 2047#define SRBF_ReceiveEvent 0x0003 2048#define SRBF_ReleaseQueue 0x0004 2049#define SRBF_AttachDevice 0x0005 2050#define SRBF_ReleaseDevice 0x0006 2051#define SRBF_Shutdown 0x0007 2052#define SRBF_Flush 0x0008 2053#define SRBF_AbortCommand 0x0010 2054#define SRBF_ReleaseRecovery 0x0011 2055#define SRBF_ResetBus 0x0012 2056#define SRBF_ResetDevice 0x0013 2057#define SRBF_TerminateIO 0x0014 2058#define SRBF_FlushQueue 0x0015 2059#define SRBF_RemoveDevice 0x0016 2060#define SRBF_DomainValidation 0x0017 2061 2062/* 2063 * SRB SCSI Status - set in aac_srb->scsi_status 2064 */ 2065#define SRB_STATUS_PENDING 0x00 2066#define SRB_STATUS_SUCCESS 0x01 2067#define SRB_STATUS_ABORTED 0x02 2068#define SRB_STATUS_ABORT_FAILED 0x03 2069#define SRB_STATUS_ERROR 0x04 2070#define SRB_STATUS_BUSY 0x05 2071#define SRB_STATUS_INVALID_REQUEST 0x06 2072#define SRB_STATUS_INVALID_PATH_ID 0x07 2073#define SRB_STATUS_NO_DEVICE 0x08 2074#define SRB_STATUS_TIMEOUT 0x09 2075#define SRB_STATUS_SELECTION_TIMEOUT 0x0A 2076#define SRB_STATUS_COMMAND_TIMEOUT 0x0B 2077#define SRB_STATUS_MESSAGE_REJECTED 0x0D 2078#define SRB_STATUS_BUS_RESET 0x0E 2079#define SRB_STATUS_PARITY_ERROR 0x0F 2080#define SRB_STATUS_REQUEST_SENSE_FAILED 0x10 2081#define SRB_STATUS_NO_HBA 0x11 2082#define SRB_STATUS_DATA_OVERRUN 0x12 2083#define SRB_STATUS_UNEXPECTED_BUS_FREE 0x13 2084#define SRB_STATUS_PHASE_SEQUENCE_FAILURE 0x14 2085#define SRB_STATUS_BAD_SRB_BLOCK_LENGTH 0x15 2086#define SRB_STATUS_REQUEST_FLUSHED 0x16 2087#define SRB_STATUS_DELAYED_RETRY 0x17 2088#define SRB_STATUS_INVALID_LUN 0x20 2089#define SRB_STATUS_INVALID_TARGET_ID 0x21 2090#define SRB_STATUS_BAD_FUNCTION 0x22 2091#define SRB_STATUS_ERROR_RECOVERY 0x23 2092#define SRB_STATUS_NOT_STARTED 0x24 2093#define SRB_STATUS_NOT_IN_USE 0x30 2094#define SRB_STATUS_FORCE_ABORT 0x31 2095#define SRB_STATUS_DOMAIN_VALIDATION_FAIL 0x32 2096 2097/* 2098 * Object-Server / Volume-Manager Dispatch Classes 2099 */ 2100 2101#define VM_Null 0 2102#define VM_NameServe 1 2103#define VM_ContainerConfig 2 2104#define VM_Ioctl 3 2105#define VM_FilesystemIoctl 4 2106#define VM_CloseAll 5 2107#define VM_CtBlockRead 6 2108#define VM_CtBlockWrite 7 2109#define VM_SliceBlockRead 8 /* raw access to configured "storage objects" */ 2110#define VM_SliceBlockWrite 9 2111#define VM_DriveBlockRead 10 /* raw access to physical devices */ 2112#define VM_DriveBlockWrite 11 2113#define VM_EnclosureMgt 12 /* enclosure management */ 2114#define VM_Unused 13 /* used to be diskset management */ 2115#define VM_CtBlockVerify 14 2116#define VM_CtPerf 15 /* performance test */ 2117#define VM_CtBlockRead64 16 2118#define VM_CtBlockWrite64 17 2119#define VM_CtBlockVerify64 18 2120#define VM_CtHostRead64 19 2121#define VM_CtHostWrite64 20 2122#define VM_DrvErrTblLog 21 2123#define VM_NameServe64 22 2124#define VM_NameServeAllBlk 30 2125 2126#define MAX_VMCOMMAND_NUM 23 /* used for sizing stats array - leave last */ 2127 2128/* 2129 * Descriptive information (eg, vital stats) 2130 * that a content manager might report. The 2131 * FileArray filesystem component is one example 2132 * of a content manager. Raw mode might be 2133 * another. 2134 */ 2135 2136struct aac_fsinfo { 2137 __le32 fsTotalSize; /* Consumed by fs, incl. metadata */ 2138 __le32 fsBlockSize; 2139 __le32 fsFragSize; 2140 __le32 fsMaxExtendSize; 2141 __le32 fsSpaceUnits; 2142 __le32 fsMaxNumFiles; 2143 __le32 fsNumFreeFiles; 2144 __le32 fsInodeDensity; 2145}; /* valid iff ObjType == FT_FILESYS && !(ContentState & FSCS_NOTCLEAN) */ 2146 2147struct aac_blockdevinfo { 2148 __le32 block_size; 2149 __le32 logical_phys_map; 2150 u8 identifier[16]; 2151}; 2152 2153union aac_contentinfo { 2154 struct aac_fsinfo filesys; 2155 struct aac_blockdevinfo bdevinfo; 2156}; 2157 2158/* 2159 * Query for Container Configuration Status 2160 */ 2161 2162#define CT_GET_CONFIG_STATUS 147 2163struct aac_get_config_status { 2164 __le32 command; /* VM_ContainerConfig */ 2165 __le32 type; /* CT_GET_CONFIG_STATUS */ 2166 __le32 parm1; 2167 __le32 parm2; 2168 __le32 parm3; 2169 __le32 parm4; 2170 __le32 parm5; 2171 __le32 count; /* sizeof(((struct aac_get_config_status_resp *)NULL)->data) */ 2172}; 2173 2174#define CFACT_CONTINUE 0 2175#define CFACT_PAUSE 1 2176#define CFACT_ABORT 2 2177struct aac_get_config_status_resp { 2178 __le32 response; /* ST_OK */ 2179 __le32 dummy0; 2180 __le32 status; /* CT_OK */ 2181 __le32 parm1; 2182 __le32 parm2; 2183 __le32 parm3; 2184 __le32 parm4; 2185 __le32 parm5; 2186 struct { 2187 __le32 action; /* CFACT_CONTINUE, CFACT_PAUSE or CFACT_ABORT */ 2188 __le16 flags; 2189 __le16 count; 2190 } data; 2191}; 2192 2193/* 2194 * Accept the configuration as-is 2195 */ 2196 2197#define CT_COMMIT_CONFIG 152 2198 2199struct aac_commit_config { 2200 __le32 command; /* VM_ContainerConfig */ 2201 __le32 type; /* CT_COMMIT_CONFIG */ 2202}; 2203 2204/* 2205 * Query for Container Configuration Status 2206 */ 2207 2208#define CT_GET_CONTAINER_COUNT 4 2209struct aac_get_container_count { 2210 __le32 command; /* VM_ContainerConfig */ 2211 __le32 type; /* CT_GET_CONTAINER_COUNT */ 2212}; 2213 2214struct aac_get_container_count_resp { 2215 __le32 response; /* ST_OK */ 2216 __le32 dummy0; 2217 __le32 MaxContainers; 2218 __le32 ContainerSwitchEntries; 2219 __le32 MaxPartitions; 2220 __le32 MaxSimpleVolumes; 2221}; 2222 2223 2224/* 2225 * Query for "mountable" objects, ie, objects that are typically 2226 * associated with a drive letter on the client (host) side. 2227 */ 2228 2229struct aac_mntent { 2230 __le32 oid; 2231 u8 name[16]; /* if applicable */ 2232 struct creation_info create_info; /* if applicable */ 2233 __le32 capacity; 2234 __le32 vol; /* substrate structure */ 2235 __le32 obj; /* FT_FILESYS, etc. */ 2236 __le32 state; /* unready for mounting, 2237 readonly, etc. */ 2238 union aac_contentinfo fileinfo; /* Info specific to content 2239 manager (eg, filesystem) */ 2240 __le32 altoid; /* != oid <==> snapshot or 2241 broken mirror exists */ 2242 __le32 capacityhigh; 2243}; 2244 2245#define FSCS_NOTCLEAN 0x0001 /* fsck is necessary before mounting */ 2246#define FSCS_READONLY 0x0002 /* possible result of broken mirror */ 2247#define FSCS_HIDDEN 0x0004 /* should be ignored - set during a clear */ 2248#define FSCS_NOT_READY 0x0008 /* Array spinning up to fulfil request */ 2249 2250struct aac_query_mount { 2251 __le32 command; 2252 __le32 type; 2253 __le32 count; 2254}; 2255 2256struct aac_mount { 2257 __le32 status; 2258 __le32 type; /* should be same as that requested */ 2259 __le32 count; 2260 struct aac_mntent mnt[1]; 2261}; 2262 2263#define CT_READ_NAME 130 2264struct aac_get_name { 2265 __le32 command; /* VM_ContainerConfig */ 2266 __le32 type; /* CT_READ_NAME */ 2267 __le32 cid; 2268 __le32 parm1; 2269 __le32 parm2; 2270 __le32 parm3; 2271 __le32 parm4; 2272 __le32 count; /* sizeof(((struct aac_get_name_resp *)NULL)->data) */ 2273}; 2274 2275struct aac_get_name_resp { 2276 __le32 dummy0; 2277 __le32 dummy1; 2278 __le32 status; /* CT_OK */ 2279 __le32 parm1; 2280 __le32 parm2; 2281 __le32 parm3; 2282 __le32 parm4; 2283 __le32 parm5; 2284 u8 data[17]; 2285}; 2286 2287#define CT_CID_TO_32BITS_UID 165 2288struct aac_get_serial { 2289 __le32 command; /* VM_ContainerConfig */ 2290 __le32 type; /* CT_CID_TO_32BITS_UID */ 2291 __le32 cid; 2292}; 2293 2294struct aac_get_serial_resp { 2295 __le32 dummy0; 2296 __le32 dummy1; 2297 __le32 status; /* CT_OK */ 2298 __le32 uid; 2299}; 2300 2301/* 2302 * The following command is sent to shut down each container. 2303 */ 2304 2305struct aac_close { 2306 __le32 command; 2307 __le32 cid; 2308}; 2309 2310struct aac_query_disk 2311{ 2312 s32 cnum; 2313 s32 bus; 2314 s32 id; 2315 s32 lun; 2316 u32 valid; 2317 u32 locked; 2318 u32 deleted; 2319 s32 instance; 2320 s8 name[10]; 2321 u32 unmapped; 2322}; 2323 2324struct aac_delete_disk { 2325 u32 disknum; 2326 u32 cnum; 2327}; 2328 2329struct fib_ioctl 2330{ 2331 u32 fibctx; 2332 s32 wait; 2333 char __user *fib; 2334}; 2335 2336struct revision 2337{ 2338 u32 compat; 2339 __le32 version; 2340 __le32 build; 2341}; 2342 2343 2344/* 2345 * Ugly - non Linux like ioctl coding for back compat. 2346 */ 2347 2348#define CTL_CODE(function, method) ( \ 2349 (4<< 16) | ((function) << 2) | (method) \ 2350) 2351 2352/* 2353 * Define the method codes for how buffers are passed for I/O and FS 2354 * controls 2355 */ 2356 2357#define METHOD_BUFFERED 0 2358#define METHOD_NEITHER 3 2359 2360/* 2361 * Filesystem ioctls 2362 */ 2363 2364#define FSACTL_SENDFIB CTL_CODE(2050, METHOD_BUFFERED) 2365#define FSACTL_SEND_RAW_SRB CTL_CODE(2067, METHOD_BUFFERED) 2366#define FSACTL_DELETE_DISK 0x163 2367#define FSACTL_QUERY_DISK 0x173 2368#define FSACTL_OPEN_GET_ADAPTER_FIB CTL_CODE(2100, METHOD_BUFFERED) 2369#define FSACTL_GET_NEXT_ADAPTER_FIB CTL_CODE(2101, METHOD_BUFFERED) 2370#define FSACTL_CLOSE_GET_ADAPTER_FIB CTL_CODE(2102, METHOD_BUFFERED) 2371#define FSACTL_MINIPORT_REV_CHECK CTL_CODE(2107, METHOD_BUFFERED) 2372#define FSACTL_GET_PCI_INFO CTL_CODE(2119, METHOD_BUFFERED) 2373#define FSACTL_FORCE_DELETE_DISK CTL_CODE(2120, METHOD_NEITHER) 2374#define FSACTL_GET_CONTAINERS 2131 2375#define FSACTL_SEND_LARGE_FIB CTL_CODE(2138, METHOD_BUFFERED) 2376#define FSACTL_RESET_IOP CTL_CODE(2140, METHOD_BUFFERED) 2377#define FSACTL_GET_HBA_INFO CTL_CODE(2150, METHOD_BUFFERED) 2378/* flags defined for IOP & HW SOFT RESET */ 2379#define HW_IOP_RESET 0x01 2380#define HW_SOFT_RESET 0x02 2381#define IOP_HWSOFT_RESET (HW_IOP_RESET | HW_SOFT_RESET) 2382/* HW Soft Reset register offset */ 2383#define IBW_SWR_OFFSET 0x4000 2384#define SOFT_RESET_TIME 60 2385 2386 2387 2388struct aac_common 2389{ 2390 /* 2391 * If this value is set to 1 then interrupt moderation will occur 2392 * in the base commuication support. 2393 */ 2394 u32 irq_mod; 2395 u32 peak_fibs; 2396 u32 zero_fibs; 2397 u32 fib_timeouts; 2398 /* 2399 * Statistical counters in debug mode 2400 */ 2401#ifdef DBG 2402 u32 FibsSent; 2403 u32 FibRecved; 2404 u32 NativeSent; 2405 u32 NativeRecved; 2406 u32 NoResponseSent; 2407 u32 NoResponseRecved; 2408 u32 AsyncSent; 2409 u32 AsyncRecved; 2410 u32 NormalSent; 2411 u32 NormalRecved; 2412#endif 2413}; 2414 2415extern struct aac_common aac_config; 2416 2417/* 2418 * This is for management ioctl purpose only. 2419 */ 2420struct aac_hba_info { 2421 2422 u8 driver_name[50]; 2423 u8 adapter_number; 2424 u8 system_io_bus_number; 2425 u8 device_number; 2426 u32 function_number; 2427 u32 vendor_id; 2428 u32 device_id; 2429 u32 sub_vendor_id; 2430 u32 sub_system_id; 2431 u32 mapped_base_address_size; 2432 u32 base_physical_address_high_part; 2433 u32 base_physical_address_low_part; 2434 2435 u32 max_command_size; 2436 u32 max_fib_size; 2437 u32 max_scatter_gather_from_os; 2438 u32 max_scatter_gather_to_fw; 2439 u32 max_outstanding_fibs; 2440 2441 u32 queue_start_threshold; 2442 u32 queue_dump_threshold; 2443 u32 max_io_size_queued; 2444 u32 outstanding_io; 2445 2446 u32 firmware_build_number; 2447 u32 bios_build_number; 2448 u32 driver_build_number; 2449 u32 serial_number_high_part; 2450 u32 serial_number_low_part; 2451 u32 supported_options; 2452 u32 feature_bits; 2453 u32 currentnumber_ports; 2454 2455 u8 new_comm_interface:1; 2456 u8 new_commands_supported:1; 2457 u8 disable_passthrough:1; 2458 u8 expose_non_dasd:1; 2459 u8 queue_allowed:1; 2460 u8 bled_check_enabled:1; 2461 u8 reserved1:1; 2462 u8 reserted2:1; 2463 2464 u32 reserved3[10]; 2465 2466}; 2467 2468/* 2469 * The following macro is used when sending and receiving FIBs. It is 2470 * only used for debugging. 2471 */ 2472 2473#ifdef DBG 2474#define FIB_COUNTER_INCREMENT(counter) (counter)++ 2475#else 2476#define FIB_COUNTER_INCREMENT(counter) 2477#endif 2478 2479/* 2480 * Adapter direct commands 2481 * Monitor/Kernel API 2482 */ 2483 2484#define BREAKPOINT_REQUEST 0x00000004 2485#define INIT_STRUCT_BASE_ADDRESS 0x00000005 2486#define READ_PERMANENT_PARAMETERS 0x0000000a 2487#define WRITE_PERMANENT_PARAMETERS 0x0000000b 2488#define HOST_CRASHING 0x0000000d 2489#define SEND_SYNCHRONOUS_FIB 0x0000000c 2490#define COMMAND_POST_RESULTS 0x00000014 2491#define GET_ADAPTER_PROPERTIES 0x00000019 2492#define GET_DRIVER_BUFFER_PROPERTIES 0x00000023 2493#define RCV_TEMP_READINGS 0x00000025 2494#define GET_COMM_PREFERRED_SETTINGS 0x00000026 2495#define IOP_RESET_FW_FIB_DUMP 0x00000034 2496#define DROP_IO 0x00000035 2497#define IOP_RESET 0x00001000 2498#define IOP_RESET_ALWAYS 0x00001001 2499#define RE_INIT_ADAPTER 0x000000ee 2500 2501#define IOP_SRC_RESET_MASK 0x00000100 2502 2503/* 2504 * Adapter Status Register 2505 * 2506 * Phase Staus mailbox is 32bits: 2507 * <31:16> = Phase Status 2508 * <15:0> = Phase 2509 * 2510 * The adapter reports is present state through the phase. Only 2511 * a single phase should be ever be set. Each phase can have multiple 2512 * phase status bits to provide more detailed information about the 2513 * state of the board. Care should be taken to ensure that any phase 2514 * status bits that are set when changing the phase are also valid 2515 * for the new phase or be cleared out. Adapter software (monitor, 2516 * iflash, kernel) is responsible for properly maintining the phase 2517 * status mailbox when it is running. 2518 * 2519 * MONKER_API Phases 2520 * 2521 * Phases are bit oriented. It is NOT valid to have multiple bits set 2522 */ 2523 2524#define SELF_TEST_FAILED 0x00000004 2525#define MONITOR_PANIC 0x00000020 2526#define KERNEL_BOOTING 0x00000040 2527#define KERNEL_UP_AND_RUNNING 0x00000080 2528#define KERNEL_PANIC 0x00000100 2529#define FLASH_UPD_PENDING 0x00002000 2530#define FLASH_UPD_SUCCESS 0x00004000 2531#define FLASH_UPD_FAILED 0x00008000 2532#define INVALID_OMR 0xffffffff 2533#define FWUPD_TIMEOUT (5 * 60) 2534 2535/* 2536 * Doorbell bit defines 2537 */ 2538 2539#define DoorBellSyncCmdAvailable (1<<0) /* Host -> Adapter */ 2540#define DoorBellPrintfDone (1<<5) /* Host -> Adapter */ 2541#define DoorBellAdapterNormCmdReady (1<<1) /* Adapter -> Host */ 2542#define DoorBellAdapterNormRespReady (1<<2) /* Adapter -> Host */ 2543#define DoorBellAdapterNormCmdNotFull (1<<3) /* Adapter -> Host */ 2544#define DoorBellAdapterNormRespNotFull (1<<4) /* Adapter -> Host */ 2545#define DoorBellPrintfReady (1<<5) /* Adapter -> Host */ 2546#define DoorBellAifPending (1<<6) /* Adapter -> Host */ 2547 2548/* PMC specific outbound doorbell bits */ 2549#define PmDoorBellResponseSent (1<<1) /* Adapter -> Host */ 2550 2551/* 2552 * For FIB communication, we need all of the following things 2553 * to send back to the user. 2554 */ 2555 2556#define AifCmdEventNotify 1 /* Notify of event */ 2557#define AifEnConfigChange 3 /* Adapter configuration change */ 2558#define AifEnContainerChange 4 /* Container configuration change */ 2559#define AifEnDeviceFailure 5 /* SCSI device failed */ 2560#define AifEnEnclosureManagement 13 /* EM_DRIVE_* */ 2561#define EM_DRIVE_INSERTION 31 2562#define EM_DRIVE_REMOVAL 32 2563#define EM_SES_DRIVE_INSERTION 33 2564#define EM_SES_DRIVE_REMOVAL 26 2565#define AifEnBatteryEvent 14 /* Change in Battery State */ 2566#define AifEnAddContainer 15 /* A new array was created */ 2567#define AifEnDeleteContainer 16 /* A container was deleted */ 2568#define AifEnExpEvent 23 /* Firmware Event Log */ 2569#define AifExeFirmwarePanic 3 /* Firmware Event Panic */ 2570#define AifHighPriority 3 /* Highest Priority Event */ 2571#define AifEnAddJBOD 30 /* JBOD created */ 2572#define AifEnDeleteJBOD 31 /* JBOD deleted */ 2573 2574#define AifBuManagerEvent 42 /* Bu management*/ 2575#define AifBuCacheDataLoss 10 2576#define AifBuCacheDataRecover 11 2577 2578#define AifCmdJobProgress 2 /* Progress report */ 2579#define AifJobCtrZero 101 /* Array Zero progress */ 2580#define AifJobStsSuccess 1 /* Job completes */ 2581#define AifJobStsRunning 102 /* Job running */ 2582#define AifCmdAPIReport 3 /* Report from other user of API */ 2583#define AifCmdDriverNotify 4 /* Notify host driver of event */ 2584#define AifDenMorphComplete 200 /* A morph operation completed */ 2585#define AifDenVolumeExtendComplete 201 /* A volume extend completed */ 2586#define AifReqJobList 100 /* Gets back complete job list */ 2587#define AifReqJobsForCtr 101 /* Gets back jobs for specific container */ 2588#define AifReqJobsForScsi 102 /* Gets back jobs for specific SCSI device */ 2589#define AifReqJobReport 103 /* Gets back a specific job report or list of them */ 2590#define AifReqTerminateJob 104 /* Terminates job */ 2591#define AifReqSuspendJob 105 /* Suspends a job */ 2592#define AifReqResumeJob 106 /* Resumes a job */ 2593#define AifReqSendAPIReport 107 /* API generic report requests */ 2594#define AifReqAPIJobStart 108 /* Start a job from the API */ 2595#define AifReqAPIJobUpdate 109 /* Update a job report from the API */ 2596#define AifReqAPIJobFinish 110 /* Finish a job from the API */ 2597 2598/* PMC NEW COMM: Request the event data */ 2599#define AifReqEvent 200 2600#define AifRawDeviceRemove 203 /* RAW device deleted */ 2601#define AifNativeDeviceAdd 204 /* native HBA device added */ 2602#define AifNativeDeviceRemove 205 /* native HBA device removed */ 2603 2604 2605/* 2606 * Adapter Initiated FIB command structures. Start with the adapter 2607 * initiated FIBs that really come from the adapter, and get responded 2608 * to by the host. 2609 */ 2610 2611struct aac_aifcmd { 2612 __le32 command; /* Tell host what type of notify this is */ 2613 __le32 seqnum; /* To allow ordering of reports (if necessary) */ 2614 u8 data[]; /* Undefined length (from kernel viewpoint) */ 2615}; 2616 2617/** 2618 * Convert capacity to cylinders 2619 * accounting for the fact capacity could be a 64 bit value 2620 * 2621 */ 2622static inline unsigned int cap_to_cyls(sector_t capacity, unsigned divisor) 2623{ 2624 sector_div(capacity, divisor); 2625 return capacity; 2626} 2627 2628static inline int aac_pci_offline(struct aac_dev *dev) 2629{ 2630 return pci_channel_offline(dev->pdev) || dev->handle_pci_error; 2631} 2632 2633static inline int aac_adapter_check_health(struct aac_dev *dev) 2634{ 2635 if (unlikely(aac_pci_offline(dev))) 2636 return -1; 2637 2638 return (dev)->a_ops.adapter_check_health(dev); 2639} 2640 2641 2642int aac_scan_host(struct aac_dev *dev); 2643 2644static inline void aac_schedule_safw_scan_worker(struct aac_dev *dev) 2645{ 2646 schedule_delayed_work(&dev->safw_rescan_work, AAC_RESCAN_DELAY); 2647} 2648 2649static inline void aac_schedule_src_reinit_aif_worker(struct aac_dev *dev) 2650{ 2651 schedule_delayed_work(&dev->src_reinit_aif_worker, AAC_RESCAN_DELAY); 2652} 2653 2654static inline void aac_safw_rescan_worker(struct work_struct *work) 2655{ 2656 struct aac_dev *dev = container_of(to_delayed_work(work), 2657 struct aac_dev, safw_rescan_work); 2658 2659 wait_event(dev->scsi_host_ptr->host_wait, 2660 !scsi_host_in_recovery(dev->scsi_host_ptr)); 2661 2662 aac_scan_host(dev); 2663} 2664 2665static inline void aac_cancel_rescan_worker(struct aac_dev *dev) 2666{ 2667 cancel_delayed_work_sync(&dev->safw_rescan_work); 2668 cancel_delayed_work_sync(&dev->src_reinit_aif_worker); 2669} 2670 2671enum aac_cmd_owner { 2672 AAC_OWNER_MIDLEVEL = 0x101, 2673 AAC_OWNER_LOWLEVEL = 0x102, 2674 AAC_OWNER_ERROR_HANDLER = 0x103, 2675 AAC_OWNER_FIRMWARE = 0x106, 2676}; 2677 2678struct aac_cmd_priv { 2679 int (*callback)(struct scsi_cmnd *); 2680 int status; 2681 enum aac_cmd_owner owner; 2682 bool sent_command; 2683}; 2684 2685static inline struct aac_cmd_priv *aac_priv(struct scsi_cmnd *cmd) 2686{ 2687 return scsi_cmd_priv(cmd); 2688} 2689 2690void aac_safw_rescan_worker(struct work_struct *work); 2691void aac_src_reinit_aif_worker(struct work_struct *work); 2692int aac_acquire_irq(struct aac_dev *dev); 2693void aac_free_irq(struct aac_dev *dev); 2694int aac_setup_safw_adapter(struct aac_dev *dev); 2695const char *aac_driverinfo(struct Scsi_Host *); 2696void aac_fib_vector_assign(struct aac_dev *dev); 2697struct fib *aac_fib_alloc(struct aac_dev *dev); 2698struct fib *aac_fib_alloc_tag(struct aac_dev *dev, struct scsi_cmnd *scmd); 2699int aac_fib_setup(struct aac_dev *dev); 2700void aac_fib_map_free(struct aac_dev *dev); 2701void aac_fib_free(struct fib * context); 2702void aac_fib_init(struct fib * context); 2703void aac_printf(struct aac_dev *dev, u32 val); 2704int aac_fib_send(u16 command, struct fib * context, unsigned long size, int priority, int wait, int reply, fib_callback callback, void *ctxt); 2705int aac_hba_send(u8 command, struct fib *context, 2706 fib_callback callback, void *ctxt); 2707int aac_consumer_get(struct aac_dev * dev, struct aac_queue * q, struct aac_entry **entry); 2708void aac_consumer_free(struct aac_dev * dev, struct aac_queue * q, u32 qnum); 2709int aac_fib_complete(struct fib * context); 2710void aac_hba_callback(void *context, struct fib *fibptr); 2711#define fib_data(fibctx) ((void *)(fibctx)->hw_fib_va->data) 2712struct aac_dev *aac_init_adapter(struct aac_dev *dev); 2713void aac_src_access_devreg(struct aac_dev *dev, int mode); 2714void aac_set_intx_mode(struct aac_dev *dev); 2715int aac_get_config_status(struct aac_dev *dev, int commit_flag); 2716int aac_get_containers(struct aac_dev *dev); 2717int aac_scsi_cmd(struct scsi_cmnd *cmd); 2718int aac_dev_ioctl(struct aac_dev *dev, unsigned int cmd, void __user *arg); 2719#ifndef shost_to_class 2720#define shost_to_class(shost) &shost->shost_dev 2721#endif 2722ssize_t aac_get_serial_number(struct device *dev, char *buf); 2723int aac_do_ioctl(struct aac_dev *dev, unsigned int cmd, void __user *arg); 2724int aac_rx_init(struct aac_dev *dev); 2725int aac_rkt_init(struct aac_dev *dev); 2726int aac_nark_init(struct aac_dev *dev); 2727int aac_sa_init(struct aac_dev *dev); 2728int aac_src_init(struct aac_dev *dev); 2729int aac_srcv_init(struct aac_dev *dev); 2730int aac_queue_get(struct aac_dev * dev, u32 * index, u32 qid, struct hw_fib * hw_fib, int wait, struct fib * fibptr, unsigned long *nonotify); 2731void aac_define_int_mode(struct aac_dev *dev); 2732unsigned int aac_response_normal(struct aac_queue * q); 2733unsigned int aac_command_normal(struct aac_queue * q); 2734unsigned int aac_intr_normal(struct aac_dev *dev, u32 Index, 2735 int isAif, int isFastResponse, 2736 struct hw_fib *aif_fib); 2737int aac_reset_adapter(struct aac_dev *dev, int forced, u8 reset_type); 2738int aac_command_thread(void *data); 2739int aac_close_fib_context(struct aac_dev * dev, struct aac_fib_context *fibctx); 2740int aac_fib_adapter_complete(struct fib * fibptr, unsigned short size); 2741struct aac_driver_ident* aac_get_driver_ident(int devtype); 2742int aac_get_adapter_info(struct aac_dev* dev); 2743int aac_send_shutdown(struct aac_dev *dev); 2744int aac_probe_container(struct aac_dev *dev, int cid); 2745int _aac_rx_init(struct aac_dev *dev); 2746int aac_rx_select_comm(struct aac_dev *dev, int comm); 2747int aac_rx_deliver_producer(struct fib * fib); 2748void aac_reinit_aif(struct aac_dev *aac, unsigned int index); 2749 2750static inline int aac_is_src(struct aac_dev *dev) 2751{ 2752 u16 device = dev->pdev->device; 2753 2754 if (device == PMC_DEVICE_S6 || 2755 device == PMC_DEVICE_S7 || 2756 device == PMC_DEVICE_S8) 2757 return 1; 2758 return 0; 2759} 2760 2761static inline int aac_supports_2T(struct aac_dev *dev) 2762{ 2763 return (dev->adapter_info.options & AAC_OPT_NEW_COMM_64); 2764} 2765 2766char * get_container_type(unsigned type); 2767extern int numacb; 2768extern char aac_driver_version[]; 2769extern int startup_timeout; 2770extern int aif_timeout; 2771extern int expose_physicals; 2772extern int aac_reset_devices; 2773extern int aac_msi; 2774extern int aac_commit; 2775extern int update_interval; 2776extern int check_interval; 2777extern int aac_check_reset; 2778extern int aac_fib_dump; 2779#endif
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