rtc-pcf85063.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * An I2C driver for the PCF85063 RTC
  4 * Copyright 2014 Rose Technology
  5 *
  6 * Author: Søren Andersen <san@rosetechnology.dk>
  7 * Maintainers: http://www.nslu2-linux.org/
  8 *
  9 * Copyright (C) 2019 Micro Crystal AG
 10 * Author: Alexandre Belloni <alexandre.belloni@bootlin.com>
 11 */
 12#include <linux/clk-provider.h>
 13#include <linux/i2c.h>
 14#include <linux/bcd.h>
 15#include <linux/rtc.h>
 16#include <linux/module.h>
 17#include <linux/of.h>
 18#include <linux/pm_wakeirq.h>
 19#include <linux/regmap.h>
 20#include <linux/spi/spi.h>
 21
 22/*
 23 * Information for this driver was pulled from the following datasheets.
 24 *
 25 *  https://www.nxp.com/docs/en/data-sheet/PCF85063A.pdf
 26 *  https://www.nxp.com/docs/en/data-sheet/PCF85063TP.pdf
 27 *
 28 *  PCF85063A -- Rev. 7 — 30 March 2018
 29 *  PCF85063TP -- Rev. 4 — 6 May 2015
 30 *
 31 *  https://www.microcrystal.com/fileadmin/Media/Products/RTC/App.Manual/RV-8263-C7_App-Manual.pdf
 32 *  RV8263 -- Rev. 1.0 — January 2019
 33 *
 34 *  https://www.microcrystal.com/fileadmin/Media/Products/RTC/App.Manual/RV-8063-C7_App-Manual.pdf
 35 *  RV8063 -- Rev. 1.1 - October 2018
 36 */
 37
 38#define PCF85063_REG_CTRL1		0x00 /* status */
 39#define PCF85063_REG_CTRL1_CAP_SEL	BIT(0)
 40#define PCF85063_REG_CTRL1_STOP		BIT(5)
 41#define PCF85063_REG_CTRL1_EXT_TEST	BIT(7)
 42#define PCF85063_REG_CTRL1_SWR		0x58
 43
 44#define PCF85063_REG_CTRL2		0x01
 45#define PCF85063_CTRL2_AF		BIT(6)
 46#define PCF85063_CTRL2_AIE		BIT(7)
 47
 48#define PCF85063_REG_OFFSET		0x02
 49#define PCF85063_OFFSET_SIGN_BIT	6	/* 2's complement sign bit */
 50#define PCF85063_OFFSET_MODE		BIT(7)
 51#define PCF85063_OFFSET_STEP0		4340
 52#define PCF85063_OFFSET_STEP1		4069
 53
 54#define PCF85063_REG_CLKO_F_MASK	0x07 /* frequency mask */
 55#define PCF85063_REG_CLKO_F_32768HZ	0x00
 56#define PCF85063_REG_CLKO_F_OFF		0x07
 57
 58#define PCF85063_REG_RAM		0x03
 59
 60#define PCF85063_REG_SC			0x04 /* datetime */
 61#define PCF85063_REG_SC_OS		0x80
 62
 63#define PCF85063_REG_ALM_S		0x0b
 64#define PCF85063_AEN			BIT(7)
 65
 66struct pcf85063_config {
 67	struct regmap_config regmap;
 68	unsigned has_alarms:1;
 69	unsigned force_cap_7000:1;
 70};
 71
 72struct pcf85063 {
 73	struct rtc_device	*rtc;
 74	struct regmap		*regmap;
 75#ifdef CONFIG_COMMON_CLK
 76	struct clk_hw		clkout_hw;
 77#endif
 78};
 79
 80static int pcf85063_rtc_read_time(struct device *dev, struct rtc_time *tm)
 81{
 82	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
 83	int rc;
 84	u8 regs[7];
 85
 86	/*
 87	 * while reading, the time/date registers are blocked and not updated
 88	 * anymore until the access is finished. To not lose a second
 89	 * event, the access must be finished within one second. So, read all
 90	 * time/date registers in one turn.
 91	 */
 92	rc = regmap_bulk_read(pcf85063->regmap, PCF85063_REG_SC, regs,
 93			      sizeof(regs));
 94	if (rc)
 95		return rc;
 96
 97	/* if the clock has lost its power it makes no sense to use its time */
 98	if (regs[0] & PCF85063_REG_SC_OS) {
 99		dev_warn(&pcf85063->rtc->dev, "Power loss detected, invalid time\n");
100		return -EINVAL;
101	}
102
103	tm->tm_sec = bcd2bin(regs[0] & 0x7F);
104	tm->tm_min = bcd2bin(regs[1] & 0x7F);
105	tm->tm_hour = bcd2bin(regs[2] & 0x3F); /* rtc hr 0-23 */
106	tm->tm_mday = bcd2bin(regs[3] & 0x3F);
107	tm->tm_wday = regs[4] & 0x07;
108	tm->tm_mon = bcd2bin(regs[5] & 0x1F) - 1; /* rtc mn 1-12 */
109	tm->tm_year = bcd2bin(regs[6]);
110	tm->tm_year += 100;
111
112	return 0;
113}
114
115static int pcf85063_rtc_set_time(struct device *dev, struct rtc_time *tm)
116{
117	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
118	int rc;
119	u8 regs[7];
120
121	/*
122	 * to accurately set the time, reset the divider chain and keep it in
123	 * reset state until all time/date registers are written
124	 */
125	rc = regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
126				PCF85063_REG_CTRL1_EXT_TEST |
127				PCF85063_REG_CTRL1_STOP,
128				PCF85063_REG_CTRL1_STOP);
129	if (rc)
130		return rc;
131
132	/* hours, minutes and seconds */
133	regs[0] = bin2bcd(tm->tm_sec) & 0x7F; /* clear OS flag */
134
135	regs[1] = bin2bcd(tm->tm_min);
136	regs[2] = bin2bcd(tm->tm_hour);
137
138	/* Day of month, 1 - 31 */
139	regs[3] = bin2bcd(tm->tm_mday);
140
141	/* Day, 0 - 6 */
142	regs[4] = tm->tm_wday & 0x07;
143
144	/* month, 1 - 12 */
145	regs[5] = bin2bcd(tm->tm_mon + 1);
146
147	/* year and century */
148	regs[6] = bin2bcd(tm->tm_year - 100);
149
150	/* write all registers at once */
151	rc = regmap_bulk_write(pcf85063->regmap, PCF85063_REG_SC,
152			       regs, sizeof(regs));
153	if (rc)
154		return rc;
155
156	/*
157	 * Write the control register as a separate action since the size of
158	 * the register space is different between the PCF85063TP and
159	 * PCF85063A devices.  The rollover point can not be used.
160	 */
161	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
162				  PCF85063_REG_CTRL1_STOP, 0);
163}
164
165static int pcf85063_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
166{
167	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
168	u8 buf[4];
169	unsigned int val;
170	int ret;
171
172	ret = regmap_bulk_read(pcf85063->regmap, PCF85063_REG_ALM_S,
173			       buf, sizeof(buf));
174	if (ret)
175		return ret;
176
177	alrm->time.tm_sec = bcd2bin(buf[0] & 0x7f);
178	alrm->time.tm_min = bcd2bin(buf[1] & 0x7f);
179	alrm->time.tm_hour = bcd2bin(buf[2] & 0x3f);
180	alrm->time.tm_mday = bcd2bin(buf[3] & 0x3f);
181
182	ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &val);
183	if (ret)
184		return ret;
185
186	alrm->enabled =  !!(val & PCF85063_CTRL2_AIE);
187
188	return 0;
189}
190
191static int pcf85063_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
192{
193	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
194	u8 buf[5];
195	int ret;
196
197	buf[0] = bin2bcd(alrm->time.tm_sec);
198	buf[1] = bin2bcd(alrm->time.tm_min);
199	buf[2] = bin2bcd(alrm->time.tm_hour);
200	buf[3] = bin2bcd(alrm->time.tm_mday);
201	buf[4] = PCF85063_AEN; /* Do not match on week day */
202
203	ret = regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
204				 PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF, 0);
205	if (ret)
206		return ret;
207
208	ret = regmap_bulk_write(pcf85063->regmap, PCF85063_REG_ALM_S,
209				buf, sizeof(buf));
210	if (ret)
211		return ret;
212
213	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
214				  PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF,
215				  alrm->enabled ? PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF : PCF85063_CTRL2_AF);
216}
217
218static int pcf85063_rtc_alarm_irq_enable(struct device *dev,
219					 unsigned int enabled)
220{
221	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
222
223	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
224				  PCF85063_CTRL2_AIE,
225				  enabled ? PCF85063_CTRL2_AIE : 0);
226}
227
228static irqreturn_t pcf85063_rtc_handle_irq(int irq, void *dev_id)
229{
230	struct pcf85063 *pcf85063 = dev_id;
231	unsigned int val;
232	int err;
233
234	err = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &val);
235	if (err)
236		return IRQ_NONE;
237
238	if (val & PCF85063_CTRL2_AF) {
239		rtc_update_irq(pcf85063->rtc, 1, RTC_IRQF | RTC_AF);
240		regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
241				   PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF,
242				   0);
243		return IRQ_HANDLED;
244	}
245
246	return IRQ_NONE;
247}
248
249static int pcf85063_read_offset(struct device *dev, long *offset)
250{
251	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
252	long val;
253	u32 reg;
254	int ret;
255
256	ret = regmap_read(pcf85063->regmap, PCF85063_REG_OFFSET, &reg);
257	if (ret < 0)
258		return ret;
259
260	val = sign_extend32(reg & ~PCF85063_OFFSET_MODE,
261			    PCF85063_OFFSET_SIGN_BIT);
262
263	if (reg & PCF85063_OFFSET_MODE)
264		*offset = val * PCF85063_OFFSET_STEP1;
265	else
266		*offset = val * PCF85063_OFFSET_STEP0;
267
268	return 0;
269}
270
271static int pcf85063_set_offset(struct device *dev, long offset)
272{
273	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
274	s8 mode0, mode1, reg;
275	unsigned int error0, error1;
276
277	if (offset > PCF85063_OFFSET_STEP0 * 63)
278		return -ERANGE;
279	if (offset < PCF85063_OFFSET_STEP0 * -64)
280		return -ERANGE;
281
282	mode0 = DIV_ROUND_CLOSEST(offset, PCF85063_OFFSET_STEP0);
283	mode1 = DIV_ROUND_CLOSEST(offset, PCF85063_OFFSET_STEP1);
284
285	error0 = abs(offset - (mode0 * PCF85063_OFFSET_STEP0));
286	error1 = abs(offset - (mode1 * PCF85063_OFFSET_STEP1));
287	if (mode1 > 63 || mode1 < -64 || error0 < error1)
288		reg = mode0 & ~PCF85063_OFFSET_MODE;
289	else
290		reg = mode1 | PCF85063_OFFSET_MODE;
291
292	return regmap_write(pcf85063->regmap, PCF85063_REG_OFFSET, reg);
293}
294
295static int pcf85063_ioctl(struct device *dev, unsigned int cmd,
296			  unsigned long arg)
297{
298	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
299	int status, ret = 0;
300
301	switch (cmd) {
302	case RTC_VL_READ:
303		ret = regmap_read(pcf85063->regmap, PCF85063_REG_SC, &status);
304		if (ret < 0)
305			return ret;
306
307		status = (status & PCF85063_REG_SC_OS) ? RTC_VL_DATA_INVALID : 0;
308
309		return put_user(status, (unsigned int __user *)arg);
310
311	default:
312		return -ENOIOCTLCMD;
313	}
314}
315
316static const struct rtc_class_ops pcf85063_rtc_ops = {
317	.read_time	= pcf85063_rtc_read_time,
318	.set_time	= pcf85063_rtc_set_time,
319	.read_offset	= pcf85063_read_offset,
320	.set_offset	= pcf85063_set_offset,
321	.read_alarm	= pcf85063_rtc_read_alarm,
322	.set_alarm	= pcf85063_rtc_set_alarm,
323	.alarm_irq_enable = pcf85063_rtc_alarm_irq_enable,
324	.ioctl		= pcf85063_ioctl,
325};
326
327static int pcf85063_nvmem_read(void *priv, unsigned int offset,
328			       void *val, size_t bytes)
329{
330	unsigned int tmp;
331	int ret;
332
333	ret = regmap_read(priv, PCF85063_REG_RAM, &tmp);
334	if (ret < 0)
335		return ret;
336
337	*(u8 *)val = tmp;
338
339	return 0;
340}
341
342static int pcf85063_nvmem_write(void *priv, unsigned int offset,
343				void *val, size_t bytes)
344{
345	return regmap_write(priv, PCF85063_REG_RAM, *(u8 *)val);
346}
347
348static int pcf85063_load_capacitance(struct pcf85063 *pcf85063,
349				     const struct device_node *np,
350				     unsigned int force_cap)
351{
352	u32 load = 7000;
353	u8 reg = 0;
354
355	if (force_cap)
356		load = force_cap;
357	else
358		of_property_read_u32(np, "quartz-load-femtofarads", &load);
359
360	switch (load) {
361	default:
362		dev_warn(&pcf85063->rtc->dev, "Unknown quartz-load-femtofarads value: %d. Assuming 7000",
363			 load);
364		fallthrough;
365	case 7000:
366		break;
367	case 12500:
368		reg = PCF85063_REG_CTRL1_CAP_SEL;
369		break;
370	}
371
372	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
373				  PCF85063_REG_CTRL1_CAP_SEL, reg);
374}
375
376#ifdef CONFIG_COMMON_CLK
377/*
378 * Handling of the clkout
379 */
380
381#define clkout_hw_to_pcf85063(_hw) container_of(_hw, struct pcf85063, clkout_hw)
382
383static int clkout_rates[] = {
384	32768,
385	16384,
386	8192,
387	4096,
388	2048,
389	1024,
390	1,
391	0
392};
393
394static unsigned long pcf85063_clkout_recalc_rate(struct clk_hw *hw,
395						 unsigned long parent_rate)
396{
397	struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
398	unsigned int buf;
399	int ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &buf);
400
401	if (ret < 0)
402		return 0;
403
404	buf &= PCF85063_REG_CLKO_F_MASK;
405	return clkout_rates[buf];
406}
407
408static int pcf85063_clkout_determine_rate(struct clk_hw *hw,
409					  struct clk_rate_request *req)
410{
411	int i;
412
413	for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
414		if (clkout_rates[i] <= req->rate) {
415			req->rate = clkout_rates[i];
416
417			return 0;
418		}
419
420	req->rate = clkout_rates[0];
421
422	return 0;
423}
424
425static int pcf85063_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
426				    unsigned long parent_rate)
427{
428	struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
429	int i;
430
431	for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
432		if (clkout_rates[i] == rate)
433			return regmap_update_bits(pcf85063->regmap,
434				PCF85063_REG_CTRL2,
435				PCF85063_REG_CLKO_F_MASK, i);
436
437	return -EINVAL;
438}
439
440static int pcf85063_clkout_control(struct clk_hw *hw, bool enable)
441{
442	struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
443	unsigned int buf;
444	int ret;
445
446	ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &buf);
447	if (ret < 0)
448		return ret;
449	buf &= PCF85063_REG_CLKO_F_MASK;
450
451	if (enable) {
452		if (buf == PCF85063_REG_CLKO_F_OFF)
453			buf = PCF85063_REG_CLKO_F_32768HZ;
454		else
455			return 0;
456	} else {
457		if (buf != PCF85063_REG_CLKO_F_OFF)
458			buf = PCF85063_REG_CLKO_F_OFF;
459		else
460			return 0;
461	}
462
463	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
464					PCF85063_REG_CLKO_F_MASK, buf);
465}
466
467static int pcf85063_clkout_prepare(struct clk_hw *hw)
468{
469	return pcf85063_clkout_control(hw, 1);
470}
471
472static void pcf85063_clkout_unprepare(struct clk_hw *hw)
473{
474	pcf85063_clkout_control(hw, 0);
475}
476
477static int pcf85063_clkout_is_prepared(struct clk_hw *hw)
478{
479	struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
480	unsigned int buf;
481	int ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &buf);
482
483	if (ret < 0)
484		return 0;
485
486	return (buf & PCF85063_REG_CLKO_F_MASK) != PCF85063_REG_CLKO_F_OFF;
487}
488
489static const struct clk_ops pcf85063_clkout_ops = {
490	.prepare = pcf85063_clkout_prepare,
491	.unprepare = pcf85063_clkout_unprepare,
492	.is_prepared = pcf85063_clkout_is_prepared,
493	.recalc_rate = pcf85063_clkout_recalc_rate,
494	.determine_rate = pcf85063_clkout_determine_rate,
495	.set_rate = pcf85063_clkout_set_rate,
496};
497
498static struct clk *pcf85063_clkout_register_clk(struct pcf85063 *pcf85063)
499{
500	struct clk *clk;
501	struct clk_init_data init;
502	struct device_node *node = pcf85063->rtc->dev.parent->of_node;
503	struct device_node *fixed_clock;
504
505	fixed_clock = of_get_child_by_name(node, "clock");
506	if (fixed_clock) {
507		/*
508		 * skip registering square wave clock when a fixed
509		 * clock has been registered. The fixed clock is
510		 * registered automatically when being referenced.
511		 */
512		of_node_put(fixed_clock);
513		return NULL;
514	}
515
516	init.name = "pcf85063-clkout";
517	init.ops = &pcf85063_clkout_ops;
518	init.flags = 0;
519	init.parent_names = NULL;
520	init.num_parents = 0;
521	pcf85063->clkout_hw.init = &init;
522
523	/* optional override of the clockname */
524	of_property_read_string(node, "clock-output-names", &init.name);
525
526	/* register the clock */
527	clk = devm_clk_register(&pcf85063->rtc->dev, &pcf85063->clkout_hw);
528
529	if (!IS_ERR(clk))
530		of_clk_add_provider(node, of_clk_src_simple_get, clk);
531
532	return clk;
533}
534#endif
535
536static int pcf85063_probe(struct device *dev, struct regmap *regmap, int irq,
537			  const struct pcf85063_config *config)
538{
539	struct pcf85063 *pcf85063;
540	unsigned int tmp;
541	int err;
542	struct nvmem_config nvmem_cfg = {
543		.name = "pcf85063_nvram",
544		.reg_read = pcf85063_nvmem_read,
545		.reg_write = pcf85063_nvmem_write,
546		.type = NVMEM_TYPE_BATTERY_BACKED,
547		.size = 1,
548	};
549
550	dev_dbg(dev, "%s\n", __func__);
551
552	pcf85063 = devm_kzalloc(dev, sizeof(struct pcf85063),
553				GFP_KERNEL);
554	if (!pcf85063)
555		return -ENOMEM;
556
557	pcf85063->regmap = regmap;
558
559	dev_set_drvdata(dev, pcf85063);
560
561	err = regmap_read(pcf85063->regmap, PCF85063_REG_SC, &tmp);
562	if (err)
563		return dev_err_probe(dev, err, "RTC chip is not present\n");
564
565	pcf85063->rtc = devm_rtc_allocate_device(dev);
566	if (IS_ERR(pcf85063->rtc))
567		return PTR_ERR(pcf85063->rtc);
568
569	/*
570	 * If a Power loss is detected, SW reset the device.
571	 * From PCF85063A datasheet:
572	 * There is a low probability that some devices will have corruption
573	 * of the registers after the automatic power-on reset...
574	 */
575	if (tmp & PCF85063_REG_SC_OS) {
576		dev_warn(dev, "POR issue detected, sending a SW reset\n");
577		err = regmap_write(pcf85063->regmap, PCF85063_REG_CTRL1,
578				   PCF85063_REG_CTRL1_SWR);
579		if (err < 0)
580			dev_warn(dev, "SW reset failed, trying to continue\n");
581	}
582
583	err = pcf85063_load_capacitance(pcf85063, dev->of_node,
584					config->force_cap_7000 ? 7000 : 0);
585	if (err < 0)
586		dev_warn(dev, "failed to set xtal load capacitance: %d",
587			 err);
588
589	pcf85063->rtc->ops = &pcf85063_rtc_ops;
590	pcf85063->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
591	pcf85063->rtc->range_max = RTC_TIMESTAMP_END_2099;
592	set_bit(RTC_FEATURE_ALARM_RES_2S, pcf85063->rtc->features);
593	clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, pcf85063->rtc->features);
594	clear_bit(RTC_FEATURE_ALARM, pcf85063->rtc->features);
595
596	if (config->has_alarms && irq > 0) {
597		unsigned long irqflags = IRQF_TRIGGER_LOW;
598
599		if (dev_fwnode(dev))
600			irqflags = 0;
601
602		err = devm_request_threaded_irq(dev, irq,
603						NULL, pcf85063_rtc_handle_irq,
604						irqflags | IRQF_ONESHOT,
605						"pcf85063", pcf85063);
606		if (err) {
607			dev_warn(&pcf85063->rtc->dev,
608				 "unable to request IRQ, alarms disabled\n");
609		} else {
610			set_bit(RTC_FEATURE_ALARM, pcf85063->rtc->features);
611			device_init_wakeup(dev, true);
612			err = dev_pm_set_wake_irq(dev, irq);
613			if (err)
614				dev_err(&pcf85063->rtc->dev,
615					"failed to enable irq wake\n");
616		}
617	}
618
619	nvmem_cfg.priv = pcf85063->regmap;
620	devm_rtc_nvmem_register(pcf85063->rtc, &nvmem_cfg);
621
622#ifdef CONFIG_COMMON_CLK
623	/* register clk in common clk framework */
624	pcf85063_clkout_register_clk(pcf85063);
625#endif
626
627	return devm_rtc_register_device(pcf85063->rtc);
628}
629
630#if IS_ENABLED(CONFIG_I2C)
631
632static const struct pcf85063_config config_pcf85063 = {
633	.regmap = {
634		.reg_bits = 8,
635		.val_bits = 8,
636		.max_register = 0x0a,
637	},
638};
639
640static const struct pcf85063_config config_pcf85063tp = {
641	.regmap = {
642		.reg_bits = 8,
643		.val_bits = 8,
644		.max_register = 0x0a,
645	},
646};
647
648static const struct pcf85063_config config_pcf85063a = {
649	.regmap = {
650		.reg_bits = 8,
651		.val_bits = 8,
652		.max_register = 0x11,
653	},
654	.has_alarms = 1,
655};
656
657static const struct pcf85063_config config_rv8263 = {
658	.regmap = {
659		.reg_bits = 8,
660		.val_bits = 8,
661		.max_register = 0x11,
662	},
663	.has_alarms = 1,
664	.force_cap_7000 = 1,
665};
666
667static const struct i2c_device_id pcf85063_ids[] = {
668	{ "pca85073a", .driver_data = (kernel_ulong_t)&config_pcf85063a },
669	{ "pcf85063", .driver_data = (kernel_ulong_t)&config_pcf85063 },
670	{ "pcf85063tp", .driver_data = (kernel_ulong_t)&config_pcf85063tp },
671	{ "pcf85063a", .driver_data = (kernel_ulong_t)&config_pcf85063a },
672	{ "rv8263", .driver_data = (kernel_ulong_t)&config_rv8263 },
673	{}
674};
675MODULE_DEVICE_TABLE(i2c, pcf85063_ids);
676
677#ifdef CONFIG_OF
678static const struct of_device_id pcf85063_of_match[] = {
679	{ .compatible = "nxp,pca85073a", .data = &config_pcf85063a },
680	{ .compatible = "nxp,pcf85063", .data = &config_pcf85063 },
681	{ .compatible = "nxp,pcf85063tp", .data = &config_pcf85063tp },
682	{ .compatible = "nxp,pcf85063a", .data = &config_pcf85063a },
683	{ .compatible = "microcrystal,rv8263", .data = &config_rv8263 },
684	{}
685};
686MODULE_DEVICE_TABLE(of, pcf85063_of_match);
687#endif
688
689static int pcf85063_i2c_probe(struct i2c_client *client)
690{
691	const struct pcf85063_config *config;
692	struct regmap *regmap;
693
694	config = i2c_get_match_data(client);
695	if (!config)
696		return -ENODEV;
697
698	regmap = devm_regmap_init_i2c(client, &config->regmap);
699	if (IS_ERR(regmap))
700		return PTR_ERR(regmap);
701
702	return pcf85063_probe(&client->dev, regmap, client->irq, config);
703}
704
705static struct i2c_driver pcf85063_driver = {
706	.driver		= {
707		.name	= "rtc-pcf85063",
708		.of_match_table = of_match_ptr(pcf85063_of_match),
709	},
710	.probe		= pcf85063_i2c_probe,
711	.id_table	= pcf85063_ids,
712};
713
714static int pcf85063_register_driver(void)
715{
716	return i2c_add_driver(&pcf85063_driver);
717}
718
719static void pcf85063_unregister_driver(void)
720{
721	i2c_del_driver(&pcf85063_driver);
722}
723
724#else
725
726static int pcf85063_register_driver(void)
727{
728	return 0;
729}
730
731static void pcf85063_unregister_driver(void)
732{
733}
734
735#endif /* IS_ENABLED(CONFIG_I2C) */
736
737#if IS_ENABLED(CONFIG_SPI_MASTER)
738
739static const struct pcf85063_config config_rv8063 = {
740	.regmap = {
741		.reg_bits = 8,
742		.val_bits = 8,
743		.max_register = 0x11,
744		.read_flag_mask = BIT(7) | BIT(5),
745		.write_flag_mask = BIT(5),
746	},
747	.has_alarms = 1,
748	.force_cap_7000 = 1,
749};
750
751static const struct spi_device_id rv8063_id[] = {
752	{ "rv8063" },
753	{}
754};
755MODULE_DEVICE_TABLE(spi, rv8063_id);
756
757static const struct of_device_id rv8063_of_match[] = {
758	{ .compatible = "microcrystal,rv8063" },
759	{}
760};
761MODULE_DEVICE_TABLE(of, rv8063_of_match);
762
763static int rv8063_probe(struct spi_device *spi)
764{
765	const struct pcf85063_config *config = &config_rv8063;
766	struct regmap *regmap;
767
768	regmap = devm_regmap_init_spi(spi, &config->regmap);
769	if (IS_ERR(regmap))
770		return PTR_ERR(regmap);
771
772	return pcf85063_probe(&spi->dev, regmap, spi->irq, config);
773}
774
775static struct spi_driver rv8063_driver = {
776	.driver         = {
777		.name   = "rv8063",
778		.of_match_table = rv8063_of_match,
779	},
780	.probe          = rv8063_probe,
781	.id_table	= rv8063_id,
782};
783
784static int __init rv8063_register_driver(void)
785{
786	return spi_register_driver(&rv8063_driver);
787}
788
789static void __exit rv8063_unregister_driver(void)
790{
791	spi_unregister_driver(&rv8063_driver);
792}
793
794#else
795
796static int __init rv8063_register_driver(void)
797{
798	return 0;
799}
800
801static void __exit rv8063_unregister_driver(void)
802{
803}
804
805#endif /* IS_ENABLED(CONFIG_SPI_MASTER) */
806
807static int __init pcf85063_init(void)
808{
809	int ret;
810
811	ret = pcf85063_register_driver();
812	if (ret)
813		return ret;
814
815	ret = rv8063_register_driver();
816	if (ret)
817		pcf85063_unregister_driver();
818
819	return ret;
820}
821module_init(pcf85063_init);
822
823static void __exit pcf85063_exit(void)
824{
825	rv8063_unregister_driver();
826	pcf85063_unregister_driver();
827}
828module_exit(pcf85063_exit);
829
830MODULE_AUTHOR("Søren Andersen <san@rosetechnology.dk>");
831MODULE_DESCRIPTION("PCF85063 RTC driver");
832MODULE_LICENSE("GPL");