rtc-isl12022.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * An I2C driver for the Intersil ISL 12022
  4 *
  5 * Author: Roman Fietze <roman.fietze@telemotive.de>
  6 *
  7 * Based on the Philips PCF8563 RTC
  8 * by Alessandro Zummo <a.zummo@towertech.it>.
  9 */
 10
 11#include <linux/bcd.h>
 12#include <linux/bitfield.h>
 13#include <linux/clk-provider.h>
 14#include <linux/err.h>
 15#include <linux/hwmon.h>
 16#include <linux/i2c.h>
 17#include <linux/module.h>
 18#include <linux/regmap.h>
 19#include <linux/rtc.h>
 20#include <linux/slab.h>
 21
 22#include <asm/byteorder.h>
 23
 24/* RTC - Real time clock registers */
 25#define ISL12022_REG_SC		0x00
 26#define ISL12022_REG_MN		0x01
 27#define ISL12022_REG_HR		0x02
 28#define ISL12022_REG_DT		0x03
 29#define ISL12022_REG_MO		0x04
 30#define ISL12022_REG_YR		0x05
 31#define ISL12022_REG_DW		0x06
 32
 33/* CSR - Control and status registers */
 34#define ISL12022_REG_SR		0x07
 35#define ISL12022_REG_INT	0x08
 36#define ISL12022_REG_PWR_VBAT	0x0a
 37#define ISL12022_REG_BETA	0x0d
 38
 39/* ALARM - Alarm registers */
 40#define ISL12022_REG_SCA0	0x10
 41#define ISL12022_REG_MNA0	0x11
 42#define ISL12022_REG_HRA0	0x12
 43#define ISL12022_REG_DTA0	0x13
 44#define ISL12022_REG_MOA0	0x14
 45#define ISL12022_REG_DWA0	0x15
 46#define ISL12022_ALARM		ISL12022_REG_SCA0
 47#define ISL12022_ALARM_LEN	(ISL12022_REG_DWA0 - ISL12022_REG_SCA0 + 1)
 48
 49/* TEMP - Temperature sensor registers */
 50#define ISL12022_REG_TEMP_L	0x28
 51
 52/* ISL register bits */
 53#define ISL12022_HR_MIL		(1 << 7)	/* military or 24 hour time */
 54
 55#define ISL12022_SR_ALM		(1 << 4)
 56#define ISL12022_SR_LBAT85	(1 << 2)
 57#define ISL12022_SR_LBAT75	(1 << 1)
 58
 59#define ISL12022_INT_ARST	(1 << 7)
 60#define ISL12022_INT_WRTC	(1 << 6)
 61#define ISL12022_INT_IM		(1 << 5)
 62#define ISL12022_INT_FOBATB	(1 << 4)
 63#define ISL12022_INT_FO_MASK	GENMASK(3, 0)
 64#define ISL12022_INT_FO_OFF	0x0
 65#define ISL12022_INT_FO_32K	0x1
 66
 67#define ISL12022_REG_VB85_MASK	GENMASK(5, 3)
 68#define ISL12022_REG_VB75_MASK	GENMASK(2, 0)
 69
 70#define ISL12022_ALARM_ENABLE	(1 << 7)	/* for all ALARM registers  */
 71
 72#define ISL12022_BETA_TSE	(1 << 7)
 73
 74static struct i2c_driver isl12022_driver;
 75
 76struct isl12022 {
 77	struct rtc_device *rtc;
 78	struct regmap *regmap;
 79	int irq;
 80	bool irq_enabled;
 81};
 82
 83static umode_t isl12022_hwmon_is_visible(const void *data,
 84					 enum hwmon_sensor_types type,
 85					 u32 attr, int channel)
 86{
 87	if (type == hwmon_temp && attr == hwmon_temp_input)
 88		return 0444;
 89
 90	return 0;
 91}
 92
 93/*
 94 * A user-initiated temperature conversion is not started by this function,
 95 * so the temperature is updated once every ~60 seconds.
 96 */
 97static int isl12022_hwmon_read_temp(struct device *dev, long *mC)
 98{
 99	struct regmap *regmap = dev_get_drvdata(dev);
100	int temp, ret;
101	__le16 buf;
102
103	ret = regmap_bulk_read(regmap, ISL12022_REG_TEMP_L, &buf, sizeof(buf));
104	if (ret)
105		return ret;
106	/*
107	 * Temperature is represented as a 10-bit number, unit half-Kelvins.
108	 */
109	temp = le16_to_cpu(buf);
110	temp *= 500;
111	temp -= 273000;
112
113	*mC = temp;
114
115	return 0;
116}
117
118static int isl12022_hwmon_read(struct device *dev,
119			       enum hwmon_sensor_types type,
120			       u32 attr, int channel, long *val)
121{
122	if (type == hwmon_temp && attr == hwmon_temp_input)
123		return isl12022_hwmon_read_temp(dev, val);
124
125	return -EOPNOTSUPP;
126}
127
128static const struct hwmon_channel_info * const isl12022_hwmon_info[] = {
129	HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT),
130	NULL
131};
132
133static const struct hwmon_ops isl12022_hwmon_ops = {
134	.is_visible = isl12022_hwmon_is_visible,
135	.read = isl12022_hwmon_read,
136};
137
138static const struct hwmon_chip_info isl12022_hwmon_chip_info = {
139	.ops = &isl12022_hwmon_ops,
140	.info = isl12022_hwmon_info,
141};
142
143static void isl12022_hwmon_register(struct device *dev)
144{
145	struct isl12022 *isl12022 = dev_get_drvdata(dev);
146	struct regmap *regmap = isl12022->regmap;
147	struct device *hwmon;
148	int ret;
149
150	if (!IS_REACHABLE(CONFIG_HWMON))
151		return;
152
153	ret = regmap_update_bits(regmap, ISL12022_REG_BETA,
154				 ISL12022_BETA_TSE, ISL12022_BETA_TSE);
155	if (ret) {
156		dev_warn(dev, "unable to enable temperature sensor\n");
157		return;
158	}
159
160	hwmon = devm_hwmon_device_register_with_info(dev, "isl12022", regmap,
161						     &isl12022_hwmon_chip_info,
162						     NULL);
163	if (IS_ERR(hwmon))
164		dev_warn(dev, "unable to register hwmon device: %pe\n", hwmon);
165}
166
167/*
168 * In the routines that deal directly with the isl12022 hardware, we use
169 * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch.
170 */
171static int isl12022_rtc_read_time(struct device *dev, struct rtc_time *tm)
172{
173	struct isl12022 *isl12022 = dev_get_drvdata(dev);
174	struct regmap *regmap = isl12022->regmap;
175	u8 buf[ISL12022_REG_INT + 1];
176	int ret;
177
178	ret = regmap_bulk_read(regmap, ISL12022_REG_SC, buf, sizeof(buf));
179	if (ret)
180		return ret;
181
182	dev_dbg(dev,
183		"raw data is sec=%02x, min=%02x, hr=%02x, mday=%02x, mon=%02x, year=%02x, wday=%02x, sr=%02x, int=%02x",
184		buf[ISL12022_REG_SC],
185		buf[ISL12022_REG_MN],
186		buf[ISL12022_REG_HR],
187		buf[ISL12022_REG_DT],
188		buf[ISL12022_REG_MO],
189		buf[ISL12022_REG_YR],
190		buf[ISL12022_REG_DW],
191		buf[ISL12022_REG_SR],
192		buf[ISL12022_REG_INT]);
193
194	tm->tm_sec = bcd2bin(buf[ISL12022_REG_SC] & 0x7F);
195	tm->tm_min = bcd2bin(buf[ISL12022_REG_MN] & 0x7F);
196	tm->tm_hour = bcd2bin(buf[ISL12022_REG_HR] & 0x3F);
197	tm->tm_mday = bcd2bin(buf[ISL12022_REG_DT] & 0x3F);
198	tm->tm_wday = buf[ISL12022_REG_DW] & 0x07;
199	tm->tm_mon = bcd2bin(buf[ISL12022_REG_MO] & 0x1F) - 1;
200	tm->tm_year = bcd2bin(buf[ISL12022_REG_YR]) + 100;
201
202	dev_dbg(dev, "%s: %ptR\n", __func__, tm);
203
204	return 0;
205}
206
207static int isl12022_rtc_set_time(struct device *dev, struct rtc_time *tm)
208{
209	struct isl12022 *isl12022 = dev_get_drvdata(dev);
210	struct regmap *regmap = isl12022->regmap;
211	int ret;
212	u8 buf[ISL12022_REG_DW + 1];
213
214	dev_dbg(dev, "%s: %ptR\n", __func__, tm);
215
216	/* Ensure the write enable bit is set. */
217	ret = regmap_update_bits(regmap, ISL12022_REG_INT,
218				 ISL12022_INT_WRTC, ISL12022_INT_WRTC);
219	if (ret)
220		return ret;
221
222	/* hours, minutes and seconds */
223	buf[ISL12022_REG_SC] = bin2bcd(tm->tm_sec);
224	buf[ISL12022_REG_MN] = bin2bcd(tm->tm_min);
225	buf[ISL12022_REG_HR] = bin2bcd(tm->tm_hour) | ISL12022_HR_MIL;
226
227	buf[ISL12022_REG_DT] = bin2bcd(tm->tm_mday);
228
229	/* month, 1 - 12 */
230	buf[ISL12022_REG_MO] = bin2bcd(tm->tm_mon + 1);
231
232	/* year and century */
233	buf[ISL12022_REG_YR] = bin2bcd(tm->tm_year % 100);
234
235	buf[ISL12022_REG_DW] = tm->tm_wday & 0x07;
236
237	return regmap_bulk_write(regmap, ISL12022_REG_SC, buf, sizeof(buf));
238}
239
240static int isl12022_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
241{
242	struct rtc_time *tm = &alarm->time;
243	struct isl12022 *isl12022 = dev_get_drvdata(dev);
244	struct regmap *regmap = isl12022->regmap;
245	u8 buf[ISL12022_ALARM_LEN];
246	unsigned int i, yr;
247	int ret;
248
249	ret = regmap_bulk_read(regmap, ISL12022_ALARM, buf, sizeof(buf));
250	if (ret) {
251		dev_dbg(dev, "%s: reading ALARM registers failed\n",
252			__func__);
253		return ret;
254	}
255
256	/* The alarm doesn't store the year so get it from the rtc section */
257	ret = regmap_read(regmap, ISL12022_REG_YR, &yr);
258	if (ret) {
259		dev_dbg(dev, "%s: reading YR register failed\n", __func__);
260		return ret;
261	}
262
263	dev_dbg(dev,
264		"%s: sc=%02x, mn=%02x, hr=%02x, dt=%02x, mo=%02x, dw=%02x yr=%u\n",
265		__func__, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], yr);
266
267	tm->tm_sec  = bcd2bin(buf[ISL12022_REG_SCA0 - ISL12022_ALARM] & 0x7F);
268	tm->tm_min  = bcd2bin(buf[ISL12022_REG_MNA0 - ISL12022_ALARM] & 0x7F);
269	tm->tm_hour = bcd2bin(buf[ISL12022_REG_HRA0 - ISL12022_ALARM] & 0x3F);
270	tm->tm_mday = bcd2bin(buf[ISL12022_REG_DTA0 - ISL12022_ALARM] & 0x3F);
271	tm->tm_mon  = bcd2bin(buf[ISL12022_REG_MOA0 - ISL12022_ALARM] & 0x1F) - 1;
272	tm->tm_wday = buf[ISL12022_REG_DWA0 - ISL12022_ALARM]         & 0x07;
273	tm->tm_year = bcd2bin(yr) + 100;
274
275	for (i = 0; i < ISL12022_ALARM_LEN; i++) {
276		if (buf[i] & ISL12022_ALARM_ENABLE) {
277			alarm->enabled = 1;
278			break;
279		}
280	}
281
282	dev_dbg(dev, "%s: %ptR\n", __func__, tm);
283
284	return 0;
285}
286
287static int isl12022_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
288{
289	struct rtc_time *alarm_tm = &alarm->time;
290	struct isl12022 *isl12022 = dev_get_drvdata(dev);
291	struct regmap *regmap = isl12022->regmap;
292	u8 regs[ISL12022_ALARM_LEN] = { 0, };
293	struct rtc_time rtc_tm;
294	int ret, enable, dw;
295
296	ret = isl12022_rtc_read_time(dev, &rtc_tm);
297	if (ret)
298		return ret;
299
300	/* If the alarm time is before the current time disable the alarm */
301	if (!alarm->enabled || rtc_tm_sub(alarm_tm, &rtc_tm) <= 0)
302		enable = 0;
303	else
304		enable = ISL12022_ALARM_ENABLE;
305
306	/*
307	 * Set non-matching day of the week to safeguard against early false
308	 * matching while setting all the alarm registers (this rtc lacks a
309	 * general alarm/irq enable/disable bit).
310	 */
311	ret = regmap_read(regmap, ISL12022_REG_DW, &dw);
312	if (ret) {
313		dev_dbg(dev, "%s: reading DW failed\n", __func__);
314		return ret;
315	}
316	/* ~4 days into the future should be enough to avoid match */
317	dw = ((dw + 4) % 7) | ISL12022_ALARM_ENABLE;
318	ret = regmap_write(regmap, ISL12022_REG_DWA0, dw);
319	if (ret) {
320		dev_dbg(dev, "%s: writing DWA0 failed\n", __func__);
321		return ret;
322	}
323
324	/* Program the alarm and enable it for each setting */
325	regs[ISL12022_REG_SCA0 - ISL12022_ALARM] = bin2bcd(alarm_tm->tm_sec) | enable;
326	regs[ISL12022_REG_MNA0 - ISL12022_ALARM] = bin2bcd(alarm_tm->tm_min) | enable;
327	regs[ISL12022_REG_HRA0 - ISL12022_ALARM] = bin2bcd(alarm_tm->tm_hour) | enable;
328	regs[ISL12022_REG_DTA0 - ISL12022_ALARM] = bin2bcd(alarm_tm->tm_mday) | enable;
329	regs[ISL12022_REG_MOA0 - ISL12022_ALARM] = bin2bcd(alarm_tm->tm_mon + 1) | enable;
330	regs[ISL12022_REG_DWA0 - ISL12022_ALARM] = bin2bcd(alarm_tm->tm_wday & 7) | enable;
331
332	/* write ALARM registers */
333	ret = regmap_bulk_write(regmap, ISL12022_ALARM, &regs, sizeof(regs));
334	if (ret) {
335		dev_dbg(dev, "%s: writing ALARM registers failed\n", __func__);
336		return ret;
337	}
338
339	return 0;
340}
341
342static irqreturn_t isl12022_rtc_interrupt(int irq, void *data)
343{
344	struct isl12022 *isl12022 = data;
345	struct rtc_device *rtc = isl12022->rtc;
346	struct device *dev = &rtc->dev;
347	struct regmap *regmap = isl12022->regmap;
348	u32 val = 0;
349	unsigned long events = 0;
350	int ret;
351
352	ret = regmap_read(regmap, ISL12022_REG_SR, &val);
353	if (ret) {
354		dev_dbg(dev, "%s: reading SR failed\n", __func__);
355		return IRQ_HANDLED;
356	}
357
358	if (val & ISL12022_SR_ALM)
359		events |= RTC_IRQF | RTC_AF;
360
361	if (events & RTC_AF)
362		dev_dbg(dev, "alarm!\n");
363
364	if (!events)
365		return IRQ_NONE;
366
367	rtc_update_irq(rtc, 1, events);
368	return IRQ_HANDLED;
369}
370
371static int isl12022_rtc_alarm_irq_enable(struct device *dev,
372					 unsigned int enabled)
373{
374	struct isl12022 *isl12022 = dev_get_drvdata(dev);
375
376	/* Make sure enabled is 0 or 1 */
377	enabled = !!enabled;
378
379	if (isl12022->irq_enabled == enabled)
380		return 0;
381
382	if (enabled)
383		enable_irq(isl12022->irq);
384	else
385		disable_irq(isl12022->irq);
386
387	isl12022->irq_enabled = enabled;
388
389	return 0;
390}
391
392static int isl12022_setup_irq(struct device *dev, int irq)
393{
394	struct isl12022 *isl12022 = dev_get_drvdata(dev);
395	struct regmap *regmap = isl12022->regmap;
396	unsigned int reg_mask, reg_val;
397	u8 buf[ISL12022_ALARM_LEN] = { 0, };
398	int ret;
399
400	/* Clear and disable all alarm registers */
401	ret = regmap_bulk_write(regmap, ISL12022_ALARM, buf, sizeof(buf));
402	if (ret)
403		return ret;
404
405	/*
406	 * Enable automatic reset of ALM bit and enable single event interrupt
407	 * mode.
408	 */
409	reg_mask = ISL12022_INT_ARST | ISL12022_INT_IM | ISL12022_INT_FO_MASK;
410	reg_val = ISL12022_INT_ARST | ISL12022_INT_FO_OFF;
411	ret = regmap_write_bits(regmap, ISL12022_REG_INT,
412				reg_mask, reg_val);
413	if (ret)
414		return ret;
415
416	isl12022->irq_enabled = true;
417	ret = devm_request_threaded_irq(dev, irq, NULL,
418					isl12022_rtc_interrupt,
419					IRQF_SHARED | IRQF_ONESHOT,
420					isl12022_driver.driver.name,
421					isl12022);
422	if (ret)
423		return dev_err_probe(dev, ret, "Unable to request irq %d\n", irq);
424
425	isl12022->irq = irq;
426	return 0;
427}
428
429static int isl12022_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
430{
431	struct isl12022 *isl12022 = dev_get_drvdata(dev);
432	struct regmap *regmap = isl12022->regmap;
433	u32 user, val;
434	int ret;
435
436	switch (cmd) {
437	case RTC_VL_READ:
438		ret = regmap_read(regmap, ISL12022_REG_SR, &val);
439		if (ret)
440			return ret;
441
442		user = 0;
443		if (val & ISL12022_SR_LBAT85)
444			user |= RTC_VL_BACKUP_LOW;
445
446		if (val & ISL12022_SR_LBAT75)
447			user |= RTC_VL_BACKUP_EMPTY;
448
449		return put_user(user, (u32 __user *)arg);
450
451	default:
452		return -ENOIOCTLCMD;
453	}
454}
455
456static const struct rtc_class_ops isl12022_rtc_ops = {
457	.ioctl		= isl12022_rtc_ioctl,
458	.read_time	= isl12022_rtc_read_time,
459	.set_time	= isl12022_rtc_set_time,
460	.read_alarm	= isl12022_rtc_read_alarm,
461	.set_alarm	= isl12022_rtc_set_alarm,
462	.alarm_irq_enable = isl12022_rtc_alarm_irq_enable,
463};
464
465static const struct regmap_config regmap_config = {
466	.reg_bits = 8,
467	.val_bits = 8,
468	.use_single_write = true,
469};
470
471static int isl12022_register_clock(struct device *dev)
472{
473	struct isl12022 *isl12022 = dev_get_drvdata(dev);
474	struct regmap *regmap = isl12022->regmap;
475	struct clk_hw *hw;
476	int ret;
477
478	if (!device_property_present(dev, "#clock-cells")) {
479		/*
480		 * Disabling the F_OUT pin reduces the power
481		 * consumption in battery mode by ~25%.
482		 */
483		regmap_update_bits(regmap, ISL12022_REG_INT, ISL12022_INT_FO_MASK,
484				   ISL12022_INT_FO_OFF);
485
486		return 0;
487	}
488
489	if (!IS_ENABLED(CONFIG_COMMON_CLK))
490		return 0;
491
492	/*
493	 * For now, only support a fixed clock of 32768Hz (the reset default).
494	 */
495	ret = regmap_update_bits(regmap, ISL12022_REG_INT,
496				 ISL12022_INT_FO_MASK, ISL12022_INT_FO_32K);
497	if (ret)
498		return ret;
499
500	hw = devm_clk_hw_register_fixed_rate(dev, "isl12022", NULL, 0, 32768);
501	if (IS_ERR(hw))
502		return PTR_ERR(hw);
503
504	return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
505}
506
507static const u32 trip_levels[2][7] = {
508	{ 2125000, 2295000, 2550000, 2805000, 3060000, 4250000, 4675000 },
509	{ 1875000, 2025000, 2250000, 2475000, 2700000, 3750000, 4125000 },
510};
511
512static void isl12022_set_trip_levels(struct device *dev)
513{
514	struct isl12022 *isl12022 = dev_get_drvdata(dev);
515	struct regmap *regmap = isl12022->regmap;
516	u32 levels[2] = {0, 0};
517	int ret, i, j, x[2];
518	u8 val, mask;
519
520	device_property_read_u32_array(dev, "isil,battery-trip-levels-microvolt",
521				       levels, 2);
522
523	for (i = 0; i < 2; i++) {
524		for (j = 0; j < ARRAY_SIZE(trip_levels[i]) - 1; j++) {
525			if (levels[i] <= trip_levels[i][j])
526				break;
527		}
528		x[i] = j;
529	}
530
531	val = FIELD_PREP(ISL12022_REG_VB85_MASK, x[0]) |
532		FIELD_PREP(ISL12022_REG_VB75_MASK, x[1]);
533	mask = ISL12022_REG_VB85_MASK | ISL12022_REG_VB75_MASK;
534
535	ret = regmap_update_bits(regmap, ISL12022_REG_PWR_VBAT, mask, val);
536	if (ret)
537		dev_warn(dev, "unable to set battery alarm levels: %d\n", ret);
538
539	/*
540	 * Force a write of the TSE bit in the BETA register, in order
541	 * to trigger an update of the LBAT75 and LBAT85 bits in the
542	 * status register. In battery backup mode, those bits have
543	 * another meaning, so without this, they may contain stale
544	 * values for up to a minute after power-on.
545	 */
546	regmap_write_bits(regmap, ISL12022_REG_BETA,
547			  ISL12022_BETA_TSE, ISL12022_BETA_TSE);
548}
549
550static int isl12022_probe(struct i2c_client *client)
551{
552	struct isl12022 *isl12022;
553	struct rtc_device *rtc;
554	struct regmap *regmap;
555	int ret;
556
557	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
558		return -ENODEV;
559
560	/* Allocate driver state */
561	isl12022 = devm_kzalloc(&client->dev, sizeof(*isl12022), GFP_KERNEL);
562	if (!isl12022)
563		return -ENOMEM;
564
565	regmap = devm_regmap_init_i2c(client, &regmap_config);
566	if (IS_ERR(regmap))
567		return dev_err_probe(&client->dev, PTR_ERR(regmap), "regmap allocation failed\n");
568	isl12022->regmap = regmap;
569
570	dev_set_drvdata(&client->dev, isl12022);
571
572	ret = isl12022_register_clock(&client->dev);
573	if (ret)
574		return ret;
575
576	isl12022_set_trip_levels(&client->dev);
577	isl12022_hwmon_register(&client->dev);
578
579	rtc = devm_rtc_allocate_device(&client->dev);
580	if (IS_ERR(rtc))
581		return PTR_ERR(rtc);
582	isl12022->rtc = rtc;
583
584	rtc->ops = &isl12022_rtc_ops;
585	rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
586	rtc->range_max = RTC_TIMESTAMP_END_2099;
587
588	if (client->irq > 0) {
589		ret = isl12022_setup_irq(&client->dev, client->irq);
590		if (ret)
591			return ret;
592	} else {
593		clear_bit(RTC_FEATURE_ALARM, rtc->features);
594	}
595
596	return devm_rtc_register_device(rtc);
597}
598
599static const struct of_device_id isl12022_dt_match[] = {
600	{ .compatible = "isl,isl12022" }, /* for backward compat., don't use */
601	{ .compatible = "isil,isl12022" },
602	{ },
603};
604MODULE_DEVICE_TABLE(of, isl12022_dt_match);
605
606static const struct i2c_device_id isl12022_id[] = {
607	{ "isl12022" },
608	{ }
609};
610MODULE_DEVICE_TABLE(i2c, isl12022_id);
611
612static struct i2c_driver isl12022_driver = {
613	.driver		= {
614		.name	= "rtc-isl12022",
615		.of_match_table = isl12022_dt_match,
616	},
617	.probe		= isl12022_probe,
618	.id_table	= isl12022_id,
619};
620
621module_i2c_driver(isl12022_driver);
622
623MODULE_AUTHOR("roman.fietze@telemotive.de");
624MODULE_DESCRIPTION("ISL 12022 RTC driver");
625MODULE_LICENSE("GPL");