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reset-k230.c
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linux-6.19.14/drivers/reset/reset-k230.c
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright (C) 2022-2024 Canaan Bright Sight Co., Ltd 4 * Copyright (C) 2024-2025 Junhui Liu <junhui.liu@pigmoral.tech> 5 * 6 * The reset management module in the K230 SoC provides reset time control 7 * registers. For RST_TYPE_CPU0, RST_TYPE_CPU1 and RST_TYPE_SW_DONE, the period 8 * during which reset is applied or removed while the clock is stopped can be 9 * set up to 15 * 0.25 = 3.75 µs. For RST_TYPE_HW_DONE, that period can be set 10 * up to 255 * 0.25 = 63.75 µs. For RST_TYPE_FLUSH, the reset bit is 11 * automatically cleared by hardware when flush completes. 12 * 13 * Although this driver does not configure the reset time registers, delays have 14 * been added to the assert, deassert, and reset operations to cover the maximum 15 * reset time. Some reset types include done bits whose toggle does not 16 * unambiguously signal whether hardware reset removal or clock-stop period 17 * expiration occurred first. Delays are therefore retained for types with done 18 * bits to ensure safe timing. 19 * 20 * Reference: K230 Technical Reference Manual V0.3.1 21 * https://kendryte-download.canaan-creative.com/developer/k230/HDK/K230%E7%A1%AC%E4%BB%B6%E6%96%87%E6%A1%A3/K230_Technical_Reference_Manual_V0.3.1_20241118.pdf 22 */ 23 24#include <linux/cleanup.h> 25#include <linux/delay.h> 26#include <linux/io.h> 27#include <linux/iopoll.h> 28#include <linux/of.h> 29#include <linux/platform_device.h> 30#include <linux/reset-controller.h> 31#include <linux/spinlock.h> 32 33#include <dt-bindings/reset/canaan,k230-rst.h> 34 35/** 36 * enum k230_rst_type - K230 reset types 37 * @RST_TYPE_CPU0: Reset type for CPU0 38 * Automatically clears, has write enable and done bit, active high 39 * @RST_TYPE_CPU1: Reset type for CPU1 40 * Manually clears, has write enable and done bit, active high 41 * @RST_TYPE_FLUSH: Reset type for CPU L2 cache flush 42 * Automatically clears, has write enable, no done bit, active high 43 * @RST_TYPE_HW_DONE: Reset type for hardware auto clear 44 * Automatically clears, no write enable, has done bit, active high 45 * @RST_TYPE_SW_DONE: Reset type for software manual clear 46 * Manually clears, no write enable and done bit, 47 * active high if ID is RST_SPI2AXI, otherwise active low 48 */ 49enum k230_rst_type { 50 RST_TYPE_CPU0, 51 RST_TYPE_CPU1, 52 RST_TYPE_FLUSH, 53 RST_TYPE_HW_DONE, 54 RST_TYPE_SW_DONE, 55}; 56 57struct k230_rst_map { 58 u32 offset; 59 enum k230_rst_type type; 60 u32 done; 61 u32 reset; 62}; 63 64struct k230_rst { 65 struct reset_controller_dev rcdev; 66 void __iomem *base; 67 /* protect register read-modify-write */ 68 spinlock_t lock; 69}; 70 71static const struct k230_rst_map k230_resets[] = { 72 [RST_CPU0] = { 0x4, RST_TYPE_CPU0, BIT(12), BIT(0) }, 73 [RST_CPU1] = { 0xc, RST_TYPE_CPU1, BIT(12), BIT(0) }, 74 [RST_CPU0_FLUSH] = { 0x4, RST_TYPE_FLUSH, 0, BIT(4) }, 75 [RST_CPU1_FLUSH] = { 0xc, RST_TYPE_FLUSH, 0, BIT(4) }, 76 [RST_AI] = { 0x14, RST_TYPE_HW_DONE, BIT(31), BIT(0) }, 77 [RST_VPU] = { 0x1c, RST_TYPE_HW_DONE, BIT(31), BIT(0) }, 78 [RST_HISYS] = { 0x2c, RST_TYPE_HW_DONE, BIT(4), BIT(0) }, 79 [RST_HISYS_AHB] = { 0x2c, RST_TYPE_HW_DONE, BIT(5), BIT(1) }, 80 [RST_SDIO0] = { 0x34, RST_TYPE_HW_DONE, BIT(28), BIT(0) }, 81 [RST_SDIO1] = { 0x34, RST_TYPE_HW_DONE, BIT(29), BIT(1) }, 82 [RST_SDIO_AXI] = { 0x34, RST_TYPE_HW_DONE, BIT(30), BIT(2) }, 83 [RST_USB0] = { 0x3c, RST_TYPE_HW_DONE, BIT(28), BIT(0) }, 84 [RST_USB1] = { 0x3c, RST_TYPE_HW_DONE, BIT(29), BIT(1) }, 85 [RST_USB0_AHB] = { 0x3c, RST_TYPE_HW_DONE, BIT(30), BIT(0) }, 86 [RST_USB1_AHB] = { 0x3c, RST_TYPE_HW_DONE, BIT(31), BIT(1) }, 87 [RST_SPI0] = { 0x44, RST_TYPE_HW_DONE, BIT(28), BIT(0) }, 88 [RST_SPI1] = { 0x44, RST_TYPE_HW_DONE, BIT(29), BIT(1) }, 89 [RST_SPI2] = { 0x44, RST_TYPE_HW_DONE, BIT(30), BIT(2) }, 90 [RST_SEC] = { 0x4c, RST_TYPE_HW_DONE, BIT(31), BIT(0) }, 91 [RST_PDMA] = { 0x54, RST_TYPE_HW_DONE, BIT(28), BIT(0) }, 92 [RST_SDMA] = { 0x54, RST_TYPE_HW_DONE, BIT(29), BIT(1) }, 93 [RST_DECOMPRESS] = { 0x5c, RST_TYPE_HW_DONE, BIT(31), BIT(0) }, 94 [RST_SRAM] = { 0x64, RST_TYPE_HW_DONE, BIT(28), BIT(0) }, 95 [RST_SHRM_AXIM] = { 0x64, RST_TYPE_HW_DONE, BIT(30), BIT(2) }, 96 [RST_SHRM_AXIS] = { 0x64, RST_TYPE_HW_DONE, BIT(31), BIT(3) }, 97 [RST_NONAI2D] = { 0x6c, RST_TYPE_HW_DONE, BIT(31), BIT(0) }, 98 [RST_MCTL] = { 0x74, RST_TYPE_HW_DONE, BIT(31), BIT(0) }, 99 [RST_ISP] = { 0x80, RST_TYPE_HW_DONE, BIT(29), BIT(6) }, 100 [RST_ISP_DW] = { 0x80, RST_TYPE_HW_DONE, BIT(28), BIT(5) }, 101 [RST_DPU] = { 0x88, RST_TYPE_HW_DONE, BIT(31), BIT(0) }, 102 [RST_DISP] = { 0x90, RST_TYPE_HW_DONE, BIT(31), BIT(0) }, 103 [RST_GPU] = { 0x98, RST_TYPE_HW_DONE, BIT(31), BIT(0) }, 104 [RST_AUDIO] = { 0xa4, RST_TYPE_HW_DONE, BIT(31), BIT(0) }, 105 [RST_TIMER0] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(0) }, 106 [RST_TIMER1] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(1) }, 107 [RST_TIMER2] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(2) }, 108 [RST_TIMER3] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(3) }, 109 [RST_TIMER4] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(4) }, 110 [RST_TIMER5] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(5) }, 111 [RST_TIMER_APB] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(6) }, 112 [RST_HDI] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(7) }, 113 [RST_WDT0] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(12) }, 114 [RST_WDT1] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(13) }, 115 [RST_WDT0_APB] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(14) }, 116 [RST_WDT1_APB] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(15) }, 117 [RST_TS_APB] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(16) }, 118 [RST_MAILBOX] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(17) }, 119 [RST_STC] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(18) }, 120 [RST_PMU] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(19) }, 121 [RST_LOSYS_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(0) }, 122 [RST_UART0] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(1) }, 123 [RST_UART1] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(2) }, 124 [RST_UART2] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(3) }, 125 [RST_UART3] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(4) }, 126 [RST_UART4] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(5) }, 127 [RST_I2C0] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(6) }, 128 [RST_I2C1] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(7) }, 129 [RST_I2C2] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(8) }, 130 [RST_I2C3] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(9) }, 131 [RST_I2C4] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(10) }, 132 [RST_JAMLINK0_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(11) }, 133 [RST_JAMLINK1_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(12) }, 134 [RST_JAMLINK2_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(13) }, 135 [RST_JAMLINK3_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(14) }, 136 [RST_CODEC_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(17) }, 137 [RST_GPIO_DB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(18) }, 138 [RST_GPIO_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(19) }, 139 [RST_ADC] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(20) }, 140 [RST_ADC_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(21) }, 141 [RST_PWM_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(22) }, 142 [RST_SHRM_APB] = { 0x64, RST_TYPE_SW_DONE, 0, BIT(1) }, 143 [RST_CSI0] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(0) }, 144 [RST_CSI1] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(1) }, 145 [RST_CSI2] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(2) }, 146 [RST_CSI_DPHY] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(3) }, 147 [RST_ISP_AHB] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(4) }, 148 [RST_M0] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(7) }, 149 [RST_M1] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(8) }, 150 [RST_M2] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(9) }, 151 [RST_SPI2AXI] = { 0xa8, RST_TYPE_SW_DONE, 0, BIT(0) } 152}; 153 154static inline struct k230_rst *to_k230_rst(struct reset_controller_dev *rcdev) 155{ 156 return container_of(rcdev, struct k230_rst, rcdev); 157} 158 159static void k230_rst_clear_done(struct k230_rst *rstc, unsigned long id, 160 bool write_en) 161{ 162 const struct k230_rst_map *rmap = &k230_resets[id]; 163 u32 reg; 164 165 guard(spinlock_irqsave)(&rstc->lock); 166 167 reg = readl(rstc->base + rmap->offset); 168 reg |= rmap->done; /* write 1 to clear */ 169 if (write_en) 170 reg |= rmap->done << 16; 171 writel(reg, rstc->base + rmap->offset); 172} 173 174static int k230_rst_wait_and_clear_done(struct k230_rst *rstc, unsigned long id, 175 bool write_en) 176{ 177 const struct k230_rst_map *rmap = &k230_resets[id]; 178 u32 reg; 179 int ret; 180 181 ret = readl_poll_timeout(rstc->base + rmap->offset, reg, 182 reg & rmap->done, 10, 1000); 183 if (ret) { 184 dev_err(rstc->rcdev.dev, "Wait for reset done timeout\n"); 185 return ret; 186 } 187 188 k230_rst_clear_done(rstc, id, write_en); 189 190 return 0; 191} 192 193static void k230_rst_update(struct k230_rst *rstc, unsigned long id, 194 bool assert, bool write_en, bool active_low) 195{ 196 const struct k230_rst_map *rmap = &k230_resets[id]; 197 u32 reg; 198 199 guard(spinlock_irqsave)(&rstc->lock); 200 201 reg = readl(rstc->base + rmap->offset); 202 if (assert ^ active_low) 203 reg |= rmap->reset; 204 else 205 reg &= ~rmap->reset; 206 if (write_en) 207 reg |= rmap->reset << 16; 208 writel(reg, rstc->base + rmap->offset); 209} 210 211static int k230_rst_assert(struct reset_controller_dev *rcdev, unsigned long id) 212{ 213 struct k230_rst *rstc = to_k230_rst(rcdev); 214 215 switch (k230_resets[id].type) { 216 case RST_TYPE_CPU1: 217 k230_rst_update(rstc, id, true, true, false); 218 break; 219 case RST_TYPE_SW_DONE: 220 k230_rst_update(rstc, id, true, false, 221 id == RST_SPI2AXI ? false : true); 222 break; 223 case RST_TYPE_CPU0: 224 case RST_TYPE_FLUSH: 225 case RST_TYPE_HW_DONE: 226 return -EOPNOTSUPP; 227 } 228 229 /* 230 * The time period when reset is applied but the clock is stopped for 231 * RST_TYPE_CPU1 and RST_TYPE_SW_DONE can be set up to 3.75us. Delay 232 * 10us to ensure proper reset timing. 233 */ 234 udelay(10); 235 236 return 0; 237} 238 239static int k230_rst_deassert(struct reset_controller_dev *rcdev, 240 unsigned long id) 241{ 242 struct k230_rst *rstc = to_k230_rst(rcdev); 243 int ret = 0; 244 245 switch (k230_resets[id].type) { 246 case RST_TYPE_CPU1: 247 k230_rst_update(rstc, id, false, true, false); 248 ret = k230_rst_wait_and_clear_done(rstc, id, true); 249 break; 250 case RST_TYPE_SW_DONE: 251 k230_rst_update(rstc, id, false, false, 252 id == RST_SPI2AXI ? false : true); 253 break; 254 case RST_TYPE_CPU0: 255 case RST_TYPE_FLUSH: 256 case RST_TYPE_HW_DONE: 257 return -EOPNOTSUPP; 258 } 259 260 /* 261 * The time period when reset is removed but the clock is stopped for 262 * RST_TYPE_CPU1 and RST_TYPE_SW_DONE can be set up to 3.75us. Delay 263 * 10us to ensure proper reset timing. 264 */ 265 udelay(10); 266 267 return ret; 268} 269 270static int k230_rst_reset(struct reset_controller_dev *rcdev, unsigned long id) 271{ 272 struct k230_rst *rstc = to_k230_rst(rcdev); 273 const struct k230_rst_map *rmap = &k230_resets[id]; 274 u32 reg; 275 int ret = 0; 276 277 switch (rmap->type) { 278 case RST_TYPE_CPU0: 279 k230_rst_clear_done(rstc, id, true); 280 k230_rst_update(rstc, id, true, true, false); 281 ret = k230_rst_wait_and_clear_done(rstc, id, true); 282 283 /* 284 * The time period when reset is applied and removed but the 285 * clock is stopped for RST_TYPE_CPU0 can be set up to 7.5us. 286 * Delay 10us to ensure proper reset timing. 287 */ 288 udelay(10); 289 290 break; 291 case RST_TYPE_FLUSH: 292 k230_rst_update(rstc, id, true, true, false); 293 294 /* Wait flush request bit auto cleared by hardware */ 295 ret = readl_poll_timeout(rstc->base + rmap->offset, reg, 296 !(reg & rmap->reset), 10, 1000); 297 if (ret) 298 dev_err(rcdev->dev, "Wait for flush done timeout\n"); 299 300 break; 301 case RST_TYPE_HW_DONE: 302 k230_rst_clear_done(rstc, id, false); 303 k230_rst_update(rstc, id, true, false, false); 304 ret = k230_rst_wait_and_clear_done(rstc, id, false); 305 306 /* 307 * The time period when reset is applied and removed but the 308 * clock is stopped for RST_TYPE_HW_DONE can be set up to 309 * 127.5us. Delay 200us to ensure proper reset timing. 310 */ 311 fsleep(200); 312 313 break; 314 case RST_TYPE_CPU1: 315 case RST_TYPE_SW_DONE: 316 k230_rst_assert(rcdev, id); 317 ret = k230_rst_deassert(rcdev, id); 318 break; 319 } 320 321 return ret; 322} 323 324static const struct reset_control_ops k230_rst_ops = { 325 .reset = k230_rst_reset, 326 .assert = k230_rst_assert, 327 .deassert = k230_rst_deassert, 328}; 329 330static int k230_rst_probe(struct platform_device *pdev) 331{ 332 struct device *dev = &pdev->dev; 333 struct k230_rst *rstc; 334 335 rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL); 336 if (!rstc) 337 return -ENOMEM; 338 339 rstc->base = devm_platform_ioremap_resource(pdev, 0); 340 if (IS_ERR(rstc->base)) 341 return PTR_ERR(rstc->base); 342 343 spin_lock_init(&rstc->lock); 344 345 rstc->rcdev.dev = dev; 346 rstc->rcdev.owner = THIS_MODULE; 347 rstc->rcdev.ops = &k230_rst_ops; 348 rstc->rcdev.nr_resets = ARRAY_SIZE(k230_resets); 349 rstc->rcdev.of_node = dev->of_node; 350 351 return devm_reset_controller_register(dev, &rstc->rcdev); 352} 353 354static const struct of_device_id k230_rst_match[] = { 355 { .compatible = "canaan,k230-rst", }, 356 { /* sentinel */ } 357}; 358MODULE_DEVICE_TABLE(of, k230_rst_match); 359 360static struct platform_driver k230_rst_driver = { 361 .probe = k230_rst_probe, 362 .driver = { 363 .name = "k230-rst", 364 .of_match_table = k230_rst_match, 365 } 366}; 367module_platform_driver(k230_rst_driver); 368 369MODULE_AUTHOR("Junhui Liu <junhui.liu@pigmoral.tech>"); 370MODULE_DESCRIPTION("Canaan K230 reset driver"); 371MODULE_LICENSE("GPL");
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