mpam_internal.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2// Copyright (C) 2025 Arm Ltd.
  3
  4#ifndef MPAM_INTERNAL_H
  5#define MPAM_INTERNAL_H
  6
  7#include <linux/arm_mpam.h>
  8#include <linux/atomic.h>
  9#include <linux/bitmap.h>
 10#include <linux/cpumask.h>
 11#include <linux/io.h>
 12#include <linux/jump_label.h>
 13#include <linux/llist.h>
 14#include <linux/mutex.h>
 15#include <linux/spinlock.h>
 16#include <linux/srcu.h>
 17#include <linux/types.h>
 18
 19#define MPAM_MSC_MAX_NUM_RIS	16
 20
 21struct platform_device;
 22
 23DECLARE_STATIC_KEY_FALSE(mpam_enabled);
 24
 25#ifdef CONFIG_MPAM_KUNIT_TEST
 26#define PACKED_FOR_KUNIT __packed
 27#else
 28#define PACKED_FOR_KUNIT
 29#endif
 30
 31static inline bool mpam_is_enabled(void)
 32{
 33	return static_branch_likely(&mpam_enabled);
 34}
 35
 36/*
 37 * Structures protected by SRCU may not be freed for a surprising amount of
 38 * time (especially if perf is running). To ensure the MPAM error interrupt can
 39 * tear down all the structures, build a list of objects that can be garbage
 40 * collected once synchronize_srcu() has returned.
 41 * If pdev is non-NULL, use devm_kfree().
 42 */
 43struct mpam_garbage {
 44	/* member of mpam_garbage */
 45	struct llist_node	llist;
 46
 47	void			*to_free;
 48	struct platform_device	*pdev;
 49};
 50
 51struct mpam_msc {
 52	/* member of mpam_all_msc */
 53	struct list_head	all_msc_list;
 54
 55	int			id;
 56	struct platform_device	*pdev;
 57
 58	/* Not modified after mpam_is_enabled() becomes true */
 59	enum mpam_msc_iface	iface;
 60	u32			nrdy_usec;
 61	cpumask_t		accessibility;
 62	bool			has_extd_esr;
 63
 64	int				reenable_error_ppi;
 65	struct mpam_msc * __percpu	*error_dev_id;
 66
 67	atomic_t		online_refs;
 68
 69	/*
 70	 * probe_lock is only taken during discovery. After discovery these
 71	 * properties become read-only and the lists are protected by SRCU.
 72	 */
 73	struct mutex		probe_lock;
 74	bool			probed;
 75	u16			partid_max;
 76	u8			pmg_max;
 77	unsigned long		ris_idxs;
 78	u32			ris_max;
 79
 80	/*
 81	 * error_irq_lock is taken when registering/unregistering the error
 82	 * interrupt and maniupulating the below flags.
 83	 */
 84	struct mutex		error_irq_lock;
 85	bool			error_irq_req;
 86	bool			error_irq_hw_enabled;
 87
 88	/* mpam_msc_ris of this component */
 89	struct list_head	ris;
 90
 91	/*
 92	 * part_sel_lock protects access to the MSC hardware registers that are
 93	 * affected by MPAMCFG_PART_SEL. (including the ID registers that vary
 94	 * by RIS).
 95	 * If needed, take msc->probe_lock first.
 96	 */
 97	struct mutex		part_sel_lock;
 98
 99	/*
100	 * cfg_lock protects the msc configuration and guards against mbwu_state
101	 * save and restore racing.
102	 */
103	struct mutex		cfg_lock;
104
105	/*
106	 * mon_sel_lock protects access to the MSC hardware registers that are
107	 * affected by MPAMCFG_MON_SEL, and the mbwu_state.
108	 * Access to mon_sel is needed from both process and interrupt contexts,
109	 * but is complicated by firmware-backed platforms that can't make any
110	 * access unless they can sleep.
111	 * Always use the mpam_mon_sel_lock() helpers.
112	 * Accesses to mon_sel need to be able to fail if they occur in the wrong
113	 * context.
114	 * If needed, take msc->probe_lock first.
115	 */
116	raw_spinlock_t		_mon_sel_lock;
117	unsigned long		_mon_sel_flags;
118
119	void __iomem		*mapped_hwpage;
120	size_t			mapped_hwpage_sz;
121
122	struct mpam_garbage	garbage;
123};
124
125/* Returning false here means accesses to mon_sel must fail and report an error. */
126static inline bool __must_check mpam_mon_sel_lock(struct mpam_msc *msc)
127{
128	/* Locking will require updating to support a firmware backed interface */
129	if (WARN_ON_ONCE(msc->iface != MPAM_IFACE_MMIO))
130		return false;
131
132	raw_spin_lock_irqsave(&msc->_mon_sel_lock, msc->_mon_sel_flags);
133	return true;
134}
135
136static inline void mpam_mon_sel_unlock(struct mpam_msc *msc)
137{
138	raw_spin_unlock_irqrestore(&msc->_mon_sel_lock, msc->_mon_sel_flags);
139}
140
141static inline void mpam_mon_sel_lock_held(struct mpam_msc *msc)
142{
143	lockdep_assert_held_once(&msc->_mon_sel_lock);
144}
145
146static inline void mpam_mon_sel_lock_init(struct mpam_msc *msc)
147{
148	raw_spin_lock_init(&msc->_mon_sel_lock);
149}
150
151/* Bits for mpam features bitmaps */
152enum mpam_device_features {
153	mpam_feat_cpor_part,
154	mpam_feat_cmax_softlim,
155	mpam_feat_cmax_cmax,
156	mpam_feat_cmax_cmin,
157	mpam_feat_cmax_cassoc,
158	mpam_feat_mbw_part,
159	mpam_feat_mbw_min,
160	mpam_feat_mbw_max,
161	mpam_feat_mbw_prop,
162	mpam_feat_intpri_part,
163	mpam_feat_intpri_part_0_low,
164	mpam_feat_dspri_part,
165	mpam_feat_dspri_part_0_low,
166	mpam_feat_msmon,
167	mpam_feat_msmon_csu,
168	mpam_feat_msmon_csu_capture,
169	mpam_feat_msmon_csu_xcl,
170	mpam_feat_msmon_csu_hw_nrdy,
171	mpam_feat_msmon_mbwu,
172	mpam_feat_msmon_mbwu_31counter,
173	mpam_feat_msmon_mbwu_44counter,
174	mpam_feat_msmon_mbwu_63counter,
175	mpam_feat_msmon_mbwu_capture,
176	mpam_feat_msmon_mbwu_rwbw,
177	mpam_feat_msmon_mbwu_hw_nrdy,
178	mpam_feat_partid_nrw,
179	MPAM_FEATURE_LAST
180};
181
182struct mpam_props {
183	DECLARE_BITMAP(features, MPAM_FEATURE_LAST);
184
185	u16			cpbm_wd;
186	u16			mbw_pbm_bits;
187	u16			bwa_wd;
188	u16			cmax_wd;
189	u16			cassoc_wd;
190	u16			intpri_wd;
191	u16			dspri_wd;
192	u16			num_csu_mon;
193	u16			num_mbwu_mon;
194
195/*
196 * Kunit tests use memset() to set up feature combinations that should be
197 * removed, and will false-positive if the compiler introduces padding that
198 * isn't cleared during sanitisation.
199 */
200} PACKED_FOR_KUNIT;
201
202#define mpam_has_feature(_feat, x)	test_bit(_feat, (x)->features)
203/*
204 * The non-atomic get/set operations are used because if struct mpam_props is
205 * packed, the alignment requirements for atomics aren't met.
206 */
207#define mpam_set_feature(_feat, x)	__set_bit(_feat, (x)->features)
208#define mpam_clear_feature(_feat, x)	__clear_bit(_feat, (x)->features)
209
210/* The values for MSMON_CFG_MBWU_FLT.RWBW */
211enum mon_filter_options {
212	COUNT_BOTH	= 0,
213	COUNT_WRITE	= 1,
214	COUNT_READ	= 2,
215};
216
217struct mon_cfg {
218	u16			mon;
219	u8			pmg;
220	bool			match_pmg;
221	bool			csu_exclude_clean;
222	u32			partid;
223	enum mon_filter_options opts;
224};
225
226/* Changes to msmon_mbwu_state are protected by the msc's mon_sel_lock. */
227struct msmon_mbwu_state {
228	bool		enabled;
229	bool		reset_on_next_read;
230	struct mon_cfg	cfg;
231
232	/*
233	 * The value to add to the new reading to account for power management,
234	 * and overflow.
235	 */
236	u64		correction;
237
238	struct mpam_garbage	garbage;
239};
240
241struct mpam_class {
242	/* mpam_components in this class */
243	struct list_head	components;
244
245	cpumask_t		affinity;
246
247	struct mpam_props	props;
248	u32			nrdy_usec;
249	u8			level;
250	enum mpam_class_types	type;
251
252	/* member of mpam_classes */
253	struct list_head	classes_list;
254
255	struct ida		ida_csu_mon;
256	struct ida		ida_mbwu_mon;
257
258	struct mpam_garbage	garbage;
259};
260
261struct mpam_config {
262	/* Which configuration values are valid. */
263	DECLARE_BITMAP(features, MPAM_FEATURE_LAST);
264
265	u32	cpbm;
266	u32	mbw_pbm;
267	u16	mbw_max;
268
269	bool	reset_cpbm;
270	bool	reset_mbw_pbm;
271	bool	reset_mbw_max;
272
273	struct mpam_garbage	garbage;
274};
275
276struct mpam_component {
277	u32			comp_id;
278
279	/* mpam_vmsc in this component */
280	struct list_head	vmsc;
281
282	cpumask_t		affinity;
283
284	/*
285	 * Array of configuration values, indexed by partid.
286	 * Read from cpuhp callbacks, hold the cpuhp lock when writing.
287	 */
288	struct mpam_config	*cfg;
289
290	/* member of mpam_class:components */
291	struct list_head	class_list;
292
293	/* parent: */
294	struct mpam_class	*class;
295
296	struct mpam_garbage	garbage;
297};
298
299struct mpam_vmsc {
300	/* member of mpam_component:vmsc_list */
301	struct list_head	comp_list;
302
303	/* mpam_msc_ris in this vmsc */
304	struct list_head	ris;
305
306	struct mpam_props	props;
307
308	/* All RIS in this vMSC are members of this MSC */
309	struct mpam_msc		*msc;
310
311	/* parent: */
312	struct mpam_component	*comp;
313
314	struct mpam_garbage	garbage;
315};
316
317struct mpam_msc_ris {
318	u8			ris_idx;
319	u64			idr;
320	struct mpam_props	props;
321	bool			in_reset_state;
322
323	cpumask_t		affinity;
324
325	/* member of mpam_vmsc:ris */
326	struct list_head	vmsc_list;
327
328	/* member of mpam_msc:ris */
329	struct list_head	msc_list;
330
331	/* parent: */
332	struct mpam_vmsc	*vmsc;
333
334	/* msmon mbwu configuration is preserved over reset */
335	struct msmon_mbwu_state	*mbwu_state;
336
337	struct mpam_garbage	garbage;
338};
339
340static inline int mpam_alloc_csu_mon(struct mpam_class *class)
341{
342	struct mpam_props *cprops = &class->props;
343
344	if (!mpam_has_feature(mpam_feat_msmon_csu, cprops))
345		return -EOPNOTSUPP;
346
347	return ida_alloc_max(&class->ida_csu_mon, cprops->num_csu_mon - 1,
348			     GFP_KERNEL);
349}
350
351static inline void mpam_free_csu_mon(struct mpam_class *class, int csu_mon)
352{
353	ida_free(&class->ida_csu_mon, csu_mon);
354}
355
356static inline int mpam_alloc_mbwu_mon(struct mpam_class *class)
357{
358	struct mpam_props *cprops = &class->props;
359
360	if (!mpam_has_feature(mpam_feat_msmon_mbwu, cprops))
361		return -EOPNOTSUPP;
362
363	return ida_alloc_max(&class->ida_mbwu_mon, cprops->num_mbwu_mon - 1,
364			     GFP_KERNEL);
365}
366
367static inline void mpam_free_mbwu_mon(struct mpam_class *class, int mbwu_mon)
368{
369	ida_free(&class->ida_mbwu_mon, mbwu_mon);
370}
371
372/* List of all classes - protected by srcu*/
373extern struct srcu_struct mpam_srcu;
374extern struct list_head mpam_classes;
375
376/* System wide partid/pmg values */
377extern u16 mpam_partid_max;
378extern u8 mpam_pmg_max;
379
380/* Scheduled work callback to enable mpam once all MSC have been probed */
381void mpam_enable(struct work_struct *work);
382void mpam_disable(struct work_struct *work);
383
384int mpam_apply_config(struct mpam_component *comp, u16 partid,
385		      struct mpam_config *cfg);
386
387int mpam_msmon_read(struct mpam_component *comp, struct mon_cfg *ctx,
388		    enum mpam_device_features, u64 *val);
389void mpam_msmon_reset_mbwu(struct mpam_component *comp, struct mon_cfg *ctx);
390
391int mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 cache_level,
392				   cpumask_t *affinity);
393
394/*
395 * MPAM MSCs have the following register layout. See:
396 * Arm Memory System Resource Partitioning and Monitoring (MPAM) System
397 * Component Specification.
398 * https://developer.arm.com/documentation/ihi0099/aa/
399 */
400#define MPAM_ARCHITECTURE_V1    0x10
401
402/* Memory mapped control pages */
403/* ID Register offsets in the memory mapped page */
404#define MPAMF_IDR		0x0000  /* features id register */
405#define MPAMF_IIDR		0x0018  /* implementer id register */
406#define MPAMF_AIDR		0x0020  /* architectural id register */
407#define MPAMF_IMPL_IDR		0x0028  /* imp-def partitioning */
408#define MPAMF_CPOR_IDR		0x0030  /* cache-portion partitioning */
409#define MPAMF_CCAP_IDR		0x0038  /* cache-capacity partitioning */
410#define MPAMF_MBW_IDR		0x0040  /* mem-bw partitioning */
411#define MPAMF_PRI_IDR		0x0048  /* priority partitioning */
412#define MPAMF_MSMON_IDR		0x0080  /* performance monitoring features */
413#define MPAMF_CSUMON_IDR	0x0088  /* cache-usage monitor */
414#define MPAMF_MBWUMON_IDR	0x0090  /* mem-bw usage monitor */
415#define MPAMF_PARTID_NRW_IDR	0x0050  /* partid-narrowing */
416
417/* Configuration and Status Register offsets in the memory mapped page */
418#define MPAMCFG_PART_SEL	0x0100  /* partid to configure */
419#define MPAMCFG_CPBM		0x1000  /* cache-portion config */
420#define MPAMCFG_CMAX		0x0108  /* cache-capacity config */
421#define MPAMCFG_CMIN		0x0110  /* cache-capacity config */
422#define MPAMCFG_CASSOC		0x0118  /* cache-associativity config */
423#define MPAMCFG_MBW_MIN		0x0200  /* min mem-bw config */
424#define MPAMCFG_MBW_MAX		0x0208  /* max mem-bw config */
425#define MPAMCFG_MBW_WINWD	0x0220  /* mem-bw accounting window config */
426#define MPAMCFG_MBW_PBM		0x2000  /* mem-bw portion bitmap config */
427#define MPAMCFG_PRI		0x0400  /* priority partitioning config */
428#define MPAMCFG_MBW_PROP	0x0500  /* mem-bw stride config */
429#define MPAMCFG_INTPARTID	0x0600  /* partid-narrowing config */
430
431#define MSMON_CFG_MON_SEL	0x0800  /* monitor selector */
432#define MSMON_CFG_CSU_FLT	0x0810  /* cache-usage monitor filter */
433#define MSMON_CFG_CSU_CTL	0x0818  /* cache-usage monitor config */
434#define MSMON_CFG_MBWU_FLT	0x0820  /* mem-bw monitor filter */
435#define MSMON_CFG_MBWU_CTL	0x0828  /* mem-bw monitor config */
436#define MSMON_CSU		0x0840  /* current cache-usage */
437#define MSMON_CSU_CAPTURE	0x0848  /* last cache-usage value captured */
438#define MSMON_MBWU		0x0860  /* current mem-bw usage value */
439#define MSMON_MBWU_CAPTURE	0x0868  /* last mem-bw value captured */
440#define MSMON_MBWU_L		0x0880  /* current long mem-bw usage value */
441#define MSMON_MBWU_L_CAPTURE	0x0890  /* last long mem-bw value captured */
442#define MSMON_CAPT_EVNT		0x0808  /* signal a capture event */
443#define MPAMF_ESR		0x00F8  /* error status register */
444#define MPAMF_ECR		0x00F0  /* error control register */
445
446/* MPAMF_IDR - MPAM features ID register */
447#define MPAMF_IDR_PARTID_MAX		GENMASK(15, 0)
448#define MPAMF_IDR_PMG_MAX		GENMASK(23, 16)
449#define MPAMF_IDR_HAS_CCAP_PART		BIT(24)
450#define MPAMF_IDR_HAS_CPOR_PART		BIT(25)
451#define MPAMF_IDR_HAS_MBW_PART		BIT(26)
452#define MPAMF_IDR_HAS_PRI_PART		BIT(27)
453#define MPAMF_IDR_EXT			BIT(28)
454#define MPAMF_IDR_HAS_IMPL_IDR		BIT(29)
455#define MPAMF_IDR_HAS_MSMON		BIT(30)
456#define MPAMF_IDR_HAS_PARTID_NRW	BIT(31)
457#define MPAMF_IDR_HAS_RIS		BIT(32)
458#define MPAMF_IDR_HAS_EXTD_ESR		BIT(38)
459#define MPAMF_IDR_HAS_ESR		BIT(39)
460#define MPAMF_IDR_RIS_MAX		GENMASK(59, 56)
461
462/* MPAMF_MSMON_IDR - MPAM performance monitoring ID register */
463#define MPAMF_MSMON_IDR_MSMON_CSU		BIT(16)
464#define MPAMF_MSMON_IDR_MSMON_MBWU		BIT(17)
465#define MPAMF_MSMON_IDR_HAS_LOCAL_CAPT_EVNT	BIT(31)
466
467/* MPAMF_CPOR_IDR - MPAM features cache portion partitioning ID register */
468#define MPAMF_CPOR_IDR_CPBM_WD			GENMASK(15, 0)
469
470/* MPAMF_CCAP_IDR - MPAM features cache capacity partitioning ID register */
471#define MPAMF_CCAP_IDR_CMAX_WD			GENMASK(5, 0)
472#define MPAMF_CCAP_IDR_CASSOC_WD		GENMASK(12, 8)
473#define MPAMF_CCAP_IDR_HAS_CASSOC		BIT(28)
474#define MPAMF_CCAP_IDR_HAS_CMIN			BIT(29)
475#define MPAMF_CCAP_IDR_NO_CMAX			BIT(30)
476#define MPAMF_CCAP_IDR_HAS_CMAX_SOFTLIM		BIT(31)
477
478/* MPAMF_MBW_IDR - MPAM features memory bandwidth partitioning ID register */
479#define MPAMF_MBW_IDR_BWA_WD		GENMASK(5, 0)
480#define MPAMF_MBW_IDR_HAS_MIN		BIT(10)
481#define MPAMF_MBW_IDR_HAS_MAX		BIT(11)
482#define MPAMF_MBW_IDR_HAS_PBM		BIT(12)
483#define MPAMF_MBW_IDR_HAS_PROP		BIT(13)
484#define MPAMF_MBW_IDR_WINDWR		BIT(14)
485#define MPAMF_MBW_IDR_BWPBM_WD		GENMASK(28, 16)
486
487/* MPAMF_PRI_IDR - MPAM features priority partitioning ID register */
488#define MPAMF_PRI_IDR_HAS_INTPRI	BIT(0)
489#define MPAMF_PRI_IDR_INTPRI_0_IS_LOW	BIT(1)
490#define MPAMF_PRI_IDR_INTPRI_WD		GENMASK(9, 4)
491#define MPAMF_PRI_IDR_HAS_DSPRI		BIT(16)
492#define MPAMF_PRI_IDR_DSPRI_0_IS_LOW	BIT(17)
493#define MPAMF_PRI_IDR_DSPRI_WD		GENMASK(25, 20)
494
495/* MPAMF_CSUMON_IDR - MPAM cache storage usage monitor ID register */
496#define MPAMF_CSUMON_IDR_NUM_MON	GENMASK(15, 0)
497#define MPAMF_CSUMON_IDR_HAS_OFLOW_CAPT	BIT(24)
498#define MPAMF_CSUMON_IDR_HAS_CEVNT_OFLW	BIT(25)
499#define MPAMF_CSUMON_IDR_HAS_OFSR	BIT(26)
500#define MPAMF_CSUMON_IDR_HAS_OFLOW_LNKG	BIT(27)
501#define MPAMF_CSUMON_IDR_HAS_XCL	BIT(29)
502#define MPAMF_CSUMON_IDR_CSU_RO		BIT(30)
503#define MPAMF_CSUMON_IDR_HAS_CAPTURE	BIT(31)
504
505/* MPAMF_MBWUMON_IDR - MPAM memory bandwidth usage monitor ID register */
506#define MPAMF_MBWUMON_IDR_NUM_MON	GENMASK(15, 0)
507#define MPAMF_MBWUMON_IDR_HAS_RWBW	BIT(28)
508#define MPAMF_MBWUMON_IDR_LWD		BIT(29)
509#define MPAMF_MBWUMON_IDR_HAS_LONG	BIT(30)
510#define MPAMF_MBWUMON_IDR_HAS_CAPTURE	BIT(31)
511
512/* MPAMF_PARTID_NRW_IDR - MPAM PARTID narrowing ID register */
513#define MPAMF_PARTID_NRW_IDR_INTPARTID_MAX	GENMASK(15, 0)
514
515/* MPAMF_IIDR - MPAM implementation ID register */
516#define MPAMF_IIDR_IMPLEMENTER	GENMASK(11, 0)
517#define MPAMF_IIDR_REVISION	GENMASK(15, 12)
518#define MPAMF_IIDR_VARIANT	GENMASK(19, 16)
519#define MPAMF_IIDR_PRODUCTID	GENMASK(31, 20)
520
521/* MPAMF_AIDR - MPAM architecture ID register */
522#define MPAMF_AIDR_ARCH_MINOR_REV	GENMASK(3, 0)
523#define MPAMF_AIDR_ARCH_MAJOR_REV	GENMASK(7, 4)
524
525/* MPAMCFG_PART_SEL - MPAM partition configuration selection register */
526#define MPAMCFG_PART_SEL_PARTID_SEL	GENMASK(15, 0)
527#define MPAMCFG_PART_SEL_INTERNAL	BIT(16)
528#define MPAMCFG_PART_SEL_RIS		GENMASK(27, 24)
529
530/* MPAMCFG_CASSOC - MPAM cache maximum associativity partition configuration register */
531#define MPAMCFG_CASSOC_CASSOC		GENMASK(15, 0)
532
533/* MPAMCFG_CMAX - MPAM cache capacity configuration register */
534#define MPAMCFG_CMAX_SOFTLIM		BIT(31)
535#define MPAMCFG_CMAX_CMAX		GENMASK(15, 0)
536
537/* MPAMCFG_CMIN - MPAM cache capacity configuration register */
538#define MPAMCFG_CMIN_CMIN		GENMASK(15, 0)
539
540/*
541 * MPAMCFG_MBW_MIN - MPAM memory minimum bandwidth partitioning configuration
542 *                   register
543 */
544#define MPAMCFG_MBW_MIN_MIN		GENMASK(15, 0)
545
546/*
547 * MPAMCFG_MBW_MAX - MPAM memory maximum bandwidth partitioning configuration
548 *                   register
549 */
550#define MPAMCFG_MBW_MAX_MAX		GENMASK(15, 0)
551#define MPAMCFG_MBW_MAX_HARDLIM		BIT(31)
552
553/*
554 * MPAMCFG_MBW_WINWD - MPAM memory bandwidth partitioning window width
555 *                     register
556 */
557#define MPAMCFG_MBW_WINWD_US_FRAC	GENMASK(7, 0)
558#define MPAMCFG_MBW_WINWD_US_INT	GENMASK(23, 8)
559
560/* MPAMCFG_PRI - MPAM priority partitioning configuration register */
561#define MPAMCFG_PRI_INTPRI		GENMASK(15, 0)
562#define MPAMCFG_PRI_DSPRI		GENMASK(31, 16)
563
564/*
565 * MPAMCFG_MBW_PROP - Memory bandwidth proportional stride partitioning
566 *                    configuration register
567 */
568#define MPAMCFG_MBW_PROP_STRIDEM1	GENMASK(15, 0)
569#define MPAMCFG_MBW_PROP_EN		BIT(31)
570
571/*
572 * MPAMCFG_INTPARTID - MPAM internal partition narrowing configuration register
573 */
574#define MPAMCFG_INTPARTID_INTPARTID	GENMASK(15, 0)
575#define MPAMCFG_INTPARTID_INTERNAL	BIT(16)
576
577/* MSMON_CFG_MON_SEL - Memory system performance monitor selection register */
578#define MSMON_CFG_MON_SEL_MON_SEL	GENMASK(15, 0)
579#define MSMON_CFG_MON_SEL_RIS		GENMASK(27, 24)
580
581/* MPAMF_ESR - MPAM Error Status Register */
582#define MPAMF_ESR_PARTID_MON	GENMASK(15, 0)
583#define MPAMF_ESR_PMG		GENMASK(23, 16)
584#define MPAMF_ESR_ERRCODE	GENMASK(27, 24)
585#define MPAMF_ESR_OVRWR		BIT(31)
586#define MPAMF_ESR_RIS		GENMASK(35, 32)
587
588/* MPAMF_ECR - MPAM Error Control Register */
589#define MPAMF_ECR_INTEN		BIT(0)
590
591/* Error conditions in accessing memory mapped registers */
592#define MPAM_ERRCODE_NONE			0
593#define MPAM_ERRCODE_PARTID_SEL_RANGE		1
594#define MPAM_ERRCODE_REQ_PARTID_RANGE		2
595#define MPAM_ERRCODE_MSMONCFG_ID_RANGE		3
596#define MPAM_ERRCODE_REQ_PMG_RANGE		4
597#define MPAM_ERRCODE_MONITOR_RANGE		5
598#define MPAM_ERRCODE_INTPARTID_RANGE		6
599#define MPAM_ERRCODE_UNEXPECTED_INTERNAL	7
600#define MPAM_ERRCODE_UNDEFINED_RIS_PART_SEL	8
601#define MPAM_ERRCODE_RIS_NO_CONTROL		9
602#define MPAM_ERRCODE_UNDEFINED_RIS_MON_SEL	10
603#define MPAM_ERRCODE_RIS_NO_MONITOR		11
604
605/*
606 * MSMON_CFG_CSU_CTL - Memory system performance monitor configure cache storage
607 *                    usage monitor control register
608 * MSMON_CFG_MBWU_CTL - Memory system performance monitor configure memory
609 *                     bandwidth usage monitor control register
610 */
611#define MSMON_CFG_x_CTL_TYPE			GENMASK(7, 0)
612#define MSMON_CFG_MBWU_CTL_OFLOW_STATUS_L	BIT(15)
613#define MSMON_CFG_x_CTL_MATCH_PARTID		BIT(16)
614#define MSMON_CFG_x_CTL_MATCH_PMG		BIT(17)
615#define MSMON_CFG_MBWU_CTL_SCLEN		BIT(19)
616#define MSMON_CFG_x_CTL_SUBTYPE			GENMASK(22, 20)
617#define MSMON_CFG_x_CTL_OFLOW_FRZ		BIT(24)
618#define MSMON_CFG_x_CTL_OFLOW_INTR		BIT(25)
619#define MSMON_CFG_x_CTL_OFLOW_STATUS		BIT(26)
620#define MSMON_CFG_x_CTL_CAPT_RESET		BIT(27)
621#define MSMON_CFG_x_CTL_CAPT_EVNT		GENMASK(30, 28)
622#define MSMON_CFG_x_CTL_EN			BIT(31)
623
624#define MSMON_CFG_MBWU_CTL_TYPE_MBWU		0x42
625#define MSMON_CFG_CSU_CTL_TYPE_CSU		0x43
626
627/*
628 * MSMON_CFG_CSU_FLT -  Memory system performance monitor configure cache storage
629 *                      usage monitor filter register
630 * MSMON_CFG_MBWU_FLT - Memory system performance monitor configure memory
631 *                      bandwidth usage monitor filter register
632 */
633#define MSMON_CFG_x_FLT_PARTID			GENMASK(15, 0)
634#define MSMON_CFG_x_FLT_PMG			GENMASK(23, 16)
635
636#define MSMON_CFG_MBWU_FLT_RWBW			GENMASK(31, 30)
637#define MSMON_CFG_CSU_FLT_XCL			BIT(31)
638
639/*
640 * MSMON_CSU - Memory system performance monitor cache storage usage monitor
641 *            register
642 * MSMON_CSU_CAPTURE -  Memory system performance monitor cache storage usage
643 *                     capture register
644 * MSMON_MBWU  - Memory system performance monitor memory bandwidth usage
645 *               monitor register
646 * MSMON_MBWU_CAPTURE - Memory system performance monitor memory bandwidth usage
647 *                     capture register
648 */
649#define MSMON___VALUE		GENMASK(30, 0)
650#define MSMON___NRDY		BIT(31)
651#define MSMON___L_NRDY		BIT(63)
652#define MSMON___L_VALUE		GENMASK(43, 0)
653#define MSMON___LWD_VALUE	GENMASK(62, 0)
654
655/*
656 * MSMON_CAPT_EVNT - Memory system performance monitoring capture event
657 *                  generation register
658 */
659#define MSMON_CAPT_EVNT_NOW	BIT(0)
660
661#endif /* MPAM_INTERNAL_H */