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rt5133-regulator.c
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linux-6.19.14/drivers/regulator/rt5133-regulator.c
1// SPDX-License-Identifier: GPL-2.0 2// Copyright (C) 2025 Richtek Technology Corp. 3// Author: ChiYuan Huang <cy_huang@richtek.com> 4// Author: ShihChia Chang <jeff_chang@richtek.com> 5 6#include <linux/crc8.h> 7#include <linux/delay.h> 8#include <linux/gpio/consumer.h> 9#include <linux/gpio/driver.h> 10#include <linux/i2c.h> 11#include <linux/interrupt.h> 12#include <linux/kernel.h> 13#include <linux/module.h> 14#include <linux/of.h> 15#include <linux/regmap.h> 16#include <linux/regulator/driver.h> 17 18#define RT5133_REG_CHIP_INFO 0x00 19#define RT5133_REG_RST_CTRL 0x06 20#define RT5133_REG_BASE_CTRL 0x09 21#define RT5133_REG_GPIO_CTRL 0x0B 22#define RT5133_REG_BASE_EVT 0x10 23#define RT5133_REG_LDO_PGB_STAT 0x15 24#define RT5133_REG_BASE_MASK 0x16 25#define RT5133_REG_LDO_SHDN 0x19 26#define RT5133_REG_LDO_ON 0x1A 27#define RT5133_REG_LDO_OFF 0x1B 28#define RT5133_REG_LDO1_CTRL1 0x20 29#define RT5133_REG_LDO1_CTRL2 0x21 30#define RT5133_REG_LDO1_CTRL3 0x22 31#define RT5133_REG_LDO2_CTRL1 0x24 32#define RT5133_REG_LDO2_CTRL2 0x25 33#define RT5133_REG_LDO2_CTRL3 0x26 34#define RT5133_REG_LDO3_CTRL1 0x28 35#define RT5133_REG_LDO3_CTRL2 0x29 36#define RT5133_REG_LDO3_CTRL3 0x2A 37#define RT5133_REG_LDO4_CTRL1 0x2C 38#define RT5133_REG_LDO4_CTRL2 0x2D 39#define RT5133_REG_LDO4_CTRL3 0x2E 40#define RT5133_REG_LDO5_CTRL1 0x30 41#define RT5133_REG_LDO5_CTRL2 0x31 42#define RT5133_REG_LDO5_CTRL3 0x32 43#define RT5133_REG_LDO6_CTRL1 0x34 44#define RT5133_REG_LDO6_CTRL2 0x35 45#define RT5133_REG_LDO6_CTRL3 0x36 46#define RT5133_REG_LDO7_CTRL1 0x38 47#define RT5133_REG_LDO7_CTRL2 0x39 48#define RT5133_REG_LDO7_CTRL3 0x3A 49#define RT5133_REG_LDO8_CTRL1 0x3C 50#define RT5133_REG_LDO8_CTRL2 0x3D 51#define RT5133_REG_LDO8_CTRL3 0x3E 52#define RT5133_REG_LDO8_CTRL4 0x3F 53 54#define RT5133_LDO_REG_BASE(_id) (0x20 + ((_id) - 1) * 4) 55 56#define RT5133_VENDOR_ID_MASK GENMASK(7, 4) 57#define RT5133_RESET_CODE 0xB1 58 59#define RT5133_FOFF_BASE_MASK BIT(1) 60#define RT5133_OCSHDN_ALL_MASK BIT(7) 61#define RT5133_OCSHDN_ALL_SHIFT (7) 62#define RT5133_PGBSHDN_ALL_MASK BIT(6) 63#define RT5133_PGBSHDN_ALL_SHIFT (6) 64 65#define RT5133_OCPTSEL_MASK BIT(5) 66#define RT5133_PGBPTSEL_MASK BIT(4) 67#define RT5133_STBTDSEL_MASK GENMASK(1, 0) 68 69#define RT5133_LDO_ENABLE_MASK BIT(7) 70#define RT5133_LDO_VSEL_MASK GENMASK(7, 5) 71#define RT5133_LDO_AD_MASK BIT(2) 72#define RT5133_LDO_SOFT_START_MASK GENMASK(1, 0) 73 74#define RT5133_GPIO_NR 3 75 76#define RT5133_LDO_PGB_EVT_MASK GENMASK(23, 16) 77#define RT5133_LDO_PGB_EVT_SHIFT 16 78#define RT5133_LDO_OC_EVT_MASK GENMASK(15, 8) 79#define RT5133_LDO_OC_EVT_SHIFT 8 80#define RT5133_VREF_EVT_MASK BIT(6) 81#define RT5133_BASE_EVT_MASK GENMASK(7, 0) 82#define RT5133_INTR_CLR_MASK GENMASK(23, 0) 83#define RT5133_INTR_BYTE_NR 3 84 85#define RT5133_MAX_I2C_BLOCK_SIZE 1 86 87#define RT5133_CRC8_POLYNOMIAL 0x7 88 89#define RT5133_I2C_ADDR_LEN 1 90#define RT5133_PREDATA_LEN 2 91#define RT5133_I2C_CRC_LEN 1 92#define RT5133_REG_ADDR_LEN 1 93#define RT5133_I2C_DUMMY_LEN 1 94 95#define I2C_ADDR_XLATE_8BIT(_addr, _rw) ((((_addr) & 0x7F) << 1) | (_rw)) 96 97enum { 98 RT5133_REGULATOR_BASE = 0, 99 RT5133_REGULATOR_LDO1, 100 RT5133_REGULATOR_LDO2, 101 RT5133_REGULATOR_LDO3, 102 RT5133_REGULATOR_LDO4, 103 RT5133_REGULATOR_LDO5, 104 RT5133_REGULATOR_LDO6, 105 RT5133_REGULATOR_LDO7, 106 RT5133_REGULATOR_LDO8, 107 RT5133_REGULATOR_MAX 108}; 109 110struct chip_data { 111 const struct regulator_desc *regulators; 112 const u8 vendor_id; 113}; 114 115struct rt5133_priv { 116 struct device *dev; 117 struct regmap *regmap; 118 struct gpio_desc *enable_gpio; 119 struct regulator_dev *rdev[RT5133_REGULATOR_MAX]; 120 struct gpio_chip gc; 121 const struct chip_data *cdata; 122 unsigned int gpio_output_flag; 123 u8 crc8_tbls[CRC8_TABLE_SIZE]; 124}; 125 126static const unsigned int vout_type1_tables[] = { 127 1800000, 2500000, 2700000, 2800000, 2900000, 3000000, 3100000, 3200000 128}; 129 130static const unsigned int vout_type2_tables[] = { 131 1700000, 1800000, 1900000, 2500000, 2700000, 2800000, 2900000, 3000000 132}; 133 134static const unsigned int vout_type3_tables[] = { 135 900000, 950000, 1000000, 1050000, 1100000, 1150000, 1200000, 1800000 136}; 137 138static const unsigned int vout_type4_tables[] = { 139 855000, 900000, 950000, 1000000, 1040000, 1090000, 1140000, 1710000 140}; 141 142static const struct regulator_ops rt5133_regulator_ops = { 143 .list_voltage = regulator_list_voltage_table, 144 .set_voltage_sel = regulator_set_voltage_sel_regmap, 145 .get_voltage_sel = regulator_get_voltage_sel_regmap, 146 .enable = regulator_enable_regmap, 147 .disable = regulator_disable_regmap, 148 .is_enabled = regulator_is_enabled_regmap, 149 .set_active_discharge = regulator_set_active_discharge_regmap, 150}; 151 152static const struct regulator_ops rt5133_base_regulator_ops = { 153 .enable = regulator_enable_regmap, 154 .disable = regulator_disable_regmap, 155 .is_enabled = regulator_is_enabled_regmap, 156}; 157 158#define RT5133_REGULATOR_DESC(_name, _node_name, vtables, _supply) \ 159{\ 160 .name = #_name,\ 161 .id = RT5133_REGULATOR_##_name,\ 162 .of_match = of_match_ptr(#_node_name),\ 163 .regulators_node = of_match_ptr("regulators"),\ 164 .supply_name = _supply,\ 165 .type = REGULATOR_VOLTAGE,\ 166 .owner = THIS_MODULE,\ 167 .ops = &rt5133_regulator_ops,\ 168 .n_voltages = ARRAY_SIZE(vtables),\ 169 .volt_table = vtables,\ 170 .enable_reg = RT5133_REG_##_name##_CTRL1,\ 171 .enable_mask = RT5133_LDO_ENABLE_MASK,\ 172 .vsel_reg = RT5133_REG_##_name##_CTRL2,\ 173 .vsel_mask = RT5133_LDO_VSEL_MASK,\ 174 .active_discharge_reg = RT5133_REG_##_name##_CTRL3,\ 175 .active_discharge_mask = RT5133_LDO_AD_MASK,\ 176} 177 178static const struct regulator_desc rt5133_regulators[] = { 179 /* For digital part, base current control */ 180 { 181 .name = "base", 182 .id = RT5133_REGULATOR_BASE, 183 .of_match = of_match_ptr("base"), 184 .regulators_node = of_match_ptr("regulators"), 185 .type = REGULATOR_VOLTAGE, 186 .owner = THIS_MODULE, 187 .ops = &rt5133_base_regulator_ops, 188 .enable_reg = RT5133_REG_BASE_CTRL, 189 .enable_mask = RT5133_FOFF_BASE_MASK, 190 .enable_is_inverted = true, 191 }, 192 RT5133_REGULATOR_DESC(LDO1, ldo1, vout_type1_tables, "base"), 193 RT5133_REGULATOR_DESC(LDO2, ldo2, vout_type1_tables, "base"), 194 RT5133_REGULATOR_DESC(LDO3, ldo3, vout_type2_tables, "base"), 195 RT5133_REGULATOR_DESC(LDO4, ldo4, vout_type2_tables, "base"), 196 RT5133_REGULATOR_DESC(LDO5, ldo5, vout_type2_tables, "base"), 197 RT5133_REGULATOR_DESC(LDO6, ldo6, vout_type2_tables, "base"), 198 RT5133_REGULATOR_DESC(LDO7, ldo7, vout_type3_tables, "vin"), 199 RT5133_REGULATOR_DESC(LDO8, ldo8, vout_type3_tables, "vin"), 200}; 201 202static const struct regulator_desc rt5133a_regulators[] = { 203 /* For digital part, base current control */ 204 { 205 .name = "base", 206 .id = RT5133_REGULATOR_BASE, 207 .of_match = of_match_ptr("base"), 208 .regulators_node = of_match_ptr("regulators"), 209 .type = REGULATOR_VOLTAGE, 210 .owner = THIS_MODULE, 211 .ops = &rt5133_base_regulator_ops, 212 .enable_reg = RT5133_REG_BASE_CTRL, 213 .enable_mask = RT5133_FOFF_BASE_MASK, 214 .enable_is_inverted = true, 215 }, 216 RT5133_REGULATOR_DESC(LDO1, ldo1, vout_type1_tables, "base"), 217 RT5133_REGULATOR_DESC(LDO2, ldo2, vout_type1_tables, "base"), 218 RT5133_REGULATOR_DESC(LDO3, ldo3, vout_type2_tables, "base"), 219 RT5133_REGULATOR_DESC(LDO4, ldo4, vout_type2_tables, "base"), 220 RT5133_REGULATOR_DESC(LDO5, ldo5, vout_type2_tables, "base"), 221 RT5133_REGULATOR_DESC(LDO6, ldo6, vout_type2_tables, "base"), 222 RT5133_REGULATOR_DESC(LDO7, ldo7, vout_type3_tables, "vin"), 223 RT5133_REGULATOR_DESC(LDO8, ldo8, vout_type4_tables, "vin"), 224}; 225 226static const struct chip_data regulator_data[] = { 227 { rt5133_regulators, 0x70}, 228 { rt5133a_regulators, 0x80}, 229}; 230 231static int rt5133_gpio_direction_output(struct gpio_chip *gpio, 232 unsigned int offset, int value) 233{ 234 struct rt5133_priv *priv = gpiochip_get_data(gpio); 235 236 if (offset >= RT5133_GPIO_NR) 237 return -EINVAL; 238 239 return regmap_update_bits(priv->regmap, RT5133_REG_GPIO_CTRL, 240 BIT(7 - offset) | BIT(3 - offset), 241 value ? BIT(7 - offset) | BIT(3 - offset) : 0); 242} 243 244static int rt5133_gpio_get(struct gpio_chip *chip, unsigned int offset) 245{ 246 struct rt5133_priv *priv = gpiochip_get_data(chip); 247 248 return !!(priv->gpio_output_flag & BIT(offset)); 249} 250 251static int rt5133_get_gpioen_mask(unsigned int offset, unsigned int *mask) 252{ 253 if (offset >= RT5133_GPIO_NR) 254 return -EINVAL; 255 256 *mask = (BIT(7 - offset) | BIT(3 - offset)); 257 258 return 0; 259} 260 261static int rt5133_gpio_set(struct gpio_chip *chip, unsigned int offset, int set_val) 262{ 263 struct rt5133_priv *priv = gpiochip_get_data(chip); 264 unsigned int mask = 0, val = 0, next_flag = priv->gpio_output_flag; 265 int ret = 0; 266 267 ret = rt5133_get_gpioen_mask(offset, &mask); 268 if (ret) { 269 dev_err(priv->dev, "%s get gpion en mask failed, offset(%d)\n", __func__, offset); 270 return ret; 271 } 272 273 val = set_val ? mask : 0; 274 275 if (set_val) 276 next_flag |= BIT(offset); 277 else 278 next_flag &= ~BIT(offset); 279 280 ret = regmap_update_bits(priv->regmap, RT5133_REG_GPIO_CTRL, mask, val); 281 if (ret) { 282 dev_err(priv->dev, "Failed to set gpio [%d] val %d\n", offset, 283 set_val); 284 return ret; 285 } 286 287 priv->gpio_output_flag = next_flag; 288 return 0; 289} 290 291static irqreturn_t rt5133_intr_handler(int irq_number, void *data) 292{ 293 struct rt5133_priv *priv = data; 294 u32 intr_evts = 0, handle_evts; 295 int i, ret; 296 297 ret = regmap_bulk_read(priv->regmap, RT5133_REG_BASE_EVT, &intr_evts, 298 RT5133_INTR_BYTE_NR); 299 if (ret) { 300 dev_err(priv->dev, "%s, read event failed\n", __func__); 301 return IRQ_NONE; 302 } 303 304 handle_evts = intr_evts & RT5133_BASE_EVT_MASK; 305 /* 306 * VREF_EVT is a special case, if base off 307 * this event will also be trigger. Skip it 308 */ 309 if (handle_evts & ~RT5133_VREF_EVT_MASK) 310 dev_dbg(priv->dev, "base event occurred [0x%02x]\n", 311 handle_evts); 312 313 handle_evts = (intr_evts & RT5133_LDO_OC_EVT_MASK) >> 314 RT5133_LDO_OC_EVT_SHIFT; 315 316 for (i = RT5133_REGULATOR_LDO1; i < RT5133_REGULATOR_MAX && handle_evts; i++) { 317 if (!(handle_evts & BIT(i - 1))) 318 continue; 319 regulator_notifier_call_chain(priv->rdev[i], 320 REGULATOR_EVENT_OVER_CURRENT, 321 &i); 322 } 323 324 handle_evts = (intr_evts & RT5133_LDO_PGB_EVT_MASK) >> 325 RT5133_LDO_PGB_EVT_SHIFT; 326 for (i = RT5133_REGULATOR_LDO1; i < RT5133_REGULATOR_MAX && handle_evts; i++) { 327 if (!(handle_evts & BIT(i - 1))) 328 continue; 329 regulator_notifier_call_chain(priv->rdev[i], 330 REGULATOR_EVENT_FAIL, &i); 331 } 332 333 ret = regmap_bulk_write(priv->regmap, RT5133_REG_BASE_EVT, &intr_evts, 334 RT5133_INTR_BYTE_NR); 335 if (ret) 336 dev_err(priv->dev, "%s, clear event failed\n", __func__); 337 338 return IRQ_HANDLED; 339} 340 341static int rt5133_enable_interrupts(int irq_no, struct rt5133_priv *priv) 342{ 343 u32 mask = RT5133_INTR_CLR_MASK; 344 int ret; 345 346 /* Force to write clear all events */ 347 ret = regmap_bulk_write(priv->regmap, RT5133_REG_BASE_EVT, &mask, 348 RT5133_INTR_BYTE_NR); 349 if (ret) { 350 dev_err(priv->dev, "Failed to clear all interrupts\n"); 351 return ret; 352 } 353 354 /* Unmask all interrupts */ 355 mask = 0; 356 ret = regmap_bulk_write(priv->regmap, RT5133_REG_BASE_MASK, &mask, 357 RT5133_INTR_BYTE_NR); 358 if (ret) { 359 dev_err(priv->dev, "Failed to unmask all interrupts\n"); 360 return ret; 361 } 362 363 return devm_request_threaded_irq(priv->dev, irq_no, NULL, 364 rt5133_intr_handler, IRQF_ONESHOT, 365 dev_name(priv->dev), priv); 366} 367 368static int rt5133_regmap_hw_read(void *context, const void *reg_buf, 369 size_t reg_size, void *val_buf, 370 size_t val_size) 371{ 372 struct rt5133_priv *priv = context; 373 struct i2c_client *client = to_i2c_client(priv->dev); 374 u8 reg = *(u8 *)reg_buf, crc; 375 u8 *buf; 376 int buf_len = RT5133_PREDATA_LEN + val_size + RT5133_I2C_CRC_LEN; 377 int read_len, ret; 378 379 buf = kzalloc(buf_len, GFP_KERNEL); 380 if (!buf) 381 return -ENOMEM; 382 383 buf[0] = I2C_ADDR_XLATE_8BIT(client->addr, I2C_SMBUS_READ); 384 buf[1] = reg; 385 386 read_len = val_size + RT5133_I2C_CRC_LEN; 387 ret = i2c_smbus_read_i2c_block_data(client, reg, read_len, 388 buf + RT5133_PREDATA_LEN); 389 390 if (ret < 0) 391 goto out_read_err; 392 393 if (ret != read_len) { 394 ret = -EIO; 395 goto out_read_err; 396 } 397 398 crc = crc8(priv->crc8_tbls, buf, RT5133_PREDATA_LEN + val_size, 0); 399 if (crc != buf[RT5133_PREDATA_LEN + val_size]) { 400 ret = -EIO; 401 goto out_read_err; 402 } 403 404 memcpy(val_buf, buf + RT5133_PREDATA_LEN, val_size); 405 dev_dbg(priv->dev, "%s, reg = 0x%02x, data = 0x%02x\n", __func__, reg, *(u8 *)val_buf); 406 407out_read_err: 408 kfree(buf); 409 return (ret < 0) ? ret : 0; 410} 411 412static int rt5133_regmap_hw_write(void *context, const void *data, size_t count) 413{ 414 struct rt5133_priv *priv = context; 415 struct i2c_client *client = to_i2c_client(priv->dev); 416 u8 reg = *(u8 *)data, crc; 417 u8 *buf; 418 int buf_len = RT5133_I2C_ADDR_LEN + count + RT5133_I2C_CRC_LEN + 419 RT5133_I2C_DUMMY_LEN; 420 int write_len, ret; 421 422 buf = kzalloc(buf_len, GFP_KERNEL); 423 if (!buf) 424 return -ENOMEM; 425 426 buf[0] = I2C_ADDR_XLATE_8BIT(client->addr, I2C_SMBUS_WRITE); 427 buf[1] = reg; 428 memcpy(buf + RT5133_PREDATA_LEN, data + RT5133_REG_ADDR_LEN, 429 count - RT5133_REG_ADDR_LEN); 430 431 crc = crc8(priv->crc8_tbls, buf, RT5133_I2C_ADDR_LEN + count, 0); 432 buf[RT5133_I2C_ADDR_LEN + count] = crc; 433 434 write_len = count - RT5133_REG_ADDR_LEN + RT5133_I2C_CRC_LEN + 435 RT5133_I2C_DUMMY_LEN; 436 ret = i2c_smbus_write_i2c_block_data(client, reg, write_len, 437 buf + RT5133_PREDATA_LEN); 438 439 dev_dbg(priv->dev, "%s, reg = 0x%02x, data = 0x%02x\n", __func__, reg, 440 *(u8 *)(buf + RT5133_PREDATA_LEN)); 441 kfree(buf); 442 return ret; 443} 444 445static const struct regmap_bus rt5133_regmap_bus = { 446 .read = rt5133_regmap_hw_read, 447 .write = rt5133_regmap_hw_write, 448 /* Due to crc, the block read/write length has the limit */ 449 .max_raw_read = RT5133_MAX_I2C_BLOCK_SIZE, 450 .max_raw_write = RT5133_MAX_I2C_BLOCK_SIZE, 451}; 452 453static bool rt5133_is_volatile_reg(struct device *dev, unsigned int reg) 454{ 455 switch (reg) { 456 case RT5133_REG_CHIP_INFO: 457 case RT5133_REG_BASE_EVT...RT5133_REG_LDO_PGB_STAT: 458 case RT5133_REG_LDO_ON...RT5133_REG_LDO_OFF: 459 case RT5133_REG_LDO1_CTRL1: 460 case RT5133_REG_LDO2_CTRL1: 461 case RT5133_REG_LDO3_CTRL1: 462 case RT5133_REG_LDO4_CTRL1: 463 case RT5133_REG_LDO5_CTRL1: 464 case RT5133_REG_LDO6_CTRL1: 465 case RT5133_REG_LDO7_CTRL1: 466 case RT5133_REG_LDO8_CTRL1: 467 return true; 468 default: 469 return false; 470 }; 471} 472 473static const struct regmap_config rt5133_regmap_config = { 474 .reg_bits = 8, 475 .val_bits = 8, 476 .max_register = RT5133_REG_LDO8_CTRL4, 477 .cache_type = REGCACHE_FLAT, 478 .num_reg_defaults_raw = RT5133_REG_LDO8_CTRL4 + 1, 479 .volatile_reg = rt5133_is_volatile_reg, 480}; 481 482static int rt5133_chip_reset(struct rt5133_priv *priv) 483{ 484 int ret; 485 486 ret = regmap_write(priv->regmap, RT5133_REG_RST_CTRL, 487 RT5133_RESET_CODE); 488 if (ret) 489 return ret; 490 491 /* Wait for register reset to take effect */ 492 udelay(2); 493 494 return 0; 495} 496 497static int rt5133_validate_vendor_info(struct rt5133_priv *priv) 498{ 499 unsigned int val = 0; 500 int i, ret; 501 502 ret = regmap_read(priv->regmap, RT5133_REG_CHIP_INFO, &val); 503 if (ret) 504 return ret; 505 506 for (i = 0; i < ARRAY_SIZE(regulator_data); i++) { 507 if ((val & RT5133_VENDOR_ID_MASK) == 508 regulator_data[i].vendor_id){ 509 priv->cdata = ®ulator_data[i]; 510 break; 511 } 512 } 513 if (!priv->cdata) { 514 dev_err(priv->dev, "Failed to find regulator match version\n"); 515 return -ENODEV; 516 } 517 518 return 0; 519} 520 521static int rt5133_parse_dt(struct rt5133_priv *priv) 522{ 523 unsigned int val = 0; 524 int ret = 0; 525 526 if (!device_property_read_bool(priv->dev, "richtek,oc-shutdown-all")) 527 val = 0; 528 else 529 val = 1 << RT5133_OCSHDN_ALL_SHIFT; 530 ret = regmap_update_bits(priv->regmap, RT5133_REG_LDO_SHDN, 531 RT5133_OCSHDN_ALL_MASK, val); 532 if (ret) 533 return ret; 534 535 if (!device_property_read_bool(priv->dev, "richtek,pgb-shutdown-all")) 536 val = 0; 537 else 538 val = 1 << RT5133_PGBSHDN_ALL_SHIFT; 539 return regmap_update_bits(priv->regmap, RT5133_REG_LDO_SHDN, 540 RT5133_PGBSHDN_ALL_MASK, val); 541} 542 543static int rt5133_probe(struct i2c_client *i2c) 544{ 545 struct rt5133_priv *priv; 546 struct regulator_config config = {0}; 547 int i, ret; 548 549 priv = devm_kzalloc(&i2c->dev, sizeof(*priv), GFP_KERNEL); 550 if (!priv) 551 return -ENOMEM; 552 553 priv->dev = &i2c->dev; 554 crc8_populate_msb(priv->crc8_tbls, RT5133_CRC8_POLYNOMIAL); 555 556 priv->enable_gpio = devm_gpiod_get_optional(&i2c->dev, "enable", 557 GPIOD_OUT_HIGH); 558 if (IS_ERR(priv->enable_gpio)) 559 dev_err(&i2c->dev, "Failed to request HWEN gpio, check if default en=high\n"); 560 561 priv->regmap = devm_regmap_init(&i2c->dev, &rt5133_regmap_bus, priv, 562 &rt5133_regmap_config); 563 if (IS_ERR(priv->regmap)) { 564 dev_err(&i2c->dev, "Failed to register regmap\n"); 565 return PTR_ERR(priv->regmap); 566 } 567 568 ret = rt5133_validate_vendor_info(priv); 569 if (ret) { 570 dev_err(&i2c->dev, "Failed to check vendor info [%d]\n", ret); 571 return ret; 572 } 573 574 ret = rt5133_chip_reset(priv); 575 if (ret) { 576 dev_err(&i2c->dev, "Failed to execute sw reset\n"); 577 return ret; 578 } 579 580 config.dev = &i2c->dev; 581 config.driver_data = priv; 582 config.regmap = priv->regmap; 583 584 for (i = 0; i < RT5133_REGULATOR_MAX; i++) { 585 priv->rdev[i] = devm_regulator_register(&i2c->dev, 586 priv->cdata->regulators + i, 587 &config); 588 if (IS_ERR(priv->rdev[i])) { 589 dev_err(&i2c->dev, 590 "Failed to register [%d] regulator\n", i); 591 return PTR_ERR(priv->rdev[i]); 592 } 593 } 594 595 ret = rt5133_parse_dt(priv); 596 if (ret) { 597 dev_err(&i2c->dev, "%s, Failed to parse dt\n", __func__); 598 return ret; 599 } 600 601 priv->gc.label = dev_name(&i2c->dev); 602 priv->gc.parent = &i2c->dev; 603 priv->gc.base = -1; 604 priv->gc.ngpio = RT5133_GPIO_NR; 605 priv->gc.set = rt5133_gpio_set; 606 priv->gc.get = rt5133_gpio_get; 607 priv->gc.direction_output = rt5133_gpio_direction_output; 608 priv->gc.can_sleep = true; 609 610 ret = devm_gpiochip_add_data(&i2c->dev, &priv->gc, priv); 611 if (ret) 612 return ret; 613 614 ret = rt5133_enable_interrupts(i2c->irq, priv); 615 if (ret) { 616 dev_err(&i2c->dev, "enable interrupt failed\n"); 617 return ret; 618 } 619 620 i2c_set_clientdata(i2c, priv); 621 622 return ret; 623} 624 625static const struct of_device_id __maybe_unused rt5133_of_match_table[] = { 626 { .compatible = "richtek,rt5133", }, 627 { } 628}; 629MODULE_DEVICE_TABLE(of, rt5133_of_match_table); 630 631static struct i2c_driver rt5133_driver = { 632 .driver = { 633 .name = "rt5133", 634 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 635 .of_match_table = rt5133_of_match_table, 636 }, 637 .probe = rt5133_probe, 638}; 639module_i2c_driver(rt5133_driver); 640 641MODULE_DESCRIPTION("RT5133 Regulator Driver"); 642MODULE_LICENSE("GPL v2");
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