system.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * AMD Address Translation Library
  4 *
  5 * system.c : Functions to read and save system-wide data
  6 *
  7 * Copyright (c) 2023, Advanced Micro Devices, Inc.
  8 * All Rights Reserved.
  9 *
 10 * Author: Yazen Ghannam <Yazen.Ghannam@amd.com>
 11 */
 12
 13#include "internal.h"
 14
 15#include <linux/prmt.h>
 16
 17const guid_t norm_to_sys_guid = GUID_INIT(0xE7180659, 0xA65D, 0x451D,
 18					  0x92, 0xCD, 0x2B, 0x56, 0xF1,
 19					  0x2B, 0xEB, 0xA6);
 20
 21int determine_node_id(struct addr_ctx *ctx, u8 socket_id, u8 die_id)
 22{
 23	u16 socket_id_bits, die_id_bits;
 24
 25	if (socket_id > 0 && df_cfg.socket_id_mask == 0) {
 26		atl_debug(ctx, "Invalid socket inputs: socket_id=%u socket_id_mask=0x%x",
 27			  socket_id, df_cfg.socket_id_mask);
 28		return -EINVAL;
 29	}
 30
 31	/* Do each step independently to avoid shift out-of-bounds issues. */
 32	socket_id_bits =	socket_id;
 33	socket_id_bits <<=	df_cfg.socket_id_shift;
 34	socket_id_bits &=	df_cfg.socket_id_mask;
 35
 36	if (die_id > 0 && df_cfg.die_id_mask == 0) {
 37		atl_debug(ctx, "Invalid die inputs: die_id=%u die_id_mask=0x%x",
 38			  die_id, df_cfg.die_id_mask);
 39		return -EINVAL;
 40	}
 41
 42	/* Do each step independently to avoid shift out-of-bounds issues. */
 43	die_id_bits =		die_id;
 44	die_id_bits <<=		df_cfg.die_id_shift;
 45	die_id_bits &=		df_cfg.die_id_mask;
 46
 47	ctx->node_id = (socket_id_bits | die_id_bits) >> df_cfg.node_id_shift;
 48	return 0;
 49}
 50
 51static void df2_get_masks_shifts(u32 mask0)
 52{
 53	df_cfg.socket_id_shift		= FIELD_GET(DF2_SOCKET_ID_SHIFT, mask0);
 54	df_cfg.socket_id_mask		= FIELD_GET(DF2_SOCKET_ID_MASK, mask0);
 55	df_cfg.die_id_shift		= FIELD_GET(DF2_DIE_ID_SHIFT, mask0);
 56	df_cfg.die_id_mask		= FIELD_GET(DF2_DIE_ID_MASK, mask0);
 57	df_cfg.node_id_shift		= df_cfg.die_id_shift;
 58	df_cfg.node_id_mask		= df_cfg.socket_id_mask | df_cfg.die_id_mask;
 59	df_cfg.component_id_mask	= ~df_cfg.node_id_mask;
 60}
 61
 62static void df3_get_masks_shifts(u32 mask0, u32 mask1)
 63{
 64	df_cfg.component_id_mask	= FIELD_GET(DF3_COMPONENT_ID_MASK, mask0);
 65	df_cfg.node_id_mask		= FIELD_GET(DF3_NODE_ID_MASK, mask0);
 66
 67	df_cfg.node_id_shift		= FIELD_GET(DF3_NODE_ID_SHIFT, mask1);
 68	df_cfg.socket_id_shift		= FIELD_GET(DF3_SOCKET_ID_SHIFT, mask1);
 69	df_cfg.socket_id_mask		= FIELD_GET(DF3_SOCKET_ID_MASK, mask1);
 70	df_cfg.die_id_mask		= FIELD_GET(DF3_DIE_ID_MASK, mask1);
 71}
 72
 73static void df3p5_get_masks_shifts(u32 mask0, u32 mask1, u32 mask2)
 74{
 75	df_cfg.component_id_mask	= FIELD_GET(DF4_COMPONENT_ID_MASK, mask0);
 76	df_cfg.node_id_mask		= FIELD_GET(DF4_NODE_ID_MASK, mask0);
 77
 78	df_cfg.node_id_shift		= FIELD_GET(DF3_NODE_ID_SHIFT, mask1);
 79	df_cfg.socket_id_shift		= FIELD_GET(DF4_SOCKET_ID_SHIFT, mask1);
 80
 81	df_cfg.socket_id_mask		= FIELD_GET(DF4_SOCKET_ID_MASK, mask2);
 82	df_cfg.die_id_mask		= FIELD_GET(DF4_DIE_ID_MASK, mask2);
 83}
 84
 85static void df4_get_masks_shifts(u32 mask0, u32 mask1, u32 mask2)
 86{
 87	df3p5_get_masks_shifts(mask0, mask1, mask2);
 88
 89	if (!(df_cfg.flags.socket_id_shift_quirk && df_cfg.socket_id_shift == 1))
 90		return;
 91
 92	df_cfg.socket_id_shift	= 0;
 93	df_cfg.socket_id_mask	= 1;
 94	df_cfg.die_id_shift	= 0;
 95	df_cfg.die_id_mask	= 0;
 96	df_cfg.node_id_shift	= 8;
 97	df_cfg.node_id_mask	= 0x100;
 98}
 99
100static int df4_get_fabric_id_mask_registers(void)
101{
102	u32 mask0, mask1, mask2;
103
104	/* Read D18F4x1B0 (SystemFabricIdMask0) */
105	if (df_indirect_read_broadcast(0, 4, 0x1B0, &mask0))
106		return -EINVAL;
107
108	/* Read D18F4x1B4 (SystemFabricIdMask1) */
109	if (df_indirect_read_broadcast(0, 4, 0x1B4, &mask1))
110		return -EINVAL;
111
112	/* Read D18F4x1B8 (SystemFabricIdMask2) */
113	if (df_indirect_read_broadcast(0, 4, 0x1B8, &mask2))
114		return -EINVAL;
115
116	df4_get_masks_shifts(mask0, mask1, mask2);
117	return 0;
118}
119
120static int df4_determine_df_rev(u32 reg)
121{
122	df_cfg.rev = FIELD_GET(DF_MINOR_REVISION, reg) < 5 ? DF4 : DF4p5;
123
124	/* Check for special cases or quirks based on Device/Vendor IDs.*/
125
126	/* Read D18F0x000 (DeviceVendorId0) */
127	if (df_indirect_read_broadcast(0, 0, 0, &reg))
128		return -EINVAL;
129
130	if (reg == DF_FUNC0_ID_ZEN4_SERVER)
131		df_cfg.flags.socket_id_shift_quirk = 1;
132
133	if (reg == DF_FUNC0_ID_MI300) {
134		df_cfg.flags.heterogeneous = 1;
135
136		if (get_umc_info_mi300())
137			return -EINVAL;
138	}
139
140	return df4_get_fabric_id_mask_registers();
141}
142
143static int determine_df_rev_legacy(void)
144{
145	u32 fabric_id_mask0, fabric_id_mask1, fabric_id_mask2;
146
147	/*
148	 * Check for DF3.5.
149	 *
150	 * Component ID Mask must be non-zero. Register D18F1x150 is
151	 * reserved pre-DF3.5, so value will be Read-as-Zero.
152	 */
153
154	/* Read D18F1x150 (SystemFabricIdMask0). */
155	if (df_indirect_read_broadcast(0, 1, 0x150, &fabric_id_mask0))
156		return -EINVAL;
157
158	if (FIELD_GET(DF4_COMPONENT_ID_MASK, fabric_id_mask0)) {
159		df_cfg.rev = DF3p5;
160
161		/* Read D18F1x154 (SystemFabricIdMask1) */
162		if (df_indirect_read_broadcast(0, 1, 0x154, &fabric_id_mask1))
163			return -EINVAL;
164
165		/* Read D18F1x158 (SystemFabricIdMask2) */
166		if (df_indirect_read_broadcast(0, 1, 0x158, &fabric_id_mask2))
167			return -EINVAL;
168
169		df3p5_get_masks_shifts(fabric_id_mask0, fabric_id_mask1, fabric_id_mask2);
170		return 0;
171	}
172
173	/*
174	 * Check for DF3.
175	 *
176	 * Component ID Mask must be non-zero. Field is Read-as-Zero on DF2.
177	 */
178
179	/* Read D18F1x208 (SystemFabricIdMask). */
180	if (df_indirect_read_broadcast(0, 1, 0x208, &fabric_id_mask0))
181		return -EINVAL;
182
183	if (FIELD_GET(DF3_COMPONENT_ID_MASK, fabric_id_mask0)) {
184		df_cfg.rev = DF3;
185
186		/* Read D18F1x20C (SystemFabricIdMask1) */
187		if (df_indirect_read_broadcast(0, 1, 0x20C, &fabric_id_mask1))
188			return -EINVAL;
189
190		df3_get_masks_shifts(fabric_id_mask0, fabric_id_mask1);
191		return 0;
192	}
193
194	/* Default to DF2. */
195	df_cfg.rev = DF2;
196	df2_get_masks_shifts(fabric_id_mask0);
197	return 0;
198}
199
200static int determine_df_rev(void)
201{
202	u32 reg;
203	u8 rev;
204
205	if (df_cfg.rev != UNKNOWN)
206		return 0;
207
208	/* Read D18F0x40 (FabricBlockInstanceCount). */
209	if (df_indirect_read_broadcast(0, 0, 0x40, &reg))
210		return -EINVAL;
211
212	/*
213	 * Revision fields added for DF4 and later.
214	 *
215	 * Major revision of '0' is found pre-DF4. Field is Read-as-Zero.
216	 */
217	rev = FIELD_GET(DF_MAJOR_REVISION, reg);
218	if (!rev)
219		return determine_df_rev_legacy();
220
221	if (rev == 4)
222		return df4_determine_df_rev(reg);
223
224	/* All other systems should have PRM handlers. */
225	if (!acpi_prm_handler_available(&norm_to_sys_guid)) {
226		pr_debug("PRM not available\n");
227		return -ENODEV;
228	}
229
230	df_cfg.flags.prm_only = true;
231	return 0;
232}
233
234static int get_dram_hole_base(void)
235{
236	u8 func = 0;
237
238	if (df_cfg.rev >= DF4)
239		func = 7;
240
241	if (df_indirect_read_broadcast(0, func, 0x104, &df_cfg.dram_hole_base))
242		return -EINVAL;
243
244	df_cfg.dram_hole_base &= DF_DRAM_HOLE_BASE_MASK;
245
246	return 0;
247}
248
249static void get_num_maps(void)
250{
251	switch (df_cfg.rev) {
252	case DF2:
253	case DF3:
254	case DF3p5:
255		df_cfg.num_coh_st_maps	= 2;
256		break;
257	case DF4:
258	case DF4p5:
259		df_cfg.num_coh_st_maps	= 4;
260		break;
261	default:
262		atl_debug_on_bad_df_rev();
263	}
264}
265
266static void apply_node_id_shift(void)
267{
268	if (df_cfg.rev == DF2)
269		return;
270
271	df_cfg.die_id_shift		= df_cfg.node_id_shift;
272	df_cfg.die_id_mask		<<= df_cfg.node_id_shift;
273	df_cfg.socket_id_mask		<<= df_cfg.node_id_shift;
274	df_cfg.socket_id_shift		+= df_cfg.node_id_shift;
275}
276
277static void dump_df_cfg(void)
278{
279	pr_debug("rev=0x%x",				df_cfg.rev);
280
281	pr_debug("component_id_mask=0x%x",		df_cfg.component_id_mask);
282	pr_debug("die_id_mask=0x%x",			df_cfg.die_id_mask);
283	pr_debug("node_id_mask=0x%x",			df_cfg.node_id_mask);
284	pr_debug("socket_id_mask=0x%x",			df_cfg.socket_id_mask);
285
286	pr_debug("die_id_shift=0x%x",			df_cfg.die_id_shift);
287	pr_debug("node_id_shift=0x%x",			df_cfg.node_id_shift);
288	pr_debug("socket_id_shift=0x%x",		df_cfg.socket_id_shift);
289
290	pr_debug("num_coh_st_maps=%u",			df_cfg.num_coh_st_maps);
291
292	pr_debug("dram_hole_base=0x%x",			df_cfg.dram_hole_base);
293	pr_debug("flags.legacy_ficaa=%u",		df_cfg.flags.legacy_ficaa);
294	pr_debug("flags.socket_id_shift_quirk=%u",	df_cfg.flags.socket_id_shift_quirk);
295}
296
297int get_df_system_info(void)
298{
299	int ret;
300
301	ret = determine_df_rev();
302	if (ret) {
303		pr_warn("Failed to determine DF Revision");
304		df_cfg.rev = UNKNOWN;
305		return ret;
306	}
307
308	if (df_cfg.flags.prm_only)
309		return 0;
310
311	apply_node_id_shift();
312
313	get_num_maps();
314
315	if (get_dram_hole_base())
316		pr_warn("Failed to read DRAM hole base");
317
318	dump_df_cfg();
319
320	return 0;
321}