pwm-tiecap.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * ECAP PWM driver
  4 *
  5 * Copyright (C) 2012 Texas Instruments, Inc. - https://www.ti.com/
  6 *
  7 * Hardware properties:
  8 * - On disable the PWM pin becomes an input, so the behaviour depends on
  9 *   external wiring.
 10 */
 11
 12#include <linux/module.h>
 13#include <linux/platform_device.h>
 14#include <linux/io.h>
 15#include <linux/err.h>
 16#include <linux/clk.h>
 17#include <linux/pm_runtime.h>
 18#include <linux/pwm.h>
 19#include <linux/of.h>
 20
 21/* ECAP registers and bits definitions */
 22#define CAP1			0x08
 23#define CAP2			0x0C
 24#define CAP3			0x10
 25#define CAP4			0x14
 26#define ECCTL2			0x2A
 27#define ECCTL2_APWM_POL_LOW	BIT(10)
 28#define ECCTL2_APWM_MODE	BIT(9)
 29#define ECCTL2_SYNC_SEL_DISA	(BIT(7) | BIT(6))
 30#define ECCTL2_TSCTR_FREERUN	BIT(4)
 31
 32struct ecap_context {
 33	u32 cap3;
 34	u32 cap4;
 35	u16 ecctl2;
 36};
 37
 38struct ecap_pwm_chip {
 39	unsigned int clk_rate;
 40	void __iomem *mmio_base;
 41	struct ecap_context ctx;
 42};
 43
 44static inline struct ecap_pwm_chip *to_ecap_pwm_chip(struct pwm_chip *chip)
 45{
 46	return pwmchip_get_drvdata(chip);
 47}
 48
 49/*
 50 * period_ns = 10^9 * period_cycles / PWM_CLK_RATE
 51 * duty_ns   = 10^9 * duty_cycles / PWM_CLK_RATE
 52 */
 53static int ecap_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 54			   int duty_ns, int period_ns, int enabled)
 55{
 56	struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
 57	u32 period_cycles, duty_cycles;
 58	unsigned long long c;
 59	u16 value;
 60
 61	c = pc->clk_rate;
 62	c = c * period_ns;
 63	do_div(c, NSEC_PER_SEC);
 64	period_cycles = (u32)c;
 65
 66	if (period_cycles < 1) {
 67		period_cycles = 1;
 68		duty_cycles = 1;
 69	} else {
 70		c = pc->clk_rate;
 71		c = c * duty_ns;
 72		do_div(c, NSEC_PER_SEC);
 73		duty_cycles = (u32)c;
 74	}
 75
 76	pm_runtime_get_sync(pwmchip_parent(chip));
 77
 78	value = readw(pc->mmio_base + ECCTL2);
 79
 80	/* Configure APWM mode & disable sync option */
 81	value |= ECCTL2_APWM_MODE | ECCTL2_SYNC_SEL_DISA;
 82
 83	writew(value, pc->mmio_base + ECCTL2);
 84
 85	if (!enabled) {
 86		/* Update active registers if not running */
 87		writel(duty_cycles, pc->mmio_base + CAP2);
 88		writel(period_cycles, pc->mmio_base + CAP1);
 89	} else {
 90		/*
 91		 * Update shadow registers to configure period and
 92		 * compare values. This helps current PWM period to
 93		 * complete on reconfiguring
 94		 */
 95		writel(duty_cycles, pc->mmio_base + CAP4);
 96		writel(period_cycles, pc->mmio_base + CAP3);
 97	}
 98
 99	if (!enabled) {
100		value = readw(pc->mmio_base + ECCTL2);
101		/* Disable APWM mode to put APWM output Low */
102		value &= ~ECCTL2_APWM_MODE;
103		writew(value, pc->mmio_base + ECCTL2);
104	}
105
106	pm_runtime_put_sync(pwmchip_parent(chip));
107
108	return 0;
109}
110
111static int ecap_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
112				 enum pwm_polarity polarity)
113{
114	struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
115	u16 value;
116
117	pm_runtime_get_sync(pwmchip_parent(chip));
118
119	value = readw(pc->mmio_base + ECCTL2);
120
121	if (polarity == PWM_POLARITY_INVERSED)
122		/* Duty cycle defines LOW period of PWM */
123		value |= ECCTL2_APWM_POL_LOW;
124	else
125		/* Duty cycle defines HIGH period of PWM */
126		value &= ~ECCTL2_APWM_POL_LOW;
127
128	writew(value, pc->mmio_base + ECCTL2);
129
130	pm_runtime_put_sync(pwmchip_parent(chip));
131
132	return 0;
133}
134
135static int ecap_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
136{
137	struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
138	u16 value;
139
140	/* Leave clock enabled on enabling PWM */
141	pm_runtime_get_sync(pwmchip_parent(chip));
142
143	/*
144	 * Enable 'Free run Time stamp counter mode' to start counter
145	 * and  'APWM mode' to enable APWM output
146	 */
147	value = readw(pc->mmio_base + ECCTL2);
148	value |= ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE;
149	writew(value, pc->mmio_base + ECCTL2);
150
151	return 0;
152}
153
154static void ecap_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
155{
156	struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
157	u16 value;
158
159	/*
160	 * Disable 'Free run Time stamp counter mode' to stop counter
161	 * and 'APWM mode' to put APWM output to low
162	 */
163	value = readw(pc->mmio_base + ECCTL2);
164	value &= ~(ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE);
165	writew(value, pc->mmio_base + ECCTL2);
166
167	/* Disable clock on PWM disable */
168	pm_runtime_put_sync(pwmchip_parent(chip));
169}
170
171static int ecap_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
172			  const struct pwm_state *state)
173{
174	int err;
175	int enabled = pwm->state.enabled;
176
177	if (state->polarity != pwm->state.polarity) {
178
179		if (enabled) {
180			ecap_pwm_disable(chip, pwm);
181			enabled = false;
182		}
183
184		err = ecap_pwm_set_polarity(chip, pwm, state->polarity);
185		if (err)
186			return err;
187	}
188
189	if (!state->enabled) {
190		if (enabled)
191			ecap_pwm_disable(chip, pwm);
192		return 0;
193	}
194
195	if (state->period > NSEC_PER_SEC)
196		return -ERANGE;
197
198	err = ecap_pwm_config(chip, pwm, state->duty_cycle,
199			      state->period, enabled);
200	if (err)
201		return err;
202
203	if (!enabled)
204		return ecap_pwm_enable(chip, pwm);
205
206	return 0;
207}
208
209static const struct pwm_ops ecap_pwm_ops = {
210	.apply = ecap_pwm_apply,
211};
212
213static const struct of_device_id ecap_of_match[] = {
214	{ .compatible	= "ti,am3352-ecap" },
215	{ .compatible	= "ti,am33xx-ecap" },
216	{},
217};
218MODULE_DEVICE_TABLE(of, ecap_of_match);
219
220static int ecap_pwm_probe(struct platform_device *pdev)
221{
222	struct device_node *np = pdev->dev.of_node;
223	struct ecap_pwm_chip *pc;
224	struct pwm_chip *chip;
225	struct clk *clk;
226	int ret;
227
228	chip = devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*pc));
229	if (IS_ERR(chip))
230		return PTR_ERR(chip);
231	pc = to_ecap_pwm_chip(chip);
232
233	clk = devm_clk_get(&pdev->dev, "fck");
234	if (IS_ERR(clk)) {
235		if (of_device_is_compatible(np, "ti,am33xx-ecap")) {
236			dev_warn(&pdev->dev, "Binding is obsolete.\n");
237			clk = devm_clk_get(pdev->dev.parent, "fck");
238		}
239	}
240
241	if (IS_ERR(clk)) {
242		dev_err(&pdev->dev, "failed to get clock\n");
243		return PTR_ERR(clk);
244	}
245
246	pc->clk_rate = clk_get_rate(clk);
247	if (!pc->clk_rate) {
248		dev_err(&pdev->dev, "failed to get clock rate\n");
249		return -EINVAL;
250	}
251
252	chip->ops = &ecap_pwm_ops;
253
254	pc->mmio_base = devm_platform_ioremap_resource(pdev, 0);
255	if (IS_ERR(pc->mmio_base))
256		return PTR_ERR(pc->mmio_base);
257
258	ret = devm_pwmchip_add(&pdev->dev, chip);
259	if (ret < 0) {
260		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
261		return ret;
262	}
263
264	platform_set_drvdata(pdev, chip);
265	pm_runtime_enable(&pdev->dev);
266
267	return 0;
268}
269
270static void ecap_pwm_remove(struct platform_device *pdev)
271{
272	pm_runtime_disable(&pdev->dev);
273}
274
275static void ecap_pwm_save_context(struct pwm_chip *chip)
276{
277	struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
278
279	pm_runtime_get_sync(pwmchip_parent(chip));
280	pc->ctx.ecctl2 = readw(pc->mmio_base + ECCTL2);
281	pc->ctx.cap4 = readl(pc->mmio_base + CAP4);
282	pc->ctx.cap3 = readl(pc->mmio_base + CAP3);
283	pm_runtime_put_sync(pwmchip_parent(chip));
284}
285
286static void ecap_pwm_restore_context(struct pwm_chip *chip)
287{
288	struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
289
290	writel(pc->ctx.cap3, pc->mmio_base + CAP3);
291	writel(pc->ctx.cap4, pc->mmio_base + CAP4);
292	writew(pc->ctx.ecctl2, pc->mmio_base + ECCTL2);
293}
294
295static int ecap_pwm_suspend(struct device *dev)
296{
297	struct pwm_chip *chip = dev_get_drvdata(dev);
298	struct pwm_device *pwm = chip->pwms;
299
300	ecap_pwm_save_context(chip);
301
302	/* Disable explicitly if PWM is running */
303	if (pwm_is_enabled(pwm))
304		pm_runtime_put_sync(dev);
305
306	return 0;
307}
308
309static int ecap_pwm_resume(struct device *dev)
310{
311	struct pwm_chip *chip = dev_get_drvdata(dev);
312	struct pwm_device *pwm = chip->pwms;
313
314	/* Enable explicitly if PWM was running */
315	if (pwm_is_enabled(pwm))
316		pm_runtime_get_sync(dev);
317
318	ecap_pwm_restore_context(chip);
319	return 0;
320}
321
322static DEFINE_SIMPLE_DEV_PM_OPS(ecap_pwm_pm_ops, ecap_pwm_suspend, ecap_pwm_resume);
323
324static struct platform_driver ecap_pwm_driver = {
325	.driver = {
326		.name = "ecap",
327		.of_match_table = ecap_of_match,
328		.pm = pm_ptr(&ecap_pwm_pm_ops),
329	},
330	.probe = ecap_pwm_probe,
331	.remove = ecap_pwm_remove,
332};
333module_platform_driver(ecap_pwm_driver);
334
335MODULE_DESCRIPTION("ECAP PWM driver");
336MODULE_AUTHOR("Texas Instruments");
337MODULE_LICENSE("GPL");