pwm-sifive.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright (C) 2017-2018 SiFive
  4 * For SiFive's PWM IP block documentation please refer Chapter 14 of
  5 * Reference Manual : https://static.dev.sifive.com/FU540-C000-v1.0.pdf
  6 *
  7 * PWM output inversion: According to the SiFive Reference manual
  8 * the output of each comparator is high whenever the value of pwms is
  9 * greater than or equal to the corresponding pwmcmpX[Reference Manual].
 10 *
 11 * Figure 29 in the same manual shows that the pwmcmpXcenter bit is
 12 * hard-tied to 0 (XNOR), which effectively inverts the comparison so that
 13 * the output goes HIGH when  `pwms < pwmcmpX`.
 14 *
 15 * In other words, each pwmcmp register actually defines the **inactive**
 16 * (low) period of the pulse, not the active time exactly opposite to what
 17 * the documentation text implies.
 18 *
 19 * To compensate, this driver always **inverts** the duty value when reading
 20 * or writing pwmcmp registers , so that users interact with a conventional
 21 * **active-high** PWM interface.
 22 *
 23 *
 24 * Limitations:
 25 * - When changing both duty cycle and period, we cannot prevent in
 26 *   software that the output might produce a period with mixed
 27 *   settings (new period length and old duty cycle).
 28 * - The hardware cannot generate a 0% duty cycle.
 29 * - The hardware generates only inverted output.
 30 */
 31#include <linux/clk.h>
 32#include <linux/io.h>
 33#include <linux/mod_devicetable.h>
 34#include <linux/module.h>
 35#include <linux/platform_device.h>
 36#include <linux/pwm.h>
 37#include <linux/slab.h>
 38#include <linux/bitfield.h>
 39
 40/* Register offsets */
 41#define PWM_SIFIVE_PWMCFG		0x0
 42#define PWM_SIFIVE_PWMCOUNT		0x8
 43#define PWM_SIFIVE_PWMS			0x10
 44#define PWM_SIFIVE_PWMCMP(i)		(0x20 + 4 * (i))
 45
 46/* PWMCFG fields */
 47#define PWM_SIFIVE_PWMCFG_SCALE		GENMASK(3, 0)
 48#define PWM_SIFIVE_PWMCFG_STICKY	BIT(8)
 49#define PWM_SIFIVE_PWMCFG_ZERO_CMP	BIT(9)
 50#define PWM_SIFIVE_PWMCFG_DEGLITCH	BIT(10)
 51#define PWM_SIFIVE_PWMCFG_EN_ALWAYS	BIT(12)
 52#define PWM_SIFIVE_PWMCFG_EN_ONCE	BIT(13)
 53#define PWM_SIFIVE_PWMCFG_CENTER	BIT(16)
 54#define PWM_SIFIVE_PWMCFG_GANG		BIT(24)
 55#define PWM_SIFIVE_PWMCFG_IP		BIT(28)
 56
 57#define PWM_SIFIVE_CMPWIDTH		16
 58#define PWM_SIFIVE_DEFAULT_PERIOD	10000000
 59
 60struct pwm_sifive_ddata {
 61	struct device *parent;
 62	struct mutex lock; /* lock to protect user_count and approx_period */
 63	struct notifier_block notifier;
 64	struct clk *clk;
 65	void __iomem *regs;
 66	unsigned int real_period;
 67	unsigned int approx_period;
 68	int user_count;
 69};
 70
 71static inline
 72struct pwm_sifive_ddata *pwm_sifive_chip_to_ddata(struct pwm_chip *chip)
 73{
 74	return pwmchip_get_drvdata(chip);
 75}
 76
 77static int pwm_sifive_request(struct pwm_chip *chip, struct pwm_device *pwm)
 78{
 79	struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
 80
 81	mutex_lock(&ddata->lock);
 82	ddata->user_count++;
 83	mutex_unlock(&ddata->lock);
 84
 85	return 0;
 86}
 87
 88static void pwm_sifive_free(struct pwm_chip *chip, struct pwm_device *pwm)
 89{
 90	struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
 91
 92	mutex_lock(&ddata->lock);
 93	ddata->user_count--;
 94	mutex_unlock(&ddata->lock);
 95}
 96
 97/* Called holding ddata->lock */
 98static void pwm_sifive_update_clock(struct pwm_sifive_ddata *ddata,
 99				    unsigned long rate)
100{
101	unsigned long long num;
102	unsigned long scale_pow;
103	int scale;
104	u32 val;
105	/*
106	 * The PWM unit is used with pwmzerocmp=0, so the only way to modify the
107	 * period length is using pwmscale which provides the number of bits the
108	 * counter is shifted before being feed to the comparators. A period
109	 * lasts (1 << (PWM_SIFIVE_CMPWIDTH + pwmscale)) clock ticks.
110	 * (1 << (PWM_SIFIVE_CMPWIDTH + scale)) * 10^9/rate = period
111	 */
112	scale_pow = div64_ul(ddata->approx_period * (u64)rate, NSEC_PER_SEC);
113	scale = clamp(ilog2(scale_pow) - PWM_SIFIVE_CMPWIDTH, 0, 0xf);
114
115	val = PWM_SIFIVE_PWMCFG_EN_ALWAYS |
116	      FIELD_PREP(PWM_SIFIVE_PWMCFG_SCALE, scale);
117	writel(val, ddata->regs + PWM_SIFIVE_PWMCFG);
118
119	/* As scale <= 15 the shift operation cannot overflow. */
120	num = (unsigned long long)NSEC_PER_SEC << (PWM_SIFIVE_CMPWIDTH + scale);
121	ddata->real_period = DIV_ROUND_UP_ULL(num, rate);
122	dev_dbg(ddata->parent,
123		"New real_period = %u ns\n", ddata->real_period);
124}
125
126static int pwm_sifive_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
127				struct pwm_state *state)
128{
129	struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
130	u32 duty, val, inactive;
131
132	inactive = readl(ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm));
133	/*
134	 * PWM hardware uses 'inactive' counts in pwmcmp, so invert to get actual duty.
135	 * Here, 'inactive' is the low time and we compute duty as max_count - inactive.
136	 */
137	duty = (1U << PWM_SIFIVE_CMPWIDTH) - 1 - inactive;
138
139	state->enabled = duty > 0;
140
141	val = readl(ddata->regs + PWM_SIFIVE_PWMCFG);
142	if (!(val & PWM_SIFIVE_PWMCFG_EN_ALWAYS))
143		state->enabled = false;
144
145	state->period = ddata->real_period;
146	state->duty_cycle = DIV_ROUND_UP_ULL((u64)duty * ddata->real_period,
147					     (1U << PWM_SIFIVE_CMPWIDTH));
148	state->polarity = PWM_POLARITY_NORMAL;
149
150	return 0;
151}
152
153static int pwm_sifive_apply(struct pwm_chip *chip, struct pwm_device *pwm,
154			    const struct pwm_state *state)
155{
156	struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
157	struct pwm_state cur_state;
158	unsigned int duty_cycle;
159	unsigned long long num;
160	bool enabled;
161	int ret = 0;
162	u64 frac;
163	u32 inactive;
164
165	if (state->polarity != PWM_POLARITY_NORMAL)
166		return -EINVAL;
167
168	cur_state = pwm->state;
169	enabled = cur_state.enabled;
170
171	duty_cycle = state->duty_cycle;
172	if (!state->enabled)
173		duty_cycle = 0;
174
175	/*
176	 * The problem of output producing mixed setting as mentioned at top,
177	 * occurs here. To minimize the window for this problem, we are
178	 * calculating the register values first and then writing them
179	 * consecutively
180	 */
181	num = (u64)duty_cycle * (1U << PWM_SIFIVE_CMPWIDTH);
182	frac = num;
183	do_div(frac, state->period);
184	/* The hardware cannot generate a 0% duty cycle */
185	frac = min(frac, (u64)(1U << PWM_SIFIVE_CMPWIDTH) - 1);
186	/* pwmcmp register must be loaded with the inactive(invert the duty) */
187	inactive = (1U << PWM_SIFIVE_CMPWIDTH) - 1 - frac;
188
189	mutex_lock(&ddata->lock);
190	if (state->period != ddata->approx_period) {
191		/*
192		 * Don't let a 2nd user change the period underneath the 1st user.
193		 * However if ddate->approx_period == 0 this is the first time we set
194		 * any period, so let whoever gets here first set the period so other
195		 * users who agree on the period won't fail.
196		 */
197		if (ddata->user_count != 1 && ddata->approx_period) {
198			mutex_unlock(&ddata->lock);
199			return -EBUSY;
200		}
201		ddata->approx_period = state->period;
202		pwm_sifive_update_clock(ddata, clk_get_rate(ddata->clk));
203	}
204	mutex_unlock(&ddata->lock);
205
206	/*
207	 * If the PWM is enabled the clk is already on. So only enable it
208	 * conditionally to have it on exactly once afterwards independent of
209	 * the PWM state.
210	 */
211	if (!enabled) {
212		ret = clk_enable(ddata->clk);
213		if (ret) {
214			dev_err(pwmchip_parent(chip), "Enable clk failed\n");
215			return ret;
216		}
217	}
218
219	writel(inactive, ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm));
220
221	if (!state->enabled)
222		clk_disable(ddata->clk);
223
224	return 0;
225}
226
227static const struct pwm_ops pwm_sifive_ops = {
228	.request = pwm_sifive_request,
229	.free = pwm_sifive_free,
230	.get_state = pwm_sifive_get_state,
231	.apply = pwm_sifive_apply,
232};
233
234static int pwm_sifive_clock_notifier(struct notifier_block *nb,
235				     unsigned long event, void *data)
236{
237	struct clk_notifier_data *ndata = data;
238	struct pwm_sifive_ddata *ddata =
239		container_of(nb, struct pwm_sifive_ddata, notifier);
240
241	if (event == POST_RATE_CHANGE) {
242		mutex_lock(&ddata->lock);
243		pwm_sifive_update_clock(ddata, ndata->new_rate);
244		mutex_unlock(&ddata->lock);
245	}
246
247	return NOTIFY_OK;
248}
249
250static int pwm_sifive_probe(struct platform_device *pdev)
251{
252	struct device *dev = &pdev->dev;
253	struct pwm_sifive_ddata *ddata;
254	struct pwm_chip *chip;
255	int ret;
256	u32 val;
257	unsigned int enabled_pwms = 0, enabled_clks = 1;
258
259	chip = devm_pwmchip_alloc(dev, 4, sizeof(*ddata));
260	if (IS_ERR(chip))
261		return PTR_ERR(chip);
262
263	ddata = pwm_sifive_chip_to_ddata(chip);
264	ddata->parent = dev;
265	mutex_init(&ddata->lock);
266	chip->ops = &pwm_sifive_ops;
267
268	ddata->regs = devm_platform_ioremap_resource(pdev, 0);
269	if (IS_ERR(ddata->regs))
270		return PTR_ERR(ddata->regs);
271
272	ddata->clk = devm_clk_get_prepared(dev, NULL);
273	if (IS_ERR(ddata->clk))
274		return dev_err_probe(dev, PTR_ERR(ddata->clk),
275				     "Unable to find controller clock\n");
276
277	ret = clk_enable(ddata->clk);
278	if (ret) {
279		dev_err(dev, "failed to enable clock for pwm: %d\n", ret);
280		return ret;
281	}
282
283	val = readl(ddata->regs + PWM_SIFIVE_PWMCFG);
284	if (val & PWM_SIFIVE_PWMCFG_EN_ALWAYS) {
285		unsigned int i;
286
287		for (i = 0; i < chip->npwm; ++i) {
288			val = readl(ddata->regs + PWM_SIFIVE_PWMCMP(i));
289			if (val > 0)
290				++enabled_pwms;
291		}
292	}
293
294	/* The clk should be on once for each running PWM. */
295	if (enabled_pwms) {
296		while (enabled_clks < enabled_pwms) {
297			/* This is not expected to fail as the clk is already on */
298			ret = clk_enable(ddata->clk);
299			if (unlikely(ret)) {
300				dev_err_probe(dev, ret, "Failed to enable clk\n");
301				goto disable_clk;
302			}
303			++enabled_clks;
304		}
305	} else {
306		clk_disable(ddata->clk);
307		enabled_clks = 0;
308	}
309
310	/* Watch for changes to underlying clock frequency */
311	ddata->notifier.notifier_call = pwm_sifive_clock_notifier;
312	ret = clk_notifier_register(ddata->clk, &ddata->notifier);
313	if (ret) {
314		dev_err(dev, "failed to register clock notifier: %d\n", ret);
315		goto disable_clk;
316	}
317
318	ret = pwmchip_add(chip);
319	if (ret < 0) {
320		dev_err(dev, "cannot register PWM: %d\n", ret);
321		goto unregister_clk;
322	}
323
324	platform_set_drvdata(pdev, chip);
325	dev_dbg(dev, "SiFive PWM chip registered %d PWMs\n", chip->npwm);
326
327	return 0;
328
329unregister_clk:
330	clk_notifier_unregister(ddata->clk, &ddata->notifier);
331disable_clk:
332	while (enabled_clks) {
333		clk_disable(ddata->clk);
334		--enabled_clks;
335	}
336
337	return ret;
338}
339
340static void pwm_sifive_remove(struct platform_device *dev)
341{
342	struct pwm_chip *chip = platform_get_drvdata(dev);
343	struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
344	struct pwm_device *pwm;
345	int ch;
346
347	pwmchip_remove(chip);
348	clk_notifier_unregister(ddata->clk, &ddata->notifier);
349
350	for (ch = 0; ch < chip->npwm; ch++) {
351		pwm = &chip->pwms[ch];
352		if (pwm->state.enabled)
353			clk_disable(ddata->clk);
354	}
355}
356
357static const struct of_device_id pwm_sifive_of_match[] = {
358	{ .compatible = "sifive,pwm0" },
359	{},
360};
361MODULE_DEVICE_TABLE(of, pwm_sifive_of_match);
362
363static struct platform_driver pwm_sifive_driver = {
364	.probe = pwm_sifive_probe,
365	.remove = pwm_sifive_remove,
366	.driver = {
367		.name = "pwm-sifive",
368		.of_match_table = pwm_sifive_of_match,
369	},
370};
371module_platform_driver(pwm_sifive_driver);
372
373MODULE_DESCRIPTION("SiFive PWM driver");
374MODULE_LICENSE("GPL v2");