pwm-rzg2l-gpt.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Renesas RZ/G2L General PWM Timer (GPT) driver
  4 *
  5 * Copyright (C) 2025 Renesas Electronics Corporation
  6 *
  7 * Hardware manual for this IP can be found here
  8 * https://www.renesas.com/eu/en/document/mah/rzg2l-group-rzg2lc-group-users-manual-hardware-0?language=en
  9 *
 10 * Limitations:
 11 * - Counter must be stopped before modifying Mode and Prescaler.
 12 * - When PWM is disabled, the output is driven to inactive.
 13 * - While the hardware supports both polarities, the driver (for now)
 14 *   only handles normal polarity.
 15 * - General PWM Timer (GPT) has 8 HW channels for PWM operations and
 16 *   each HW channel have 2 IOs.
 17 * - Each IO is modelled as an independent PWM channel.
 18 * - When both channels are used, disabling the channel on one stops the
 19 *   other.
 20 * - When both channels are used, the period of both IOs in the HW channel
 21 *   must be same (for now).
 22 */
 23
 24#include <linux/bitfield.h>
 25#include <linux/clk.h>
 26#include <linux/io.h>
 27#include <linux/limits.h>
 28#include <linux/module.h>
 29#include <linux/of.h>
 30#include <linux/platform_device.h>
 31#include <linux/pwm.h>
 32#include <linux/reset.h>
 33#include <linux/time.h>
 34#include <linux/units.h>
 35
 36#define RZG2L_GET_CH(hwpwm)	((hwpwm) / 2)
 37#define RZG2L_GET_CH_OFFS(ch)	(0x100 * (ch))
 38
 39#define RZG2L_GTCR(ch)		(0x2c + RZG2L_GET_CH_OFFS(ch))
 40#define RZG2L_GTUDDTYC(ch)	(0x30 + RZG2L_GET_CH_OFFS(ch))
 41#define RZG2L_GTIOR(ch)		(0x34 + RZG2L_GET_CH_OFFS(ch))
 42#define RZG2L_GTBER(ch)		(0x40 + RZG2L_GET_CH_OFFS(ch))
 43#define RZG2L_GTCNT(ch)		(0x48 + RZG2L_GET_CH_OFFS(ch))
 44#define RZG2L_GTCCR(ch, sub_ch)	(0x4c + RZG2L_GET_CH_OFFS(ch) + 4 * (sub_ch))
 45#define RZG2L_GTPR(ch)		(0x64 + RZG2L_GET_CH_OFFS(ch))
 46
 47#define RZG2L_GTCR_CST		BIT(0)
 48#define RZG2L_GTCR_MD		GENMASK(18, 16)
 49#define RZG2L_GTCR_TPCS		GENMASK(26, 24)
 50
 51#define RZG2L_GTCR_MD_SAW_WAVE_PWM_MODE	FIELD_PREP(RZG2L_GTCR_MD, 0)
 52
 53#define RZG2L_GTUDDTYC_UP	BIT(0)
 54#define RZG2L_GTUDDTYC_UDF	BIT(1)
 55#define RZG2L_GTUDDTYC_UP_COUNTING	(RZG2L_GTUDDTYC_UP | RZG2L_GTUDDTYC_UDF)
 56
 57#define RZG2L_GTIOR_GTIOA	GENMASK(4, 0)
 58#define RZG2L_GTIOR_GTIOB	GENMASK(20, 16)
 59#define RZG2L_GTIOR_GTIOx(sub_ch)	((sub_ch) ? RZG2L_GTIOR_GTIOB : RZG2L_GTIOR_GTIOA)
 60#define RZG2L_GTIOR_OAE		BIT(8)
 61#define RZG2L_GTIOR_OBE		BIT(24)
 62#define RZG2L_GTIOR_OxE(sub_ch)		((sub_ch) ? RZG2L_GTIOR_OBE : RZG2L_GTIOR_OAE)
 63
 64#define RZG2L_INIT_OUT_HI_OUT_HI_END_TOGGLE	0x1b
 65#define RZG2L_GTIOR_GTIOA_OUT_HI_END_TOGGLE_CMP_MATCH \
 66	(RZG2L_INIT_OUT_HI_OUT_HI_END_TOGGLE | RZG2L_GTIOR_OAE)
 67#define RZG2L_GTIOR_GTIOB_OUT_HI_END_TOGGLE_CMP_MATCH \
 68	(FIELD_PREP(RZG2L_GTIOR_GTIOB, RZG2L_INIT_OUT_HI_OUT_HI_END_TOGGLE) | RZG2L_GTIOR_OBE)
 69
 70#define RZG2L_GTIOR_GTIOx_OUT_HI_END_TOGGLE_CMP_MATCH(sub_ch) \
 71	((sub_ch) ? RZG2L_GTIOR_GTIOB_OUT_HI_END_TOGGLE_CMP_MATCH : \
 72	 RZG2L_GTIOR_GTIOA_OUT_HI_END_TOGGLE_CMP_MATCH)
 73
 74#define RZG2L_MAX_HW_CHANNELS	8
 75#define RZG2L_CHANNELS_PER_IO	2
 76#define RZG2L_MAX_PWM_CHANNELS	(RZG2L_MAX_HW_CHANNELS * RZG2L_CHANNELS_PER_IO)
 77#define RZG2L_MAX_SCALE_FACTOR	1024
 78#define RZG2L_MAX_TICKS		((u64)U32_MAX * RZG2L_MAX_SCALE_FACTOR)
 79
 80struct rzg2l_gpt_chip {
 81	void __iomem *mmio;
 82	struct mutex lock; /* lock to protect shared channel resources */
 83	unsigned long rate_khz;
 84	u32 period_ticks[RZG2L_MAX_HW_CHANNELS];
 85	u32 channel_request_count[RZG2L_MAX_HW_CHANNELS];
 86	u32 channel_enable_count[RZG2L_MAX_HW_CHANNELS];
 87};
 88
 89static inline struct rzg2l_gpt_chip *to_rzg2l_gpt_chip(struct pwm_chip *chip)
 90{
 91	return pwmchip_get_drvdata(chip);
 92}
 93
 94static inline unsigned int rzg2l_gpt_subchannel(unsigned int hwpwm)
 95{
 96	return hwpwm & 0x1;
 97}
 98
 99static inline unsigned int rzg2l_gpt_sibling(unsigned int hwpwm)
100{
101	return hwpwm ^ 0x1;
102}
103
104static void rzg2l_gpt_write(struct rzg2l_gpt_chip *rzg2l_gpt, u32 reg, u32 data)
105{
106	writel(data, rzg2l_gpt->mmio + reg);
107}
108
109static u32 rzg2l_gpt_read(struct rzg2l_gpt_chip *rzg2l_gpt, u32 reg)
110{
111	return readl(rzg2l_gpt->mmio + reg);
112}
113
114static void rzg2l_gpt_modify(struct rzg2l_gpt_chip *rzg2l_gpt, u32 reg, u32 clr,
115			     u32 set)
116{
117	rzg2l_gpt_write(rzg2l_gpt, reg,
118			(rzg2l_gpt_read(rzg2l_gpt, reg) & ~clr) | set);
119}
120
121static u8 rzg2l_gpt_calculate_prescale(struct rzg2l_gpt_chip *rzg2l_gpt,
122				       u64 period_ticks)
123{
124	u32 prescaled_period_ticks;
125	u8 prescale;
126
127	prescaled_period_ticks = period_ticks >> 32;
128	if (prescaled_period_ticks >= 256)
129		prescale = 5;
130	else
131		prescale = (fls(prescaled_period_ticks) + 1) / 2;
132
133	return prescale;
134}
135
136static int rzg2l_gpt_request(struct pwm_chip *chip, struct pwm_device *pwm)
137{
138	struct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip);
139	u32 ch = RZG2L_GET_CH(pwm->hwpwm);
140
141	guard(mutex)(&rzg2l_gpt->lock);
142	rzg2l_gpt->channel_request_count[ch]++;
143
144	return 0;
145}
146
147static void rzg2l_gpt_free(struct pwm_chip *chip, struct pwm_device *pwm)
148{
149	struct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip);
150	u32 ch = RZG2L_GET_CH(pwm->hwpwm);
151
152	guard(mutex)(&rzg2l_gpt->lock);
153	rzg2l_gpt->channel_request_count[ch]--;
154}
155
156static bool rzg2l_gpt_is_ch_enabled(struct rzg2l_gpt_chip *rzg2l_gpt, u8 hwpwm)
157{
158	u8 ch = RZG2L_GET_CH(hwpwm);
159	u32 val;
160
161	val = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCR(ch));
162	if (!(val & RZG2L_GTCR_CST))
163		return false;
164
165	val = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTIOR(ch));
166
167	return val & RZG2L_GTIOR_OxE(rzg2l_gpt_subchannel(hwpwm));
168}
169
170/* Caller holds the lock while calling rzg2l_gpt_enable() */
171static void rzg2l_gpt_enable(struct rzg2l_gpt_chip *rzg2l_gpt,
172			     struct pwm_device *pwm)
173{
174	u8 sub_ch = rzg2l_gpt_subchannel(pwm->hwpwm);
175	u32 val = RZG2L_GTIOR_GTIOx(sub_ch) | RZG2L_GTIOR_OxE(sub_ch);
176	u8 ch = RZG2L_GET_CH(pwm->hwpwm);
177
178	/* Enable pin output */
179	rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTIOR(ch), val,
180			 RZG2L_GTIOR_GTIOx_OUT_HI_END_TOGGLE_CMP_MATCH(sub_ch));
181
182	if (!rzg2l_gpt->channel_enable_count[ch])
183		rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), 0, RZG2L_GTCR_CST);
184
185	rzg2l_gpt->channel_enable_count[ch]++;
186}
187
188/* Caller holds the lock while calling rzg2l_gpt_disable() */
189static void rzg2l_gpt_disable(struct rzg2l_gpt_chip *rzg2l_gpt,
190			      struct pwm_device *pwm)
191{
192	u8 sub_ch = rzg2l_gpt_subchannel(pwm->hwpwm);
193	u8 ch = RZG2L_GET_CH(pwm->hwpwm);
194
195	/* Stop count, Output low on GTIOCx pin when counting stops */
196	rzg2l_gpt->channel_enable_count[ch]--;
197
198	if (!rzg2l_gpt->channel_enable_count[ch])
199		rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), RZG2L_GTCR_CST, 0);
200
201	/* Disable pin output */
202	rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTIOR(ch), RZG2L_GTIOR_OxE(sub_ch), 0);
203}
204
205static u64 rzg2l_gpt_calculate_period_or_duty(struct rzg2l_gpt_chip *rzg2l_gpt,
206					      u32 val, u8 prescale)
207{
208	u64 tmp;
209
210	/*
211	 * The calculation doesn't overflow an u64 because prescale ≤ 5 and so
212	 * tmp = val << (2 * prescale) * USEC_PER_SEC
213	 *     < 2^32 * 2^10 * 10^6
214	 *     < 2^32 * 2^10 * 2^20
215	 *     = 2^62
216	 */
217	tmp = (u64)val << (2 * prescale);
218	tmp *= USEC_PER_SEC;
219
220	return DIV64_U64_ROUND_UP(tmp, rzg2l_gpt->rate_khz);
221}
222
223static int rzg2l_gpt_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
224			       struct pwm_state *state)
225{
226	struct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip);
227
228	state->enabled = rzg2l_gpt_is_ch_enabled(rzg2l_gpt, pwm->hwpwm);
229	if (state->enabled) {
230		u32 sub_ch = rzg2l_gpt_subchannel(pwm->hwpwm);
231		u32 ch = RZG2L_GET_CH(pwm->hwpwm);
232		u8 prescale;
233		u32 val;
234
235		val = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCR(ch));
236		prescale = FIELD_GET(RZG2L_GTCR_TPCS, val);
237
238		val = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTPR(ch));
239		state->period = rzg2l_gpt_calculate_period_or_duty(rzg2l_gpt, val, prescale);
240
241		val = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCCR(ch, sub_ch));
242		state->duty_cycle = rzg2l_gpt_calculate_period_or_duty(rzg2l_gpt, val, prescale);
243		if (state->duty_cycle > state->period)
244			state->duty_cycle = state->period;
245	}
246
247	state->polarity = PWM_POLARITY_NORMAL;
248
249	return 0;
250}
251
252static u32 rzg2l_gpt_calculate_pv_or_dc(u64 period_or_duty_cycle, u8 prescale)
253{
254	return min_t(u64, DIV_ROUND_DOWN_ULL(period_or_duty_cycle, 1 << (2 * prescale)),
255		     U32_MAX);
256}
257
258/* Caller holds the lock while calling rzg2l_gpt_config() */
259static int rzg2l_gpt_config(struct pwm_chip *chip, struct pwm_device *pwm,
260			    const struct pwm_state *state)
261{
262	struct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip);
263	u8 sub_ch = rzg2l_gpt_subchannel(pwm->hwpwm);
264	u8 ch = RZG2L_GET_CH(pwm->hwpwm);
265	u64 period_ticks, duty_ticks;
266	unsigned long pv, dc;
267	u8 prescale;
268
269	/* Limit period/duty cycle to max value supported by the HW */
270	period_ticks = mul_u64_u64_div_u64(state->period, rzg2l_gpt->rate_khz, USEC_PER_SEC);
271	if (period_ticks > RZG2L_MAX_TICKS)
272		period_ticks = RZG2L_MAX_TICKS;
273	/*
274	 * GPT counter is shared by the two IOs of a single channel, so
275	 * prescale and period can NOT be modified when there are multiple IOs
276	 * in use with different settings.
277	 */
278	if (rzg2l_gpt->channel_request_count[ch] > 1) {
279		u8 sibling_ch = rzg2l_gpt_sibling(pwm->hwpwm);
280
281		if (rzg2l_gpt_is_ch_enabled(rzg2l_gpt, sibling_ch)) {
282			if (period_ticks < rzg2l_gpt->period_ticks[ch])
283				return -EBUSY;
284
285			period_ticks = rzg2l_gpt->period_ticks[ch];
286		}
287	}
288
289	prescale = rzg2l_gpt_calculate_prescale(rzg2l_gpt, period_ticks);
290	pv = rzg2l_gpt_calculate_pv_or_dc(period_ticks, prescale);
291
292	duty_ticks = mul_u64_u64_div_u64(state->duty_cycle, rzg2l_gpt->rate_khz, USEC_PER_SEC);
293	if (duty_ticks > period_ticks)
294		duty_ticks = period_ticks;
295	dc = rzg2l_gpt_calculate_pv_or_dc(duty_ticks, prescale);
296
297	/*
298	 * GPT counter is shared by multiple channels, we cache the period ticks
299	 * from the first enabled channel and use the same value for both
300	 * channels.
301	 */
302	rzg2l_gpt->period_ticks[ch] = period_ticks;
303
304	/*
305	 * Counter must be stopped before modifying mode, prescaler, timer
306	 * counter and buffer enable registers. These registers are shared
307	 * between both channels. So allow updating these registers only for the
308	 * first enabled channel.
309	 */
310	if (rzg2l_gpt->channel_enable_count[ch] <= 1) {
311		rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), RZG2L_GTCR_CST, 0);
312
313		/* GPT set operating mode (saw-wave up-counting) */
314		rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), RZG2L_GTCR_MD,
315				 RZG2L_GTCR_MD_SAW_WAVE_PWM_MODE);
316
317		/* Set count direction */
318		rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTUDDTYC(ch), RZG2L_GTUDDTYC_UP_COUNTING);
319
320		/* Select count clock */
321		rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), RZG2L_GTCR_TPCS,
322				 FIELD_PREP(RZG2L_GTCR_TPCS, prescale));
323
324		/* Set period */
325		rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTPR(ch), pv);
326	}
327
328	/* Set duty cycle */
329	rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTCCR(ch, sub_ch), dc);
330
331	if (rzg2l_gpt->channel_enable_count[ch] <= 1) {
332		/* Set initial value for counter */
333		rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTCNT(ch), 0);
334
335		/* Set no buffer operation */
336		rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTBER(ch), 0);
337
338		/* Restart the counter after updating the registers */
339		rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch),
340				 RZG2L_GTCR_CST, RZG2L_GTCR_CST);
341	}
342
343	return 0;
344}
345
346static int rzg2l_gpt_apply(struct pwm_chip *chip, struct pwm_device *pwm,
347			   const struct pwm_state *state)
348{
349	struct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip);
350	bool enabled = pwm->state.enabled;
351	int ret;
352
353	if (state->polarity != PWM_POLARITY_NORMAL)
354		return -EINVAL;
355
356	guard(mutex)(&rzg2l_gpt->lock);
357	if (!state->enabled) {
358		if (enabled)
359			rzg2l_gpt_disable(rzg2l_gpt, pwm);
360
361		return 0;
362	}
363
364	ret = rzg2l_gpt_config(chip, pwm, state);
365	if (!ret && !enabled)
366		rzg2l_gpt_enable(rzg2l_gpt, pwm);
367
368	return ret;
369}
370
371static const struct pwm_ops rzg2l_gpt_ops = {
372	.request = rzg2l_gpt_request,
373	.free = rzg2l_gpt_free,
374	.get_state = rzg2l_gpt_get_state,
375	.apply = rzg2l_gpt_apply,
376};
377
378static int rzg2l_gpt_probe(struct platform_device *pdev)
379{
380	struct rzg2l_gpt_chip *rzg2l_gpt;
381	struct device *dev = &pdev->dev;
382	struct reset_control *rstc;
383	struct pwm_chip *chip;
384	unsigned long rate;
385	struct clk *clk;
386	int ret;
387
388	chip = devm_pwmchip_alloc(dev, RZG2L_MAX_PWM_CHANNELS, sizeof(*rzg2l_gpt));
389	if (IS_ERR(chip))
390		return PTR_ERR(chip);
391	rzg2l_gpt = to_rzg2l_gpt_chip(chip);
392
393	rzg2l_gpt->mmio = devm_platform_ioremap_resource(pdev, 0);
394	if (IS_ERR(rzg2l_gpt->mmio))
395		return PTR_ERR(rzg2l_gpt->mmio);
396
397	rstc = devm_reset_control_get_exclusive_deasserted(dev, NULL);
398	if (IS_ERR(rstc))
399		return dev_err_probe(dev, PTR_ERR(rstc), "Cannot deassert reset control\n");
400
401	clk = devm_clk_get_enabled(dev, NULL);
402	if (IS_ERR(clk))
403		return dev_err_probe(dev, PTR_ERR(clk), "Cannot get clock\n");
404
405	ret = devm_clk_rate_exclusive_get(dev, clk);
406	if (ret)
407		return ret;
408
409	rate = clk_get_rate(clk);
410	if (!rate)
411		return dev_err_probe(dev, -EINVAL, "The gpt clk rate is 0");
412
413	/*
414	 * Refuse clk rates > 1 GHz to prevent overflow later for computing
415	 * period and duty cycle.
416	 */
417	if (rate > NSEC_PER_SEC)
418		return dev_err_probe(dev, -EINVAL, "The gpt clk rate is > 1GHz");
419
420	/*
421	 * Rate is in MHz and is always integer for peripheral clk
422	 * 2^32 * 2^10 (prescalar) * 10^6 (rate_khz) < 2^64
423	 * So make sure rate is multiple of 1000.
424	 */
425	rzg2l_gpt->rate_khz = rate / KILO;
426	if (rzg2l_gpt->rate_khz * KILO != rate)
427		return dev_err_probe(dev, -EINVAL, "Rate is not multiple of 1000");
428
429	mutex_init(&rzg2l_gpt->lock);
430
431	chip->ops = &rzg2l_gpt_ops;
432	ret = devm_pwmchip_add(dev, chip);
433	if (ret)
434		return dev_err_probe(dev, ret, "Failed to add PWM chip\n");
435
436	return 0;
437}
438
439static const struct of_device_id rzg2l_gpt_of_table[] = {
440	{ .compatible = "renesas,rzg2l-gpt", },
441	{ /* Sentinel */ }
442};
443MODULE_DEVICE_TABLE(of, rzg2l_gpt_of_table);
444
445static struct platform_driver rzg2l_gpt_driver = {
446	.driver = {
447		.name = "pwm-rzg2l-gpt",
448		.of_match_table = rzg2l_gpt_of_table,
449	},
450	.probe = rzg2l_gpt_probe,
451};
452module_platform_driver(rzg2l_gpt_driver);
453
454MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
455MODULE_DESCRIPTION("Renesas RZ/G2L General PWM Timer (GPT) Driver");
456MODULE_LICENSE("GPL");