pwm-microchip-core.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * corePWM driver for Microchip "soft" FPGA IP cores.
  4 *
  5 * Copyright (c) 2021-2023 Microchip Corporation. All rights reserved.
  6 * Author: Conor Dooley <conor.dooley@microchip.com>
  7 * Documentation:
  8 * https://www.microsemi.com/document-portal/doc_download/1245275-corepwm-hb
  9 *
 10 * Limitations:
 11 * - If the IP block is configured without "shadow registers", all register
 12 *   writes will take effect immediately, causing glitches on the output.
 13 *   If shadow registers *are* enabled, setting the "SYNC_UPDATE" register
 14 *   notifies the core that it needs to update the registers defining the
 15 *   waveform from the contents of the "shadow registers". Otherwise, changes
 16 *   will take effective immediately, even for those channels.
 17 *   As setting the period/duty cycle takes 4 register writes, there is a window
 18 *   in which this races against the start of a new period.
 19 * - The IP block has no concept of a duty cycle, only rising/falling edges of
 20 *   the waveform. Unfortunately, if the rising & falling edges registers have
 21 *   the same value written to them the IP block will do whichever of a rising
 22 *   or a falling edge is possible. I.E. a 50% waveform at twice the requested
 23 *   period. Therefore to get a 0% waveform, the output is set the max high/low
 24 *   time depending on polarity.
 25 *   If the duty cycle is 0%, and the requested period is less than the
 26 *   available period resolution, this will manifest as a ~100% waveform (with
 27 *   some output glitches) rather than 50%.
 28 * - The PWM period is set for the whole IP block not per channel. The driver
 29 *   will only change the period if no other PWM output is enabled.
 30 */
 31
 32#include <linux/clk.h>
 33#include <linux/delay.h>
 34#include <linux/err.h>
 35#include <linux/io.h>
 36#include <linux/ktime.h>
 37#include <linux/math.h>
 38#include <linux/module.h>
 39#include <linux/of.h>
 40#include <linux/platform_device.h>
 41#include <linux/pwm.h>
 42
 43#define MCHPCOREPWM_PRESCALE_MAX	0xff
 44#define MCHPCOREPWM_PERIOD_STEPS_MAX	0xfe
 45#define MCHPCOREPWM_PERIOD_MAX		0xff00
 46
 47#define MCHPCOREPWM_PRESCALE	0x00
 48#define MCHPCOREPWM_PERIOD	0x04
 49#define MCHPCOREPWM_EN(i)	(0x08 + 0x04 * (i)) /* 0x08, 0x0c */
 50#define MCHPCOREPWM_POSEDGE(i)	(0x10 + 0x08 * (i)) /* 0x10, 0x18, ..., 0x88 */
 51#define MCHPCOREPWM_NEGEDGE(i)	(0x14 + 0x08 * (i)) /* 0x14, 0x1c, ..., 0x8c */
 52#define MCHPCOREPWM_SYNC_UPD	0xe4
 53#define MCHPCOREPWM_TIMEOUT_MS	100u
 54
 55struct mchp_core_pwm_chip {
 56	struct clk *clk;
 57	void __iomem *base;
 58	ktime_t update_timestamp;
 59	u32 sync_update_mask;
 60	u16 channel_enabled;
 61};
 62
 63static inline struct mchp_core_pwm_chip *to_mchp_core_pwm(struct pwm_chip *chip)
 64{
 65	return pwmchip_get_drvdata(chip);
 66}
 67
 68static void mchp_core_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm,
 69				 bool enable, u64 period)
 70{
 71	struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
 72	u8 channel_enable, reg_offset, shift;
 73
 74	/*
 75	 * There are two adjacent 8 bit control regs, the lower reg controls
 76	 * 0-7 and the upper reg 8-15. Check if the pwm is in the upper reg
 77	 * and if so, offset by the bus width.
 78	 */
 79	reg_offset = MCHPCOREPWM_EN(pwm->hwpwm >> 3);
 80	shift = pwm->hwpwm & 7;
 81
 82	channel_enable = readb_relaxed(mchp_core_pwm->base + reg_offset);
 83	channel_enable &= ~(1 << shift);
 84	channel_enable |= (enable << shift);
 85
 86	writel_relaxed(channel_enable, mchp_core_pwm->base + reg_offset);
 87	mchp_core_pwm->channel_enabled &= ~BIT(pwm->hwpwm);
 88	mchp_core_pwm->channel_enabled |= enable << pwm->hwpwm;
 89
 90	/*
 91	 * The updated values will not appear on the bus until they have been
 92	 * applied to the waveform at the beginning of the next period.
 93	 * This is a NO-OP if the channel does not have shadow registers.
 94	 */
 95	if (mchp_core_pwm->sync_update_mask & (1 << pwm->hwpwm))
 96		mchp_core_pwm->update_timestamp = ktime_add_ns(ktime_get(), period);
 97}
 98
 99static void mchp_core_pwm_wait_for_sync_update(struct mchp_core_pwm_chip *mchp_core_pwm,
100					       unsigned int channel)
101{
102	/*
103	 * If a shadow register is used for this PWM channel, and iff there is
104	 * a pending update to the waveform, we must wait for it to be applied
105	 * before attempting to read its state. Reading the registers yields
106	 * the currently implemented settings & the new ones are only readable
107	 * once the current period has ended.
108	 */
109
110	if (mchp_core_pwm->sync_update_mask & (1 << channel)) {
111		ktime_t current_time = ktime_get();
112		s64 remaining_ns;
113		u32 delay_us;
114
115		remaining_ns = ktime_to_ns(ktime_sub(mchp_core_pwm->update_timestamp,
116						     current_time));
117
118		/*
119		 * If the update has gone through, don't bother waiting for
120		 * obvious reasons. Otherwise wait around for an appropriate
121		 * amount of time for the update to go through.
122		 */
123		if (remaining_ns <= 0)
124			return;
125
126		delay_us = DIV_ROUND_UP_ULL(remaining_ns, NSEC_PER_USEC);
127		fsleep(delay_us);
128	}
129}
130
131static u64 mchp_core_pwm_calc_duty(const struct pwm_state *state, u64 clk_rate,
132				   u8 prescale, u8 period_steps)
133{
134	u64 duty_steps, tmp;
135
136	/*
137	 * Calculate the duty cycle in multiples of the prescaled period:
138	 * duty_steps = duty_in_ns / step_in_ns
139	 * step_in_ns = (prescale * NSEC_PER_SEC) / clk_rate
140	 * The code below is rearranged slightly to only divide once.
141	 */
142	tmp = (((u64)prescale) + 1) * NSEC_PER_SEC;
143	duty_steps = mul_u64_u64_div_u64(state->duty_cycle, clk_rate, tmp);
144
145	return duty_steps;
146}
147
148static void mchp_core_pwm_apply_duty(struct pwm_chip *chip, struct pwm_device *pwm,
149				     const struct pwm_state *state, u64 duty_steps,
150				     u16 period_steps)
151{
152	struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
153	u8 posedge, negedge;
154	u8 first_edge = 0, second_edge = duty_steps;
155
156	/*
157	 * Setting posedge == negedge doesn't yield a constant output,
158	 * so that's an unsuitable setting to model duty_steps = 0.
159	 * In that case set the unwanted edge to a value that never
160	 * triggers.
161	 */
162	if (duty_steps == 0)
163		first_edge = period_steps + 1;
164
165	if (state->polarity == PWM_POLARITY_INVERSED) {
166		negedge = first_edge;
167		posedge = second_edge;
168	} else {
169		posedge = first_edge;
170		negedge = second_edge;
171	}
172
173	/*
174	 * Set the sync bit which ensures that periods that already started are
175	 * completed unaltered. At each counter reset event the values are
176	 * updated from the shadow registers.
177	 */
178	writel_relaxed(posedge, mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm));
179	writel_relaxed(negedge, mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm));
180}
181
182static int mchp_core_pwm_calc_period(const struct pwm_state *state, unsigned long clk_rate,
183				     u16 *prescale, u16 *period_steps)
184{
185	u64 tmp;
186
187	/*
188	 * Calculate the period cycles and prescale values.
189	 * The registers are each 8 bits wide & multiplied to compute the period
190	 * using the formula:
191	 *           (prescale + 1) * (period_steps + 1)
192	 * period = -------------------------------------
193	 *                      clk_rate
194	 * so the maximum period that can be generated is 0x10000 times the
195	 * period of the input clock.
196	 * However, due to the design of the "hardware", it is not possible to
197	 * attain a 100% duty cycle if the full range of period_steps is used.
198	 * Therefore period_steps is restricted to 0xfe and the maximum multiple
199	 * of the clock period attainable is (0xff + 1) * (0xfe + 1) = 0xff00
200	 *
201	 * The prescale and period_steps registers operate similarly to
202	 * CLK_DIVIDER_ONE_BASED, where the value used by the hardware is that
203	 * in the register plus one.
204	 * It's therefore not possible to set a period lower than 1/clk_rate, so
205	 * if tmp is 0, abort. Without aborting, we will set a period that is
206	 * greater than that requested and, more importantly, will trigger the
207	 * neg-/pos-edge issue described in the limitations.
208	 */
209	tmp = mul_u64_u64_div_u64(state->period, clk_rate, NSEC_PER_SEC);
210	if (tmp >= MCHPCOREPWM_PERIOD_MAX) {
211		*prescale = MCHPCOREPWM_PRESCALE_MAX;
212		*period_steps = MCHPCOREPWM_PERIOD_STEPS_MAX;
213
214		return 0;
215	}
216
217	/*
218	 * There are multiple strategies that could be used to choose the
219	 * prescale & period_steps values.
220	 * Here the idea is to pick values so that the selection of duty cycles
221	 * is as finegrain as possible, while also keeping the period less than
222	 * that requested.
223	 *
224	 * A simple way to satisfy the first condition is to always set
225	 * period_steps to its maximum value. This neatly also satisfies the
226	 * second condition too, since using the maximum value of period_steps
227	 * to calculate prescale actually calculates its upper bound.
228	 * Integer division will ensure a round down, so the period will thereby
229	 * always be less than that requested.
230	 *
231	 * The downside of this approach is a significant degree of inaccuracy,
232	 * especially as tmp approaches integer multiples of
233	 * MCHPCOREPWM_PERIOD_STEPS_MAX.
234	 *
235	 * As we must produce a period less than that requested, and for the
236	 * sake of creating a simple algorithm, disallow small values of tmp
237	 * that would need special handling.
238	 */
239	if (tmp < MCHPCOREPWM_PERIOD_STEPS_MAX + 1)
240		return -EINVAL;
241
242	/*
243	 * This "optimal" value for prescale is be calculated using the maximum
244	 * permitted value of period_steps, 0xfe.
245	 *
246	 *                period * clk_rate
247	 * prescale = ------------------------- - 1
248	 *            NSEC_PER_SEC * (0xfe + 1)
249	 *
250	 *
251	 *  period * clk_rate
252	 * ------------------- was precomputed as `tmp`
253	 *    NSEC_PER_SEC
254	 */
255	*prescale = ((u16)tmp) / (MCHPCOREPWM_PERIOD_STEPS_MAX + 1) - 1;
256
257	/*
258	 * period_steps can be computed from prescale:
259	 *                      period * clk_rate
260	 * period_steps = ----------------------------- - 1
261	 *                NSEC_PER_SEC * (prescale + 1)
262	 *
263	 * However, in this approximation, we simply use the maximum value that
264	 * was used to compute prescale.
265	 */
266	*period_steps = MCHPCOREPWM_PERIOD_STEPS_MAX;
267
268	return 0;
269}
270
271static int mchp_core_pwm_apply_locked(struct pwm_chip *chip, struct pwm_device *pwm,
272				      const struct pwm_state *state)
273{
274	struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
275	bool period_locked;
276	unsigned long clk_rate;
277	u64 duty_steps;
278	u16 prescale, period_steps;
279	int ret;
280
281	if (!state->enabled) {
282		mchp_core_pwm_enable(chip, pwm, false, pwm->state.period);
283		return 0;
284	}
285
286	/*
287	 * If clk_rate is too big, the following multiplication might overflow.
288	 * However this is implausible, as the fabric of current FPGAs cannot
289	 * provide clocks at a rate high enough.
290	 */
291	clk_rate = clk_get_rate(mchp_core_pwm->clk);
292	if (clk_rate >= NSEC_PER_SEC)
293		return -EINVAL;
294
295	ret = mchp_core_pwm_calc_period(state, clk_rate, &prescale, &period_steps);
296	if (ret)
297		return ret;
298
299	/*
300	 * If the only thing that has changed is the duty cycle or the polarity,
301	 * we can shortcut the calculations and just compute/apply the new duty
302	 * cycle pos & neg edges
303	 * As all the channels share the same period, do not allow it to be
304	 * changed if any other channels are enabled.
305	 * If the period is locked, it may not be possible to use a period
306	 * less than that requested. In that case, we just abort.
307	 */
308	period_locked = mchp_core_pwm->channel_enabled & ~(1 << pwm->hwpwm);
309
310	if (period_locked) {
311		u16 hw_prescale;
312		u16 hw_period_steps;
313
314		hw_prescale = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);
315		hw_period_steps = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD);
316
317		if ((period_steps + 1) * (prescale + 1) <
318		    (hw_period_steps + 1) * (hw_prescale + 1))
319			return -EINVAL;
320
321		/*
322		 * It is possible that something could have set the period_steps
323		 * register to 0xff, which would prevent us from setting a 100%
324		 * or 0% relative duty cycle, as explained above in
325		 * mchp_core_pwm_calc_period().
326		 * The period is locked and we cannot change this, so we abort.
327		 */
328		if (hw_period_steps > MCHPCOREPWM_PERIOD_STEPS_MAX)
329			return -EINVAL;
330
331		prescale = hw_prescale;
332		period_steps = hw_period_steps;
333	}
334
335	duty_steps = mchp_core_pwm_calc_duty(state, clk_rate, prescale, period_steps);
336
337	/*
338	 * Because the period is not per channel, it is possible that the
339	 * requested duty cycle is longer than the period, in which case cap it
340	 * to the period, IOW a 100% duty cycle.
341	 */
342	if (duty_steps > period_steps)
343		duty_steps = period_steps + 1;
344
345	if (!period_locked) {
346		writel_relaxed(prescale, mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);
347		writel_relaxed(period_steps, mchp_core_pwm->base + MCHPCOREPWM_PERIOD);
348	}
349
350	mchp_core_pwm_apply_duty(chip, pwm, state, duty_steps, period_steps);
351
352	mchp_core_pwm_enable(chip, pwm, true, pwm->state.period);
353
354	return 0;
355}
356
357static int mchp_core_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
358			       const struct pwm_state *state)
359{
360	struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
361
362	mchp_core_pwm_wait_for_sync_update(mchp_core_pwm, pwm->hwpwm);
363
364	return mchp_core_pwm_apply_locked(chip, pwm, state);
365}
366
367static int mchp_core_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
368				   struct pwm_state *state)
369{
370	struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
371	u64 rate;
372	u16 prescale, period_steps;
373	u8 duty_steps, posedge, negedge;
374
375	mchp_core_pwm_wait_for_sync_update(mchp_core_pwm, pwm->hwpwm);
376
377	if (mchp_core_pwm->channel_enabled & (1 << pwm->hwpwm))
378		state->enabled = true;
379	else
380		state->enabled = false;
381
382	rate = clk_get_rate(mchp_core_pwm->clk);
383
384	/*
385	 * Calculating the period:
386	 * The registers are each 8 bits wide & multiplied to compute the period
387	 * using the formula:
388	 *           (prescale + 1) * (period_steps + 1)
389	 * period = -------------------------------------
390	 *                      clk_rate
391	 *
392	 * Note:
393	 * The prescale and period_steps registers operate similarly to
394	 * CLK_DIVIDER_ONE_BASED, where the value used by the hardware is that
395	 * in the register plus one.
396	 */
397	prescale = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);
398	period_steps = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD);
399
400	state->period = (period_steps + 1) * (prescale + 1);
401	state->period *= NSEC_PER_SEC;
402	state->period = DIV64_U64_ROUND_UP(state->period, rate);
403
404	posedge = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm));
405	negedge = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm));
406
407	if (negedge == posedge) {
408		state->duty_cycle = state->period;
409		state->period *= 2;
410	} else {
411		duty_steps = abs((s16)posedge - (s16)negedge);
412		state->duty_cycle = duty_steps * (prescale + 1) * NSEC_PER_SEC;
413		state->duty_cycle = DIV64_U64_ROUND_UP(state->duty_cycle, rate);
414	}
415
416	state->polarity = negedge < posedge ? PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL;
417
418	return 0;
419}
420
421static const struct pwm_ops mchp_core_pwm_ops = {
422	.apply = mchp_core_pwm_apply,
423	.get_state = mchp_core_pwm_get_state,
424};
425
426static const struct of_device_id mchp_core_of_match[] = {
427	{
428		.compatible = "microchip,corepwm-rtl-v4",
429	},
430	{ /* sentinel */ }
431};
432MODULE_DEVICE_TABLE(of, mchp_core_of_match);
433
434static int mchp_core_pwm_probe(struct platform_device *pdev)
435{
436	struct pwm_chip *chip;
437	struct mchp_core_pwm_chip *mchp_core_pwm;
438	struct resource *regs;
439	int ret;
440
441	chip = devm_pwmchip_alloc(&pdev->dev, 16, sizeof(*mchp_core_pwm));
442	if (IS_ERR(chip))
443		return PTR_ERR(chip);
444	mchp_core_pwm = to_mchp_core_pwm(chip);
445
446	mchp_core_pwm->base = devm_platform_get_and_ioremap_resource(pdev, 0, &regs);
447	if (IS_ERR(mchp_core_pwm->base))
448		return PTR_ERR(mchp_core_pwm->base);
449
450	mchp_core_pwm->clk = devm_clk_get_enabled(&pdev->dev, NULL);
451	if (IS_ERR(mchp_core_pwm->clk))
452		return dev_err_probe(&pdev->dev, PTR_ERR(mchp_core_pwm->clk),
453				     "failed to get PWM clock\n");
454
455	if (of_property_read_u32(pdev->dev.of_node, "microchip,sync-update-mask",
456				 &mchp_core_pwm->sync_update_mask))
457		mchp_core_pwm->sync_update_mask = 0;
458
459	chip->ops = &mchp_core_pwm_ops;
460
461	mchp_core_pwm->channel_enabled = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_EN(0));
462	mchp_core_pwm->channel_enabled |=
463		readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_EN(1)) << 8;
464
465	/*
466	 * Enable synchronous update mode for all channels for which shadow
467	 * registers have been synthesised.
468	 */
469	writel_relaxed(1U, mchp_core_pwm->base + MCHPCOREPWM_SYNC_UPD);
470	mchp_core_pwm->update_timestamp = ktime_get();
471
472	ret = devm_pwmchip_add(&pdev->dev, chip);
473	if (ret)
474		return dev_err_probe(&pdev->dev, ret, "Failed to add pwmchip\n");
475
476	return 0;
477}
478
479static struct platform_driver mchp_core_pwm_driver = {
480	.driver = {
481		.name = "mchp-core-pwm",
482		.of_match_table = mchp_core_of_match,
483	},
484	.probe = mchp_core_pwm_probe,
485};
486module_platform_driver(mchp_core_pwm_driver);
487
488MODULE_LICENSE("GPL");
489MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
490MODULE_DESCRIPTION("corePWM driver for Microchip FPGAs");