pwm-imx-tpm.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright 2018-2019 NXP.
  4 *
  5 * Limitations:
  6 * - The TPM counter and period counter are shared between
  7 *   multiple channels, so all channels should use same period
  8 *   settings.
  9 * - Changes to polarity cannot be latched at the time of the
 10 *   next period start.
 11 * - Changing period and duty cycle together isn't atomic,
 12 *   with the wrong timing it might happen that a period is
 13 *   produced with old duty cycle but new period settings.
 14 */
 15
 16#include <linux/bitfield.h>
 17#include <linux/bitops.h>
 18#include <linux/clk.h>
 19#include <linux/err.h>
 20#include <linux/io.h>
 21#include <linux/module.h>
 22#include <linux/of.h>
 23#include <linux/pinctrl/consumer.h>
 24#include <linux/platform_device.h>
 25#include <linux/pwm.h>
 26#include <linux/slab.h>
 27
 28#define PWM_IMX_TPM_PARAM	0x4
 29#define PWM_IMX_TPM_GLOBAL	0x8
 30#define PWM_IMX_TPM_SC		0x10
 31#define PWM_IMX_TPM_CNT		0x14
 32#define PWM_IMX_TPM_MOD		0x18
 33#define PWM_IMX_TPM_CnSC(n)	(0x20 + (n) * 0x8)
 34#define PWM_IMX_TPM_CnV(n)	(0x24 + (n) * 0x8)
 35
 36#define PWM_IMX_TPM_PARAM_CHAN			GENMASK(7, 0)
 37
 38#define PWM_IMX_TPM_SC_PS			GENMASK(2, 0)
 39#define PWM_IMX_TPM_SC_CMOD			GENMASK(4, 3)
 40#define PWM_IMX_TPM_SC_CMOD_INC_EVERY_CLK	FIELD_PREP(PWM_IMX_TPM_SC_CMOD, 1)
 41#define PWM_IMX_TPM_SC_CPWMS			BIT(5)
 42
 43#define PWM_IMX_TPM_CnSC_CHF	BIT(7)
 44#define PWM_IMX_TPM_CnSC_MSB	BIT(5)
 45#define PWM_IMX_TPM_CnSC_MSA	BIT(4)
 46
 47/*
 48 * The reference manual describes this field as two separate bits. The
 49 * semantic of the two bits isn't orthogonal though, so they are treated
 50 * together as a 2-bit field here.
 51 */
 52#define PWM_IMX_TPM_CnSC_ELS	GENMASK(3, 2)
 53#define PWM_IMX_TPM_CnSC_ELS_INVERSED	FIELD_PREP(PWM_IMX_TPM_CnSC_ELS, 1)
 54#define PWM_IMX_TPM_CnSC_ELS_NORMAL	FIELD_PREP(PWM_IMX_TPM_CnSC_ELS, 2)
 55
 56
 57#define PWM_IMX_TPM_MOD_WIDTH	16
 58#define PWM_IMX_TPM_MOD_MOD	GENMASK(PWM_IMX_TPM_MOD_WIDTH - 1, 0)
 59
 60struct imx_tpm_pwm_chip {
 61	struct clk *clk;
 62	void __iomem *base;
 63	struct mutex lock;
 64	u32 user_count;
 65	u32 enable_count;
 66	u32 real_period;
 67};
 68
 69struct imx_tpm_pwm_param {
 70	u8 prescale;
 71	u32 mod;
 72	u32 val;
 73};
 74
 75static inline struct imx_tpm_pwm_chip *
 76to_imx_tpm_pwm_chip(struct pwm_chip *chip)
 77{
 78	return pwmchip_get_drvdata(chip);
 79}
 80
 81/*
 82 * This function determines for a given pwm_state *state that a consumer
 83 * might request the pwm_state *real_state that eventually is implemented
 84 * by the hardware and the necessary register values (in *p) to achieve
 85 * this.
 86 */
 87static int pwm_imx_tpm_round_state(struct pwm_chip *chip,
 88				   struct imx_tpm_pwm_param *p,
 89				   struct pwm_state *real_state,
 90				   const struct pwm_state *state)
 91{
 92	struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
 93	u32 rate, prescale, period_count, clock_unit;
 94	u64 tmp;
 95
 96	rate = clk_get_rate(tpm->clk);
 97	tmp = (u64)state->period * rate;
 98	clock_unit = DIV_ROUND_CLOSEST_ULL(tmp, NSEC_PER_SEC);
 99	if (clock_unit <= PWM_IMX_TPM_MOD_MOD)
100		prescale = 0;
101	else
102		prescale = ilog2(clock_unit) + 1 - PWM_IMX_TPM_MOD_WIDTH;
103
104	if ((!FIELD_FIT(PWM_IMX_TPM_SC_PS, prescale)))
105		return -ERANGE;
106	p->prescale = prescale;
107
108	period_count = (clock_unit + ((1 << prescale) >> 1)) >> prescale;
109	if (period_count == 0)
110		return -EINVAL;
111	p->mod = period_count - 1;
112
113	/* calculate real period HW can support */
114	tmp = (u64)period_count << prescale;
115	tmp *= NSEC_PER_SEC;
116	real_state->period = DIV_ROUND_CLOSEST_ULL(tmp, rate);
117
118	/*
119	 * if eventually the PWM output is inactive, either
120	 * duty cycle is 0 or status is disabled, need to
121	 * make sure the output pin is inactive.
122	 */
123	if (!state->enabled)
124		real_state->duty_cycle = 0;
125	else
126		real_state->duty_cycle = state->duty_cycle;
127
128	tmp = (u64)p->mod * real_state->duty_cycle;
129	p->val = DIV64_U64_ROUND_CLOSEST(tmp, real_state->period);
130
131	real_state->polarity = state->polarity;
132	real_state->enabled = state->enabled;
133
134	return 0;
135}
136
137static int pwm_imx_tpm_get_state(struct pwm_chip *chip,
138				 struct pwm_device *pwm,
139				 struct pwm_state *state)
140{
141	struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
142	u32 rate, val, prescale;
143	u64 tmp;
144
145	/* get period */
146	state->period = tpm->real_period;
147
148	/* get duty cycle */
149	rate = clk_get_rate(tpm->clk);
150	val = readl(tpm->base + PWM_IMX_TPM_SC);
151	prescale = FIELD_GET(PWM_IMX_TPM_SC_PS, val);
152	tmp = readl(tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm));
153	tmp = (tmp << prescale) * NSEC_PER_SEC;
154	state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, rate);
155
156	/* get polarity */
157	val = readl(tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
158	if ((val & PWM_IMX_TPM_CnSC_ELS) == PWM_IMX_TPM_CnSC_ELS_INVERSED)
159		state->polarity = PWM_POLARITY_INVERSED;
160	else
161		/*
162		 * Assume reserved values (2b00 and 2b11) to yield
163		 * normal polarity.
164		 */
165		state->polarity = PWM_POLARITY_NORMAL;
166
167	/* get channel status */
168	state->enabled = FIELD_GET(PWM_IMX_TPM_CnSC_ELS, val) ? true : false;
169
170	return 0;
171}
172
173/* this function is supposed to be called with mutex hold */
174static int pwm_imx_tpm_apply_hw(struct pwm_chip *chip,
175				struct imx_tpm_pwm_param *p,
176				struct pwm_state *state,
177				struct pwm_device *pwm)
178{
179	struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
180	bool period_update = false;
181	bool duty_update = false;
182	u32 val, cmod, cur_prescale;
183	unsigned long timeout;
184	struct pwm_state c;
185
186	if (state->period != tpm->real_period) {
187		/*
188		 * TPM counter is shared by multiple channels, so
189		 * prescale and period can NOT be modified when
190		 * there are multiple channels in use with different
191		 * period settings.
192		 */
193		if (tpm->user_count > 1)
194			return -EBUSY;
195
196		val = readl(tpm->base + PWM_IMX_TPM_SC);
197		cmod = FIELD_GET(PWM_IMX_TPM_SC_CMOD, val);
198		cur_prescale = FIELD_GET(PWM_IMX_TPM_SC_PS, val);
199		if (cmod && cur_prescale != p->prescale)
200			return -EBUSY;
201
202		/* set TPM counter prescale */
203		val &= ~PWM_IMX_TPM_SC_PS;
204		val |= FIELD_PREP(PWM_IMX_TPM_SC_PS, p->prescale);
205		writel(val, tpm->base + PWM_IMX_TPM_SC);
206
207		/*
208		 * if the counter is disabled (CMOD == 0), programming the new
209		 * period length (MOD) will not reset the counter (CNT). If
210		 * CNT.COUNT happens to be bigger than the new MOD value then
211		 * the counter will end up being reset way too late. Therefore,
212		 * manually reset it to 0.
213		 */
214		if (!cmod)
215			writel(0x0, tpm->base + PWM_IMX_TPM_CNT);
216		/*
217		 * set period count:
218		 * if the PWM is disabled (CMOD[1:0] = 2b00), then MOD register
219		 * is updated when MOD register is written.
220		 *
221		 * if the PWM is enabled (CMOD[1:0] ≠ 2b00), the period length
222		 * is latched into hardware when the next period starts.
223		 */
224		writel(p->mod, tpm->base + PWM_IMX_TPM_MOD);
225		tpm->real_period = state->period;
226		period_update = true;
227	}
228
229	pwm_imx_tpm_get_state(chip, pwm, &c);
230
231	/* polarity is NOT allowed to be changed if PWM is active */
232	if (c.enabled && c.polarity != state->polarity)
233		return -EBUSY;
234
235	if (state->duty_cycle != c.duty_cycle) {
236		/*
237		 * set channel value:
238		 * if the PWM is disabled (CMOD[1:0] = 2b00), then CnV register
239		 * is updated when CnV register is written.
240		 *
241		 * if the PWM is enabled (CMOD[1:0] ≠ 2b00), the duty length
242		 * is latched into hardware when the next period starts.
243		 */
244		writel(p->val, tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm));
245		duty_update = true;
246	}
247
248	/* make sure MOD & CnV registers are updated */
249	if (period_update || duty_update) {
250		timeout = jiffies + msecs_to_jiffies(tpm->real_period /
251						     NSEC_PER_MSEC + 1);
252		while (readl(tpm->base + PWM_IMX_TPM_MOD) != p->mod
253		       || readl(tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm))
254		       != p->val) {
255			if (time_after(jiffies, timeout))
256				return -ETIME;
257			cpu_relax();
258		}
259	}
260
261	/*
262	 * polarity settings will enabled/disable output status
263	 * immediately, so if the channel is disabled, need to
264	 * make sure MSA/MSB/ELS are set to 0 which means channel
265	 * disabled.
266	 */
267	val = readl(tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
268	val &= ~(PWM_IMX_TPM_CnSC_ELS | PWM_IMX_TPM_CnSC_MSA |
269		 PWM_IMX_TPM_CnSC_MSB);
270	if (state->enabled) {
271		/*
272		 * set polarity (for edge-aligned PWM modes)
273		 *
274		 * ELS[1:0] = 2b10 yields normal polarity behaviour,
275		 * ELS[1:0] = 2b01 yields inversed polarity.
276		 * The other values are reserved.
277		 */
278		val |= PWM_IMX_TPM_CnSC_MSB;
279		val |= (state->polarity == PWM_POLARITY_NORMAL) ?
280			PWM_IMX_TPM_CnSC_ELS_NORMAL :
281			PWM_IMX_TPM_CnSC_ELS_INVERSED;
282	}
283	writel(val, tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
284
285	/* control the counter status */
286	if (state->enabled != c.enabled) {
287		val = readl(tpm->base + PWM_IMX_TPM_SC);
288		if (state->enabled) {
289			if (++tpm->enable_count == 1)
290				val |= PWM_IMX_TPM_SC_CMOD_INC_EVERY_CLK;
291		} else {
292			if (--tpm->enable_count == 0)
293				val &= ~PWM_IMX_TPM_SC_CMOD;
294		}
295		writel(val, tpm->base + PWM_IMX_TPM_SC);
296	}
297
298	return 0;
299}
300
301static int pwm_imx_tpm_apply(struct pwm_chip *chip,
302			     struct pwm_device *pwm,
303			     const struct pwm_state *state)
304{
305	struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
306	struct imx_tpm_pwm_param param;
307	struct pwm_state real_state;
308	int ret;
309
310	ret = pwm_imx_tpm_round_state(chip, &param, &real_state, state);
311	if (ret)
312		return ret;
313
314	mutex_lock(&tpm->lock);
315	ret = pwm_imx_tpm_apply_hw(chip, &param, &real_state, pwm);
316	mutex_unlock(&tpm->lock);
317
318	return ret;
319}
320
321static int pwm_imx_tpm_request(struct pwm_chip *chip, struct pwm_device *pwm)
322{
323	struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
324
325	mutex_lock(&tpm->lock);
326	tpm->user_count++;
327	mutex_unlock(&tpm->lock);
328
329	return 0;
330}
331
332static void pwm_imx_tpm_free(struct pwm_chip *chip, struct pwm_device *pwm)
333{
334	struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
335
336	mutex_lock(&tpm->lock);
337	tpm->user_count--;
338	mutex_unlock(&tpm->lock);
339}
340
341static const struct pwm_ops imx_tpm_pwm_ops = {
342	.request = pwm_imx_tpm_request,
343	.free = pwm_imx_tpm_free,
344	.get_state = pwm_imx_tpm_get_state,
345	.apply = pwm_imx_tpm_apply,
346};
347
348static int pwm_imx_tpm_probe(struct platform_device *pdev)
349{
350	struct pwm_chip *chip;
351	struct imx_tpm_pwm_chip *tpm;
352	struct clk *clk;
353	void __iomem *base;
354	int ret;
355	unsigned int npwm;
356	u32 val;
357
358	base = devm_platform_ioremap_resource(pdev, 0);
359	if (IS_ERR(base))
360		return PTR_ERR(base);
361
362	clk = devm_clk_get_enabled(&pdev->dev, NULL);
363	if (IS_ERR(clk))
364		return dev_err_probe(&pdev->dev, PTR_ERR(clk),
365				     "failed to get PWM clock\n");
366
367	/* get number of channels */
368	val = readl(base + PWM_IMX_TPM_PARAM);
369	npwm = FIELD_GET(PWM_IMX_TPM_PARAM_CHAN, val);
370
371	chip = devm_pwmchip_alloc(&pdev->dev, npwm, sizeof(*tpm));
372	if (IS_ERR(chip))
373		return PTR_ERR(chip);
374	tpm = to_imx_tpm_pwm_chip(chip);
375
376	platform_set_drvdata(pdev, tpm);
377
378	tpm->base = base;
379	tpm->clk = clk;
380
381	chip->ops = &imx_tpm_pwm_ops;
382
383	mutex_init(&tpm->lock);
384
385	ret = devm_pwmchip_add(&pdev->dev, chip);
386	if (ret)
387		return dev_err_probe(&pdev->dev, ret, "failed to add PWM chip\n");
388
389	return 0;
390}
391
392static int pwm_imx_tpm_suspend(struct device *dev)
393{
394	struct imx_tpm_pwm_chip *tpm = dev_get_drvdata(dev);
395	int ret;
396
397	if (tpm->enable_count > 0)
398		return -EBUSY;
399
400	/*
401	 * Force 'real_period' to be zero to force period update code
402	 * can be executed after system resume back, since suspend causes
403	 * the period related registers to become their reset values.
404	 */
405	tpm->real_period = 0;
406
407	clk_disable_unprepare(tpm->clk);
408
409	ret = pinctrl_pm_select_sleep_state(dev);
410	if (ret)
411		clk_prepare_enable(tpm->clk);
412
413	return ret;
414}
415
416static int pwm_imx_tpm_resume(struct device *dev)
417{
418	struct imx_tpm_pwm_chip *tpm = dev_get_drvdata(dev);
419	int ret = 0;
420
421	ret = pinctrl_pm_select_default_state(dev);
422	if (ret)
423		return ret;
424
425	ret = clk_prepare_enable(tpm->clk);
426	if (ret) {
427		dev_err(dev, "failed to prepare or enable clock: %d\n", ret);
428		pinctrl_pm_select_sleep_state(dev);
429	}
430
431	return ret;
432}
433
434static DEFINE_SIMPLE_DEV_PM_OPS(imx_tpm_pwm_pm,
435				pwm_imx_tpm_suspend, pwm_imx_tpm_resume);
436
437static const struct of_device_id imx_tpm_pwm_dt_ids[] = {
438	{ .compatible = "fsl,imx7ulp-pwm", },
439	{ /* sentinel */ }
440};
441MODULE_DEVICE_TABLE(of, imx_tpm_pwm_dt_ids);
442
443static struct platform_driver imx_tpm_pwm_driver = {
444	.driver = {
445		.name = "imx7ulp-tpm-pwm",
446		.of_match_table = imx_tpm_pwm_dt_ids,
447		.pm = pm_ptr(&imx_tpm_pwm_pm),
448	},
449	.probe	= pwm_imx_tpm_probe,
450};
451module_platform_driver(imx_tpm_pwm_driver);
452
453MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>");
454MODULE_DESCRIPTION("i.MX TPM PWM Driver");
455MODULE_LICENSE("GPL v2");