pwm-img.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Imagination Technologies Pulse Width Modulator driver
  4 *
  5 * Copyright (c) 2014-2015, Imagination Technologies
  6 *
  7 * Based on drivers/pwm/pwm-tegra.c, Copyright (c) 2010, NVIDIA Corporation
  8 */
  9
 10#include <linux/clk.h>
 11#include <linux/err.h>
 12#include <linux/io.h>
 13#include <linux/mfd/syscon.h>
 14#include <linux/module.h>
 15#include <linux/of.h>
 16#include <linux/platform_device.h>
 17#include <linux/pm_runtime.h>
 18#include <linux/property.h>
 19#include <linux/pwm.h>
 20#include <linux/regmap.h>
 21#include <linux/slab.h>
 22
 23/* PWM registers */
 24#define PWM_CTRL_CFG				0x0000
 25#define PWM_CTRL_CFG_NO_SUB_DIV			0
 26#define PWM_CTRL_CFG_SUB_DIV0			1
 27#define PWM_CTRL_CFG_SUB_DIV1			2
 28#define PWM_CTRL_CFG_SUB_DIV0_DIV1		3
 29#define PWM_CTRL_CFG_DIV_SHIFT(ch)		((ch) * 2 + 4)
 30#define PWM_CTRL_CFG_DIV_MASK			0x3
 31
 32#define PWM_CH_CFG(ch)				(0x4 + (ch) * 4)
 33#define PWM_CH_CFG_TMBASE_SHIFT			0
 34#define PWM_CH_CFG_DUTY_SHIFT			16
 35
 36#define PERIP_PWM_PDM_CONTROL			0x0140
 37#define PERIP_PWM_PDM_CONTROL_CH_MASK		0x1
 38#define PERIP_PWM_PDM_CONTROL_CH_SHIFT(ch)	((ch) * 4)
 39
 40#define IMG_PWM_PM_TIMEOUT			1000 /* ms */
 41
 42/*
 43 * PWM period is specified with a timebase register,
 44 * in number of step periods. The PWM duty cycle is also
 45 * specified in step periods, in the [0, $timebase] range.
 46 * In other words, the timebase imposes the duty cycle
 47 * resolution. Therefore, let's constraint the timebase to
 48 * a minimum value to allow a sane range of duty cycle values.
 49 * Imposing a minimum timebase, will impose a maximum PWM frequency.
 50 *
 51 * The value chosen is completely arbitrary.
 52 */
 53#define MIN_TMBASE_STEPS			16
 54
 55#define IMG_PWM_NPWM				4
 56
 57struct img_pwm_soc_data {
 58	u32 max_timebase;
 59};
 60
 61struct img_pwm_chip {
 62	struct clk	*pwm_clk;
 63	struct clk	*sys_clk;
 64	void __iomem	*base;
 65	struct regmap	*periph_regs;
 66	int		max_period_ns;
 67	int		min_period_ns;
 68	const struct img_pwm_soc_data   *data;
 69	u32		suspend_ctrl_cfg;
 70	u32		suspend_ch_cfg[IMG_PWM_NPWM];
 71};
 72
 73static inline struct img_pwm_chip *to_img_pwm_chip(struct pwm_chip *chip)
 74{
 75	return pwmchip_get_drvdata(chip);
 76}
 77
 78static inline void img_pwm_writel(struct img_pwm_chip *imgchip,
 79				  u32 reg, u32 val)
 80{
 81	writel(val, imgchip->base + reg);
 82}
 83
 84static inline u32 img_pwm_readl(struct img_pwm_chip *imgchip, u32 reg)
 85{
 86	return readl(imgchip->base + reg);
 87}
 88
 89static int img_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 90			  int duty_ns, int period_ns)
 91{
 92	u32 val, div, duty, timebase;
 93	unsigned long mul, output_clk_hz, input_clk_hz;
 94	struct img_pwm_chip *imgchip = to_img_pwm_chip(chip);
 95	unsigned int max_timebase = imgchip->data->max_timebase;
 96	int ret;
 97
 98	if (period_ns < imgchip->min_period_ns ||
 99	    period_ns > imgchip->max_period_ns) {
100		dev_err(pwmchip_parent(chip), "configured period not in range\n");
101		return -ERANGE;
102	}
103
104	input_clk_hz = clk_get_rate(imgchip->pwm_clk);
105	output_clk_hz = DIV_ROUND_UP(NSEC_PER_SEC, period_ns);
106
107	mul = DIV_ROUND_UP(input_clk_hz, output_clk_hz);
108	if (mul <= max_timebase) {
109		div = PWM_CTRL_CFG_NO_SUB_DIV;
110		timebase = DIV_ROUND_UP(mul, 1);
111	} else if (mul <= max_timebase * 8) {
112		div = PWM_CTRL_CFG_SUB_DIV0;
113		timebase = DIV_ROUND_UP(mul, 8);
114	} else if (mul <= max_timebase * 64) {
115		div = PWM_CTRL_CFG_SUB_DIV1;
116		timebase = DIV_ROUND_UP(mul, 64);
117	} else if (mul <= max_timebase * 512) {
118		div = PWM_CTRL_CFG_SUB_DIV0_DIV1;
119		timebase = DIV_ROUND_UP(mul, 512);
120	} else {
121		dev_err(pwmchip_parent(chip),
122			"failed to configure timebase steps/divider value\n");
123		return -EINVAL;
124	}
125
126	duty = DIV_ROUND_UP(timebase * duty_ns, period_ns);
127
128	ret = pm_runtime_resume_and_get(pwmchip_parent(chip));
129	if (ret < 0)
130		return ret;
131
132	val = img_pwm_readl(imgchip, PWM_CTRL_CFG);
133	val &= ~(PWM_CTRL_CFG_DIV_MASK << PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm));
134	val |= (div & PWM_CTRL_CFG_DIV_MASK) <<
135		PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm);
136	img_pwm_writel(imgchip, PWM_CTRL_CFG, val);
137
138	val = (duty << PWM_CH_CFG_DUTY_SHIFT) |
139	      (timebase << PWM_CH_CFG_TMBASE_SHIFT);
140	img_pwm_writel(imgchip, PWM_CH_CFG(pwm->hwpwm), val);
141
142	pm_runtime_put_autosuspend(pwmchip_parent(chip));
143
144	return 0;
145}
146
147static int img_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
148{
149	u32 val;
150	struct img_pwm_chip *imgchip = to_img_pwm_chip(chip);
151	int ret;
152
153	ret = pm_runtime_resume_and_get(pwmchip_parent(chip));
154	if (ret < 0)
155		return ret;
156
157	val = img_pwm_readl(imgchip, PWM_CTRL_CFG);
158	val |= BIT(pwm->hwpwm);
159	img_pwm_writel(imgchip, PWM_CTRL_CFG, val);
160
161	regmap_clear_bits(imgchip->periph_regs, PERIP_PWM_PDM_CONTROL,
162			  PERIP_PWM_PDM_CONTROL_CH_MASK <<
163			  PERIP_PWM_PDM_CONTROL_CH_SHIFT(pwm->hwpwm));
164
165	return 0;
166}
167
168static void img_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
169{
170	u32 val;
171	struct img_pwm_chip *imgchip = to_img_pwm_chip(chip);
172
173	val = img_pwm_readl(imgchip, PWM_CTRL_CFG);
174	val &= ~BIT(pwm->hwpwm);
175	img_pwm_writel(imgchip, PWM_CTRL_CFG, val);
176
177	pm_runtime_put_autosuspend(pwmchip_parent(chip));
178}
179
180static int img_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
181			 const struct pwm_state *state)
182{
183	int err;
184
185	if (state->polarity != PWM_POLARITY_NORMAL)
186		return -EINVAL;
187
188	if (!state->enabled) {
189		if (pwm->state.enabled)
190			img_pwm_disable(chip, pwm);
191
192		return 0;
193	}
194
195	err = img_pwm_config(chip, pwm, state->duty_cycle, state->period);
196	if (err)
197		return err;
198
199	if (!pwm->state.enabled)
200		err = img_pwm_enable(chip, pwm);
201
202	return err;
203}
204
205static const struct pwm_ops img_pwm_ops = {
206	.apply = img_pwm_apply,
207};
208
209static const struct img_pwm_soc_data pistachio_pwm = {
210	.max_timebase = 255,
211};
212
213static const struct of_device_id img_pwm_of_match[] = {
214	{
215		.compatible = "img,pistachio-pwm",
216		.data = &pistachio_pwm,
217	},
218	{ }
219};
220MODULE_DEVICE_TABLE(of, img_pwm_of_match);
221
222static int img_pwm_runtime_suspend(struct device *dev)
223{
224	struct pwm_chip *chip = dev_get_drvdata(dev);
225	struct img_pwm_chip *imgchip = to_img_pwm_chip(chip);
226
227	clk_disable_unprepare(imgchip->pwm_clk);
228	clk_disable_unprepare(imgchip->sys_clk);
229
230	return 0;
231}
232
233static int img_pwm_runtime_resume(struct device *dev)
234{
235	struct pwm_chip *chip = dev_get_drvdata(dev);
236	struct img_pwm_chip *imgchip = to_img_pwm_chip(chip);
237	int ret;
238
239	ret = clk_prepare_enable(imgchip->sys_clk);
240	if (ret < 0) {
241		dev_err(dev, "could not prepare or enable sys clock\n");
242		return ret;
243	}
244
245	ret = clk_prepare_enable(imgchip->pwm_clk);
246	if (ret < 0) {
247		dev_err(dev, "could not prepare or enable pwm clock\n");
248		clk_disable_unprepare(imgchip->sys_clk);
249		return ret;
250	}
251
252	return 0;
253}
254
255static int img_pwm_probe(struct platform_device *pdev)
256{
257	int ret;
258	u64 val;
259	unsigned long clk_rate;
260	struct pwm_chip *chip;
261	struct img_pwm_chip *imgchip;
262
263	chip = devm_pwmchip_alloc(&pdev->dev, IMG_PWM_NPWM, sizeof(*imgchip));
264	if (IS_ERR(chip))
265		return PTR_ERR(chip);
266	imgchip = to_img_pwm_chip(chip);
267
268	imgchip->base = devm_platform_ioremap_resource(pdev, 0);
269	if (IS_ERR(imgchip->base))
270		return PTR_ERR(imgchip->base);
271
272	imgchip->data = device_get_match_data(&pdev->dev);
273
274	imgchip->periph_regs = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
275							       "img,cr-periph");
276	if (IS_ERR(imgchip->periph_regs))
277		return PTR_ERR(imgchip->periph_regs);
278
279	imgchip->sys_clk = devm_clk_get(&pdev->dev, "sys");
280	if (IS_ERR(imgchip->sys_clk)) {
281		dev_err(&pdev->dev, "failed to get system clock\n");
282		return PTR_ERR(imgchip->sys_clk);
283	}
284
285	imgchip->pwm_clk = devm_clk_get(&pdev->dev, "pwm");
286	if (IS_ERR(imgchip->pwm_clk)) {
287		dev_err(&pdev->dev, "failed to get pwm clock\n");
288		return PTR_ERR(imgchip->pwm_clk);
289	}
290
291	platform_set_drvdata(pdev, chip);
292
293	pm_runtime_set_autosuspend_delay(&pdev->dev, IMG_PWM_PM_TIMEOUT);
294	pm_runtime_use_autosuspend(&pdev->dev);
295	pm_runtime_enable(&pdev->dev);
296	if (!pm_runtime_enabled(&pdev->dev)) {
297		ret = img_pwm_runtime_resume(&pdev->dev);
298		if (ret)
299			goto err_pm_disable;
300	}
301
302	clk_rate = clk_get_rate(imgchip->pwm_clk);
303	if (!clk_rate) {
304		dev_err(&pdev->dev, "imgchip clock has no frequency\n");
305		ret = -EINVAL;
306		goto err_suspend;
307	}
308
309	/* The maximum input clock divider is 512 */
310	val = (u64)NSEC_PER_SEC * 512 * imgchip->data->max_timebase;
311	do_div(val, clk_rate);
312	imgchip->max_period_ns = val;
313
314	val = (u64)NSEC_PER_SEC * MIN_TMBASE_STEPS;
315	do_div(val, clk_rate);
316	imgchip->min_period_ns = val;
317
318	chip->ops = &img_pwm_ops;
319
320	ret = pwmchip_add(chip);
321	if (ret < 0) {
322		dev_err(&pdev->dev, "pwmchip_add failed: %d\n", ret);
323		goto err_suspend;
324	}
325
326	return 0;
327
328err_suspend:
329	if (!pm_runtime_enabled(&pdev->dev))
330		img_pwm_runtime_suspend(&pdev->dev);
331err_pm_disable:
332	pm_runtime_disable(&pdev->dev);
333	pm_runtime_dont_use_autosuspend(&pdev->dev);
334	return ret;
335}
336
337static void img_pwm_remove(struct platform_device *pdev)
338{
339	struct pwm_chip *chip = platform_get_drvdata(pdev);
340
341	pm_runtime_disable(&pdev->dev);
342	if (!pm_runtime_status_suspended(&pdev->dev))
343		img_pwm_runtime_suspend(&pdev->dev);
344
345	pwmchip_remove(chip);
346}
347
348#ifdef CONFIG_PM_SLEEP
349static int img_pwm_suspend(struct device *dev)
350{
351	struct pwm_chip *chip = dev_get_drvdata(dev);
352	struct img_pwm_chip *imgchip = to_img_pwm_chip(chip);
353	int i, ret;
354
355	if (pm_runtime_status_suspended(dev)) {
356		ret = img_pwm_runtime_resume(dev);
357		if (ret)
358			return ret;
359	}
360
361	for (i = 0; i < chip->npwm; i++)
362		imgchip->suspend_ch_cfg[i] = img_pwm_readl(imgchip,
363							   PWM_CH_CFG(i));
364
365	imgchip->suspend_ctrl_cfg = img_pwm_readl(imgchip, PWM_CTRL_CFG);
366
367	img_pwm_runtime_suspend(dev);
368
369	return 0;
370}
371
372static int img_pwm_resume(struct device *dev)
373{
374	struct pwm_chip *chip = dev_get_drvdata(dev);
375	struct img_pwm_chip *imgchip = to_img_pwm_chip(chip);
376	int ret;
377	int i;
378
379	ret = img_pwm_runtime_resume(dev);
380	if (ret)
381		return ret;
382
383	for (i = 0; i < chip->npwm; i++)
384		img_pwm_writel(imgchip, PWM_CH_CFG(i),
385			       imgchip->suspend_ch_cfg[i]);
386
387	img_pwm_writel(imgchip, PWM_CTRL_CFG, imgchip->suspend_ctrl_cfg);
388
389	for (i = 0; i < chip->npwm; i++)
390		if (imgchip->suspend_ctrl_cfg & BIT(i))
391			regmap_clear_bits(imgchip->periph_regs,
392					  PERIP_PWM_PDM_CONTROL,
393					  PERIP_PWM_PDM_CONTROL_CH_MASK <<
394					  PERIP_PWM_PDM_CONTROL_CH_SHIFT(i));
395
396	if (pm_runtime_status_suspended(dev))
397		img_pwm_runtime_suspend(dev);
398
399	return 0;
400}
401#endif /* CONFIG_PM */
402
403static const struct dev_pm_ops img_pwm_pm_ops = {
404	SET_RUNTIME_PM_OPS(img_pwm_runtime_suspend,
405			   img_pwm_runtime_resume,
406			   NULL)
407	SET_SYSTEM_SLEEP_PM_OPS(img_pwm_suspend, img_pwm_resume)
408};
409
410static struct platform_driver img_pwm_driver = {
411	.driver = {
412		.name = "img-pwm",
413		.pm = &img_pwm_pm_ops,
414		.of_match_table = img_pwm_of_match,
415	},
416	.probe = img_pwm_probe,
417	.remove = img_pwm_remove,
418};
419module_platform_driver(img_pwm_driver);
420
421MODULE_AUTHOR("Sai Masarapu <Sai.Masarapu@imgtec.com>");
422MODULE_DESCRIPTION("Imagination Technologies PWM DAC driver");
423MODULE_LICENSE("GPL v2");