pwm-axi-pwmgen.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Analog Devices AXI PWM generator
  4 *
  5 * Copyright 2024 Analog Devices Inc.
  6 * Copyright 2024 Baylibre SAS
  7 *
  8 * Device docs: https://analogdevicesinc.github.io/hdl/library/axi_pwm_gen/index.html
  9 *
 10 * Limitations:
 11 * - The writes to registers for period and duty are shadowed until
 12 *   LOAD_CONFIG is written to AXI_PWMGEN_REG_RSTN, at which point
 13 *   they take effect.
 14 * - Writing LOAD_CONFIG also has the effect of re-synchronizing all
 15 *   enabled channels, which could cause glitching on other channels. It
 16 *   is therefore expected that channels are assigned harmonic periods
 17 *   and all have a single user coordinating this.
 18 * - Supports normal polarity. Does not support changing polarity.
 19 * - On disable, the PWM output becomes low (inactive).
 20 */
 21#include <linux/adi-axi-common.h>
 22#include <linux/bits.h>
 23#include <linux/clk.h>
 24#include <linux/err.h>
 25#include <linux/io.h>
 26#include <linux/minmax.h>
 27#include <linux/module.h>
 28#include <linux/platform_device.h>
 29#include <linux/pwm.h>
 30#include <linux/regmap.h>
 31#include <linux/slab.h>
 32
 33#define AXI_PWMGEN_REG_ID		0x04
 34#define AXI_PWMGEN_REG_SCRATCHPAD	0x08
 35#define AXI_PWMGEN_REG_CORE_MAGIC	0x0C
 36#define AXI_PWMGEN_REG_RSTN		0x10
 37#define   AXI_PWMGEN_REG_RSTN_LOAD_CONFIG	BIT(1)
 38#define   AXI_PWMGEN_REG_RSTN_RESET		BIT(0)
 39#define AXI_PWMGEN_REG_NPWM		0x14
 40#define AXI_PWMGEN_REG_CONFIG		0x18
 41#define   AXI_PWMGEN_REG_CONFIG_FORCE_ALIGN	BIT(1)
 42#define AXI_PWMGEN_CHX_PERIOD(ch)	(0x40 + (4 * (ch)))
 43#define AXI_PWMGEN_CHX_DUTY(ch)		(0x80 + (4 * (ch)))
 44#define AXI_PWMGEN_CHX_OFFSET(ch)	(0xC0 + (4 * (ch)))
 45#define AXI_PWMGEN_REG_CORE_MAGIC_VAL	0x601A3471 /* Identification number to test during setup */
 46
 47struct axi_pwmgen_ddata {
 48	struct regmap *regmap;
 49	unsigned long clk_rate_hz;
 50};
 51
 52static const struct regmap_config axi_pwmgen_regmap_config = {
 53	.reg_bits = 32,
 54	.reg_stride = 4,
 55	.val_bits = 32,
 56	.max_register = 0xFC,
 57};
 58
 59/* This represents a hardware configuration for one channel */
 60struct axi_pwmgen_waveform {
 61	u32 period_cnt;
 62	u32 duty_cycle_cnt;
 63	u32 duty_offset_cnt;
 64};
 65
 66static struct axi_pwmgen_ddata *axi_pwmgen_ddata_from_chip(struct pwm_chip *chip)
 67{
 68	return pwmchip_get_drvdata(chip);
 69}
 70
 71static int axi_pwmgen_round_waveform_tohw(struct pwm_chip *chip,
 72					  struct pwm_device *pwm,
 73					  const struct pwm_waveform *wf,
 74					  void *_wfhw)
 75{
 76	struct axi_pwmgen_waveform *wfhw = _wfhw;
 77	struct axi_pwmgen_ddata *ddata = axi_pwmgen_ddata_from_chip(chip);
 78	int ret = 0;
 79
 80	if (wf->period_length_ns == 0) {
 81		*wfhw = (struct axi_pwmgen_waveform){
 82			.period_cnt = 0,
 83			.duty_cycle_cnt = 0,
 84			.duty_offset_cnt = 0,
 85		};
 86	} else {
 87		/* With ddata->clk_rate_hz < NSEC_PER_SEC this won't overflow. */
 88		wfhw->period_cnt = min_t(u64,
 89					 mul_u64_u32_div(wf->period_length_ns, ddata->clk_rate_hz, NSEC_PER_SEC),
 90					 U32_MAX);
 91
 92		if (wfhw->period_cnt == 0) {
 93			/*
 94			 * The specified period is too short for the hardware.
 95			 * So round up .period_cnt to 1 (i.e. the smallest
 96			 * possible period). With .duty_cycle and .duty_offset
 97			 * being less than or equal to .period, their rounded
 98			 * value must be 0.
 99			 */
100			wfhw->period_cnt = 1;
101			wfhw->duty_cycle_cnt = 0;
102			wfhw->duty_offset_cnt = 0;
103			ret = 1;
104		} else {
105			wfhw->duty_cycle_cnt = min_t(u64,
106						     mul_u64_u32_div(wf->duty_length_ns, ddata->clk_rate_hz, NSEC_PER_SEC),
107						     U32_MAX);
108			wfhw->duty_offset_cnt = min_t(u64,
109						      mul_u64_u32_div(wf->duty_offset_ns, ddata->clk_rate_hz, NSEC_PER_SEC),
110						      U32_MAX);
111		}
112	}
113
114	dev_dbg(&chip->dev, "pwm#%u: %lld/%lld [+%lld] @%lu -> PERIOD: %08x, DUTY: %08x, OFFSET: %08x\n",
115		pwm->hwpwm, wf->duty_length_ns, wf->period_length_ns, wf->duty_offset_ns,
116		ddata->clk_rate_hz, wfhw->period_cnt, wfhw->duty_cycle_cnt, wfhw->duty_offset_cnt);
117
118	return ret;
119}
120
121static int axi_pwmgen_round_waveform_fromhw(struct pwm_chip *chip, struct pwm_device *pwm,
122					     const void *_wfhw, struct pwm_waveform *wf)
123{
124	const struct axi_pwmgen_waveform *wfhw = _wfhw;
125	struct axi_pwmgen_ddata *ddata = axi_pwmgen_ddata_from_chip(chip);
126
127	wf->period_length_ns = DIV64_U64_ROUND_UP((u64)wfhw->period_cnt * NSEC_PER_SEC,
128					ddata->clk_rate_hz);
129
130	wf->duty_length_ns = DIV64_U64_ROUND_UP((u64)wfhw->duty_cycle_cnt * NSEC_PER_SEC,
131					    ddata->clk_rate_hz);
132
133	wf->duty_offset_ns = DIV64_U64_ROUND_UP((u64)wfhw->duty_offset_cnt * NSEC_PER_SEC,
134					     ddata->clk_rate_hz);
135
136	return 0;
137}
138
139static int axi_pwmgen_write_waveform(struct pwm_chip *chip,
140				     struct pwm_device *pwm,
141				     const void *_wfhw)
142{
143	const struct axi_pwmgen_waveform *wfhw = _wfhw;
144	struct axi_pwmgen_ddata *ddata = axi_pwmgen_ddata_from_chip(chip);
145	struct regmap *regmap = ddata->regmap;
146	unsigned int ch = pwm->hwpwm;
147	int ret;
148
149	ret = regmap_write(regmap, AXI_PWMGEN_CHX_PERIOD(ch), wfhw->period_cnt);
150	if (ret)
151		return ret;
152
153	ret = regmap_write(regmap, AXI_PWMGEN_CHX_DUTY(ch), wfhw->duty_cycle_cnt);
154	if (ret)
155		return ret;
156
157	ret = regmap_write(regmap, AXI_PWMGEN_CHX_OFFSET(ch), wfhw->duty_offset_cnt);
158	if (ret)
159		return ret;
160
161	return regmap_write(regmap, AXI_PWMGEN_REG_RSTN, AXI_PWMGEN_REG_RSTN_LOAD_CONFIG);
162}
163
164static int axi_pwmgen_read_waveform(struct pwm_chip *chip,
165				    struct pwm_device *pwm,
166				    void *_wfhw)
167{
168	struct axi_pwmgen_waveform *wfhw = _wfhw;
169	struct axi_pwmgen_ddata *ddata = axi_pwmgen_ddata_from_chip(chip);
170	struct regmap *regmap = ddata->regmap;
171	unsigned int ch = pwm->hwpwm;
172	int ret;
173
174	ret = regmap_read(regmap, AXI_PWMGEN_CHX_PERIOD(ch), &wfhw->period_cnt);
175	if (ret)
176		return ret;
177
178	ret = regmap_read(regmap, AXI_PWMGEN_CHX_DUTY(ch), &wfhw->duty_cycle_cnt);
179	if (ret)
180		return ret;
181
182	ret = regmap_read(regmap, AXI_PWMGEN_CHX_OFFSET(ch), &wfhw->duty_offset_cnt);
183	if (ret)
184		return ret;
185
186	if (wfhw->duty_cycle_cnt > wfhw->period_cnt)
187		wfhw->duty_cycle_cnt = wfhw->period_cnt;
188
189	/* XXX: is this the actual behaviour of the hardware? */
190	if (wfhw->duty_offset_cnt >= wfhw->period_cnt) {
191		wfhw->duty_cycle_cnt = 0;
192		wfhw->duty_offset_cnt = 0;
193	}
194
195	return 0;
196}
197
198static const struct pwm_ops axi_pwmgen_pwm_ops = {
199	.sizeof_wfhw = sizeof(struct axi_pwmgen_waveform),
200	.round_waveform_tohw = axi_pwmgen_round_waveform_tohw,
201	.round_waveform_fromhw = axi_pwmgen_round_waveform_fromhw,
202	.read_waveform = axi_pwmgen_read_waveform,
203	.write_waveform = axi_pwmgen_write_waveform,
204};
205
206static int axi_pwmgen_setup(struct regmap *regmap, struct device *dev)
207{
208	int ret;
209	u32 val;
210
211	ret = regmap_read(regmap, AXI_PWMGEN_REG_CORE_MAGIC, &val);
212	if (ret)
213		return ret;
214
215	if (val != AXI_PWMGEN_REG_CORE_MAGIC_VAL)
216		return dev_err_probe(dev, -ENODEV,
217			"failed to read expected value from register: got %08x, expected %08x\n",
218			val, AXI_PWMGEN_REG_CORE_MAGIC_VAL);
219
220	ret = regmap_read(regmap, ADI_AXI_REG_VERSION, &val);
221	if (ret)
222		return ret;
223
224	if (ADI_AXI_PCORE_VER_MAJOR(val) != 2) {
225		return dev_err_probe(dev, -ENODEV, "Unsupported peripheral version %u.%u.%u\n",
226			ADI_AXI_PCORE_VER_MAJOR(val),
227			ADI_AXI_PCORE_VER_MINOR(val),
228			ADI_AXI_PCORE_VER_PATCH(val));
229	}
230
231	/* Enable the core */
232	ret = regmap_clear_bits(regmap, AXI_PWMGEN_REG_RSTN, AXI_PWMGEN_REG_RSTN_RESET);
233	if (ret)
234		return ret;
235
236	/*
237	 * Enable force align so that changes to PWM period and duty cycle take
238	 * effect immediately. Otherwise, the effect of the change is delayed
239	 * until the period of all channels run out, which can be long after the
240	 * apply function returns.
241	 */
242	ret = regmap_set_bits(regmap, AXI_PWMGEN_REG_CONFIG, AXI_PWMGEN_REG_CONFIG_FORCE_ALIGN);
243	if (ret)
244		return ret;
245
246	ret = regmap_read(regmap, AXI_PWMGEN_REG_NPWM, &val);
247	if (ret)
248		return ret;
249
250	/* Return the number of PWMs */
251	return val;
252}
253
254static int axi_pwmgen_probe(struct platform_device *pdev)
255{
256	struct device *dev = &pdev->dev;
257	struct regmap *regmap;
258	struct pwm_chip *chip;
259	struct axi_pwmgen_ddata *ddata;
260	struct clk *axi_clk, *clk;
261	void __iomem *io_base;
262	int ret;
263
264	io_base = devm_platform_ioremap_resource(pdev, 0);
265	if (IS_ERR(io_base))
266		return PTR_ERR(io_base);
267
268	regmap = devm_regmap_init_mmio(dev, io_base, &axi_pwmgen_regmap_config);
269	if (IS_ERR(regmap))
270		return dev_err_probe(dev, PTR_ERR(regmap),
271				     "failed to init register map\n");
272
273	ret = axi_pwmgen_setup(regmap, dev);
274	if (ret < 0)
275		return ret;
276
277	chip = devm_pwmchip_alloc(dev, ret, sizeof(*ddata));
278	if (IS_ERR(chip))
279		return PTR_ERR(chip);
280	ddata = pwmchip_get_drvdata(chip);
281	ddata->regmap = regmap;
282
283	/*
284	 * Using NULL here instead of "axi" for backwards compatibility. There
285	 * are some dtbs that don't give clock-names and have the "ext" clock
286	 * as the one and only clock (due to mistake in the original bindings).
287	 */
288	axi_clk = devm_clk_get_enabled(dev, NULL);
289	if (IS_ERR(axi_clk))
290		return dev_err_probe(dev, PTR_ERR(axi_clk), "failed to get axi clock\n");
291
292	clk = devm_clk_get_optional_enabled(dev, "ext");
293	if (IS_ERR(clk))
294		return dev_err_probe(dev, PTR_ERR(clk), "failed to get ext clock\n");
295
296	/*
297	 * If there is no "ext" clock, it means the HDL was compiled with
298	 * ASYNC_CLK_EN=0. In this case, the AXI clock is also used for the
299	 * PWM output clock.
300	 */
301	if (!clk)
302		clk = axi_clk;
303
304	ret = devm_clk_rate_exclusive_get(dev, clk);
305	if (ret)
306		return dev_err_probe(dev, ret, "failed to get exclusive rate\n");
307
308	ddata->clk_rate_hz = clk_get_rate(clk);
309	if (!ddata->clk_rate_hz || ddata->clk_rate_hz > NSEC_PER_SEC)
310		return dev_err_probe(dev, -EINVAL,
311				     "Invalid clock rate: %lu\n", ddata->clk_rate_hz);
312
313	chip->ops = &axi_pwmgen_pwm_ops;
314	chip->atomic = true;
315
316	ret = devm_pwmchip_add(dev, chip);
317	if (ret)
318		return dev_err_probe(dev, ret, "could not add PWM chip\n");
319
320	return 0;
321}
322
323static const struct of_device_id axi_pwmgen_ids[] = {
324	{ .compatible = "adi,axi-pwmgen-2.00.a" },
325	{ }
326};
327MODULE_DEVICE_TABLE(of, axi_pwmgen_ids);
328
329static struct platform_driver axi_pwmgen_driver = {
330	.driver = {
331		.name = "axi-pwmgen",
332		.of_match_table = axi_pwmgen_ids,
333	},
334	.probe = axi_pwmgen_probe,
335};
336module_platform_driver(axi_pwmgen_driver);
337
338MODULE_LICENSE("GPL");
339MODULE_AUTHOR("Sergiu Cuciurean <sergiu.cuciurean@analog.com>");
340MODULE_AUTHOR("Trevor Gamblin <tgamblin@baylibre.com>");
341MODULE_DESCRIPTION("Driver for the Analog Devices AXI PWM generator");