pwm-atmel.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Driver for Atmel Pulse Width Modulation Controller
  4 *
  5 * Copyright (C) 2013 Atmel Corporation
  6 *		 Bo Shen <voice.shen@atmel.com>
  7 *
  8 * Links to reference manuals for the supported PWM chips can be found in
  9 * Documentation/arch/arm/microchip.rst.
 10 *
 11 * Limitations:
 12 * - Periods start with the inactive level.
 13 * - Hardware has to be stopped in general to update settings.
 14 *
 15 * Software bugs/possible improvements:
 16 * - When atmel_pwm_apply() is called with state->enabled=false a change in
 17 *   state->polarity isn't honored.
 18 * - Instead of sleeping to wait for a completed period, the interrupt
 19 *   functionality could be used.
 20 */
 21
 22#include <linux/clk.h>
 23#include <linux/delay.h>
 24#include <linux/err.h>
 25#include <linux/io.h>
 26#include <linux/module.h>
 27#include <linux/of.h>
 28#include <linux/platform_device.h>
 29#include <linux/pwm.h>
 30#include <linux/slab.h>
 31
 32/* The following is global registers for PWM controller */
 33#define PWM_ENA			0x04
 34#define PWM_DIS			0x08
 35#define PWM_SR			0x0C
 36#define PWM_ISR			0x1C
 37/* Bit field in SR */
 38#define PWM_SR_ALL_CH_MASK	0x0F
 39
 40/* The following register is PWM channel related registers */
 41#define PWM_CH_REG_OFFSET	0x200
 42#define PWM_CH_REG_SIZE		0x20
 43
 44#define PWM_CMR			0x0
 45/* Bit field in CMR */
 46#define PWM_CMR_CPOL		(1 << 9)
 47#define PWM_CMR_UPD_CDTY	(1 << 10)
 48#define PWM_CMR_CPRE_MSK	0xF
 49
 50/* The following registers for PWM v1 */
 51#define PWMV1_CDTY		0x04
 52#define PWMV1_CPRD		0x08
 53#define PWMV1_CUPD		0x10
 54
 55/* The following registers for PWM v2 */
 56#define PWMV2_CDTY		0x04
 57#define PWMV2_CDTYUPD		0x08
 58#define PWMV2_CPRD		0x0C
 59#define PWMV2_CPRDUPD		0x10
 60
 61#define PWM_MAX_PRES		10
 62
 63struct atmel_pwm_registers {
 64	u8 period;
 65	u8 period_upd;
 66	u8 duty;
 67	u8 duty_upd;
 68};
 69
 70struct atmel_pwm_config {
 71	u32 period_bits;
 72};
 73
 74struct atmel_pwm_data {
 75	struct atmel_pwm_registers regs;
 76	struct atmel_pwm_config cfg;
 77};
 78
 79struct atmel_pwm_chip {
 80	struct clk *clk;
 81	void __iomem *base;
 82	const struct atmel_pwm_data *data;
 83
 84	/*
 85	 * The hardware supports a mechanism to update a channel's duty cycle at
 86	 * the end of the currently running period. When such an update is
 87	 * pending we delay disabling the PWM until the new configuration is
 88	 * active because otherwise pmw_config(duty_cycle=0); pwm_disable();
 89	 * might not result in an inactive output.
 90	 * This bitmask tracks for which channels an update is pending in
 91	 * hardware.
 92	 */
 93	u32 update_pending;
 94};
 95
 96static inline struct atmel_pwm_chip *to_atmel_pwm_chip(struct pwm_chip *chip)
 97{
 98	return pwmchip_get_drvdata(chip);
 99}
100
101static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip,
102				  unsigned long offset)
103{
104	return readl_relaxed(chip->base + offset);
105}
106
107static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip,
108				    unsigned long offset, unsigned long val)
109{
110	writel_relaxed(val, chip->base + offset);
111}
112
113static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip,
114				     unsigned int ch, unsigned long offset)
115{
116	unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
117
118	return atmel_pwm_readl(chip, base + offset);
119}
120
121static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip,
122				       unsigned int ch, unsigned long offset,
123				       unsigned long val)
124{
125	unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
126
127	atmel_pwm_writel(chip, base + offset, val);
128}
129
130static void atmel_pwm_update_pending(struct atmel_pwm_chip *chip)
131{
132	/*
133	 * Each channel that has its bit in ISR set started a new period since
134	 * ISR was cleared and so there is no more update pending.  Note that
135	 * reading ISR clears it, so this needs to handle all channels to not
136	 * loose information.
137	 */
138	u32 isr = atmel_pwm_readl(chip, PWM_ISR);
139
140	chip->update_pending &= ~isr;
141}
142
143static void atmel_pwm_set_pending(struct atmel_pwm_chip *chip, unsigned int ch)
144{
145	/*
146	 * Clear pending flags in hardware because otherwise there might still
147	 * be a stale flag in ISR.
148	 */
149	atmel_pwm_update_pending(chip);
150
151	chip->update_pending |= (1 << ch);
152}
153
154static int atmel_pwm_test_pending(struct atmel_pwm_chip *chip, unsigned int ch)
155{
156	int ret = 0;
157
158	if (chip->update_pending & (1 << ch)) {
159		atmel_pwm_update_pending(chip);
160
161		if (chip->update_pending & (1 << ch))
162			ret = 1;
163	}
164
165	return ret;
166}
167
168static int atmel_pwm_wait_nonpending(struct atmel_pwm_chip *chip, unsigned int ch)
169{
170	unsigned long timeout = jiffies + 2 * HZ;
171	int ret;
172
173	while ((ret = atmel_pwm_test_pending(chip, ch)) &&
174	       time_before(jiffies, timeout))
175		usleep_range(10, 100);
176
177	return ret ? -ETIMEDOUT : 0;
178}
179
180static int atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip,
181					     unsigned long clkrate,
182					     const struct pwm_state *state,
183					     unsigned long *cprd, u32 *pres)
184{
185	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
186	unsigned long long cycles = state->period;
187	int shift;
188
189	/* Calculate the period cycles and prescale value */
190	cycles *= clkrate;
191	do_div(cycles, NSEC_PER_SEC);
192
193	/*
194	 * The register for the period length is cfg.period_bits bits wide.
195	 * So for each bit the number of clock cycles is wider divide the input
196	 * clock frequency by two using pres and shift cprd accordingly.
197	 */
198	shift = fls(cycles) - atmel_pwm->data->cfg.period_bits;
199
200	if (shift > PWM_MAX_PRES) {
201		dev_err(pwmchip_parent(chip), "pres exceeds the maximum value\n");
202		return -EINVAL;
203	} else if (shift > 0) {
204		*pres = shift;
205		cycles >>= *pres;
206	} else {
207		*pres = 0;
208	}
209
210	*cprd = cycles;
211
212	return 0;
213}
214
215static void atmel_pwm_calculate_cdty(const struct pwm_state *state,
216				     unsigned long clkrate, unsigned long cprd,
217				     u32 pres, unsigned long *cdty)
218{
219	unsigned long long cycles = state->duty_cycle;
220
221	cycles *= clkrate;
222	do_div(cycles, NSEC_PER_SEC);
223	cycles >>= pres;
224	*cdty = cprd - cycles;
225}
226
227static void atmel_pwm_update_cdty(struct pwm_chip *chip, struct pwm_device *pwm,
228				  unsigned long cdty)
229{
230	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
231	u32 val;
232
233	if (atmel_pwm->data->regs.duty_upd ==
234	    atmel_pwm->data->regs.period_upd) {
235		val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
236		val &= ~PWM_CMR_UPD_CDTY;
237		atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
238	}
239
240	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
241			    atmel_pwm->data->regs.duty_upd, cdty);
242	atmel_pwm_set_pending(atmel_pwm, pwm->hwpwm);
243}
244
245static void atmel_pwm_set_cprd_cdty(struct pwm_chip *chip,
246				    struct pwm_device *pwm,
247				    unsigned long cprd, unsigned long cdty)
248{
249	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
250
251	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
252			    atmel_pwm->data->regs.duty, cdty);
253	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
254			    atmel_pwm->data->regs.period, cprd);
255}
256
257static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm,
258			      bool disable_clk)
259{
260	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
261	unsigned long timeout;
262
263	atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm);
264
265	atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm);
266
267	/*
268	 * Wait for the PWM channel disable operation to be effective before
269	 * stopping the clock.
270	 */
271	timeout = jiffies + 2 * HZ;
272
273	while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) &&
274	       time_before(jiffies, timeout))
275		usleep_range(10, 100);
276
277	if (disable_clk)
278		clk_disable(atmel_pwm->clk);
279}
280
281static int atmel_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
282			   const struct pwm_state *state)
283{
284	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
285	unsigned long cprd, cdty;
286	u32 pres, val;
287	int ret;
288
289	if (state->enabled) {
290		unsigned long clkrate = clk_get_rate(atmel_pwm->clk);
291
292		if (pwm->state.enabled &&
293		    pwm->state.polarity == state->polarity &&
294		    pwm->state.period == state->period) {
295			u32 cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
296
297			cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
298						  atmel_pwm->data->regs.period);
299			pres = cmr & PWM_CMR_CPRE_MSK;
300
301			atmel_pwm_calculate_cdty(state, clkrate, cprd, pres, &cdty);
302			atmel_pwm_update_cdty(chip, pwm, cdty);
303			return 0;
304		}
305
306		ret = atmel_pwm_calculate_cprd_and_pres(chip, clkrate, state, &cprd,
307							&pres);
308		if (ret) {
309			dev_err(pwmchip_parent(chip),
310				"failed to calculate cprd and prescaler\n");
311			return ret;
312		}
313
314		atmel_pwm_calculate_cdty(state, clkrate, cprd, pres, &cdty);
315
316		if (pwm->state.enabled) {
317			atmel_pwm_disable(chip, pwm, false);
318		} else {
319			ret = clk_enable(atmel_pwm->clk);
320			if (ret) {
321				dev_err(pwmchip_parent(chip), "failed to enable clock\n");
322				return ret;
323			}
324		}
325
326		/* It is necessary to preserve CPOL, inside CMR */
327		val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
328		val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK);
329		if (state->polarity == PWM_POLARITY_NORMAL)
330			val &= ~PWM_CMR_CPOL;
331		else
332			val |= PWM_CMR_CPOL;
333		atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
334		atmel_pwm_set_cprd_cdty(chip, pwm, cprd, cdty);
335		atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm);
336	} else if (pwm->state.enabled) {
337		atmel_pwm_disable(chip, pwm, true);
338	}
339
340	return 0;
341}
342
343static int atmel_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
344			       struct pwm_state *state)
345{
346	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
347	u32 sr, cmr;
348
349	sr = atmel_pwm_readl(atmel_pwm, PWM_SR);
350	cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
351
352	if (sr & (1 << pwm->hwpwm)) {
353		unsigned long rate = clk_get_rate(atmel_pwm->clk);
354		u32 cdty, cprd, pres;
355		u64 tmp;
356
357		pres = cmr & PWM_CMR_CPRE_MSK;
358
359		cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
360					  atmel_pwm->data->regs.period);
361		tmp = (u64)cprd * NSEC_PER_SEC;
362		tmp <<= pres;
363		state->period = DIV64_U64_ROUND_UP(tmp, rate);
364
365		/* Wait for an updated duty_cycle queued in hardware */
366		atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm);
367
368		cdty = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
369					  atmel_pwm->data->regs.duty);
370		tmp = (u64)(cprd - cdty) * NSEC_PER_SEC;
371		tmp <<= pres;
372		state->duty_cycle = DIV64_U64_ROUND_UP(tmp, rate);
373
374		state->enabled = true;
375	} else {
376		state->enabled = false;
377	}
378
379	if (cmr & PWM_CMR_CPOL)
380		state->polarity = PWM_POLARITY_INVERSED;
381	else
382		state->polarity = PWM_POLARITY_NORMAL;
383
384	return 0;
385}
386
387static const struct pwm_ops atmel_pwm_ops = {
388	.apply = atmel_pwm_apply,
389	.get_state = atmel_pwm_get_state,
390};
391
392static const struct atmel_pwm_data atmel_sam9rl_pwm_data = {
393	.regs = {
394		.period		= PWMV1_CPRD,
395		.period_upd	= PWMV1_CUPD,
396		.duty		= PWMV1_CDTY,
397		.duty_upd	= PWMV1_CUPD,
398	},
399	.cfg = {
400		/* 16 bits to keep period and duty. */
401		.period_bits	= 16,
402	},
403};
404
405static const struct atmel_pwm_data atmel_sama5_pwm_data = {
406	.regs = {
407		.period		= PWMV2_CPRD,
408		.period_upd	= PWMV2_CPRDUPD,
409		.duty		= PWMV2_CDTY,
410		.duty_upd	= PWMV2_CDTYUPD,
411	},
412	.cfg = {
413		/* 16 bits to keep period and duty. */
414		.period_bits	= 16,
415	},
416};
417
418static const struct atmel_pwm_data mchp_sam9x60_pwm_data = {
419	.regs = {
420		.period		= PWMV1_CPRD,
421		.period_upd	= PWMV1_CUPD,
422		.duty		= PWMV1_CDTY,
423		.duty_upd	= PWMV1_CUPD,
424	},
425	.cfg = {
426		/* 32 bits to keep period and duty. */
427		.period_bits	= 32,
428	},
429};
430
431static const struct of_device_id atmel_pwm_dt_ids[] = {
432	{
433		.compatible = "atmel,at91sam9rl-pwm",
434		.data = &atmel_sam9rl_pwm_data,
435	}, {
436		.compatible = "atmel,sama5d3-pwm",
437		.data = &atmel_sama5_pwm_data,
438	}, {
439		.compatible = "atmel,sama5d2-pwm",
440		.data = &atmel_sama5_pwm_data,
441	}, {
442		.compatible = "microchip,sam9x60-pwm",
443		.data = &mchp_sam9x60_pwm_data,
444	}, {
445		/* sentinel */
446	},
447};
448MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids);
449
450static int atmel_pwm_enable_clk_if_on(struct pwm_chip *chip, bool on)
451{
452	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
453	unsigned int i, cnt = 0;
454	unsigned long sr;
455	int ret = 0;
456
457	sr = atmel_pwm_readl(atmel_pwm, PWM_SR) & PWM_SR_ALL_CH_MASK;
458	if (!sr)
459		return 0;
460
461	cnt = bitmap_weight(&sr, chip->npwm);
462
463	if (!on)
464		goto disable_clk;
465
466	for (i = 0; i < cnt; i++) {
467		ret = clk_enable(atmel_pwm->clk);
468		if (ret) {
469			dev_err(pwmchip_parent(chip),
470				"failed to enable clock for pwm %pe\n",
471				ERR_PTR(ret));
472
473			cnt = i;
474			goto disable_clk;
475		}
476	}
477
478	return 0;
479
480disable_clk:
481	while (cnt--)
482		clk_disable(atmel_pwm->clk);
483
484	return ret;
485}
486
487static int atmel_pwm_probe(struct platform_device *pdev)
488{
489	struct atmel_pwm_chip *atmel_pwm;
490	struct pwm_chip *chip;
491	int ret;
492
493	chip = devm_pwmchip_alloc(&pdev->dev, 4, sizeof(*atmel_pwm));
494	if (IS_ERR(chip))
495		return PTR_ERR(chip);
496
497	atmel_pwm = to_atmel_pwm_chip(chip);
498	atmel_pwm->data = of_device_get_match_data(&pdev->dev);
499
500	atmel_pwm->update_pending = 0;
501
502	atmel_pwm->base = devm_platform_ioremap_resource(pdev, 0);
503	if (IS_ERR(atmel_pwm->base))
504		return PTR_ERR(atmel_pwm->base);
505
506	atmel_pwm->clk = devm_clk_get_prepared(&pdev->dev, NULL);
507	if (IS_ERR(atmel_pwm->clk))
508		return dev_err_probe(&pdev->dev, PTR_ERR(atmel_pwm->clk),
509				     "failed to get prepared PWM clock\n");
510
511	chip->ops = &atmel_pwm_ops;
512
513	ret = atmel_pwm_enable_clk_if_on(chip, true);
514	if (ret < 0)
515		return ret;
516
517	ret = devm_pwmchip_add(&pdev->dev, chip);
518	if (ret < 0) {
519		dev_err_probe(&pdev->dev, ret, "failed to add PWM chip\n");
520		goto disable_clk;
521	}
522
523	return 0;
524
525disable_clk:
526	atmel_pwm_enable_clk_if_on(chip, false);
527
528	return ret;
529}
530
531static struct platform_driver atmel_pwm_driver = {
532	.driver = {
533		.name = "atmel-pwm",
534		.of_match_table = atmel_pwm_dt_ids,
535	},
536	.probe = atmel_pwm_probe,
537};
538module_platform_driver(atmel_pwm_driver);
539
540MODULE_ALIAS("platform:atmel-pwm");
541MODULE_AUTHOR("Bo Shen <voice.shen@atmel.com>");
542MODULE_DESCRIPTION("Atmel PWM driver");
543MODULE_LICENSE("GPL v2");