FILE
ptp_ocp.c
File preview with syntax highlighting.
linux-6.19.14/drivers/ptp/ptp_ocp.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* Copyright (c) 2020 Facebook */ 3 4#include <linux/bits.h> 5#include <linux/err.h> 6#include <linux/kernel.h> 7#include <linux/module.h> 8#include <linux/debugfs.h> 9#include <linux/init.h> 10#include <linux/pci.h> 11#include <linux/serial_8250.h> 12#include <linux/clkdev.h> 13#include <linux/clk-provider.h> 14#include <linux/platform_device.h> 15#include <linux/platform_data/i2c-xiic.h> 16#include <linux/platform_data/i2c-ocores.h> 17#include <linux/ptp_clock_kernel.h> 18#include <linux/spi/spi.h> 19#include <linux/spi/xilinx_spi.h> 20#include <linux/spi/altera.h> 21#include <net/devlink.h> 22#include <linux/i2c.h> 23#include <linux/mtd/mtd.h> 24#include <linux/nvmem-consumer.h> 25#include <linux/crc16.h> 26#include <linux/dpll.h> 27 28#define PCI_DEVICE_ID_META_TIMECARD 0x0400 29 30#define PCI_VENDOR_ID_CELESTICA 0x18d4 31#define PCI_DEVICE_ID_CELESTICA_TIMECARD 0x1008 32 33#define PCI_VENDOR_ID_OROLIA 0x1ad7 34#define PCI_DEVICE_ID_OROLIA_ARTCARD 0xa000 35 36#define PCI_VENDOR_ID_ADVA 0xad5a 37#define PCI_DEVICE_ID_ADVA_TIMECARD 0x0400 38 39static struct class timecard_class = { 40 .name = "timecard", 41}; 42 43struct ocp_reg { 44 u32 ctrl; 45 u32 status; 46 u32 select; 47 u32 version; 48 u32 time_ns; 49 u32 time_sec; 50 u32 __pad0[2]; 51 u32 adjust_ns; 52 u32 adjust_sec; 53 u32 __pad1[2]; 54 u32 offset_ns; 55 u32 offset_window_ns; 56 u32 __pad2[2]; 57 u32 drift_ns; 58 u32 drift_window_ns; 59 u32 __pad3[6]; 60 u32 servo_offset_p; 61 u32 servo_offset_i; 62 u32 servo_drift_p; 63 u32 servo_drift_i; 64 u32 status_offset; 65 u32 status_drift; 66}; 67 68struct ptp_ocp_servo_conf { 69 u32 servo_offset_p; 70 u32 servo_offset_i; 71 u32 servo_drift_p; 72 u32 servo_drift_i; 73}; 74 75#define OCP_CTRL_ENABLE BIT(0) 76#define OCP_CTRL_ADJUST_TIME BIT(1) 77#define OCP_CTRL_ADJUST_OFFSET BIT(2) 78#define OCP_CTRL_ADJUST_DRIFT BIT(3) 79#define OCP_CTRL_ADJUST_SERVO BIT(8) 80#define OCP_CTRL_READ_TIME_REQ BIT(30) 81#define OCP_CTRL_READ_TIME_DONE BIT(31) 82 83#define OCP_STATUS_IN_SYNC BIT(0) 84#define OCP_STATUS_IN_HOLDOVER BIT(1) 85 86#define OCP_SELECT_CLK_NONE 0 87#define OCP_SELECT_CLK_REG 0xfe 88 89struct tod_reg { 90 u32 ctrl; 91 u32 status; 92 u32 uart_polarity; 93 u32 version; 94 u32 adj_sec; 95 u32 __pad0[3]; 96 u32 uart_baud; 97 u32 __pad1[3]; 98 u32 utc_status; 99 u32 leap; 100}; 101 102#define TOD_CTRL_PROTOCOL BIT(28) 103#define TOD_CTRL_DISABLE_FMT_A BIT(17) 104#define TOD_CTRL_DISABLE_FMT_B BIT(16) 105#define TOD_CTRL_ENABLE BIT(0) 106#define TOD_CTRL_GNSS_MASK GENMASK(3, 0) 107#define TOD_CTRL_GNSS_SHIFT 24 108 109#define TOD_STATUS_UTC_MASK GENMASK(7, 0) 110#define TOD_STATUS_UTC_VALID BIT(8) 111#define TOD_STATUS_LEAP_ANNOUNCE BIT(12) 112#define TOD_STATUS_LEAP_VALID BIT(16) 113 114struct ts_reg { 115 u32 enable; 116 u32 error; 117 u32 polarity; 118 u32 version; 119 u32 __pad0[4]; 120 u32 cable_delay; 121 u32 __pad1[3]; 122 u32 intr; 123 u32 intr_mask; 124 u32 event_count; 125 u32 __pad2[1]; 126 u32 ts_count; 127 u32 time_ns; 128 u32 time_sec; 129 u32 data_width; 130 u32 data; 131}; 132 133struct pps_reg { 134 u32 ctrl; 135 u32 status; 136 u32 __pad0[6]; 137 u32 cable_delay; 138}; 139 140#define PPS_STATUS_FILTER_ERR BIT(0) 141#define PPS_STATUS_SUPERV_ERR BIT(1) 142 143struct img_reg { 144 u32 version; 145}; 146 147struct gpio_reg { 148 u32 gpio1; 149 u32 __pad0; 150 u32 gpio2; 151 u32 __pad1; 152}; 153 154struct irig_master_reg { 155 u32 ctrl; 156 u32 status; 157 u32 __pad0; 158 u32 version; 159 u32 adj_sec; 160 u32 mode_ctrl; 161}; 162 163#define IRIG_M_CTRL_ENABLE BIT(0) 164 165struct irig_slave_reg { 166 u32 ctrl; 167 u32 status; 168 u32 __pad0; 169 u32 version; 170 u32 adj_sec; 171 u32 mode_ctrl; 172}; 173 174#define IRIG_S_CTRL_ENABLE BIT(0) 175 176struct dcf_master_reg { 177 u32 ctrl; 178 u32 status; 179 u32 __pad0; 180 u32 version; 181 u32 adj_sec; 182}; 183 184#define DCF_M_CTRL_ENABLE BIT(0) 185 186struct dcf_slave_reg { 187 u32 ctrl; 188 u32 status; 189 u32 __pad0; 190 u32 version; 191 u32 adj_sec; 192}; 193 194#define DCF_S_CTRL_ENABLE BIT(0) 195 196struct signal_reg { 197 u32 enable; 198 u32 status; 199 u32 polarity; 200 u32 version; 201 u32 __pad0[4]; 202 u32 cable_delay; 203 u32 __pad1[3]; 204 u32 intr; 205 u32 intr_mask; 206 u32 __pad2[2]; 207 u32 start_ns; 208 u32 start_sec; 209 u32 pulse_ns; 210 u32 pulse_sec; 211 u32 period_ns; 212 u32 period_sec; 213 u32 repeat_count; 214}; 215 216struct frequency_reg { 217 u32 ctrl; 218 u32 status; 219}; 220 221struct board_config_reg { 222 u32 mro50_serial_activate; 223}; 224 225#define FREQ_STATUS_VALID BIT(31) 226#define FREQ_STATUS_ERROR BIT(30) 227#define FREQ_STATUS_OVERRUN BIT(29) 228#define FREQ_STATUS_MASK GENMASK(23, 0) 229 230struct ptp_ocp_flash_info { 231 const char *name; 232 int pci_offset; 233 int data_size; 234 void *data; 235}; 236 237struct ptp_ocp_firmware_header { 238 char magic[4]; 239 __be16 pci_vendor_id; 240 __be16 pci_device_id; 241 __be32 image_size; 242 __be16 hw_revision; 243 __be16 crc; 244}; 245 246#define OCP_FIRMWARE_MAGIC_HEADER "OCPC" 247 248struct ptp_ocp_i2c_info { 249 const char *name; 250 unsigned long fixed_rate; 251 size_t data_size; 252 void *data; 253}; 254 255struct ptp_ocp_ext_info { 256 int index; 257 irqreturn_t (*irq_fcn)(int irq, void *priv); 258 int (*enable)(void *priv, u32 req, bool enable); 259}; 260 261struct ptp_ocp_ext_src { 262 void __iomem *mem; 263 struct ptp_ocp *bp; 264 struct ptp_ocp_ext_info *info; 265 int irq_vec; 266}; 267 268enum ptp_ocp_sma_mode { 269 SMA_MODE_IN, 270 SMA_MODE_OUT, 271}; 272 273static struct dpll_pin_frequency ptp_ocp_sma_freq[] = { 274 DPLL_PIN_FREQUENCY_1PPS, 275 DPLL_PIN_FREQUENCY_10MHZ, 276 DPLL_PIN_FREQUENCY_IRIG_B, 277 DPLL_PIN_FREQUENCY_DCF77, 278}; 279 280struct ptp_ocp_sma_connector { 281 enum ptp_ocp_sma_mode mode; 282 bool fixed_fcn; 283 bool fixed_dir; 284 bool disabled; 285 u8 default_fcn; 286 struct dpll_pin *dpll_pin; 287 struct dpll_pin_properties dpll_prop; 288}; 289 290struct ocp_attr_group { 291 u64 cap; 292 const struct attribute_group *group; 293}; 294 295#define OCP_CAP_BASIC BIT(0) 296#define OCP_CAP_SIGNAL BIT(1) 297#define OCP_CAP_FREQ BIT(2) 298 299struct ptp_ocp_signal { 300 ktime_t period; 301 ktime_t pulse; 302 ktime_t phase; 303 ktime_t start; 304 int duty; 305 bool polarity; 306 bool running; 307}; 308 309struct ptp_ocp_serial_port { 310 int line; 311 int baud; 312}; 313 314#define OCP_BOARD_ID_LEN 13 315#define OCP_SERIAL_LEN 6 316#define OCP_SMA_NUM 4 317#define OCP_SIGNAL_NUM 4 318#define OCP_FREQ_NUM 4 319 320enum { 321 PORT_GNSS, 322 PORT_GNSS2, 323 PORT_MAC, /* miniature atomic clock */ 324 PORT_NMEA, 325 326 __PORT_COUNT, 327}; 328 329struct ptp_ocp { 330 struct pci_dev *pdev; 331 struct device dev; 332 spinlock_t lock; 333 struct ocp_reg __iomem *reg; 334 struct tod_reg __iomem *tod; 335 struct pps_reg __iomem *pps_to_ext; 336 struct pps_reg __iomem *pps_to_clk; 337 struct board_config_reg __iomem *board_config; 338 struct gpio_reg __iomem *pps_select; 339 struct gpio_reg __iomem *sma_map1; 340 struct gpio_reg __iomem *sma_map2; 341 struct irig_master_reg __iomem *irig_out; 342 struct irig_slave_reg __iomem *irig_in; 343 struct dcf_master_reg __iomem *dcf_out; 344 struct dcf_slave_reg __iomem *dcf_in; 345 struct tod_reg __iomem *nmea_out; 346 struct frequency_reg __iomem *freq_in[OCP_FREQ_NUM]; 347 struct ptp_ocp_ext_src *signal_out[OCP_SIGNAL_NUM]; 348 struct ptp_ocp_ext_src *pps; 349 struct ptp_ocp_ext_src *ts0; 350 struct ptp_ocp_ext_src *ts1; 351 struct ptp_ocp_ext_src *ts2; 352 struct ptp_ocp_ext_src *ts3; 353 struct ptp_ocp_ext_src *ts4; 354 struct ocp_art_gpio_reg __iomem *art_sma; 355 struct img_reg __iomem *image; 356 struct ptp_clock *ptp; 357 struct ptp_clock_info ptp_info; 358 struct platform_device *i2c_ctrl; 359 struct platform_device *spi_flash; 360 struct clk_hw *i2c_clk; 361 struct timer_list watchdog; 362 const struct attribute_group **attr_group; 363 const struct ptp_ocp_eeprom_map *eeprom_map; 364 struct dentry *debug_root; 365 bool sync; 366 time64_t gnss_lost; 367 struct delayed_work sync_work; 368 int id; 369 int n_irqs; 370 struct ptp_ocp_serial_port port[__PORT_COUNT]; 371 bool fw_loader; 372 u8 fw_tag; 373 u16 fw_version; 374 u8 board_id[OCP_BOARD_ID_LEN]; 375 u8 serial[OCP_SERIAL_LEN]; 376 bool has_eeprom_data; 377 u32 pps_req_map; 378 int flash_start; 379 u32 utc_tai_offset; 380 u32 ts_window_adjust; 381 u64 fw_cap; 382 struct ptp_ocp_signal signal[OCP_SIGNAL_NUM]; 383 struct ptp_ocp_sma_connector sma[OCP_SMA_NUM]; 384 const struct ocp_sma_op *sma_op; 385 struct dpll_device *dpll; 386 int signals_nr; 387 int freq_in_nr; 388}; 389 390#define OCP_REQ_TIMESTAMP BIT(0) 391#define OCP_REQ_PPS BIT(1) 392 393struct ocp_resource { 394 unsigned long offset; 395 int size; 396 int irq_vec; 397 int (*setup)(struct ptp_ocp *bp, struct ocp_resource *r); 398 void *extra; 399 unsigned long bp_offset; 400 const char * const name; 401}; 402 403static int ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r); 404static int ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r); 405static int ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r); 406static int ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r); 407static int ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r); 408static int ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r); 409static irqreturn_t ptp_ocp_ts_irq(int irq, void *priv); 410static irqreturn_t ptp_ocp_signal_irq(int irq, void *priv); 411static int ptp_ocp_ts_enable(void *priv, u32 req, bool enable); 412static int ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen, 413 struct ptp_perout_request *req); 414static int ptp_ocp_signal_enable(void *priv, u32 req, bool enable); 415static int ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr); 416 417static int ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r); 418 419static int ptp_ocp_adva_board_init(struct ptp_ocp *bp, struct ocp_resource *r); 420 421static const struct ocp_attr_group fb_timecard_groups[]; 422 423static const struct ocp_attr_group art_timecard_groups[]; 424 425static const struct ocp_attr_group adva_timecard_groups[]; 426 427struct ptp_ocp_eeprom_map { 428 u16 off; 429 u16 len; 430 u32 bp_offset; 431 const void * const tag; 432}; 433 434#define EEPROM_ENTRY(addr, member) \ 435 .off = addr, \ 436 .len = sizeof_field(struct ptp_ocp, member), \ 437 .bp_offset = offsetof(struct ptp_ocp, member) 438 439#define BP_MAP_ENTRY_ADDR(bp, map) ({ \ 440 (void *)((uintptr_t)(bp) + (map)->bp_offset); \ 441}) 442 443static struct ptp_ocp_eeprom_map fb_eeprom_map[] = { 444 { EEPROM_ENTRY(0x43, board_id) }, 445 { EEPROM_ENTRY(0x00, serial), .tag = "mac" }, 446 { } 447}; 448 449static struct ptp_ocp_eeprom_map art_eeprom_map[] = { 450 { EEPROM_ENTRY(0x200 + 0x43, board_id) }, 451 { EEPROM_ENTRY(0x200 + 0x63, serial) }, 452 { } 453}; 454 455#define bp_assign_entry(bp, res, val) ({ \ 456 uintptr_t addr = (uintptr_t)(bp) + (res)->bp_offset; \ 457 *(typeof(val) *)addr = val; \ 458}) 459 460#define OCP_RES_LOCATION(member) \ 461 .name = #member, .bp_offset = offsetof(struct ptp_ocp, member) 462 463#define OCP_MEM_RESOURCE(member) \ 464 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_mem 465 466#define OCP_SERIAL_RESOURCE(member) \ 467 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_serial 468 469#define OCP_I2C_RESOURCE(member) \ 470 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_i2c 471 472#define OCP_SPI_RESOURCE(member) \ 473 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_spi 474 475#define OCP_EXT_RESOURCE(member) \ 476 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_ext 477 478/* This is the MSI vector mapping used. 479 * 0: PPS (TS5) 480 * 1: TS0 481 * 2: TS1 482 * 3: GNSS1 483 * 4: GNSS2 484 * 5: MAC 485 * 6: TS2 486 * 7: I2C controller 487 * 8: HWICAP (notused) 488 * 9: SPI Flash 489 * 10: NMEA 490 * 11: Signal Generator 1 491 * 12: Signal Generator 2 492 * 13: Signal Generator 3 493 * 14: Signal Generator 4 494 * 15: TS3 495 * 16: TS4 496 -- 497 * 8: Orolia TS1 498 * 10: Orolia TS2 499 * 11: Orolia TS0 (GNSS) 500 * 12: Orolia PPS 501 * 14: Orolia TS3 502 * 15: Orolia TS4 503 */ 504 505static struct ocp_resource ocp_fb_resource[] = { 506 { 507 OCP_MEM_RESOURCE(reg), 508 .offset = 0x01000000, .size = 0x10000, 509 }, 510 { 511 OCP_EXT_RESOURCE(ts0), 512 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1, 513 .extra = &(struct ptp_ocp_ext_info) { 514 .index = 0, 515 .irq_fcn = ptp_ocp_ts_irq, 516 .enable = ptp_ocp_ts_enable, 517 }, 518 }, 519 { 520 OCP_EXT_RESOURCE(ts1), 521 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2, 522 .extra = &(struct ptp_ocp_ext_info) { 523 .index = 1, 524 .irq_fcn = ptp_ocp_ts_irq, 525 .enable = ptp_ocp_ts_enable, 526 }, 527 }, 528 { 529 OCP_EXT_RESOURCE(ts2), 530 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6, 531 .extra = &(struct ptp_ocp_ext_info) { 532 .index = 2, 533 .irq_fcn = ptp_ocp_ts_irq, 534 .enable = ptp_ocp_ts_enable, 535 }, 536 }, 537 { 538 OCP_EXT_RESOURCE(ts3), 539 .offset = 0x01110000, .size = 0x10000, .irq_vec = 15, 540 .extra = &(struct ptp_ocp_ext_info) { 541 .index = 3, 542 .irq_fcn = ptp_ocp_ts_irq, 543 .enable = ptp_ocp_ts_enable, 544 }, 545 }, 546 { 547 OCP_EXT_RESOURCE(ts4), 548 .offset = 0x01120000, .size = 0x10000, .irq_vec = 16, 549 .extra = &(struct ptp_ocp_ext_info) { 550 .index = 4, 551 .irq_fcn = ptp_ocp_ts_irq, 552 .enable = ptp_ocp_ts_enable, 553 }, 554 }, 555 /* Timestamp for PHC and/or PPS generator */ 556 { 557 OCP_EXT_RESOURCE(pps), 558 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0, 559 .extra = &(struct ptp_ocp_ext_info) { 560 .index = 5, 561 .irq_fcn = ptp_ocp_ts_irq, 562 .enable = ptp_ocp_ts_enable, 563 }, 564 }, 565 { 566 OCP_EXT_RESOURCE(signal_out[0]), 567 .offset = 0x010D0000, .size = 0x10000, .irq_vec = 11, 568 .extra = &(struct ptp_ocp_ext_info) { 569 .index = 1, 570 .irq_fcn = ptp_ocp_signal_irq, 571 .enable = ptp_ocp_signal_enable, 572 }, 573 }, 574 { 575 OCP_EXT_RESOURCE(signal_out[1]), 576 .offset = 0x010E0000, .size = 0x10000, .irq_vec = 12, 577 .extra = &(struct ptp_ocp_ext_info) { 578 .index = 2, 579 .irq_fcn = ptp_ocp_signal_irq, 580 .enable = ptp_ocp_signal_enable, 581 }, 582 }, 583 { 584 OCP_EXT_RESOURCE(signal_out[2]), 585 .offset = 0x010F0000, .size = 0x10000, .irq_vec = 13, 586 .extra = &(struct ptp_ocp_ext_info) { 587 .index = 3, 588 .irq_fcn = ptp_ocp_signal_irq, 589 .enable = ptp_ocp_signal_enable, 590 }, 591 }, 592 { 593 OCP_EXT_RESOURCE(signal_out[3]), 594 .offset = 0x01100000, .size = 0x10000, .irq_vec = 14, 595 .extra = &(struct ptp_ocp_ext_info) { 596 .index = 4, 597 .irq_fcn = ptp_ocp_signal_irq, 598 .enable = ptp_ocp_signal_enable, 599 }, 600 }, 601 { 602 OCP_MEM_RESOURCE(pps_to_ext), 603 .offset = 0x01030000, .size = 0x10000, 604 }, 605 { 606 OCP_MEM_RESOURCE(pps_to_clk), 607 .offset = 0x01040000, .size = 0x10000, 608 }, 609 { 610 OCP_MEM_RESOURCE(tod), 611 .offset = 0x01050000, .size = 0x10000, 612 }, 613 { 614 OCP_MEM_RESOURCE(irig_in), 615 .offset = 0x01070000, .size = 0x10000, 616 }, 617 { 618 OCP_MEM_RESOURCE(irig_out), 619 .offset = 0x01080000, .size = 0x10000, 620 }, 621 { 622 OCP_MEM_RESOURCE(dcf_in), 623 .offset = 0x01090000, .size = 0x10000, 624 }, 625 { 626 OCP_MEM_RESOURCE(dcf_out), 627 .offset = 0x010A0000, .size = 0x10000, 628 }, 629 { 630 OCP_MEM_RESOURCE(nmea_out), 631 .offset = 0x010B0000, .size = 0x10000, 632 }, 633 { 634 OCP_MEM_RESOURCE(image), 635 .offset = 0x00020000, .size = 0x1000, 636 }, 637 { 638 OCP_MEM_RESOURCE(pps_select), 639 .offset = 0x00130000, .size = 0x1000, 640 }, 641 { 642 OCP_MEM_RESOURCE(sma_map1), 643 .offset = 0x00140000, .size = 0x1000, 644 }, 645 { 646 OCP_MEM_RESOURCE(sma_map2), 647 .offset = 0x00220000, .size = 0x1000, 648 }, 649 { 650 OCP_I2C_RESOURCE(i2c_ctrl), 651 .offset = 0x00150000, .size = 0x10000, .irq_vec = 7, 652 .extra = &(struct ptp_ocp_i2c_info) { 653 .name = "xiic-i2c", 654 .fixed_rate = 50000000, 655 .data_size = sizeof(struct xiic_i2c_platform_data), 656 .data = &(struct xiic_i2c_platform_data) { 657 .num_devices = 2, 658 .devices = (struct i2c_board_info[]) { 659 { I2C_BOARD_INFO("24c02", 0x50) }, 660 { I2C_BOARD_INFO("24mac402", 0x58), 661 .platform_data = "mac" }, 662 }, 663 }, 664 }, 665 }, 666 { 667 OCP_SERIAL_RESOURCE(port[PORT_GNSS]), 668 .offset = 0x00160000 + 0x1000, .irq_vec = 3, 669 .extra = &(struct ptp_ocp_serial_port) { 670 .baud = 115200, 671 }, 672 }, 673 { 674 OCP_SERIAL_RESOURCE(port[PORT_GNSS2]), 675 .offset = 0x00170000 + 0x1000, .irq_vec = 4, 676 .extra = &(struct ptp_ocp_serial_port) { 677 .baud = 115200, 678 }, 679 }, 680 { 681 OCP_SERIAL_RESOURCE(port[PORT_MAC]), 682 .offset = 0x00180000 + 0x1000, .irq_vec = 5, 683 .extra = &(struct ptp_ocp_serial_port) { 684 .baud = 57600, 685 }, 686 }, 687 { 688 OCP_SERIAL_RESOURCE(port[PORT_NMEA]), 689 .offset = 0x00190000 + 0x1000, .irq_vec = 10, 690 }, 691 { 692 OCP_SPI_RESOURCE(spi_flash), 693 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9, 694 .extra = &(struct ptp_ocp_flash_info) { 695 .name = "xilinx_spi", .pci_offset = 0, 696 .data_size = sizeof(struct xspi_platform_data), 697 .data = &(struct xspi_platform_data) { 698 .num_chipselect = 1, 699 .bits_per_word = 8, 700 .num_devices = 1, 701 .force_irq = true, 702 .devices = &(struct spi_board_info) { 703 .modalias = "spi-nor", 704 }, 705 }, 706 }, 707 }, 708 { 709 OCP_MEM_RESOURCE(freq_in[0]), 710 .offset = 0x01200000, .size = 0x10000, 711 }, 712 { 713 OCP_MEM_RESOURCE(freq_in[1]), 714 .offset = 0x01210000, .size = 0x10000, 715 }, 716 { 717 OCP_MEM_RESOURCE(freq_in[2]), 718 .offset = 0x01220000, .size = 0x10000, 719 }, 720 { 721 OCP_MEM_RESOURCE(freq_in[3]), 722 .offset = 0x01230000, .size = 0x10000, 723 }, 724 { 725 .setup = ptp_ocp_fb_board_init, 726 .extra = &(struct ptp_ocp_servo_conf) { 727 .servo_offset_p = 0x2000, 728 .servo_offset_i = 0x1000, 729 .servo_drift_p = 0, 730 .servo_drift_i = 0, 731 }, 732 }, 733 { } 734}; 735 736#define OCP_ART_CONFIG_SIZE 144 737#define OCP_ART_TEMP_TABLE_SIZE 368 738 739struct ocp_art_gpio_reg { 740 struct { 741 u32 gpio; 742 u32 __pad[3]; 743 } map[4]; 744}; 745 746static struct ocp_resource ocp_art_resource[] = { 747 { 748 OCP_MEM_RESOURCE(reg), 749 .offset = 0x01000000, .size = 0x10000, 750 }, 751 { 752 OCP_SERIAL_RESOURCE(port[PORT_GNSS]), 753 .offset = 0x00160000 + 0x1000, .irq_vec = 3, 754 .extra = &(struct ptp_ocp_serial_port) { 755 .baud = 115200, 756 }, 757 }, 758 { 759 OCP_MEM_RESOURCE(art_sma), 760 .offset = 0x003C0000, .size = 0x1000, 761 }, 762 /* Timestamp associated with GNSS1 receiver PPS */ 763 { 764 OCP_EXT_RESOURCE(ts0), 765 .offset = 0x360000, .size = 0x20, .irq_vec = 12, 766 .extra = &(struct ptp_ocp_ext_info) { 767 .index = 0, 768 .irq_fcn = ptp_ocp_ts_irq, 769 .enable = ptp_ocp_ts_enable, 770 }, 771 }, 772 { 773 OCP_EXT_RESOURCE(ts1), 774 .offset = 0x380000, .size = 0x20, .irq_vec = 8, 775 .extra = &(struct ptp_ocp_ext_info) { 776 .index = 1, 777 .irq_fcn = ptp_ocp_ts_irq, 778 .enable = ptp_ocp_ts_enable, 779 }, 780 }, 781 { 782 OCP_EXT_RESOURCE(ts2), 783 .offset = 0x390000, .size = 0x20, .irq_vec = 10, 784 .extra = &(struct ptp_ocp_ext_info) { 785 .index = 2, 786 .irq_fcn = ptp_ocp_ts_irq, 787 .enable = ptp_ocp_ts_enable, 788 }, 789 }, 790 { 791 OCP_EXT_RESOURCE(ts3), 792 .offset = 0x3A0000, .size = 0x20, .irq_vec = 14, 793 .extra = &(struct ptp_ocp_ext_info) { 794 .index = 3, 795 .irq_fcn = ptp_ocp_ts_irq, 796 .enable = ptp_ocp_ts_enable, 797 }, 798 }, 799 { 800 OCP_EXT_RESOURCE(ts4), 801 .offset = 0x3B0000, .size = 0x20, .irq_vec = 15, 802 .extra = &(struct ptp_ocp_ext_info) { 803 .index = 4, 804 .irq_fcn = ptp_ocp_ts_irq, 805 .enable = ptp_ocp_ts_enable, 806 }, 807 }, 808 /* Timestamp associated with Internal PPS of the card */ 809 { 810 OCP_EXT_RESOURCE(pps), 811 .offset = 0x00330000, .size = 0x20, .irq_vec = 11, 812 .extra = &(struct ptp_ocp_ext_info) { 813 .index = 5, 814 .irq_fcn = ptp_ocp_ts_irq, 815 .enable = ptp_ocp_ts_enable, 816 }, 817 }, 818 { 819 OCP_SPI_RESOURCE(spi_flash), 820 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9, 821 .extra = &(struct ptp_ocp_flash_info) { 822 .name = "spi_altera", .pci_offset = 0, 823 .data_size = sizeof(struct altera_spi_platform_data), 824 .data = &(struct altera_spi_platform_data) { 825 .num_chipselect = 1, 826 .num_devices = 1, 827 .devices = &(struct spi_board_info) { 828 .modalias = "spi-nor", 829 }, 830 }, 831 }, 832 }, 833 { 834 OCP_I2C_RESOURCE(i2c_ctrl), 835 .offset = 0x350000, .size = 0x100, .irq_vec = 4, 836 .extra = &(struct ptp_ocp_i2c_info) { 837 .name = "ocores-i2c", 838 .fixed_rate = 400000, 839 .data_size = sizeof(struct ocores_i2c_platform_data), 840 .data = &(struct ocores_i2c_platform_data) { 841 .clock_khz = 125000, 842 .bus_khz = 400, 843 .num_devices = 1, 844 .devices = &(struct i2c_board_info) { 845 I2C_BOARD_INFO("24c08", 0x50), 846 }, 847 }, 848 }, 849 }, 850 { 851 OCP_SERIAL_RESOURCE(port[PORT_MAC]), 852 .offset = 0x00190000, .irq_vec = 7, 853 .extra = &(struct ptp_ocp_serial_port) { 854 .baud = 9600, 855 }, 856 }, 857 { 858 OCP_MEM_RESOURCE(board_config), 859 .offset = 0x210000, .size = 0x1000, 860 }, 861 { 862 .setup = ptp_ocp_art_board_init, 863 .extra = &(struct ptp_ocp_servo_conf) { 864 .servo_offset_p = 0x2000, 865 .servo_offset_i = 0x1000, 866 .servo_drift_p = 0, 867 .servo_drift_i = 0, 868 }, 869 }, 870 { } 871}; 872 873static struct ocp_resource ocp_adva_resource[] = { 874 { 875 OCP_MEM_RESOURCE(reg), 876 .offset = 0x01000000, .size = 0x10000, 877 }, 878 { 879 OCP_EXT_RESOURCE(ts0), 880 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1, 881 .extra = &(struct ptp_ocp_ext_info) { 882 .index = 0, 883 .irq_fcn = ptp_ocp_ts_irq, 884 .enable = ptp_ocp_ts_enable, 885 }, 886 }, 887 { 888 OCP_EXT_RESOURCE(ts1), 889 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2, 890 .extra = &(struct ptp_ocp_ext_info) { 891 .index = 1, 892 .irq_fcn = ptp_ocp_ts_irq, 893 .enable = ptp_ocp_ts_enable, 894 }, 895 }, 896 { 897 OCP_EXT_RESOURCE(ts2), 898 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6, 899 .extra = &(struct ptp_ocp_ext_info) { 900 .index = 2, 901 .irq_fcn = ptp_ocp_ts_irq, 902 .enable = ptp_ocp_ts_enable, 903 }, 904 }, 905 /* Timestamp for PHC and/or PPS generator */ 906 { 907 OCP_EXT_RESOURCE(pps), 908 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0, 909 .extra = &(struct ptp_ocp_ext_info) { 910 .index = 5, 911 .irq_fcn = ptp_ocp_ts_irq, 912 .enable = ptp_ocp_ts_enable, 913 }, 914 }, 915 { 916 OCP_EXT_RESOURCE(signal_out[0]), 917 .offset = 0x010D0000, .size = 0x10000, .irq_vec = 11, 918 .extra = &(struct ptp_ocp_ext_info) { 919 .index = 1, 920 .irq_fcn = ptp_ocp_signal_irq, 921 .enable = ptp_ocp_signal_enable, 922 }, 923 }, 924 { 925 OCP_EXT_RESOURCE(signal_out[1]), 926 .offset = 0x010E0000, .size = 0x10000, .irq_vec = 12, 927 .extra = &(struct ptp_ocp_ext_info) { 928 .index = 2, 929 .irq_fcn = ptp_ocp_signal_irq, 930 .enable = ptp_ocp_signal_enable, 931 }, 932 }, 933 { 934 OCP_MEM_RESOURCE(pps_to_ext), 935 .offset = 0x01030000, .size = 0x10000, 936 }, 937 { 938 OCP_MEM_RESOURCE(pps_to_clk), 939 .offset = 0x01040000, .size = 0x10000, 940 }, 941 { 942 OCP_MEM_RESOURCE(tod), 943 .offset = 0x01050000, .size = 0x10000, 944 }, 945 { 946 OCP_MEM_RESOURCE(image), 947 .offset = 0x00020000, .size = 0x1000, 948 }, 949 { 950 OCP_MEM_RESOURCE(pps_select), 951 .offset = 0x00130000, .size = 0x1000, 952 }, 953 { 954 OCP_MEM_RESOURCE(sma_map1), 955 .offset = 0x00140000, .size = 0x1000, 956 }, 957 { 958 OCP_MEM_RESOURCE(sma_map2), 959 .offset = 0x00220000, .size = 0x1000, 960 }, 961 { 962 OCP_SERIAL_RESOURCE(port[PORT_GNSS]), 963 .offset = 0x00160000 + 0x1000, .irq_vec = 3, 964 .extra = &(struct ptp_ocp_serial_port) { 965 .baud = 9600, 966 }, 967 }, 968 { 969 OCP_SERIAL_RESOURCE(port[PORT_MAC]), 970 .offset = 0x00180000 + 0x1000, .irq_vec = 5, 971 .extra = &(struct ptp_ocp_serial_port) { 972 .baud = 115200, 973 }, 974 }, 975 { 976 OCP_MEM_RESOURCE(freq_in[0]), 977 .offset = 0x01200000, .size = 0x10000, 978 }, 979 { 980 OCP_MEM_RESOURCE(freq_in[1]), 981 .offset = 0x01210000, .size = 0x10000, 982 }, 983 { 984 OCP_SPI_RESOURCE(spi_flash), 985 .offset = 0x00310400, .size = 0x10000, .irq_vec = 9, 986 .extra = &(struct ptp_ocp_flash_info) { 987 .name = "spi_altera", .pci_offset = 0, 988 .data_size = sizeof(struct altera_spi_platform_data), 989 .data = &(struct altera_spi_platform_data) { 990 .num_chipselect = 1, 991 .num_devices = 1, 992 .devices = &(struct spi_board_info) { 993 .modalias = "spi-nor", 994 }, 995 }, 996 }, 997 }, 998 { 999 OCP_I2C_RESOURCE(i2c_ctrl), 1000 .offset = 0x150000, .size = 0x100, .irq_vec = 7, 1001 .extra = &(struct ptp_ocp_i2c_info) { 1002 .name = "ocores-i2c", 1003 .fixed_rate = 50000000, 1004 .data_size = sizeof(struct ocores_i2c_platform_data), 1005 .data = &(struct ocores_i2c_platform_data) { 1006 .clock_khz = 50000, 1007 .bus_khz = 100, 1008 .reg_io_width = 4, // 32-bit/4-byte 1009 .reg_shift = 2, // 32-bit addressing 1010 .num_devices = 2, 1011 .devices = (struct i2c_board_info[]) { 1012 { I2C_BOARD_INFO("24c02", 0x50) }, 1013 { I2C_BOARD_INFO("24mac402", 0x58), 1014 .platform_data = "mac" }, 1015 }, 1016 }, 1017 }, 1018 }, 1019 { 1020 .setup = ptp_ocp_adva_board_init, 1021 .extra = &(struct ptp_ocp_servo_conf) { 1022 .servo_offset_p = 0xc000, 1023 .servo_offset_i = 0x1000, 1024 .servo_drift_p = 0, 1025 .servo_drift_i = 0, 1026 }, 1027 }, 1028 { } 1029}; 1030 1031static const struct pci_device_id ptp_ocp_pcidev_id[] = { 1032 { PCI_DEVICE_DATA(META, TIMECARD, &ocp_fb_resource) }, 1033 { PCI_DEVICE_DATA(CELESTICA, TIMECARD, &ocp_fb_resource) }, 1034 { PCI_DEVICE_DATA(OROLIA, ARTCARD, &ocp_art_resource) }, 1035 { PCI_DEVICE_DATA(ADVA, TIMECARD, &ocp_adva_resource) }, 1036 { } 1037}; 1038MODULE_DEVICE_TABLE(pci, ptp_ocp_pcidev_id); 1039 1040static DEFINE_MUTEX(ptp_ocp_lock); 1041static DEFINE_IDR(ptp_ocp_idr); 1042 1043struct ocp_selector { 1044 const char *name; 1045 int value; 1046 u64 frequency; 1047}; 1048 1049static const struct ocp_selector ptp_ocp_clock[] = { 1050 { .name = "NONE", .value = 0 }, 1051 { .name = "TOD", .value = 1 }, 1052 { .name = "IRIG", .value = 2 }, 1053 { .name = "PPS", .value = 3 }, 1054 { .name = "PTP", .value = 4 }, 1055 { .name = "RTC", .value = 5 }, 1056 { .name = "DCF", .value = 6 }, 1057 { .name = "REGS", .value = 0xfe }, 1058 { .name = "EXT", .value = 0xff }, 1059 { } 1060}; 1061 1062#define SMA_DISABLE BIT(16) 1063#define SMA_ENABLE BIT(15) 1064#define SMA_SELECT_MASK GENMASK(14, 0) 1065 1066static const struct ocp_selector ptp_ocp_sma_in[] = { 1067 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000 }, 1068 { .name = "PPS1", .value = 0x0001, .frequency = 1 }, 1069 { .name = "PPS2", .value = 0x0002, .frequency = 1 }, 1070 { .name = "TS1", .value = 0x0004, .frequency = 0 }, 1071 { .name = "TS2", .value = 0x0008, .frequency = 0 }, 1072 { .name = "IRIG", .value = 0x0010, .frequency = 10000 }, 1073 { .name = "DCF", .value = 0x0020, .frequency = 77500 }, 1074 { .name = "TS3", .value = 0x0040, .frequency = 0 }, 1075 { .name = "TS4", .value = 0x0080, .frequency = 0 }, 1076 { .name = "FREQ1", .value = 0x0100, .frequency = 0 }, 1077 { .name = "FREQ2", .value = 0x0200, .frequency = 0 }, 1078 { .name = "FREQ3", .value = 0x0400, .frequency = 0 }, 1079 { .name = "FREQ4", .value = 0x0800, .frequency = 0 }, 1080 { .name = "None", .value = SMA_DISABLE, .frequency = 0 }, 1081 { } 1082}; 1083 1084static const struct ocp_selector ptp_ocp_sma_out[] = { 1085 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000 }, 1086 { .name = "PHC", .value = 0x0001, .frequency = 1 }, 1087 { .name = "MAC", .value = 0x0002, .frequency = 1 }, 1088 { .name = "GNSS1", .value = 0x0004, .frequency = 1 }, 1089 { .name = "GNSS2", .value = 0x0008, .frequency = 1 }, 1090 { .name = "IRIG", .value = 0x0010, .frequency = 10000 }, 1091 { .name = "DCF", .value = 0x0020, .frequency = 77000 }, 1092 { .name = "GEN1", .value = 0x0040 }, 1093 { .name = "GEN2", .value = 0x0080 }, 1094 { .name = "GEN3", .value = 0x0100 }, 1095 { .name = "GEN4", .value = 0x0200 }, 1096 { .name = "GND", .value = 0x2000 }, 1097 { .name = "VCC", .value = 0x4000 }, 1098 { } 1099}; 1100 1101static const struct ocp_selector ptp_ocp_art_sma_in[] = { 1102 { .name = "PPS1", .value = 0x0001, .frequency = 1 }, 1103 { .name = "10Mhz", .value = 0x0008, .frequency = 1000000 }, 1104 { } 1105}; 1106 1107static const struct ocp_selector ptp_ocp_art_sma_out[] = { 1108 { .name = "PHC", .value = 0x0002, .frequency = 1 }, 1109 { .name = "GNSS", .value = 0x0004, .frequency = 1 }, 1110 { .name = "10Mhz", .value = 0x0010, .frequency = 10000000 }, 1111 { } 1112}; 1113 1114static const struct ocp_selector ptp_ocp_adva_sma_in[] = { 1115 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000}, 1116 { .name = "PPS1", .value = 0x0001, .frequency = 1 }, 1117 { .name = "PPS2", .value = 0x0002, .frequency = 1 }, 1118 { .name = "TS1", .value = 0x0004, .frequency = 0 }, 1119 { .name = "TS2", .value = 0x0008, .frequency = 0 }, 1120 { .name = "FREQ1", .value = 0x0100, .frequency = 0 }, 1121 { .name = "FREQ2", .value = 0x0200, .frequency = 0 }, 1122 { .name = "None", .value = SMA_DISABLE, .frequency = 0 }, 1123 { } 1124}; 1125 1126static const struct ocp_selector ptp_ocp_adva_sma_out[] = { 1127 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000}, 1128 { .name = "PHC", .value = 0x0001, .frequency = 1 }, 1129 { .name = "MAC", .value = 0x0002, .frequency = 1 }, 1130 { .name = "GNSS1", .value = 0x0004, .frequency = 1 }, 1131 { .name = "GEN1", .value = 0x0040 }, 1132 { .name = "GEN2", .value = 0x0080 }, 1133 { .name = "GND", .value = 0x2000 }, 1134 { .name = "VCC", .value = 0x4000 }, 1135 { } 1136}; 1137 1138struct ocp_sma_op { 1139 const struct ocp_selector *tbl[2]; 1140 void (*init)(struct ptp_ocp *bp); 1141 u32 (*get)(struct ptp_ocp *bp, int sma_nr); 1142 int (*set_inputs)(struct ptp_ocp *bp, int sma_nr, u32 val); 1143 int (*set_output)(struct ptp_ocp *bp, int sma_nr, u32 val); 1144}; 1145 1146static void 1147ptp_ocp_sma_init(struct ptp_ocp *bp) 1148{ 1149 return bp->sma_op->init(bp); 1150} 1151 1152static u32 1153ptp_ocp_sma_get(struct ptp_ocp *bp, int sma_nr) 1154{ 1155 return bp->sma_op->get(bp, sma_nr); 1156} 1157 1158static int 1159ptp_ocp_sma_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val) 1160{ 1161 return bp->sma_op->set_inputs(bp, sma_nr, val); 1162} 1163 1164static int 1165ptp_ocp_sma_set_output(struct ptp_ocp *bp, int sma_nr, u32 val) 1166{ 1167 return bp->sma_op->set_output(bp, sma_nr, val); 1168} 1169 1170static const char * 1171ptp_ocp_select_name_from_val(const struct ocp_selector *tbl, int val) 1172{ 1173 int i; 1174 1175 for (i = 0; tbl[i].name; i++) 1176 if (tbl[i].value == val) 1177 return tbl[i].name; 1178 return NULL; 1179} 1180 1181static int 1182ptp_ocp_select_val_from_name(const struct ocp_selector *tbl, const char *name) 1183{ 1184 const char *select; 1185 int i; 1186 1187 for (i = 0; tbl[i].name; i++) { 1188 select = tbl[i].name; 1189 if (!strncasecmp(name, select, strlen(select))) 1190 return tbl[i].value; 1191 } 1192 return -EINVAL; 1193} 1194 1195static ssize_t 1196ptp_ocp_select_table_show(const struct ocp_selector *tbl, char *buf) 1197{ 1198 ssize_t count; 1199 int i; 1200 1201 count = 0; 1202 for (i = 0; tbl[i].name; i++) 1203 count += sysfs_emit_at(buf, count, "%s ", tbl[i].name); 1204 if (count) 1205 count--; 1206 count += sysfs_emit_at(buf, count, "\n"); 1207 return count; 1208} 1209 1210static int 1211__ptp_ocp_gettime_locked(struct ptp_ocp *bp, struct timespec64 *ts, 1212 struct ptp_system_timestamp *sts) 1213{ 1214 u32 ctrl, time_sec, time_ns; 1215 int i; 1216 1217 ptp_read_system_prets(sts); 1218 1219 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE; 1220 iowrite32(ctrl, &bp->reg->ctrl); 1221 1222 for (i = 0; i < 100; i++) { 1223 ctrl = ioread32(&bp->reg->ctrl); 1224 if (ctrl & OCP_CTRL_READ_TIME_DONE) 1225 break; 1226 } 1227 ptp_read_system_postts(sts); 1228 1229 if (sts && bp->ts_window_adjust) { 1230 s64 ns = timespec64_to_ns(&sts->post_ts); 1231 1232 sts->post_ts = ns_to_timespec64(ns - bp->ts_window_adjust); 1233 } 1234 1235 time_ns = ioread32(&bp->reg->time_ns); 1236 time_sec = ioread32(&bp->reg->time_sec); 1237 1238 ts->tv_sec = time_sec; 1239 ts->tv_nsec = time_ns; 1240 1241 return ctrl & OCP_CTRL_READ_TIME_DONE ? 0 : -ETIMEDOUT; 1242} 1243 1244static int 1245ptp_ocp_gettimex(struct ptp_clock_info *ptp_info, struct timespec64 *ts, 1246 struct ptp_system_timestamp *sts) 1247{ 1248 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info); 1249 unsigned long flags; 1250 int err; 1251 1252 spin_lock_irqsave(&bp->lock, flags); 1253 err = __ptp_ocp_gettime_locked(bp, ts, sts); 1254 spin_unlock_irqrestore(&bp->lock, flags); 1255 1256 return err; 1257} 1258 1259static void 1260__ptp_ocp_settime_locked(struct ptp_ocp *bp, const struct timespec64 *ts) 1261{ 1262 u32 ctrl, time_sec, time_ns; 1263 u32 select; 1264 1265 time_ns = ts->tv_nsec; 1266 time_sec = ts->tv_sec; 1267 1268 select = ioread32(&bp->reg->select); 1269 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select); 1270 1271 iowrite32(time_ns, &bp->reg->adjust_ns); 1272 iowrite32(time_sec, &bp->reg->adjust_sec); 1273 1274 ctrl = OCP_CTRL_ADJUST_TIME | OCP_CTRL_ENABLE; 1275 iowrite32(ctrl, &bp->reg->ctrl); 1276 1277 /* restore clock selection */ 1278 iowrite32(select >> 16, &bp->reg->select); 1279} 1280 1281static int 1282ptp_ocp_settime(struct ptp_clock_info *ptp_info, const struct timespec64 *ts) 1283{ 1284 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info); 1285 unsigned long flags; 1286 1287 spin_lock_irqsave(&bp->lock, flags); 1288 __ptp_ocp_settime_locked(bp, ts); 1289 spin_unlock_irqrestore(&bp->lock, flags); 1290 1291 return 0; 1292} 1293 1294static void 1295__ptp_ocp_adjtime_locked(struct ptp_ocp *bp, u32 adj_val) 1296{ 1297 u32 select, ctrl; 1298 1299 select = ioread32(&bp->reg->select); 1300 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select); 1301 1302 iowrite32(adj_val, &bp->reg->offset_ns); 1303 iowrite32(NSEC_PER_SEC, &bp->reg->offset_window_ns); 1304 1305 ctrl = OCP_CTRL_ADJUST_OFFSET | OCP_CTRL_ENABLE; 1306 iowrite32(ctrl, &bp->reg->ctrl); 1307 1308 /* restore clock selection */ 1309 iowrite32(select >> 16, &bp->reg->select); 1310} 1311 1312static void 1313ptp_ocp_adjtime_coarse(struct ptp_ocp *bp, s64 delta_ns) 1314{ 1315 struct timespec64 ts; 1316 unsigned long flags; 1317 int err; 1318 1319 spin_lock_irqsave(&bp->lock, flags); 1320 err = __ptp_ocp_gettime_locked(bp, &ts, NULL); 1321 if (likely(!err)) { 1322 set_normalized_timespec64(&ts, ts.tv_sec, 1323 ts.tv_nsec + delta_ns); 1324 __ptp_ocp_settime_locked(bp, &ts); 1325 } 1326 spin_unlock_irqrestore(&bp->lock, flags); 1327} 1328 1329static int 1330ptp_ocp_adjtime(struct ptp_clock_info *ptp_info, s64 delta_ns) 1331{ 1332 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info); 1333 unsigned long flags; 1334 u32 adj_ns, sign; 1335 1336 if (delta_ns > NSEC_PER_SEC || -delta_ns > NSEC_PER_SEC) { 1337 ptp_ocp_adjtime_coarse(bp, delta_ns); 1338 return 0; 1339 } 1340 1341 sign = delta_ns < 0 ? BIT(31) : 0; 1342 adj_ns = sign ? -delta_ns : delta_ns; 1343 1344 spin_lock_irqsave(&bp->lock, flags); 1345 __ptp_ocp_adjtime_locked(bp, sign | adj_ns); 1346 spin_unlock_irqrestore(&bp->lock, flags); 1347 1348 return 0; 1349} 1350 1351static int 1352ptp_ocp_null_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm) 1353{ 1354 if (scaled_ppm == 0) 1355 return 0; 1356 1357 return -EOPNOTSUPP; 1358} 1359 1360static s32 1361ptp_ocp_null_getmaxphase(struct ptp_clock_info *ptp_info) 1362{ 1363 return 0; 1364} 1365 1366static int 1367ptp_ocp_null_adjphase(struct ptp_clock_info *ptp_info, s32 phase_ns) 1368{ 1369 return -EOPNOTSUPP; 1370} 1371 1372static int 1373ptp_ocp_enable(struct ptp_clock_info *ptp_info, struct ptp_clock_request *rq, 1374 int on) 1375{ 1376 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info); 1377 struct ptp_ocp_ext_src *ext = NULL; 1378 u32 req; 1379 int err; 1380 1381 switch (rq->type) { 1382 case PTP_CLK_REQ_EXTTS: 1383 req = OCP_REQ_TIMESTAMP; 1384 switch (rq->extts.index) { 1385 case 0: 1386 ext = bp->ts0; 1387 break; 1388 case 1: 1389 ext = bp->ts1; 1390 break; 1391 case 2: 1392 ext = bp->ts2; 1393 break; 1394 case 3: 1395 ext = bp->ts3; 1396 break; 1397 case 4: 1398 ext = bp->ts4; 1399 break; 1400 case 5: 1401 ext = bp->pps; 1402 break; 1403 } 1404 break; 1405 case PTP_CLK_REQ_PPS: 1406 req = OCP_REQ_PPS; 1407 ext = bp->pps; 1408 break; 1409 case PTP_CLK_REQ_PEROUT: 1410 switch (rq->perout.index) { 1411 case 0: 1412 /* This is a request for 1PPS on an output SMA. 1413 * Allow, but assume manual configuration. 1414 */ 1415 if (on && (rq->perout.period.sec != 1 || 1416 rq->perout.period.nsec != 0)) 1417 return -EINVAL; 1418 return 0; 1419 case 1: 1420 case 2: 1421 case 3: 1422 case 4: 1423 req = rq->perout.index - 1; 1424 ext = bp->signal_out[req]; 1425 err = ptp_ocp_signal_from_perout(bp, req, &rq->perout); 1426 if (err) 1427 return err; 1428 break; 1429 } 1430 break; 1431 default: 1432 return -EOPNOTSUPP; 1433 } 1434 1435 err = -ENXIO; 1436 if (ext) 1437 err = ext->info->enable(ext, req, on); 1438 1439 return err; 1440} 1441 1442static int 1443ptp_ocp_verify(struct ptp_clock_info *ptp_info, unsigned pin, 1444 enum ptp_pin_function func, unsigned chan) 1445{ 1446 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info); 1447 char buf[16]; 1448 1449 switch (func) { 1450 case PTP_PF_NONE: 1451 snprintf(buf, sizeof(buf), "IN: None"); 1452 break; 1453 case PTP_PF_EXTTS: 1454 /* Allow timestamps, but require sysfs configuration. */ 1455 return 0; 1456 case PTP_PF_PEROUT: 1457 /* channel 0 is 1PPS from PHC. 1458 * channels 1..4 are the frequency generators. 1459 */ 1460 if (chan) 1461 snprintf(buf, sizeof(buf), "OUT: GEN%d", chan); 1462 else 1463 snprintf(buf, sizeof(buf), "OUT: PHC"); 1464 break; 1465 default: 1466 return -EOPNOTSUPP; 1467 } 1468 1469 return ptp_ocp_sma_store(bp, buf, pin + 1); 1470} 1471 1472static const struct ptp_clock_info ptp_ocp_clock_info = { 1473 .owner = THIS_MODULE, 1474 .name = KBUILD_MODNAME, 1475 .max_adj = 100000000, 1476 .gettimex64 = ptp_ocp_gettimex, 1477 .settime64 = ptp_ocp_settime, 1478 .adjtime = ptp_ocp_adjtime, 1479 .adjfine = ptp_ocp_null_adjfine, 1480 .adjphase = ptp_ocp_null_adjphase, 1481 .getmaxphase = ptp_ocp_null_getmaxphase, 1482 .enable = ptp_ocp_enable, 1483 .verify = ptp_ocp_verify, 1484 .pps = true, 1485 .n_ext_ts = 6, 1486 .n_per_out = 5, 1487 .supported_extts_flags = PTP_STRICT_FLAGS | PTP_RISING_EDGE, 1488 .supported_perout_flags = PTP_PEROUT_DUTY_CYCLE | PTP_PEROUT_PHASE, 1489}; 1490 1491static void 1492__ptp_ocp_clear_drift_locked(struct ptp_ocp *bp) 1493{ 1494 u32 ctrl, select; 1495 1496 select = ioread32(&bp->reg->select); 1497 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select); 1498 1499 iowrite32(0, &bp->reg->drift_ns); 1500 1501 ctrl = OCP_CTRL_ADJUST_DRIFT | OCP_CTRL_ENABLE; 1502 iowrite32(ctrl, &bp->reg->ctrl); 1503 1504 /* restore clock selection */ 1505 iowrite32(select >> 16, &bp->reg->select); 1506} 1507 1508static void 1509ptp_ocp_utc_distribute(struct ptp_ocp *bp, u32 val) 1510{ 1511 unsigned long flags; 1512 1513 spin_lock_irqsave(&bp->lock, flags); 1514 1515 bp->utc_tai_offset = val; 1516 1517 if (bp->irig_out) 1518 iowrite32(val, &bp->irig_out->adj_sec); 1519 if (bp->dcf_out) 1520 iowrite32(val, &bp->dcf_out->adj_sec); 1521 if (bp->nmea_out) 1522 iowrite32(val, &bp->nmea_out->adj_sec); 1523 1524 spin_unlock_irqrestore(&bp->lock, flags); 1525} 1526 1527static void 1528ptp_ocp_watchdog(struct timer_list *t) 1529{ 1530 struct ptp_ocp *bp = timer_container_of(bp, t, watchdog); 1531 unsigned long flags; 1532 u32 status, utc_offset; 1533 1534 status = ioread32(&bp->pps_to_clk->status); 1535 1536 if (status & PPS_STATUS_SUPERV_ERR) { 1537 iowrite32(status, &bp->pps_to_clk->status); 1538 if (!bp->gnss_lost) { 1539 spin_lock_irqsave(&bp->lock, flags); 1540 __ptp_ocp_clear_drift_locked(bp); 1541 spin_unlock_irqrestore(&bp->lock, flags); 1542 bp->gnss_lost = ktime_get_real_seconds(); 1543 } 1544 1545 } else if (bp->gnss_lost) { 1546 bp->gnss_lost = 0; 1547 } 1548 1549 /* if GNSS provides correct data we can rely on 1550 * it to get leap second information 1551 */ 1552 if (bp->tod) { 1553 status = ioread32(&bp->tod->utc_status); 1554 utc_offset = status & TOD_STATUS_UTC_MASK; 1555 if (status & TOD_STATUS_UTC_VALID && 1556 utc_offset != bp->utc_tai_offset) 1557 ptp_ocp_utc_distribute(bp, utc_offset); 1558 } 1559 1560 mod_timer(&bp->watchdog, jiffies + HZ); 1561} 1562 1563static void 1564ptp_ocp_estimate_pci_timing(struct ptp_ocp *bp) 1565{ 1566 ktime_t start, end, delay = U64_MAX; 1567 u32 ctrl; 1568 int i; 1569 1570 for (i = 0; i < 3; i++) { 1571 ctrl = ioread32(&bp->reg->ctrl); 1572 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE; 1573 1574 iowrite32(ctrl, &bp->reg->ctrl); 1575 1576 start = ktime_get_raw_ns(); 1577 1578 ctrl = ioread32(&bp->reg->ctrl); 1579 1580 end = ktime_get_raw_ns(); 1581 1582 delay = min(delay, end - start); 1583 } 1584 bp->ts_window_adjust = (delay >> 5) * 3; 1585} 1586 1587static int 1588ptp_ocp_init_clock(struct ptp_ocp *bp, struct ptp_ocp_servo_conf *servo_conf) 1589{ 1590 struct timespec64 ts; 1591 u32 ctrl; 1592 1593 ctrl = OCP_CTRL_ENABLE; 1594 iowrite32(ctrl, &bp->reg->ctrl); 1595 1596 /* servo configuration */ 1597 iowrite32(servo_conf->servo_offset_p, &bp->reg->servo_offset_p); 1598 iowrite32(servo_conf->servo_offset_i, &bp->reg->servo_offset_i); 1599 iowrite32(servo_conf->servo_drift_p, &bp->reg->servo_drift_p); 1600 iowrite32(servo_conf->servo_drift_p, &bp->reg->servo_drift_i); 1601 1602 /* latch servo values */ 1603 ctrl |= OCP_CTRL_ADJUST_SERVO; 1604 iowrite32(ctrl, &bp->reg->ctrl); 1605 1606 if ((ioread32(&bp->reg->ctrl) & OCP_CTRL_ENABLE) == 0) { 1607 dev_err(&bp->pdev->dev, "clock not enabled\n"); 1608 return -ENODEV; 1609 } 1610 1611 ptp_ocp_estimate_pci_timing(bp); 1612 1613 bp->sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC; 1614 if (!bp->sync) { 1615 ktime_get_clocktai_ts64(&ts); 1616 ptp_ocp_settime(&bp->ptp_info, &ts); 1617 } 1618 1619 /* If there is a clock supervisor, then enable the watchdog */ 1620 if (bp->pps_to_clk) { 1621 timer_setup(&bp->watchdog, ptp_ocp_watchdog, 0); 1622 mod_timer(&bp->watchdog, jiffies + HZ); 1623 } 1624 1625 return 0; 1626} 1627 1628static void 1629ptp_ocp_tod_init(struct ptp_ocp *bp) 1630{ 1631 u32 ctrl, reg; 1632 1633 ctrl = ioread32(&bp->tod->ctrl); 1634 ctrl |= TOD_CTRL_PROTOCOL | TOD_CTRL_ENABLE; 1635 ctrl &= ~(TOD_CTRL_DISABLE_FMT_A | TOD_CTRL_DISABLE_FMT_B); 1636 iowrite32(ctrl, &bp->tod->ctrl); 1637 1638 reg = ioread32(&bp->tod->utc_status); 1639 if (reg & TOD_STATUS_UTC_VALID) 1640 ptp_ocp_utc_distribute(bp, reg & TOD_STATUS_UTC_MASK); 1641} 1642 1643static const char * 1644ptp_ocp_tod_proto_name(const int idx) 1645{ 1646 static const char * const proto_name[] = { 1647 "NMEA", "NMEA_ZDA", "NMEA_RMC", "NMEA_none", 1648 "UBX", "UBX_UTC", "UBX_LS", "UBX_none" 1649 }; 1650 return proto_name[idx]; 1651} 1652 1653static const char * 1654ptp_ocp_tod_gnss_name(int idx) 1655{ 1656 static const char * const gnss_name[] = { 1657 "ALL", "COMBINED", "GPS", "GLONASS", "GALILEO", "BEIDOU", 1658 "Unknown" 1659 }; 1660 if (idx >= ARRAY_SIZE(gnss_name)) 1661 idx = ARRAY_SIZE(gnss_name) - 1; 1662 return gnss_name[idx]; 1663} 1664 1665static const char * 1666ptp_ocp_tty_port_name(int idx) 1667{ 1668 static const char * const tty_name[] = { 1669 "GNSS", "GNSS2", "MAC", "NMEA" 1670 }; 1671 return tty_name[idx]; 1672} 1673 1674struct ptp_ocp_nvmem_match_info { 1675 struct ptp_ocp *bp; 1676 const void * const tag; 1677}; 1678 1679static int 1680ptp_ocp_nvmem_match(struct device *dev, const void *data) 1681{ 1682 const struct ptp_ocp_nvmem_match_info *info = data; 1683 1684 dev = dev->parent; 1685 if (!i2c_verify_client(dev) || info->tag != dev->platform_data) 1686 return 0; 1687 1688 while ((dev = dev->parent)) 1689 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME)) 1690 return info->bp == dev_get_drvdata(dev); 1691 return 0; 1692} 1693 1694static inline struct nvmem_device * 1695ptp_ocp_nvmem_device_get(struct ptp_ocp *bp, const void * const tag) 1696{ 1697 struct ptp_ocp_nvmem_match_info info = { .bp = bp, .tag = tag }; 1698 1699 return nvmem_device_find(&info, ptp_ocp_nvmem_match); 1700} 1701 1702static inline void 1703ptp_ocp_nvmem_device_put(struct nvmem_device **nvmemp) 1704{ 1705 if (!IS_ERR_OR_NULL(*nvmemp)) 1706 nvmem_device_put(*nvmemp); 1707 *nvmemp = NULL; 1708} 1709 1710static void 1711ptp_ocp_read_eeprom(struct ptp_ocp *bp) 1712{ 1713 const struct ptp_ocp_eeprom_map *map; 1714 struct nvmem_device *nvmem; 1715 const void *tag; 1716 int ret; 1717 1718 if (!bp->i2c_ctrl) 1719 return; 1720 1721 tag = NULL; 1722 nvmem = NULL; 1723 1724 for (map = bp->eeprom_map; map->len; map++) { 1725 if (map->tag != tag) { 1726 tag = map->tag; 1727 ptp_ocp_nvmem_device_put(&nvmem); 1728 } 1729 if (!nvmem) { 1730 nvmem = ptp_ocp_nvmem_device_get(bp, tag); 1731 if (IS_ERR(nvmem)) { 1732 ret = PTR_ERR(nvmem); 1733 goto fail; 1734 } 1735 } 1736 ret = nvmem_device_read(nvmem, map->off, map->len, 1737 BP_MAP_ENTRY_ADDR(bp, map)); 1738 if (ret != map->len) 1739 goto fail; 1740 } 1741 1742 bp->has_eeprom_data = true; 1743 1744out: 1745 ptp_ocp_nvmem_device_put(&nvmem); 1746 return; 1747 1748fail: 1749 dev_err(&bp->pdev->dev, "could not read eeprom: %d\n", ret); 1750 goto out; 1751} 1752 1753static struct device * 1754ptp_ocp_find_flash(struct ptp_ocp *bp) 1755{ 1756 struct device *dev, *last; 1757 1758 last = NULL; 1759 dev = &bp->spi_flash->dev; 1760 1761 while ((dev = device_find_any_child(dev))) { 1762 if (!strcmp("mtd", dev_bus_name(dev))) 1763 break; 1764 put_device(last); 1765 last = dev; 1766 } 1767 put_device(last); 1768 1769 return dev; 1770} 1771 1772static int 1773ptp_ocp_devlink_fw_image(struct devlink *devlink, const struct firmware *fw, 1774 const u8 **data, size_t *size) 1775{ 1776 struct ptp_ocp *bp = devlink_priv(devlink); 1777 const struct ptp_ocp_firmware_header *hdr; 1778 size_t offset, length; 1779 u16 crc; 1780 1781 hdr = (const struct ptp_ocp_firmware_header *)fw->data; 1782 if (memcmp(hdr->magic, OCP_FIRMWARE_MAGIC_HEADER, 4)) { 1783 devlink_flash_update_status_notify(devlink, 1784 "No firmware header found, cancel firmware upgrade", 1785 NULL, 0, 0); 1786 return -EINVAL; 1787 } 1788 1789 if (be16_to_cpu(hdr->pci_vendor_id) != bp->pdev->vendor || 1790 be16_to_cpu(hdr->pci_device_id) != bp->pdev->device) { 1791 devlink_flash_update_status_notify(devlink, 1792 "Firmware image compatibility check failed", 1793 NULL, 0, 0); 1794 return -EINVAL; 1795 } 1796 1797 offset = sizeof(*hdr); 1798 length = be32_to_cpu(hdr->image_size); 1799 if (length != (fw->size - offset)) { 1800 devlink_flash_update_status_notify(devlink, 1801 "Firmware image size check failed", 1802 NULL, 0, 0); 1803 return -EINVAL; 1804 } 1805 1806 crc = crc16(0xffff, &fw->data[offset], length); 1807 if (be16_to_cpu(hdr->crc) != crc) { 1808 devlink_flash_update_status_notify(devlink, 1809 "Firmware image CRC check failed", 1810 NULL, 0, 0); 1811 return -EINVAL; 1812 } 1813 1814 *data = &fw->data[offset]; 1815 *size = length; 1816 1817 return 0; 1818} 1819 1820static int 1821ptp_ocp_devlink_flash(struct devlink *devlink, struct device *dev, 1822 const struct firmware *fw) 1823{ 1824 struct mtd_info *mtd = dev_get_drvdata(dev); 1825 struct ptp_ocp *bp = devlink_priv(devlink); 1826 size_t off, len, size, resid, wrote; 1827 struct erase_info erase; 1828 size_t base, blksz; 1829 const u8 *data; 1830 int err; 1831 1832 err = ptp_ocp_devlink_fw_image(devlink, fw, &data, &size); 1833 if (err) 1834 goto out; 1835 1836 off = 0; 1837 base = bp->flash_start; 1838 blksz = 4096; 1839 resid = size; 1840 1841 while (resid) { 1842 devlink_flash_update_status_notify(devlink, "Flashing", 1843 NULL, off, size); 1844 1845 len = min_t(size_t, resid, blksz); 1846 erase.addr = base + off; 1847 erase.len = blksz; 1848 1849 err = mtd_erase(mtd, &erase); 1850 if (err) 1851 goto out; 1852 1853 err = mtd_write(mtd, base + off, len, &wrote, data + off); 1854 if (err) 1855 goto out; 1856 1857 off += blksz; 1858 resid -= len; 1859 } 1860out: 1861 return err; 1862} 1863 1864static int 1865ptp_ocp_devlink_flash_update(struct devlink *devlink, 1866 struct devlink_flash_update_params *params, 1867 struct netlink_ext_ack *extack) 1868{ 1869 struct ptp_ocp *bp = devlink_priv(devlink); 1870 struct device *dev; 1871 const char *msg; 1872 int err; 1873 1874 dev = ptp_ocp_find_flash(bp); 1875 if (!dev) { 1876 dev_err(&bp->pdev->dev, "Can't find Flash SPI adapter\n"); 1877 return -ENODEV; 1878 } 1879 1880 devlink_flash_update_status_notify(devlink, "Preparing to flash", 1881 NULL, 0, 0); 1882 1883 err = ptp_ocp_devlink_flash(devlink, dev, params->fw); 1884 1885 msg = err ? "Flash error" : "Flash complete"; 1886 devlink_flash_update_status_notify(devlink, msg, NULL, 0, 0); 1887 1888 put_device(dev); 1889 return err; 1890} 1891 1892static int 1893ptp_ocp_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req, 1894 struct netlink_ext_ack *extack) 1895{ 1896 struct ptp_ocp *bp = devlink_priv(devlink); 1897 const char *fw_image; 1898 char buf[32]; 1899 int err; 1900 1901 fw_image = bp->fw_loader ? "loader" : "fw"; 1902 sprintf(buf, "%d.%d", bp->fw_tag, bp->fw_version); 1903 err = devlink_info_version_running_put(req, fw_image, buf); 1904 if (err) 1905 return err; 1906 1907 if (!bp->has_eeprom_data) { 1908 ptp_ocp_read_eeprom(bp); 1909 if (!bp->has_eeprom_data) 1910 return 0; 1911 } 1912 1913 sprintf(buf, "%pM", bp->serial); 1914 err = devlink_info_serial_number_put(req, buf); 1915 if (err) 1916 return err; 1917 1918 err = devlink_info_version_fixed_put(req, 1919 DEVLINK_INFO_VERSION_GENERIC_BOARD_ID, 1920 bp->board_id); 1921 if (err) 1922 return err; 1923 1924 return 0; 1925} 1926 1927static const struct devlink_ops ptp_ocp_devlink_ops = { 1928 .flash_update = ptp_ocp_devlink_flash_update, 1929 .info_get = ptp_ocp_devlink_info_get, 1930}; 1931 1932static void __iomem * 1933__ptp_ocp_get_mem(struct ptp_ocp *bp, resource_size_t start, int size) 1934{ 1935 struct resource res = DEFINE_RES_MEM_NAMED(start, size, "ptp_ocp"); 1936 1937 return devm_ioremap_resource(&bp->pdev->dev, &res); 1938} 1939 1940static void __iomem * 1941ptp_ocp_get_mem(struct ptp_ocp *bp, struct ocp_resource *r) 1942{ 1943 resource_size_t start; 1944 1945 start = pci_resource_start(bp->pdev, 0) + r->offset; 1946 return __ptp_ocp_get_mem(bp, start, r->size); 1947} 1948 1949static int 1950ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r) 1951{ 1952 struct ptp_ocp_flash_info *info; 1953 struct pci_dev *pdev = bp->pdev; 1954 struct platform_device *p; 1955 struct resource res[2]; 1956 resource_size_t start; 1957 int id; 1958 1959 start = pci_resource_start(pdev, 0) + r->offset; 1960 res[0] = DEFINE_RES_MEM(start, r->size); 1961 res[1] = DEFINE_RES_IRQ(pci_irq_vector(pdev, r->irq_vec)); 1962 1963 info = r->extra; 1964 id = pci_dev_id(pdev) << 1; 1965 id += info->pci_offset; 1966 1967 p = platform_device_register_resndata(&pdev->dev, info->name, id, 1968 res, ARRAY_SIZE(res), info->data, 1969 info->data_size); 1970 if (IS_ERR(p)) 1971 return PTR_ERR(p); 1972 1973 bp_assign_entry(bp, r, p); 1974 1975 return 0; 1976} 1977 1978static struct platform_device * 1979ptp_ocp_i2c_bus(struct pci_dev *pdev, struct ocp_resource *r, int id) 1980{ 1981 struct ptp_ocp_i2c_info *info; 1982 struct resource res[2]; 1983 resource_size_t start; 1984 1985 info = r->extra; 1986 start = pci_resource_start(pdev, 0) + r->offset; 1987 res[0] = DEFINE_RES_MEM(start, r->size); 1988 res[1] = DEFINE_RES_IRQ(pci_irq_vector(pdev, r->irq_vec)); 1989 1990 return platform_device_register_resndata(&pdev->dev, info->name, 1991 id, res, ARRAY_SIZE(res), 1992 info->data, info->data_size); 1993} 1994 1995static int 1996ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r) 1997{ 1998 struct pci_dev *pdev = bp->pdev; 1999 struct ptp_ocp_i2c_info *info; 2000 struct platform_device *p; 2001 struct clk_hw *clk; 2002 char buf[32]; 2003 int id; 2004 2005 info = r->extra; 2006 id = pci_dev_id(bp->pdev); 2007 2008 sprintf(buf, "AXI.%d", id); 2009 clk = clk_hw_register_fixed_rate(&pdev->dev, buf, NULL, 0, 2010 info->fixed_rate); 2011 if (IS_ERR(clk)) 2012 return PTR_ERR(clk); 2013 bp->i2c_clk = clk; 2014 2015 sprintf(buf, "%s.%d", info->name, id); 2016 devm_clk_hw_register_clkdev(&pdev->dev, clk, NULL, buf); 2017 p = ptp_ocp_i2c_bus(bp->pdev, r, id); 2018 if (IS_ERR(p)) 2019 return PTR_ERR(p); 2020 2021 bp_assign_entry(bp, r, p); 2022 2023 return 0; 2024} 2025 2026/* The expectation is that this is triggered only on error. */ 2027static irqreturn_t 2028ptp_ocp_signal_irq(int irq, void *priv) 2029{ 2030 struct ptp_ocp_ext_src *ext = priv; 2031 struct signal_reg __iomem *reg = ext->mem; 2032 struct ptp_ocp *bp = ext->bp; 2033 u32 enable, status; 2034 int gen; 2035 2036 gen = ext->info->index - 1; 2037 2038 enable = ioread32(®->enable); 2039 status = ioread32(®->status); 2040 2041 /* disable generator on error */ 2042 if (status || !enable) { 2043 iowrite32(0, ®->intr_mask); 2044 iowrite32(0, ®->enable); 2045 bp->signal[gen].running = false; 2046 } 2047 2048 iowrite32(0, ®->intr); /* ack interrupt */ 2049 2050 return IRQ_HANDLED; 2051} 2052 2053static int 2054ptp_ocp_signal_set(struct ptp_ocp *bp, int gen, struct ptp_ocp_signal *s) 2055{ 2056 struct ptp_system_timestamp sts; 2057 struct timespec64 ts; 2058 ktime_t start_ns; 2059 int err; 2060 2061 if (!s->period) 2062 return 0; 2063 2064 if (!s->pulse) 2065 s->pulse = ktime_divns(s->period * s->duty, 100); 2066 2067 err = ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts); 2068 if (err) 2069 return err; 2070 2071 start_ns = ktime_set(ts.tv_sec, ts.tv_nsec) + NSEC_PER_MSEC; 2072 if (!s->start) { 2073 /* roundup() does not work on 32-bit systems */ 2074 s->start = DIV64_U64_ROUND_UP(start_ns, s->period); 2075 s->start *= s->period; 2076 s->start = ktime_add(s->start, s->phase); 2077 } 2078 2079 if (s->duty < 1 || s->duty > 99) 2080 return -EINVAL; 2081 2082 if (s->pulse < 1 || s->pulse > s->period) 2083 return -EINVAL; 2084 2085 if (s->start < start_ns) 2086 return -EINVAL; 2087 2088 bp->signal[gen] = *s; 2089 2090 return 0; 2091} 2092 2093static int 2094ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen, 2095 struct ptp_perout_request *req) 2096{ 2097 struct ptp_ocp_signal s = { }; 2098 2099 s.polarity = bp->signal[gen].polarity; 2100 s.period = ktime_set(req->period.sec, req->period.nsec); 2101 if (!s.period) 2102 return 0; 2103 2104 if (req->flags & PTP_PEROUT_DUTY_CYCLE) { 2105 s.pulse = ktime_set(req->on.sec, req->on.nsec); 2106 s.duty = ktime_divns(s.pulse * 100, s.period); 2107 } 2108 2109 if (req->flags & PTP_PEROUT_PHASE) 2110 s.phase = ktime_set(req->phase.sec, req->phase.nsec); 2111 else 2112 s.start = ktime_set(req->start.sec, req->start.nsec); 2113 2114 return ptp_ocp_signal_set(bp, gen, &s); 2115} 2116 2117static int 2118ptp_ocp_signal_enable(void *priv, u32 req, bool enable) 2119{ 2120 struct ptp_ocp_ext_src *ext = priv; 2121 struct signal_reg __iomem *reg = ext->mem; 2122 struct ptp_ocp *bp = ext->bp; 2123 struct timespec64 ts; 2124 int gen; 2125 2126 gen = ext->info->index - 1; 2127 2128 iowrite32(0, ®->intr_mask); 2129 iowrite32(0, ®->enable); 2130 bp->signal[gen].running = false; 2131 if (!enable) 2132 return 0; 2133 2134 ts = ktime_to_timespec64(bp->signal[gen].start); 2135 iowrite32(ts.tv_sec, ®->start_sec); 2136 iowrite32(ts.tv_nsec, ®->start_ns); 2137 2138 ts = ktime_to_timespec64(bp->signal[gen].period); 2139 iowrite32(ts.tv_sec, ®->period_sec); 2140 iowrite32(ts.tv_nsec, ®->period_ns); 2141 2142 ts = ktime_to_timespec64(bp->signal[gen].pulse); 2143 iowrite32(ts.tv_sec, ®->pulse_sec); 2144 iowrite32(ts.tv_nsec, ®->pulse_ns); 2145 2146 iowrite32(bp->signal[gen].polarity, ®->polarity); 2147 iowrite32(0, ®->repeat_count); 2148 2149 iowrite32(0, ®->intr); /* clear interrupt state */ 2150 iowrite32(1, ®->intr_mask); /* enable interrupt */ 2151 iowrite32(3, ®->enable); /* valid & enable */ 2152 2153 bp->signal[gen].running = true; 2154 2155 return 0; 2156} 2157 2158static irqreturn_t 2159ptp_ocp_ts_irq(int irq, void *priv) 2160{ 2161 struct ptp_ocp_ext_src *ext = priv; 2162 struct ts_reg __iomem *reg = ext->mem; 2163 struct ptp_clock_event ev; 2164 u32 sec, nsec; 2165 2166 if (ext == ext->bp->pps) { 2167 if (ext->bp->pps_req_map & OCP_REQ_PPS) { 2168 ev.type = PTP_CLOCK_PPS; 2169 ptp_clock_event(ext->bp->ptp, &ev); 2170 } 2171 2172 if ((ext->bp->pps_req_map & ~OCP_REQ_PPS) == 0) 2173 goto out; 2174 } 2175 2176 /* XXX should fix API - this converts s/ns -> ts -> s/ns */ 2177 sec = ioread32(®->time_sec); 2178 nsec = ioread32(®->time_ns); 2179 2180 ev.type = PTP_CLOCK_EXTTS; 2181 ev.index = ext->info->index; 2182 ev.timestamp = sec * NSEC_PER_SEC + nsec; 2183 2184 ptp_clock_event(ext->bp->ptp, &ev); 2185 2186out: 2187 iowrite32(1, ®->intr); /* write 1 to ack */ 2188 2189 return IRQ_HANDLED; 2190} 2191 2192static int 2193ptp_ocp_ts_enable(void *priv, u32 req, bool enable) 2194{ 2195 struct ptp_ocp_ext_src *ext = priv; 2196 struct ts_reg __iomem *reg = ext->mem; 2197 struct ptp_ocp *bp = ext->bp; 2198 2199 if (ext == bp->pps) { 2200 u32 old_map = bp->pps_req_map; 2201 2202 if (enable) 2203 bp->pps_req_map |= req; 2204 else 2205 bp->pps_req_map &= ~req; 2206 2207 /* if no state change, just return */ 2208 if ((!!old_map ^ !!bp->pps_req_map) == 0) 2209 return 0; 2210 } 2211 2212 if (enable) { 2213 iowrite32(1, ®->enable); 2214 iowrite32(1, ®->intr_mask); 2215 iowrite32(1, ®->intr); 2216 } else { 2217 iowrite32(0, ®->intr_mask); 2218 iowrite32(0, ®->enable); 2219 } 2220 2221 return 0; 2222} 2223 2224static void 2225ptp_ocp_unregister_ext(struct ptp_ocp_ext_src *ext) 2226{ 2227 if (!ext) 2228 return; 2229 2230 ext->info->enable(ext, ~0, false); 2231 pci_free_irq(ext->bp->pdev, ext->irq_vec, ext); 2232 kfree(ext); 2233} 2234 2235static int 2236ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r) 2237{ 2238 struct pci_dev *pdev = bp->pdev; 2239 struct ptp_ocp_ext_src *ext; 2240 int err; 2241 2242 ext = kzalloc(sizeof(*ext), GFP_KERNEL); 2243 if (!ext) 2244 return -ENOMEM; 2245 2246 ext->mem = ptp_ocp_get_mem(bp, r); 2247 if (IS_ERR(ext->mem)) { 2248 err = PTR_ERR(ext->mem); 2249 goto out; 2250 } 2251 2252 ext->bp = bp; 2253 ext->info = r->extra; 2254 ext->irq_vec = r->irq_vec; 2255 2256 err = pci_request_irq(pdev, r->irq_vec, ext->info->irq_fcn, NULL, 2257 ext, "ocp%d.%s", bp->id, r->name); 2258 if (err) { 2259 dev_err(&pdev->dev, "Could not get irq %d\n", r->irq_vec); 2260 goto out; 2261 } 2262 2263 bp_assign_entry(bp, r, ext); 2264 2265 return 0; 2266 2267out: 2268 kfree(ext); 2269 return err; 2270} 2271 2272static int 2273ptp_ocp_serial_line(struct ptp_ocp *bp, struct ocp_resource *r) 2274{ 2275 struct pci_dev *pdev = bp->pdev; 2276 struct uart_8250_port uart; 2277 2278 /* Setting UPF_IOREMAP and leaving port.membase unspecified lets 2279 * the serial port device claim and release the pci resource. 2280 */ 2281 memset(&uart, 0, sizeof(uart)); 2282 uart.port.dev = &pdev->dev; 2283 uart.port.iotype = UPIO_MEM; 2284 uart.port.regshift = 2; 2285 uart.port.mapbase = pci_resource_start(pdev, 0) + r->offset; 2286 uart.port.irq = pci_irq_vector(pdev, r->irq_vec); 2287 uart.port.uartclk = 50000000; 2288 uart.port.flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_NO_THRE_TEST; 2289 uart.port.type = PORT_16550A; 2290 2291 return serial8250_register_8250_port(&uart); 2292} 2293 2294static int 2295ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r) 2296{ 2297 struct ptp_ocp_serial_port *p = (struct ptp_ocp_serial_port *)r->extra; 2298 struct ptp_ocp_serial_port port = {}; 2299 2300 port.line = ptp_ocp_serial_line(bp, r); 2301 if (port.line < 0) 2302 return port.line; 2303 2304 if (p) 2305 port.baud = p->baud; 2306 2307 bp_assign_entry(bp, r, port); 2308 2309 return 0; 2310} 2311 2312static int 2313ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r) 2314{ 2315 void __iomem *mem; 2316 2317 mem = ptp_ocp_get_mem(bp, r); 2318 if (IS_ERR(mem)) 2319 return PTR_ERR(mem); 2320 2321 bp_assign_entry(bp, r, mem); 2322 2323 return 0; 2324} 2325 2326static void 2327ptp_ocp_nmea_out_init(struct ptp_ocp *bp) 2328{ 2329 if (!bp->nmea_out) 2330 return; 2331 2332 iowrite32(0, &bp->nmea_out->ctrl); /* disable */ 2333 iowrite32(7, &bp->nmea_out->uart_baud); /* 115200 */ 2334 iowrite32(1, &bp->nmea_out->ctrl); /* enable */ 2335} 2336 2337static void 2338_ptp_ocp_signal_init(struct ptp_ocp_signal *s, struct signal_reg __iomem *reg) 2339{ 2340 u32 val; 2341 2342 iowrite32(0, ®->enable); /* disable */ 2343 2344 val = ioread32(®->polarity); 2345 s->polarity = val ? true : false; 2346 s->duty = 50; 2347} 2348 2349static void 2350ptp_ocp_signal_init(struct ptp_ocp *bp) 2351{ 2352 int i; 2353 2354 for (i = 0; i < 4; i++) 2355 if (bp->signal_out[i]) 2356 _ptp_ocp_signal_init(&bp->signal[i], 2357 bp->signal_out[i]->mem); 2358} 2359 2360static void 2361ptp_ocp_attr_group_del(struct ptp_ocp *bp) 2362{ 2363 sysfs_remove_groups(&bp->dev.kobj, bp->attr_group); 2364 kfree(bp->attr_group); 2365} 2366 2367static int 2368ptp_ocp_attr_group_add(struct ptp_ocp *bp, 2369 const struct ocp_attr_group *attr_tbl) 2370{ 2371 int count, i; 2372 int err; 2373 2374 count = 0; 2375 for (i = 0; attr_tbl[i].cap; i++) 2376 if (attr_tbl[i].cap & bp->fw_cap) 2377 count++; 2378 2379 bp->attr_group = kcalloc(count + 1, sizeof(*bp->attr_group), 2380 GFP_KERNEL); 2381 if (!bp->attr_group) 2382 return -ENOMEM; 2383 2384 count = 0; 2385 for (i = 0; attr_tbl[i].cap; i++) 2386 if (attr_tbl[i].cap & bp->fw_cap) 2387 bp->attr_group[count++] = attr_tbl[i].group; 2388 2389 err = sysfs_create_groups(&bp->dev.kobj, bp->attr_group); 2390 if (err) 2391 bp->attr_group[0] = NULL; 2392 2393 return err; 2394} 2395 2396static void 2397ptp_ocp_enable_fpga(u32 __iomem *reg, u32 bit, bool enable) 2398{ 2399 u32 ctrl; 2400 bool on; 2401 2402 ctrl = ioread32(reg); 2403 on = ctrl & bit; 2404 if (on ^ enable) { 2405 ctrl &= ~bit; 2406 ctrl |= enable ? bit : 0; 2407 iowrite32(ctrl, reg); 2408 } 2409} 2410 2411static void 2412ptp_ocp_irig_out(struct ptp_ocp *bp, bool enable) 2413{ 2414 return ptp_ocp_enable_fpga(&bp->irig_out->ctrl, 2415 IRIG_M_CTRL_ENABLE, enable); 2416} 2417 2418static void 2419ptp_ocp_irig_in(struct ptp_ocp *bp, bool enable) 2420{ 2421 return ptp_ocp_enable_fpga(&bp->irig_in->ctrl, 2422 IRIG_S_CTRL_ENABLE, enable); 2423} 2424 2425static void 2426ptp_ocp_dcf_out(struct ptp_ocp *bp, bool enable) 2427{ 2428 return ptp_ocp_enable_fpga(&bp->dcf_out->ctrl, 2429 DCF_M_CTRL_ENABLE, enable); 2430} 2431 2432static void 2433ptp_ocp_dcf_in(struct ptp_ocp *bp, bool enable) 2434{ 2435 return ptp_ocp_enable_fpga(&bp->dcf_in->ctrl, 2436 DCF_S_CTRL_ENABLE, enable); 2437} 2438 2439static void 2440__handle_signal_outputs(struct ptp_ocp *bp, u32 val) 2441{ 2442 ptp_ocp_irig_out(bp, val & 0x00100010); 2443 ptp_ocp_dcf_out(bp, val & 0x00200020); 2444} 2445 2446static void 2447__handle_signal_inputs(struct ptp_ocp *bp, u32 val) 2448{ 2449 ptp_ocp_irig_in(bp, val & 0x00100010); 2450 ptp_ocp_dcf_in(bp, val & 0x00200020); 2451} 2452 2453static u32 2454ptp_ocp_sma_fb_get(struct ptp_ocp *bp, int sma_nr) 2455{ 2456 u32 __iomem *gpio; 2457 u32 shift; 2458 2459 if (bp->sma[sma_nr - 1].fixed_fcn) 2460 return (sma_nr - 1) & 1; 2461 2462 if (bp->sma[sma_nr - 1].mode == SMA_MODE_IN) 2463 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1; 2464 else 2465 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2; 2466 shift = sma_nr & 1 ? 0 : 16; 2467 2468 return (ioread32(gpio) >> shift) & 0xffff; 2469} 2470 2471static int 2472ptp_ocp_sma_fb_set_output(struct ptp_ocp *bp, int sma_nr, u32 val) 2473{ 2474 u32 reg, mask, shift; 2475 unsigned long flags; 2476 u32 __iomem *gpio; 2477 2478 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2; 2479 shift = sma_nr & 1 ? 0 : 16; 2480 2481 mask = 0xffff << (16 - shift); 2482 2483 spin_lock_irqsave(&bp->lock, flags); 2484 2485 reg = ioread32(gpio); 2486 reg = (reg & mask) | (val << shift); 2487 2488 __handle_signal_outputs(bp, reg); 2489 2490 iowrite32(reg, gpio); 2491 2492 spin_unlock_irqrestore(&bp->lock, flags); 2493 2494 return 0; 2495} 2496 2497static int 2498ptp_ocp_sma_fb_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val) 2499{ 2500 u32 reg, mask, shift; 2501 unsigned long flags; 2502 u32 __iomem *gpio; 2503 2504 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1; 2505 shift = sma_nr & 1 ? 0 : 16; 2506 2507 mask = 0xffff << (16 - shift); 2508 2509 spin_lock_irqsave(&bp->lock, flags); 2510 2511 reg = ioread32(gpio); 2512 reg = (reg & mask) | (val << shift); 2513 2514 __handle_signal_inputs(bp, reg); 2515 2516 iowrite32(reg, gpio); 2517 2518 spin_unlock_irqrestore(&bp->lock, flags); 2519 2520 return 0; 2521} 2522 2523static void 2524ptp_ocp_sma_fb_init(struct ptp_ocp *bp) 2525{ 2526 struct dpll_pin_properties prop = { 2527 .board_label = NULL, 2528 .type = DPLL_PIN_TYPE_EXT, 2529 .capabilities = DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE, 2530 .freq_supported_num = ARRAY_SIZE(ptp_ocp_sma_freq), 2531 .freq_supported = ptp_ocp_sma_freq, 2532 2533 }; 2534 u32 reg; 2535 int i; 2536 2537 /* defaults */ 2538 for (i = 0; i < OCP_SMA_NUM; i++) { 2539 bp->sma[i].default_fcn = i & 1; 2540 bp->sma[i].dpll_prop = prop; 2541 bp->sma[i].dpll_prop.board_label = 2542 bp->ptp_info.pin_config[i].name; 2543 } 2544 bp->sma[0].mode = SMA_MODE_IN; 2545 bp->sma[1].mode = SMA_MODE_IN; 2546 bp->sma[2].mode = SMA_MODE_OUT; 2547 bp->sma[3].mode = SMA_MODE_OUT; 2548 /* If no SMA1 map, the pin functions and directions are fixed. */ 2549 if (!bp->sma_map1) { 2550 for (i = 0; i < OCP_SMA_NUM; i++) { 2551 bp->sma[i].fixed_fcn = true; 2552 bp->sma[i].fixed_dir = true; 2553 bp->sma[i].dpll_prop.capabilities &= 2554 ~DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE; 2555 } 2556 return; 2557 } 2558 2559 /* If SMA2 GPIO output map is all 1, it is not present. 2560 * This indicates the firmware has fixed direction SMA pins. 2561 */ 2562 reg = ioread32(&bp->sma_map2->gpio2); 2563 if (reg == 0xffffffff) { 2564 for (i = 0; i < OCP_SMA_NUM; i++) 2565 bp->sma[i].fixed_dir = true; 2566 } else { 2567 reg = ioread32(&bp->sma_map1->gpio1); 2568 bp->sma[0].mode = reg & BIT(15) ? SMA_MODE_IN : SMA_MODE_OUT; 2569 bp->sma[1].mode = reg & BIT(31) ? SMA_MODE_IN : SMA_MODE_OUT; 2570 2571 reg = ioread32(&bp->sma_map1->gpio2); 2572 bp->sma[2].mode = reg & BIT(15) ? SMA_MODE_OUT : SMA_MODE_IN; 2573 bp->sma[3].mode = reg & BIT(31) ? SMA_MODE_OUT : SMA_MODE_IN; 2574 } 2575} 2576 2577static const struct ocp_sma_op ocp_fb_sma_op = { 2578 .tbl = { ptp_ocp_sma_in, ptp_ocp_sma_out }, 2579 .init = ptp_ocp_sma_fb_init, 2580 .get = ptp_ocp_sma_fb_get, 2581 .set_inputs = ptp_ocp_sma_fb_set_inputs, 2582 .set_output = ptp_ocp_sma_fb_set_output, 2583}; 2584 2585static int 2586ptp_ocp_sma_adva_set_output(struct ptp_ocp *bp, int sma_nr, u32 val) 2587{ 2588 u32 reg, mask, shift; 2589 unsigned long flags; 2590 u32 __iomem *gpio; 2591 2592 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2; 2593 shift = sma_nr & 1 ? 0 : 16; 2594 2595 mask = 0xffff << (16 - shift); 2596 2597 spin_lock_irqsave(&bp->lock, flags); 2598 2599 reg = ioread32(gpio); 2600 reg = (reg & mask) | (val << shift); 2601 2602 iowrite32(reg, gpio); 2603 2604 spin_unlock_irqrestore(&bp->lock, flags); 2605 2606 return 0; 2607} 2608 2609static int 2610ptp_ocp_sma_adva_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val) 2611{ 2612 u32 reg, mask, shift; 2613 unsigned long flags; 2614 u32 __iomem *gpio; 2615 2616 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1; 2617 shift = sma_nr & 1 ? 0 : 16; 2618 2619 mask = 0xffff << (16 - shift); 2620 2621 spin_lock_irqsave(&bp->lock, flags); 2622 2623 reg = ioread32(gpio); 2624 reg = (reg & mask) | (val << shift); 2625 2626 iowrite32(reg, gpio); 2627 2628 spin_unlock_irqrestore(&bp->lock, flags); 2629 2630 return 0; 2631} 2632 2633static const struct ocp_sma_op ocp_adva_sma_op = { 2634 .tbl = { ptp_ocp_adva_sma_in, ptp_ocp_adva_sma_out }, 2635 .init = ptp_ocp_sma_fb_init, 2636 .get = ptp_ocp_sma_fb_get, 2637 .set_inputs = ptp_ocp_sma_adva_set_inputs, 2638 .set_output = ptp_ocp_sma_adva_set_output, 2639}; 2640 2641static int 2642ptp_ocp_set_pins(struct ptp_ocp *bp) 2643{ 2644 struct ptp_pin_desc *config; 2645 int i; 2646 2647 config = kcalloc(4, sizeof(*config), GFP_KERNEL); 2648 if (!config) 2649 return -ENOMEM; 2650 2651 for (i = 0; i < 4; i++) { 2652 sprintf(config[i].name, "sma%d", i + 1); 2653 config[i].index = i; 2654 } 2655 2656 bp->ptp_info.n_pins = 4; 2657 bp->ptp_info.pin_config = config; 2658 2659 return 0; 2660} 2661 2662static void 2663ptp_ocp_fb_set_version(struct ptp_ocp *bp) 2664{ 2665 u64 cap = OCP_CAP_BASIC; 2666 u32 version; 2667 2668 version = ioread32(&bp->image->version); 2669 2670 /* if lower 16 bits are empty, this is the fw loader. */ 2671 if ((version & 0xffff) == 0) { 2672 version = version >> 16; 2673 bp->fw_loader = true; 2674 } 2675 2676 bp->fw_tag = version >> 15; 2677 bp->fw_version = version & 0x7fff; 2678 2679 if (bp->fw_tag) { 2680 /* FPGA firmware */ 2681 if (version >= 5) 2682 cap |= OCP_CAP_SIGNAL | OCP_CAP_FREQ; 2683 } else { 2684 /* SOM firmware */ 2685 if (version >= 19) 2686 cap |= OCP_CAP_SIGNAL; 2687 if (version >= 20) 2688 cap |= OCP_CAP_FREQ; 2689 } 2690 2691 bp->fw_cap = cap; 2692} 2693 2694/* FB specific board initializers; last "resource" registered. */ 2695static int 2696ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r) 2697{ 2698 int err; 2699 2700 bp->flash_start = 1024 * 4096; 2701 bp->eeprom_map = fb_eeprom_map; 2702 bp->fw_version = ioread32(&bp->image->version); 2703 bp->sma_op = &ocp_fb_sma_op; 2704 bp->signals_nr = 4; 2705 bp->freq_in_nr = 4; 2706 2707 ptp_ocp_fb_set_version(bp); 2708 2709 ptp_ocp_tod_init(bp); 2710 ptp_ocp_nmea_out_init(bp); 2711 ptp_ocp_signal_init(bp); 2712 2713 err = ptp_ocp_attr_group_add(bp, fb_timecard_groups); 2714 if (err) 2715 return err; 2716 2717 err = ptp_ocp_set_pins(bp); 2718 if (err) 2719 return err; 2720 ptp_ocp_sma_init(bp); 2721 2722 return ptp_ocp_init_clock(bp, r->extra); 2723} 2724 2725static bool 2726ptp_ocp_allow_irq(struct ptp_ocp *bp, struct ocp_resource *r) 2727{ 2728 bool allow = !r->irq_vec || r->irq_vec < bp->n_irqs; 2729 2730 if (!allow) 2731 dev_err(&bp->pdev->dev, "irq %d out of range, skipping %s\n", 2732 r->irq_vec, r->name); 2733 return allow; 2734} 2735 2736static int 2737ptp_ocp_register_resources(struct ptp_ocp *bp, kernel_ulong_t driver_data) 2738{ 2739 struct ocp_resource *r, *table; 2740 int err = 0; 2741 2742 table = (struct ocp_resource *)driver_data; 2743 for (r = table; r->setup; r++) { 2744 if (!ptp_ocp_allow_irq(bp, r)) 2745 continue; 2746 err = r->setup(bp, r); 2747 if (err) { 2748 dev_err(&bp->pdev->dev, 2749 "Could not register %s: err %d\n", 2750 r->name, err); 2751 break; 2752 } 2753 } 2754 return err; 2755} 2756 2757static void 2758ptp_ocp_art_sma_init(struct ptp_ocp *bp) 2759{ 2760 struct dpll_pin_properties prop = { 2761 .board_label = NULL, 2762 .type = DPLL_PIN_TYPE_EXT, 2763 .capabilities = 0, 2764 .freq_supported_num = ARRAY_SIZE(ptp_ocp_sma_freq), 2765 .freq_supported = ptp_ocp_sma_freq, 2766 2767 }; 2768 u32 reg; 2769 int i; 2770 2771 /* defaults */ 2772 bp->sma[0].mode = SMA_MODE_IN; 2773 bp->sma[1].mode = SMA_MODE_IN; 2774 bp->sma[2].mode = SMA_MODE_OUT; 2775 bp->sma[3].mode = SMA_MODE_OUT; 2776 2777 bp->sma[0].default_fcn = 0x08; /* IN: 10Mhz */ 2778 bp->sma[1].default_fcn = 0x01; /* IN: PPS1 */ 2779 bp->sma[2].default_fcn = 0x10; /* OUT: 10Mhz */ 2780 bp->sma[3].default_fcn = 0x02; /* OUT: PHC */ 2781 2782 for (i = 0; i < OCP_SMA_NUM; i++) { 2783 /* If no SMA map, the pin functions and directions are fixed. */ 2784 bp->sma[i].dpll_prop = prop; 2785 bp->sma[i].dpll_prop.board_label = 2786 bp->ptp_info.pin_config[i].name; 2787 if (!bp->art_sma) { 2788 bp->sma[i].fixed_fcn = true; 2789 bp->sma[i].fixed_dir = true; 2790 continue; 2791 } 2792 reg = ioread32(&bp->art_sma->map[i].gpio); 2793 2794 switch (reg & 0xff) { 2795 case 0: 2796 bp->sma[i].fixed_fcn = true; 2797 bp->sma[i].fixed_dir = true; 2798 break; 2799 case 1: 2800 case 8: 2801 bp->sma[i].mode = SMA_MODE_IN; 2802 bp->sma[i].dpll_prop.capabilities = 2803 DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE; 2804 break; 2805 default: 2806 bp->sma[i].mode = SMA_MODE_OUT; 2807 bp->sma[i].dpll_prop.capabilities = 2808 DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE; 2809 break; 2810 } 2811 } 2812} 2813 2814static u32 2815ptp_ocp_art_sma_get(struct ptp_ocp *bp, int sma_nr) 2816{ 2817 if (bp->sma[sma_nr - 1].fixed_fcn) 2818 return bp->sma[sma_nr - 1].default_fcn; 2819 2820 return ioread32(&bp->art_sma->map[sma_nr - 1].gpio) & 0xff; 2821} 2822 2823/* note: store 0 is considered invalid. */ 2824static int 2825ptp_ocp_art_sma_set(struct ptp_ocp *bp, int sma_nr, u32 val) 2826{ 2827 unsigned long flags; 2828 u32 __iomem *gpio; 2829 int err = 0; 2830 u32 reg; 2831 2832 val &= SMA_SELECT_MASK; 2833 if (hweight32(val) > 1) 2834 return -EINVAL; 2835 2836 gpio = &bp->art_sma->map[sma_nr - 1].gpio; 2837 2838 spin_lock_irqsave(&bp->lock, flags); 2839 reg = ioread32(gpio); 2840 if (((reg >> 16) & val) == 0) { 2841 err = -EOPNOTSUPP; 2842 } else { 2843 reg = (reg & 0xff00) | (val & 0xff); 2844 iowrite32(reg, gpio); 2845 } 2846 spin_unlock_irqrestore(&bp->lock, flags); 2847 2848 return err; 2849} 2850 2851static const struct ocp_sma_op ocp_art_sma_op = { 2852 .tbl = { ptp_ocp_art_sma_in, ptp_ocp_art_sma_out }, 2853 .init = ptp_ocp_art_sma_init, 2854 .get = ptp_ocp_art_sma_get, 2855 .set_inputs = ptp_ocp_art_sma_set, 2856 .set_output = ptp_ocp_art_sma_set, 2857}; 2858 2859/* ART specific board initializers; last "resource" registered. */ 2860static int 2861ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r) 2862{ 2863 int err; 2864 2865 bp->flash_start = 0x1000000; 2866 bp->eeprom_map = art_eeprom_map; 2867 bp->fw_cap = OCP_CAP_BASIC; 2868 bp->fw_version = ioread32(&bp->reg->version); 2869 bp->fw_tag = 2; 2870 bp->sma_op = &ocp_art_sma_op; 2871 bp->signals_nr = 4; 2872 bp->freq_in_nr = 4; 2873 2874 /* Enable MAC serial port during initialisation */ 2875 iowrite32(1, &bp->board_config->mro50_serial_activate); 2876 2877 err = ptp_ocp_set_pins(bp); 2878 if (err) 2879 return err; 2880 ptp_ocp_sma_init(bp); 2881 2882 err = ptp_ocp_attr_group_add(bp, art_timecard_groups); 2883 if (err) 2884 return err; 2885 2886 return ptp_ocp_init_clock(bp, r->extra); 2887} 2888 2889/* ADVA specific board initializers; last "resource" registered. */ 2890static int 2891ptp_ocp_adva_board_init(struct ptp_ocp *bp, struct ocp_resource *r) 2892{ 2893 int err; 2894 u32 version; 2895 2896 bp->flash_start = 0xA00000; 2897 bp->eeprom_map = fb_eeprom_map; 2898 bp->sma_op = &ocp_adva_sma_op; 2899 bp->signals_nr = 2; 2900 bp->freq_in_nr = 2; 2901 2902 version = ioread32(&bp->image->version); 2903 /* if lower 16 bits are empty, this is the fw loader. */ 2904 if ((version & 0xffff) == 0) { 2905 version = version >> 16; 2906 bp->fw_loader = true; 2907 } 2908 bp->fw_tag = 3; 2909 bp->fw_version = version & 0xffff; 2910 bp->fw_cap = OCP_CAP_BASIC | OCP_CAP_SIGNAL | OCP_CAP_FREQ; 2911 2912 ptp_ocp_tod_init(bp); 2913 ptp_ocp_nmea_out_init(bp); 2914 ptp_ocp_signal_init(bp); 2915 2916 err = ptp_ocp_attr_group_add(bp, adva_timecard_groups); 2917 if (err) 2918 return err; 2919 2920 err = ptp_ocp_set_pins(bp); 2921 if (err) 2922 return err; 2923 ptp_ocp_sma_init(bp); 2924 2925 return ptp_ocp_init_clock(bp, r->extra); 2926} 2927 2928static ssize_t 2929ptp_ocp_show_output(const struct ocp_selector *tbl, u32 val, char *buf, 2930 int def_val) 2931{ 2932 const char *name; 2933 ssize_t count; 2934 2935 count = sysfs_emit(buf, "OUT: "); 2936 name = ptp_ocp_select_name_from_val(tbl, val); 2937 if (!name) 2938 name = ptp_ocp_select_name_from_val(tbl, def_val); 2939 count += sysfs_emit_at(buf, count, "%s\n", name); 2940 return count; 2941} 2942 2943static ssize_t 2944ptp_ocp_show_inputs(const struct ocp_selector *tbl, u32 val, char *buf, 2945 int def_val) 2946{ 2947 const char *name; 2948 ssize_t count; 2949 int i; 2950 2951 count = sysfs_emit(buf, "IN: "); 2952 for (i = 0; tbl[i].name; i++) { 2953 if (val & tbl[i].value) { 2954 name = tbl[i].name; 2955 count += sysfs_emit_at(buf, count, "%s ", name); 2956 } 2957 } 2958 if (!val && def_val >= 0) { 2959 name = ptp_ocp_select_name_from_val(tbl, def_val); 2960 count += sysfs_emit_at(buf, count, "%s ", name); 2961 } 2962 if (count) 2963 count--; 2964 count += sysfs_emit_at(buf, count, "\n"); 2965 return count; 2966} 2967 2968static int 2969sma_parse_inputs(const struct ocp_selector * const tbl[], const char *buf, 2970 enum ptp_ocp_sma_mode *mode) 2971{ 2972 int idx, count, dir; 2973 char **argv; 2974 int ret; 2975 2976 argv = argv_split(GFP_KERNEL, buf, &count); 2977 if (!argv) 2978 return -ENOMEM; 2979 2980 ret = -EINVAL; 2981 if (!count) 2982 goto out; 2983 2984 idx = 0; 2985 dir = *mode == SMA_MODE_IN ? 0 : 1; 2986 if (!strcasecmp("IN:", argv[0])) { 2987 dir = 0; 2988 idx++; 2989 } 2990 if (!strcasecmp("OUT:", argv[0])) { 2991 dir = 1; 2992 idx++; 2993 } 2994 *mode = dir == 0 ? SMA_MODE_IN : SMA_MODE_OUT; 2995 2996 ret = 0; 2997 for (; idx < count; idx++) 2998 ret |= ptp_ocp_select_val_from_name(tbl[dir], argv[idx]); 2999 if (ret < 0) 3000 ret = -EINVAL; 3001 3002out: 3003 argv_free(argv); 3004 return ret; 3005} 3006 3007static ssize_t 3008ptp_ocp_sma_show(struct ptp_ocp *bp, int sma_nr, char *buf, 3009 int default_in_val, int default_out_val) 3010{ 3011 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1]; 3012 const struct ocp_selector * const *tbl; 3013 u32 val; 3014 3015 tbl = bp->sma_op->tbl; 3016 val = ptp_ocp_sma_get(bp, sma_nr) & SMA_SELECT_MASK; 3017 3018 if (sma->mode == SMA_MODE_IN) { 3019 if (sma->disabled) 3020 val = SMA_DISABLE; 3021 return ptp_ocp_show_inputs(tbl[0], val, buf, default_in_val); 3022 } 3023 3024 return ptp_ocp_show_output(tbl[1], val, buf, default_out_val); 3025} 3026 3027static ssize_t 3028sma1_show(struct device *dev, struct device_attribute *attr, char *buf) 3029{ 3030 struct ptp_ocp *bp = dev_get_drvdata(dev); 3031 3032 return ptp_ocp_sma_show(bp, 1, buf, 0, 1); 3033} 3034 3035static ssize_t 3036sma2_show(struct device *dev, struct device_attribute *attr, char *buf) 3037{ 3038 struct ptp_ocp *bp = dev_get_drvdata(dev); 3039 3040 return ptp_ocp_sma_show(bp, 2, buf, -1, 1); 3041} 3042 3043static ssize_t 3044sma3_show(struct device *dev, struct device_attribute *attr, char *buf) 3045{ 3046 struct ptp_ocp *bp = dev_get_drvdata(dev); 3047 3048 return ptp_ocp_sma_show(bp, 3, buf, -1, 0); 3049} 3050 3051static ssize_t 3052sma4_show(struct device *dev, struct device_attribute *attr, char *buf) 3053{ 3054 struct ptp_ocp *bp = dev_get_drvdata(dev); 3055 3056 return ptp_ocp_sma_show(bp, 4, buf, -1, 1); 3057} 3058 3059static int 3060ptp_ocp_sma_store_val(struct ptp_ocp *bp, int val, enum ptp_ocp_sma_mode mode, int sma_nr) 3061{ 3062 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1]; 3063 3064 if (sma->fixed_dir && (mode != sma->mode || val & SMA_DISABLE)) 3065 return -EOPNOTSUPP; 3066 3067 if (sma->fixed_fcn) { 3068 if (val != sma->default_fcn) 3069 return -EOPNOTSUPP; 3070 return 0; 3071 } 3072 3073 sma->disabled = !!(val & SMA_DISABLE); 3074 3075 if (mode != sma->mode) { 3076 if (mode == SMA_MODE_IN) 3077 ptp_ocp_sma_set_output(bp, sma_nr, 0); 3078 else 3079 ptp_ocp_sma_set_inputs(bp, sma_nr, 0); 3080 sma->mode = mode; 3081 } 3082 3083 if (!sma->fixed_dir) 3084 val |= SMA_ENABLE; /* add enable bit */ 3085 3086 if (sma->disabled) 3087 val = 0; 3088 3089 if (mode == SMA_MODE_IN) 3090 val = ptp_ocp_sma_set_inputs(bp, sma_nr, val); 3091 else 3092 val = ptp_ocp_sma_set_output(bp, sma_nr, val); 3093 3094 return val; 3095} 3096 3097static int 3098ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr) 3099{ 3100 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1]; 3101 enum ptp_ocp_sma_mode mode; 3102 int val; 3103 3104 mode = sma->mode; 3105 val = sma_parse_inputs(bp->sma_op->tbl, buf, &mode); 3106 if (val < 0) 3107 return val; 3108 return ptp_ocp_sma_store_val(bp, val, mode, sma_nr); 3109} 3110 3111static ssize_t 3112sma1_store(struct device *dev, struct device_attribute *attr, 3113 const char *buf, size_t count) 3114{ 3115 struct ptp_ocp *bp = dev_get_drvdata(dev); 3116 int err; 3117 3118 err = ptp_ocp_sma_store(bp, buf, 1); 3119 return err ? err : count; 3120} 3121 3122static ssize_t 3123sma2_store(struct device *dev, struct device_attribute *attr, 3124 const char *buf, size_t count) 3125{ 3126 struct ptp_ocp *bp = dev_get_drvdata(dev); 3127 int err; 3128 3129 err = ptp_ocp_sma_store(bp, buf, 2); 3130 return err ? err : count; 3131} 3132 3133static ssize_t 3134sma3_store(struct device *dev, struct device_attribute *attr, 3135 const char *buf, size_t count) 3136{ 3137 struct ptp_ocp *bp = dev_get_drvdata(dev); 3138 int err; 3139 3140 err = ptp_ocp_sma_store(bp, buf, 3); 3141 return err ? err : count; 3142} 3143 3144static ssize_t 3145sma4_store(struct device *dev, struct device_attribute *attr, 3146 const char *buf, size_t count) 3147{ 3148 struct ptp_ocp *bp = dev_get_drvdata(dev); 3149 int err; 3150 3151 err = ptp_ocp_sma_store(bp, buf, 4); 3152 return err ? err : count; 3153} 3154static DEVICE_ATTR_RW(sma1); 3155static DEVICE_ATTR_RW(sma2); 3156static DEVICE_ATTR_RW(sma3); 3157static DEVICE_ATTR_RW(sma4); 3158 3159static ssize_t 3160available_sma_inputs_show(struct device *dev, 3161 struct device_attribute *attr, char *buf) 3162{ 3163 struct ptp_ocp *bp = dev_get_drvdata(dev); 3164 3165 return ptp_ocp_select_table_show(bp->sma_op->tbl[0], buf); 3166} 3167static DEVICE_ATTR_RO(available_sma_inputs); 3168 3169static ssize_t 3170available_sma_outputs_show(struct device *dev, 3171 struct device_attribute *attr, char *buf) 3172{ 3173 struct ptp_ocp *bp = dev_get_drvdata(dev); 3174 3175 return ptp_ocp_select_table_show(bp->sma_op->tbl[1], buf); 3176} 3177static DEVICE_ATTR_RO(available_sma_outputs); 3178 3179#define EXT_ATTR_RO(_group, _name, _val) \ 3180 struct dev_ext_attribute dev_attr_##_group##_val##_##_name = \ 3181 { __ATTR_RO(_name), (void *)_val } 3182#define EXT_ATTR_RW(_group, _name, _val) \ 3183 struct dev_ext_attribute dev_attr_##_group##_val##_##_name = \ 3184 { __ATTR_RW(_name), (void *)_val } 3185#define to_ext_attr(x) container_of(x, struct dev_ext_attribute, attr) 3186 3187/* period [duty [phase [polarity]]] */ 3188static ssize_t 3189signal_store(struct device *dev, struct device_attribute *attr, 3190 const char *buf, size_t count) 3191{ 3192 struct dev_ext_attribute *ea = to_ext_attr(attr); 3193 struct ptp_ocp *bp = dev_get_drvdata(dev); 3194 struct ptp_ocp_signal s = { }; 3195 int gen = (uintptr_t)ea->var; 3196 int argc, err; 3197 char **argv; 3198 3199 argv = argv_split(GFP_KERNEL, buf, &argc); 3200 if (!argv) 3201 return -ENOMEM; 3202 3203 err = -EINVAL; 3204 s.duty = bp->signal[gen].duty; 3205 s.phase = bp->signal[gen].phase; 3206 s.period = bp->signal[gen].period; 3207 s.polarity = bp->signal[gen].polarity; 3208 3209 switch (argc) { 3210 case 4: 3211 argc--; 3212 err = kstrtobool(argv[argc], &s.polarity); 3213 if (err) 3214 goto out; 3215 fallthrough; 3216 case 3: 3217 argc--; 3218 err = kstrtou64(argv[argc], 0, &s.phase); 3219 if (err) 3220 goto out; 3221 fallthrough; 3222 case 2: 3223 argc--; 3224 err = kstrtoint(argv[argc], 0, &s.duty); 3225 if (err) 3226 goto out; 3227 fallthrough; 3228 case 1: 3229 argc--; 3230 err = kstrtou64(argv[argc], 0, &s.period); 3231 if (err) 3232 goto out; 3233 break; 3234 default: 3235 goto out; 3236 } 3237 3238 err = ptp_ocp_signal_set(bp, gen, &s); 3239 if (err) 3240 goto out; 3241 3242 err = ptp_ocp_signal_enable(bp->signal_out[gen], gen, s.period != 0); 3243 3244out: 3245 argv_free(argv); 3246 return err ? err : count; 3247} 3248 3249static ssize_t 3250signal_show(struct device *dev, struct device_attribute *attr, char *buf) 3251{ 3252 struct dev_ext_attribute *ea = to_ext_attr(attr); 3253 struct ptp_ocp *bp = dev_get_drvdata(dev); 3254 struct ptp_ocp_signal *signal; 3255 int gen = (uintptr_t)ea->var; 3256 struct timespec64 ts; 3257 3258 signal = &bp->signal[gen]; 3259 3260 ts = ktime_to_timespec64(signal->start); 3261 3262 return sysfs_emit(buf, "%llu %d %llu %d %ptT TAI\n", 3263 signal->period, signal->duty, signal->phase, signal->polarity, 3264 &ts.tv_sec); 3265} 3266static EXT_ATTR_RW(signal, signal, 0); 3267static EXT_ATTR_RW(signal, signal, 1); 3268static EXT_ATTR_RW(signal, signal, 2); 3269static EXT_ATTR_RW(signal, signal, 3); 3270 3271static ssize_t 3272duty_show(struct device *dev, struct device_attribute *attr, char *buf) 3273{ 3274 struct dev_ext_attribute *ea = to_ext_attr(attr); 3275 struct ptp_ocp *bp = dev_get_drvdata(dev); 3276 int i = (uintptr_t)ea->var; 3277 3278 return sysfs_emit(buf, "%d\n", bp->signal[i].duty); 3279} 3280static EXT_ATTR_RO(signal, duty, 0); 3281static EXT_ATTR_RO(signal, duty, 1); 3282static EXT_ATTR_RO(signal, duty, 2); 3283static EXT_ATTR_RO(signal, duty, 3); 3284 3285static ssize_t 3286period_show(struct device *dev, struct device_attribute *attr, char *buf) 3287{ 3288 struct dev_ext_attribute *ea = to_ext_attr(attr); 3289 struct ptp_ocp *bp = dev_get_drvdata(dev); 3290 int i = (uintptr_t)ea->var; 3291 3292 return sysfs_emit(buf, "%llu\n", bp->signal[i].period); 3293} 3294static EXT_ATTR_RO(signal, period, 0); 3295static EXT_ATTR_RO(signal, period, 1); 3296static EXT_ATTR_RO(signal, period, 2); 3297static EXT_ATTR_RO(signal, period, 3); 3298 3299static ssize_t 3300phase_show(struct device *dev, struct device_attribute *attr, char *buf) 3301{ 3302 struct dev_ext_attribute *ea = to_ext_attr(attr); 3303 struct ptp_ocp *bp = dev_get_drvdata(dev); 3304 int i = (uintptr_t)ea->var; 3305 3306 return sysfs_emit(buf, "%llu\n", bp->signal[i].phase); 3307} 3308static EXT_ATTR_RO(signal, phase, 0); 3309static EXT_ATTR_RO(signal, phase, 1); 3310static EXT_ATTR_RO(signal, phase, 2); 3311static EXT_ATTR_RO(signal, phase, 3); 3312 3313static ssize_t 3314polarity_show(struct device *dev, struct device_attribute *attr, 3315 char *buf) 3316{ 3317 struct dev_ext_attribute *ea = to_ext_attr(attr); 3318 struct ptp_ocp *bp = dev_get_drvdata(dev); 3319 int i = (uintptr_t)ea->var; 3320 3321 return sysfs_emit(buf, "%d\n", bp->signal[i].polarity); 3322} 3323static EXT_ATTR_RO(signal, polarity, 0); 3324static EXT_ATTR_RO(signal, polarity, 1); 3325static EXT_ATTR_RO(signal, polarity, 2); 3326static EXT_ATTR_RO(signal, polarity, 3); 3327 3328static ssize_t 3329running_show(struct device *dev, struct device_attribute *attr, char *buf) 3330{ 3331 struct dev_ext_attribute *ea = to_ext_attr(attr); 3332 struct ptp_ocp *bp = dev_get_drvdata(dev); 3333 int i = (uintptr_t)ea->var; 3334 3335 return sysfs_emit(buf, "%d\n", bp->signal[i].running); 3336} 3337static EXT_ATTR_RO(signal, running, 0); 3338static EXT_ATTR_RO(signal, running, 1); 3339static EXT_ATTR_RO(signal, running, 2); 3340static EXT_ATTR_RO(signal, running, 3); 3341 3342static ssize_t 3343start_show(struct device *dev, struct device_attribute *attr, char *buf) 3344{ 3345 struct dev_ext_attribute *ea = to_ext_attr(attr); 3346 struct ptp_ocp *bp = dev_get_drvdata(dev); 3347 int i = (uintptr_t)ea->var; 3348 struct timespec64 ts; 3349 3350 ts = ktime_to_timespec64(bp->signal[i].start); 3351 return sysfs_emit(buf, "%llu.%lu\n", ts.tv_sec, ts.tv_nsec); 3352} 3353static EXT_ATTR_RO(signal, start, 0); 3354static EXT_ATTR_RO(signal, start, 1); 3355static EXT_ATTR_RO(signal, start, 2); 3356static EXT_ATTR_RO(signal, start, 3); 3357 3358static ssize_t 3359seconds_store(struct device *dev, struct device_attribute *attr, 3360 const char *buf, size_t count) 3361{ 3362 struct dev_ext_attribute *ea = to_ext_attr(attr); 3363 struct ptp_ocp *bp = dev_get_drvdata(dev); 3364 int idx = (uintptr_t)ea->var; 3365 u32 val; 3366 int err; 3367 3368 err = kstrtou32(buf, 0, &val); 3369 if (err) 3370 return err; 3371 if (val > 0xff) 3372 return -EINVAL; 3373 3374 if (val) 3375 val = (val << 8) | 0x1; 3376 3377 iowrite32(val, &bp->freq_in[idx]->ctrl); 3378 3379 return count; 3380} 3381 3382static ssize_t 3383seconds_show(struct device *dev, struct device_attribute *attr, char *buf) 3384{ 3385 struct dev_ext_attribute *ea = to_ext_attr(attr); 3386 struct ptp_ocp *bp = dev_get_drvdata(dev); 3387 int idx = (uintptr_t)ea->var; 3388 u32 val; 3389 3390 val = ioread32(&bp->freq_in[idx]->ctrl); 3391 if (val & 1) 3392 val = (val >> 8) & 0xff; 3393 else 3394 val = 0; 3395 3396 return sysfs_emit(buf, "%u\n", val); 3397} 3398static EXT_ATTR_RW(freq, seconds, 0); 3399static EXT_ATTR_RW(freq, seconds, 1); 3400static EXT_ATTR_RW(freq, seconds, 2); 3401static EXT_ATTR_RW(freq, seconds, 3); 3402 3403static ssize_t 3404frequency_show(struct device *dev, struct device_attribute *attr, char *buf) 3405{ 3406 struct dev_ext_attribute *ea = to_ext_attr(attr); 3407 struct ptp_ocp *bp = dev_get_drvdata(dev); 3408 int idx = (uintptr_t)ea->var; 3409 u32 val; 3410 3411 val = ioread32(&bp->freq_in[idx]->status); 3412 if (val & FREQ_STATUS_ERROR) 3413 return sysfs_emit(buf, "error\n"); 3414 if (val & FREQ_STATUS_OVERRUN) 3415 return sysfs_emit(buf, "overrun\n"); 3416 if (val & FREQ_STATUS_VALID) 3417 return sysfs_emit(buf, "%lu\n", val & FREQ_STATUS_MASK); 3418 return 0; 3419} 3420static EXT_ATTR_RO(freq, frequency, 0); 3421static EXT_ATTR_RO(freq, frequency, 1); 3422static EXT_ATTR_RO(freq, frequency, 2); 3423static EXT_ATTR_RO(freq, frequency, 3); 3424 3425static ssize_t 3426ptp_ocp_tty_show(struct device *dev, struct device_attribute *attr, char *buf) 3427{ 3428 struct dev_ext_attribute *ea = to_ext_attr(attr); 3429 struct ptp_ocp *bp = dev_get_drvdata(dev); 3430 3431 /* 3432 * NOTE: This output does not include a trailing newline for backward 3433 * compatibility. Existing userspace software uses this value directly 3434 * as a device path (e.g., "/dev/ttyS4"), and adding a newline would 3435 * break those applications. Do not add a newline to this output. 3436 */ 3437 return sysfs_emit(buf, "ttyS%d", bp->port[(uintptr_t)ea->var].line); 3438} 3439 3440static umode_t 3441ptp_ocp_timecard_tty_is_visible(struct kobject *kobj, struct attribute *attr, int n) 3442{ 3443 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj)); 3444 struct ptp_ocp_serial_port *port; 3445 struct device_attribute *dattr; 3446 struct dev_ext_attribute *ea; 3447 3448 if (strncmp(attr->name, "tty", 3)) 3449 return attr->mode; 3450 3451 dattr = container_of(attr, struct device_attribute, attr); 3452 ea = container_of(dattr, struct dev_ext_attribute, attr); 3453 port = &bp->port[(uintptr_t)ea->var]; 3454 return port->line == -1 ? 0 : 0444; 3455} 3456 3457#define EXT_TTY_ATTR_RO(_name, _val) \ 3458 struct dev_ext_attribute dev_attr_tty##_name = \ 3459 { __ATTR(tty##_name, 0444, ptp_ocp_tty_show, NULL), (void *)_val } 3460 3461static EXT_TTY_ATTR_RO(GNSS, PORT_GNSS); 3462static EXT_TTY_ATTR_RO(GNSS2, PORT_GNSS2); 3463static EXT_TTY_ATTR_RO(MAC, PORT_MAC); 3464static EXT_TTY_ATTR_RO(NMEA, PORT_NMEA); 3465static struct attribute *ptp_ocp_timecard_tty_attrs[] = { 3466 &dev_attr_ttyGNSS.attr.attr, 3467 &dev_attr_ttyGNSS2.attr.attr, 3468 &dev_attr_ttyMAC.attr.attr, 3469 &dev_attr_ttyNMEA.attr.attr, 3470 NULL, 3471}; 3472 3473static const struct attribute_group ptp_ocp_timecard_tty_group = { 3474 .name = "tty", 3475 .attrs = ptp_ocp_timecard_tty_attrs, 3476 .is_visible = ptp_ocp_timecard_tty_is_visible, 3477}; 3478 3479static ssize_t 3480serialnum_show(struct device *dev, struct device_attribute *attr, char *buf) 3481{ 3482 struct ptp_ocp *bp = dev_get_drvdata(dev); 3483 3484 if (!bp->has_eeprom_data) 3485 ptp_ocp_read_eeprom(bp); 3486 3487 return sysfs_emit(buf, "%pM\n", bp->serial); 3488} 3489static DEVICE_ATTR_RO(serialnum); 3490 3491static ssize_t 3492gnss_sync_show(struct device *dev, struct device_attribute *attr, char *buf) 3493{ 3494 struct ptp_ocp *bp = dev_get_drvdata(dev); 3495 ssize_t ret; 3496 3497 if (bp->gnss_lost) 3498 ret = sysfs_emit(buf, "LOST @ %ptT\n", &bp->gnss_lost); 3499 else 3500 ret = sysfs_emit(buf, "SYNC\n"); 3501 3502 return ret; 3503} 3504static DEVICE_ATTR_RO(gnss_sync); 3505 3506static ssize_t 3507utc_tai_offset_show(struct device *dev, 3508 struct device_attribute *attr, char *buf) 3509{ 3510 struct ptp_ocp *bp = dev_get_drvdata(dev); 3511 3512 return sysfs_emit(buf, "%d\n", bp->utc_tai_offset); 3513} 3514 3515static ssize_t 3516utc_tai_offset_store(struct device *dev, 3517 struct device_attribute *attr, 3518 const char *buf, size_t count) 3519{ 3520 struct ptp_ocp *bp = dev_get_drvdata(dev); 3521 int err; 3522 u32 val; 3523 3524 err = kstrtou32(buf, 0, &val); 3525 if (err) 3526 return err; 3527 3528 ptp_ocp_utc_distribute(bp, val); 3529 3530 return count; 3531} 3532static DEVICE_ATTR_RW(utc_tai_offset); 3533 3534static ssize_t 3535ts_window_adjust_show(struct device *dev, 3536 struct device_attribute *attr, char *buf) 3537{ 3538 struct ptp_ocp *bp = dev_get_drvdata(dev); 3539 3540 return sysfs_emit(buf, "%d\n", bp->ts_window_adjust); 3541} 3542 3543static ssize_t 3544ts_window_adjust_store(struct device *dev, 3545 struct device_attribute *attr, 3546 const char *buf, size_t count) 3547{ 3548 struct ptp_ocp *bp = dev_get_drvdata(dev); 3549 int err; 3550 u32 val; 3551 3552 err = kstrtou32(buf, 0, &val); 3553 if (err) 3554 return err; 3555 3556 bp->ts_window_adjust = val; 3557 3558 return count; 3559} 3560static DEVICE_ATTR_RW(ts_window_adjust); 3561 3562static ssize_t 3563irig_b_mode_show(struct device *dev, struct device_attribute *attr, char *buf) 3564{ 3565 struct ptp_ocp *bp = dev_get_drvdata(dev); 3566 u32 val; 3567 3568 val = ioread32(&bp->irig_out->ctrl); 3569 val = (val >> 16) & 0x07; 3570 return sysfs_emit(buf, "%d\n", val); 3571} 3572 3573static ssize_t 3574irig_b_mode_store(struct device *dev, 3575 struct device_attribute *attr, 3576 const char *buf, size_t count) 3577{ 3578 struct ptp_ocp *bp = dev_get_drvdata(dev); 3579 unsigned long flags; 3580 int err; 3581 u32 reg; 3582 u8 val; 3583 3584 err = kstrtou8(buf, 0, &val); 3585 if (err) 3586 return err; 3587 if (val > 7) 3588 return -EINVAL; 3589 3590 reg = ((val & 0x7) << 16); 3591 3592 spin_lock_irqsave(&bp->lock, flags); 3593 iowrite32(0, &bp->irig_out->ctrl); /* disable */ 3594 iowrite32(reg, &bp->irig_out->ctrl); /* change mode */ 3595 iowrite32(reg | IRIG_M_CTRL_ENABLE, &bp->irig_out->ctrl); 3596 spin_unlock_irqrestore(&bp->lock, flags); 3597 3598 return count; 3599} 3600static DEVICE_ATTR_RW(irig_b_mode); 3601 3602static ssize_t 3603clock_source_show(struct device *dev, struct device_attribute *attr, char *buf) 3604{ 3605 struct ptp_ocp *bp = dev_get_drvdata(dev); 3606 const char *p; 3607 u32 select; 3608 3609 select = ioread32(&bp->reg->select); 3610 p = ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16); 3611 3612 return sysfs_emit(buf, "%s\n", p); 3613} 3614 3615static ssize_t 3616clock_source_store(struct device *dev, struct device_attribute *attr, 3617 const char *buf, size_t count) 3618{ 3619 struct ptp_ocp *bp = dev_get_drvdata(dev); 3620 unsigned long flags; 3621 int val; 3622 3623 val = ptp_ocp_select_val_from_name(ptp_ocp_clock, buf); 3624 if (val < 0) 3625 return val; 3626 3627 spin_lock_irqsave(&bp->lock, flags); 3628 iowrite32(val, &bp->reg->select); 3629 spin_unlock_irqrestore(&bp->lock, flags); 3630 3631 return count; 3632} 3633static DEVICE_ATTR_RW(clock_source); 3634 3635static ssize_t 3636available_clock_sources_show(struct device *dev, 3637 struct device_attribute *attr, char *buf) 3638{ 3639 return ptp_ocp_select_table_show(ptp_ocp_clock, buf); 3640} 3641static DEVICE_ATTR_RO(available_clock_sources); 3642 3643static ssize_t 3644clock_status_drift_show(struct device *dev, 3645 struct device_attribute *attr, char *buf) 3646{ 3647 struct ptp_ocp *bp = dev_get_drvdata(dev); 3648 u32 val; 3649 int res; 3650 3651 val = ioread32(&bp->reg->status_drift); 3652 res = (val & ~INT_MAX) ? -1 : 1; 3653 res *= (val & INT_MAX); 3654 return sysfs_emit(buf, "%d\n", res); 3655} 3656static DEVICE_ATTR_RO(clock_status_drift); 3657 3658static ssize_t 3659clock_status_offset_show(struct device *dev, 3660 struct device_attribute *attr, char *buf) 3661{ 3662 struct ptp_ocp *bp = dev_get_drvdata(dev); 3663 u32 val; 3664 int res; 3665 3666 val = ioread32(&bp->reg->status_offset); 3667 res = (val & ~INT_MAX) ? -1 : 1; 3668 res *= (val & INT_MAX); 3669 return sysfs_emit(buf, "%d\n", res); 3670} 3671static DEVICE_ATTR_RO(clock_status_offset); 3672 3673static ssize_t 3674tod_correction_show(struct device *dev, 3675 struct device_attribute *attr, char *buf) 3676{ 3677 struct ptp_ocp *bp = dev_get_drvdata(dev); 3678 u32 val; 3679 int res; 3680 3681 val = ioread32(&bp->tod->adj_sec); 3682 res = (val & ~INT_MAX) ? -1 : 1; 3683 res *= (val & INT_MAX); 3684 return sysfs_emit(buf, "%d\n", res); 3685} 3686 3687static ssize_t 3688tod_correction_store(struct device *dev, struct device_attribute *attr, 3689 const char *buf, size_t count) 3690{ 3691 struct ptp_ocp *bp = dev_get_drvdata(dev); 3692 unsigned long flags; 3693 int err, res; 3694 u32 val = 0; 3695 3696 err = kstrtos32(buf, 0, &res); 3697 if (err) 3698 return err; 3699 if (res < 0) { 3700 res *= -1; 3701 val |= BIT(31); 3702 } 3703 val |= res; 3704 3705 spin_lock_irqsave(&bp->lock, flags); 3706 iowrite32(val, &bp->tod->adj_sec); 3707 spin_unlock_irqrestore(&bp->lock, flags); 3708 3709 return count; 3710} 3711static DEVICE_ATTR_RW(tod_correction); 3712 3713#define _DEVICE_SIGNAL_GROUP_ATTRS(_nr) \ 3714 static struct attribute *fb_timecard_signal##_nr##_attrs[] = { \ 3715 &dev_attr_signal##_nr##_signal.attr.attr, \ 3716 &dev_attr_signal##_nr##_duty.attr.attr, \ 3717 &dev_attr_signal##_nr##_phase.attr.attr, \ 3718 &dev_attr_signal##_nr##_period.attr.attr, \ 3719 &dev_attr_signal##_nr##_polarity.attr.attr, \ 3720 &dev_attr_signal##_nr##_running.attr.attr, \ 3721 &dev_attr_signal##_nr##_start.attr.attr, \ 3722 NULL, \ 3723 } 3724 3725#define DEVICE_SIGNAL_GROUP(_name, _nr) \ 3726 _DEVICE_SIGNAL_GROUP_ATTRS(_nr); \ 3727 static const struct attribute_group \ 3728 fb_timecard_signal##_nr##_group = { \ 3729 .name = #_name, \ 3730 .attrs = fb_timecard_signal##_nr##_attrs, \ 3731} 3732 3733DEVICE_SIGNAL_GROUP(gen1, 0); 3734DEVICE_SIGNAL_GROUP(gen2, 1); 3735DEVICE_SIGNAL_GROUP(gen3, 2); 3736DEVICE_SIGNAL_GROUP(gen4, 3); 3737 3738#define _DEVICE_FREQ_GROUP_ATTRS(_nr) \ 3739 static struct attribute *fb_timecard_freq##_nr##_attrs[] = { \ 3740 &dev_attr_freq##_nr##_seconds.attr.attr, \ 3741 &dev_attr_freq##_nr##_frequency.attr.attr, \ 3742 NULL, \ 3743 } 3744 3745#define DEVICE_FREQ_GROUP(_name, _nr) \ 3746 _DEVICE_FREQ_GROUP_ATTRS(_nr); \ 3747 static const struct attribute_group \ 3748 fb_timecard_freq##_nr##_group = { \ 3749 .name = #_name, \ 3750 .attrs = fb_timecard_freq##_nr##_attrs, \ 3751} 3752 3753DEVICE_FREQ_GROUP(freq1, 0); 3754DEVICE_FREQ_GROUP(freq2, 1); 3755DEVICE_FREQ_GROUP(freq3, 2); 3756DEVICE_FREQ_GROUP(freq4, 3); 3757 3758static ssize_t 3759disciplining_config_read(struct file *filp, struct kobject *kobj, 3760 const struct bin_attribute *bin_attr, char *buf, 3761 loff_t off, size_t count) 3762{ 3763 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj)); 3764 size_t size = OCP_ART_CONFIG_SIZE; 3765 struct nvmem_device *nvmem; 3766 ssize_t err; 3767 3768 nvmem = ptp_ocp_nvmem_device_get(bp, NULL); 3769 if (IS_ERR(nvmem)) 3770 return PTR_ERR(nvmem); 3771 3772 if (off > size) { 3773 err = 0; 3774 goto out; 3775 } 3776 3777 if (off + count > size) 3778 count = size - off; 3779 3780 // the configuration is in the very beginning of the EEPROM 3781 err = nvmem_device_read(nvmem, off, count, buf); 3782 if (err != count) { 3783 err = -EFAULT; 3784 goto out; 3785 } 3786 3787out: 3788 ptp_ocp_nvmem_device_put(&nvmem); 3789 3790 return err; 3791} 3792 3793static ssize_t 3794disciplining_config_write(struct file *filp, struct kobject *kobj, 3795 const struct bin_attribute *bin_attr, char *buf, 3796 loff_t off, size_t count) 3797{ 3798 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj)); 3799 struct nvmem_device *nvmem; 3800 ssize_t err; 3801 3802 /* Allow write of the whole area only */ 3803 if (off || count != OCP_ART_CONFIG_SIZE) 3804 return -EFAULT; 3805 3806 nvmem = ptp_ocp_nvmem_device_get(bp, NULL); 3807 if (IS_ERR(nvmem)) 3808 return PTR_ERR(nvmem); 3809 3810 err = nvmem_device_write(nvmem, 0x00, count, buf); 3811 if (err != count) 3812 err = -EFAULT; 3813 3814 ptp_ocp_nvmem_device_put(&nvmem); 3815 3816 return err; 3817} 3818static const BIN_ATTR_RW(disciplining_config, OCP_ART_CONFIG_SIZE); 3819 3820static ssize_t 3821temperature_table_read(struct file *filp, struct kobject *kobj, 3822 const struct bin_attribute *bin_attr, char *buf, 3823 loff_t off, size_t count) 3824{ 3825 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj)); 3826 size_t size = OCP_ART_TEMP_TABLE_SIZE; 3827 struct nvmem_device *nvmem; 3828 ssize_t err; 3829 3830 nvmem = ptp_ocp_nvmem_device_get(bp, NULL); 3831 if (IS_ERR(nvmem)) 3832 return PTR_ERR(nvmem); 3833 3834 if (off > size) { 3835 err = 0; 3836 goto out; 3837 } 3838 3839 if (off + count > size) 3840 count = size - off; 3841 3842 // the configuration is in the very beginning of the EEPROM 3843 err = nvmem_device_read(nvmem, 0x90 + off, count, buf); 3844 if (err != count) { 3845 err = -EFAULT; 3846 goto out; 3847 } 3848 3849out: 3850 ptp_ocp_nvmem_device_put(&nvmem); 3851 3852 return err; 3853} 3854 3855static ssize_t 3856temperature_table_write(struct file *filp, struct kobject *kobj, 3857 const struct bin_attribute *bin_attr, char *buf, 3858 loff_t off, size_t count) 3859{ 3860 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj)); 3861 struct nvmem_device *nvmem; 3862 ssize_t err; 3863 3864 /* Allow write of the whole area only */ 3865 if (off || count != OCP_ART_TEMP_TABLE_SIZE) 3866 return -EFAULT; 3867 3868 nvmem = ptp_ocp_nvmem_device_get(bp, NULL); 3869 if (IS_ERR(nvmem)) 3870 return PTR_ERR(nvmem); 3871 3872 err = nvmem_device_write(nvmem, 0x90, count, buf); 3873 if (err != count) 3874 err = -EFAULT; 3875 3876 ptp_ocp_nvmem_device_put(&nvmem); 3877 3878 return err; 3879} 3880static const BIN_ATTR_RW(temperature_table, OCP_ART_TEMP_TABLE_SIZE); 3881 3882static struct attribute *fb_timecard_attrs[] = { 3883 &dev_attr_serialnum.attr, 3884 &dev_attr_gnss_sync.attr, 3885 &dev_attr_clock_source.attr, 3886 &dev_attr_available_clock_sources.attr, 3887 &dev_attr_sma1.attr, 3888 &dev_attr_sma2.attr, 3889 &dev_attr_sma3.attr, 3890 &dev_attr_sma4.attr, 3891 &dev_attr_available_sma_inputs.attr, 3892 &dev_attr_available_sma_outputs.attr, 3893 &dev_attr_clock_status_drift.attr, 3894 &dev_attr_clock_status_offset.attr, 3895 &dev_attr_irig_b_mode.attr, 3896 &dev_attr_utc_tai_offset.attr, 3897 &dev_attr_ts_window_adjust.attr, 3898 &dev_attr_tod_correction.attr, 3899 NULL, 3900}; 3901 3902static const struct attribute_group fb_timecard_group = { 3903 .attrs = fb_timecard_attrs, 3904}; 3905 3906static const struct ocp_attr_group fb_timecard_groups[] = { 3907 { .cap = OCP_CAP_BASIC, .group = &fb_timecard_group }, 3908 { .cap = OCP_CAP_BASIC, .group = &ptp_ocp_timecard_tty_group }, 3909 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal0_group }, 3910 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal1_group }, 3911 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal2_group }, 3912 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal3_group }, 3913 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq0_group }, 3914 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq1_group }, 3915 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq2_group }, 3916 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq3_group }, 3917 { }, 3918}; 3919 3920static struct attribute *art_timecard_attrs[] = { 3921 &dev_attr_serialnum.attr, 3922 &dev_attr_clock_source.attr, 3923 &dev_attr_available_clock_sources.attr, 3924 &dev_attr_utc_tai_offset.attr, 3925 &dev_attr_ts_window_adjust.attr, 3926 &dev_attr_sma1.attr, 3927 &dev_attr_sma2.attr, 3928 &dev_attr_sma3.attr, 3929 &dev_attr_sma4.attr, 3930 &dev_attr_available_sma_inputs.attr, 3931 &dev_attr_available_sma_outputs.attr, 3932 NULL, 3933}; 3934 3935static const struct bin_attribute *const bin_art_timecard_attrs[] = { 3936 &bin_attr_disciplining_config, 3937 &bin_attr_temperature_table, 3938 NULL, 3939}; 3940 3941static const struct attribute_group art_timecard_group = { 3942 .attrs = art_timecard_attrs, 3943 .bin_attrs = bin_art_timecard_attrs, 3944}; 3945 3946static const struct ocp_attr_group art_timecard_groups[] = { 3947 { .cap = OCP_CAP_BASIC, .group = &art_timecard_group }, 3948 { .cap = OCP_CAP_BASIC, .group = &ptp_ocp_timecard_tty_group }, 3949 { }, 3950}; 3951 3952static struct attribute *adva_timecard_attrs[] = { 3953 &dev_attr_serialnum.attr, 3954 &dev_attr_gnss_sync.attr, 3955 &dev_attr_clock_source.attr, 3956 &dev_attr_available_clock_sources.attr, 3957 &dev_attr_sma1.attr, 3958 &dev_attr_sma2.attr, 3959 &dev_attr_sma3.attr, 3960 &dev_attr_sma4.attr, 3961 &dev_attr_available_sma_inputs.attr, 3962 &dev_attr_available_sma_outputs.attr, 3963 &dev_attr_clock_status_drift.attr, 3964 &dev_attr_clock_status_offset.attr, 3965 &dev_attr_ts_window_adjust.attr, 3966 &dev_attr_tod_correction.attr, 3967 NULL, 3968}; 3969 3970static const struct attribute_group adva_timecard_group = { 3971 .attrs = adva_timecard_attrs, 3972}; 3973 3974static const struct ocp_attr_group adva_timecard_groups[] = { 3975 { .cap = OCP_CAP_BASIC, .group = &adva_timecard_group }, 3976 { .cap = OCP_CAP_BASIC, .group = &ptp_ocp_timecard_tty_group }, 3977 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal0_group }, 3978 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal1_group }, 3979 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq0_group }, 3980 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq1_group }, 3981 { }, 3982}; 3983 3984static void 3985gpio_input_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit, 3986 const char *def) 3987{ 3988 int i; 3989 3990 for (i = 0; i < 4; i++) { 3991 if (bp->sma[i].mode != SMA_MODE_IN) 3992 continue; 3993 if (map[i][0] & (1 << bit)) { 3994 sprintf(buf, "sma%d", i + 1); 3995 return; 3996 } 3997 } 3998 if (!def) 3999 def = "----"; 4000 strcpy(buf, def); 4001} 4002 4003static void 4004gpio_output_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit) 4005{ 4006 char *ans = buf; 4007 int i; 4008 4009 strcpy(ans, "----"); 4010 for (i = 0; i < 4; i++) { 4011 if (bp->sma[i].mode != SMA_MODE_OUT) 4012 continue; 4013 if (map[i][1] & (1 << bit)) 4014 ans += sprintf(ans, "sma%d ", i + 1); 4015 } 4016} 4017 4018static void 4019_signal_summary_show(struct seq_file *s, struct ptp_ocp *bp, int nr) 4020{ 4021 struct signal_reg __iomem *reg = bp->signal_out[nr]->mem; 4022 struct ptp_ocp_signal *signal = &bp->signal[nr]; 4023 char label[16]; 4024 bool on; 4025 u32 val; 4026 4027 on = signal->running; 4028 sprintf(label, "GEN%d", nr + 1); 4029 seq_printf(s, "%7s: %s, period:%llu duty:%d%% phase:%llu pol:%d", 4030 label, on ? " ON" : "OFF", 4031 signal->period, signal->duty, signal->phase, 4032 signal->polarity); 4033 4034 val = ioread32(®->enable); 4035 seq_printf(s, " [%x", val); 4036 val = ioread32(®->status); 4037 seq_printf(s, " %x]", val); 4038 4039 seq_printf(s, " start:%llu\n", signal->start); 4040} 4041 4042static void 4043_frequency_summary_show(struct seq_file *s, int nr, 4044 struct frequency_reg __iomem *reg) 4045{ 4046 char label[16]; 4047 bool on; 4048 u32 val; 4049 4050 if (!reg) 4051 return; 4052 4053 sprintf(label, "FREQ%d", nr + 1); 4054 val = ioread32(®->ctrl); 4055 on = val & 1; 4056 val = (val >> 8) & 0xff; 4057 seq_printf(s, "%7s: %s, sec:%u", 4058 label, 4059 on ? " ON" : "OFF", 4060 val); 4061 4062 val = ioread32(®->status); 4063 if (val & FREQ_STATUS_ERROR) 4064 seq_printf(s, ", error"); 4065 if (val & FREQ_STATUS_OVERRUN) 4066 seq_printf(s, ", overrun"); 4067 if (val & FREQ_STATUS_VALID) 4068 seq_printf(s, ", freq %lu Hz", val & FREQ_STATUS_MASK); 4069 seq_printf(s, " reg:%x\n", val); 4070} 4071 4072static int 4073ptp_ocp_summary_show(struct seq_file *s, void *data) 4074{ 4075 struct device *dev = s->private; 4076 struct ptp_system_timestamp sts; 4077 struct ts_reg __iomem *ts_reg; 4078 char *buf, *src, *mac_src; 4079 struct timespec64 ts; 4080 struct ptp_ocp *bp; 4081 u16 sma_val[4][2]; 4082 u32 ctrl, val; 4083 bool on, map; 4084 int i; 4085 4086 buf = (char *)__get_free_page(GFP_KERNEL); 4087 if (!buf) 4088 return -ENOMEM; 4089 4090 bp = dev_get_drvdata(dev); 4091 4092 seq_printf(s, "%7s: /dev/ptp%d\n", "PTP", ptp_clock_index(bp->ptp)); 4093 for (i = 0; i < __PORT_COUNT; i++) { 4094 if (bp->port[i].line != -1) 4095 seq_printf(s, "%7s: /dev/ttyS%d\n", ptp_ocp_tty_port_name(i), 4096 bp->port[i].line); 4097 } 4098 4099 memset(sma_val, 0xff, sizeof(sma_val)); 4100 if (bp->sma_map1) { 4101 u32 reg; 4102 4103 reg = ioread32(&bp->sma_map1->gpio1); 4104 sma_val[0][0] = reg & 0xffff; 4105 sma_val[1][0] = reg >> 16; 4106 4107 reg = ioread32(&bp->sma_map1->gpio2); 4108 sma_val[2][1] = reg & 0xffff; 4109 sma_val[3][1] = reg >> 16; 4110 4111 reg = ioread32(&bp->sma_map2->gpio1); 4112 sma_val[2][0] = reg & 0xffff; 4113 sma_val[3][0] = reg >> 16; 4114 4115 reg = ioread32(&bp->sma_map2->gpio2); 4116 sma_val[0][1] = reg & 0xffff; 4117 sma_val[1][1] = reg >> 16; 4118 } 4119 4120 sma1_show(dev, NULL, buf); 4121 seq_printf(s, " sma1: %04x,%04x %s", 4122 sma_val[0][0], sma_val[0][1], buf); 4123 4124 sma2_show(dev, NULL, buf); 4125 seq_printf(s, " sma2: %04x,%04x %s", 4126 sma_val[1][0], sma_val[1][1], buf); 4127 4128 sma3_show(dev, NULL, buf); 4129 seq_printf(s, " sma3: %04x,%04x %s", 4130 sma_val[2][0], sma_val[2][1], buf); 4131 4132 sma4_show(dev, NULL, buf); 4133 seq_printf(s, " sma4: %04x,%04x %s", 4134 sma_val[3][0], sma_val[3][1], buf); 4135 4136 if (bp->ts0) { 4137 ts_reg = bp->ts0->mem; 4138 on = ioread32(&ts_reg->enable); 4139 src = "GNSS1"; 4140 seq_printf(s, "%7s: %s, src: %s\n", "TS0", 4141 on ? " ON" : "OFF", src); 4142 } 4143 4144 if (bp->ts1) { 4145 ts_reg = bp->ts1->mem; 4146 on = ioread32(&ts_reg->enable); 4147 gpio_input_map(buf, bp, sma_val, 2, NULL); 4148 seq_printf(s, "%7s: %s, src: %s\n", "TS1", 4149 on ? " ON" : "OFF", buf); 4150 } 4151 4152 if (bp->ts2) { 4153 ts_reg = bp->ts2->mem; 4154 on = ioread32(&ts_reg->enable); 4155 gpio_input_map(buf, bp, sma_val, 3, NULL); 4156 seq_printf(s, "%7s: %s, src: %s\n", "TS2", 4157 on ? " ON" : "OFF", buf); 4158 } 4159 4160 if (bp->ts3) { 4161 ts_reg = bp->ts3->mem; 4162 on = ioread32(&ts_reg->enable); 4163 gpio_input_map(buf, bp, sma_val, 6, NULL); 4164 seq_printf(s, "%7s: %s, src: %s\n", "TS3", 4165 on ? " ON" : "OFF", buf); 4166 } 4167 4168 if (bp->ts4) { 4169 ts_reg = bp->ts4->mem; 4170 on = ioread32(&ts_reg->enable); 4171 gpio_input_map(buf, bp, sma_val, 7, NULL); 4172 seq_printf(s, "%7s: %s, src: %s\n", "TS4", 4173 on ? " ON" : "OFF", buf); 4174 } 4175 4176 if (bp->pps) { 4177 ts_reg = bp->pps->mem; 4178 src = "PHC"; 4179 on = ioread32(&ts_reg->enable); 4180 map = !!(bp->pps_req_map & OCP_REQ_TIMESTAMP); 4181 seq_printf(s, "%7s: %s, src: %s\n", "TS5", 4182 on && map ? " ON" : "OFF", src); 4183 4184 map = !!(bp->pps_req_map & OCP_REQ_PPS); 4185 seq_printf(s, "%7s: %s, src: %s\n", "PPS", 4186 on && map ? " ON" : "OFF", src); 4187 } 4188 4189 if (bp->fw_cap & OCP_CAP_SIGNAL) 4190 for (i = 0; i < bp->signals_nr; i++) 4191 _signal_summary_show(s, bp, i); 4192 4193 if (bp->fw_cap & OCP_CAP_FREQ) 4194 for (i = 0; i < bp->freq_in_nr; i++) 4195 _frequency_summary_show(s, i, bp->freq_in[i]); 4196 4197 if (bp->irig_out) { 4198 ctrl = ioread32(&bp->irig_out->ctrl); 4199 on = ctrl & IRIG_M_CTRL_ENABLE; 4200 val = ioread32(&bp->irig_out->status); 4201 gpio_output_map(buf, bp, sma_val, 4); 4202 seq_printf(s, "%7s: %s, error: %d, mode %d, out: %s\n", "IRIG", 4203 on ? " ON" : "OFF", val, (ctrl >> 16), buf); 4204 } 4205 4206 if (bp->irig_in) { 4207 on = ioread32(&bp->irig_in->ctrl) & IRIG_S_CTRL_ENABLE; 4208 val = ioread32(&bp->irig_in->status); 4209 gpio_input_map(buf, bp, sma_val, 4, NULL); 4210 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "IRIG in", 4211 on ? " ON" : "OFF", val, buf); 4212 } 4213 4214 if (bp->dcf_out) { 4215 on = ioread32(&bp->dcf_out->ctrl) & DCF_M_CTRL_ENABLE; 4216 val = ioread32(&bp->dcf_out->status); 4217 gpio_output_map(buf, bp, sma_val, 5); 4218 seq_printf(s, "%7s: %s, error: %d, out: %s\n", "DCF", 4219 on ? " ON" : "OFF", val, buf); 4220 } 4221 4222 if (bp->dcf_in) { 4223 on = ioread32(&bp->dcf_in->ctrl) & DCF_S_CTRL_ENABLE; 4224 val = ioread32(&bp->dcf_in->status); 4225 gpio_input_map(buf, bp, sma_val, 5, NULL); 4226 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "DCF in", 4227 on ? " ON" : "OFF", val, buf); 4228 } 4229 4230 if (bp->nmea_out) { 4231 on = ioread32(&bp->nmea_out->ctrl) & 1; 4232 val = ioread32(&bp->nmea_out->status); 4233 seq_printf(s, "%7s: %s, error: %d\n", "NMEA", 4234 on ? " ON" : "OFF", val); 4235 } 4236 4237 /* compute src for PPS1, used below. */ 4238 if (bp->pps_select) { 4239 val = ioread32(&bp->pps_select->gpio1); 4240 src = &buf[80]; 4241 mac_src = "GNSS1"; 4242 if (val & 0x01) { 4243 gpio_input_map(src, bp, sma_val, 0, NULL); 4244 mac_src = src; 4245 } else if (val & 0x02) { 4246 src = "MAC"; 4247 } else if (val & 0x04) { 4248 src = "GNSS1"; 4249 } else { 4250 src = "----"; 4251 mac_src = src; 4252 } 4253 } else { 4254 src = "?"; 4255 mac_src = src; 4256 } 4257 seq_printf(s, "MAC PPS1 src: %s\n", mac_src); 4258 4259 gpio_input_map(buf, bp, sma_val, 1, "GNSS2"); 4260 seq_printf(s, "MAC PPS2 src: %s\n", buf); 4261 4262 /* assumes automatic switchover/selection */ 4263 val = ioread32(&bp->reg->select); 4264 switch (val >> 16) { 4265 case 0: 4266 sprintf(buf, "----"); 4267 break; 4268 case 2: 4269 sprintf(buf, "IRIG"); 4270 break; 4271 case 3: 4272 sprintf(buf, "%s via PPS1", src); 4273 break; 4274 case 6: 4275 sprintf(buf, "DCF"); 4276 break; 4277 default: 4278 strcpy(buf, "unknown"); 4279 break; 4280 } 4281 seq_printf(s, "%7s: %s, state: %s\n", "PHC src", buf, 4282 bp->sync ? "sync" : "unsynced"); 4283 4284 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts)) { 4285 struct timespec64 sys_ts; 4286 s64 pre_ns, post_ns, ns; 4287 4288 pre_ns = timespec64_to_ns(&sts.pre_ts); 4289 post_ns = timespec64_to_ns(&sts.post_ts); 4290 ns = (pre_ns + post_ns) / 2; 4291 ns += (s64)bp->utc_tai_offset * NSEC_PER_SEC; 4292 sys_ts = ns_to_timespec64(ns); 4293 4294 seq_printf(s, "%7s: %ptSp == %ptS TAI\n", "PHC", &ts, &ts); 4295 seq_printf(s, "%7s: %ptSp == %ptS UTC offset %d\n", "SYS", 4296 &sys_ts, &sys_ts, bp->utc_tai_offset); 4297 seq_printf(s, "%7s: PHC:SYS offset: %lld window: %lld\n", "", 4298 timespec64_to_ns(&ts) - ns, 4299 post_ns - pre_ns); 4300 } 4301 4302 free_page((unsigned long)buf); 4303 return 0; 4304} 4305DEFINE_SHOW_ATTRIBUTE(ptp_ocp_summary); 4306 4307static int 4308ptp_ocp_tod_status_show(struct seq_file *s, void *data) 4309{ 4310 struct device *dev = s->private; 4311 struct ptp_ocp *bp; 4312 u32 val; 4313 int idx; 4314 4315 bp = dev_get_drvdata(dev); 4316 4317 val = ioread32(&bp->tod->ctrl); 4318 if (!(val & TOD_CTRL_ENABLE)) { 4319 seq_printf(s, "TOD Slave disabled\n"); 4320 return 0; 4321 } 4322 seq_printf(s, "TOD Slave enabled, Control Register 0x%08X\n", val); 4323 4324 idx = val & TOD_CTRL_PROTOCOL ? 4 : 0; 4325 idx += (val >> 16) & 3; 4326 seq_printf(s, "Protocol %s\n", ptp_ocp_tod_proto_name(idx)); 4327 4328 idx = (val >> TOD_CTRL_GNSS_SHIFT) & TOD_CTRL_GNSS_MASK; 4329 seq_printf(s, "GNSS %s\n", ptp_ocp_tod_gnss_name(idx)); 4330 4331 val = ioread32(&bp->tod->version); 4332 seq_printf(s, "TOD Version %d.%d.%d\n", 4333 val >> 24, (val >> 16) & 0xff, val & 0xffff); 4334 4335 val = ioread32(&bp->tod->status); 4336 seq_printf(s, "Status register: 0x%08X\n", val); 4337 4338 val = ioread32(&bp->tod->adj_sec); 4339 idx = (val & ~INT_MAX) ? -1 : 1; 4340 idx *= (val & INT_MAX); 4341 seq_printf(s, "Correction seconds: %d\n", idx); 4342 4343 val = ioread32(&bp->tod->utc_status); 4344 seq_printf(s, "UTC status register: 0x%08X\n", val); 4345 seq_printf(s, "UTC offset: %ld valid:%d\n", 4346 val & TOD_STATUS_UTC_MASK, val & TOD_STATUS_UTC_VALID ? 1 : 0); 4347 seq_printf(s, "Leap second info valid:%d, Leap second announce %d\n", 4348 val & TOD_STATUS_LEAP_VALID ? 1 : 0, 4349 val & TOD_STATUS_LEAP_ANNOUNCE ? 1 : 0); 4350 4351 val = ioread32(&bp->tod->leap); 4352 seq_printf(s, "Time to next leap second (in sec): %d\n", (s32) val); 4353 4354 return 0; 4355} 4356DEFINE_SHOW_ATTRIBUTE(ptp_ocp_tod_status); 4357 4358static struct dentry *ptp_ocp_debugfs_root; 4359 4360static void 4361ptp_ocp_debugfs_add_device(struct ptp_ocp *bp) 4362{ 4363 struct dentry *d; 4364 4365 d = debugfs_create_dir(dev_name(&bp->dev), ptp_ocp_debugfs_root); 4366 bp->debug_root = d; 4367 debugfs_create_file("summary", 0444, bp->debug_root, 4368 &bp->dev, &ptp_ocp_summary_fops); 4369 if (bp->tod) 4370 debugfs_create_file("tod_status", 0444, bp->debug_root, 4371 &bp->dev, &ptp_ocp_tod_status_fops); 4372} 4373 4374static void 4375ptp_ocp_debugfs_remove_device(struct ptp_ocp *bp) 4376{ 4377 debugfs_remove_recursive(bp->debug_root); 4378} 4379 4380static void 4381ptp_ocp_debugfs_init(void) 4382{ 4383 ptp_ocp_debugfs_root = debugfs_create_dir("timecard", NULL); 4384} 4385 4386static void 4387ptp_ocp_debugfs_fini(void) 4388{ 4389 debugfs_remove_recursive(ptp_ocp_debugfs_root); 4390} 4391 4392static void 4393ptp_ocp_dev_release(struct device *dev) 4394{ 4395 struct ptp_ocp *bp = dev_get_drvdata(dev); 4396 4397 mutex_lock(&ptp_ocp_lock); 4398 idr_remove(&ptp_ocp_idr, bp->id); 4399 mutex_unlock(&ptp_ocp_lock); 4400} 4401 4402static int 4403ptp_ocp_device_init(struct ptp_ocp *bp, struct pci_dev *pdev) 4404{ 4405 int i, err; 4406 4407 mutex_lock(&ptp_ocp_lock); 4408 err = idr_alloc(&ptp_ocp_idr, bp, 0, 0, GFP_KERNEL); 4409 mutex_unlock(&ptp_ocp_lock); 4410 if (err < 0) { 4411 dev_err(&pdev->dev, "idr_alloc failed: %d\n", err); 4412 return err; 4413 } 4414 bp->id = err; 4415 4416 bp->ptp_info = ptp_ocp_clock_info; 4417 spin_lock_init(&bp->lock); 4418 4419 for (i = 0; i < __PORT_COUNT; i++) 4420 bp->port[i].line = -1; 4421 4422 bp->pdev = pdev; 4423 4424 device_initialize(&bp->dev); 4425 dev_set_name(&bp->dev, "ocp%d", bp->id); 4426 bp->dev.class = &timecard_class; 4427 bp->dev.parent = &pdev->dev; 4428 bp->dev.release = ptp_ocp_dev_release; 4429 dev_set_drvdata(&bp->dev, bp); 4430 4431 err = device_add(&bp->dev); 4432 if (err) { 4433 dev_err(&bp->dev, "device add failed: %d\n", err); 4434 goto out; 4435 } 4436 4437 pci_set_drvdata(pdev, bp); 4438 4439 return 0; 4440 4441out: 4442 put_device(&bp->dev); 4443 return err; 4444} 4445 4446static void 4447ptp_ocp_symlink(struct ptp_ocp *bp, struct device *child, const char *link) 4448{ 4449 struct device *dev = &bp->dev; 4450 4451 if (sysfs_create_link(&dev->kobj, &child->kobj, link)) 4452 dev_err(dev, "%s symlink failed\n", link); 4453} 4454 4455static void 4456ptp_ocp_link_child(struct ptp_ocp *bp, const char *name, const char *link) 4457{ 4458 struct device *dev, *child; 4459 4460 dev = &bp->pdev->dev; 4461 4462 child = device_find_child_by_name(dev, name); 4463 if (!child) { 4464 dev_err(dev, "Could not find device %s\n", name); 4465 return; 4466 } 4467 4468 ptp_ocp_symlink(bp, child, link); 4469 put_device(child); 4470} 4471 4472static int 4473ptp_ocp_complete(struct ptp_ocp *bp) 4474{ 4475 struct pps_device *pps; 4476 char buf[32]; 4477 4478 sprintf(buf, "ptp%d", ptp_clock_index(bp->ptp)); 4479 ptp_ocp_link_child(bp, buf, "ptp"); 4480 4481 pps = pps_lookup_dev(bp->ptp); 4482 if (pps) 4483 ptp_ocp_symlink(bp, &pps->dev, "pps"); 4484 4485 ptp_ocp_debugfs_add_device(bp); 4486 4487 return 0; 4488} 4489 4490static void 4491ptp_ocp_phc_info(struct ptp_ocp *bp) 4492{ 4493 struct timespec64 ts; 4494 u32 version, select; 4495 4496 version = ioread32(&bp->reg->version); 4497 select = ioread32(&bp->reg->select); 4498 dev_info(&bp->pdev->dev, "Version %d.%d.%d, clock %s, device ptp%d\n", 4499 version >> 24, (version >> 16) & 0xff, version & 0xffff, 4500 ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16), 4501 ptp_clock_index(bp->ptp)); 4502 4503 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, NULL)) 4504 dev_info(&bp->pdev->dev, "Time: %ptSp, %s\n", 4505 &ts, bp->sync ? "in-sync" : "UNSYNCED"); 4506} 4507 4508static void 4509ptp_ocp_serial_info(struct device *dev, const char *name, int port, int baud) 4510{ 4511 if (port != -1) 4512 dev_info(dev, "%5s: /dev/ttyS%-2d @ %6d\n", name, port, baud); 4513} 4514 4515static void 4516ptp_ocp_info(struct ptp_ocp *bp) 4517{ 4518 static int nmea_baud[] = { 4519 1200, 2400, 4800, 9600, 19200, 38400, 4520 57600, 115200, 230400, 460800, 921600, 4521 1000000, 2000000 4522 }; 4523 struct device *dev = &bp->pdev->dev; 4524 u32 reg; 4525 int i; 4526 4527 ptp_ocp_phc_info(bp); 4528 4529 for (i = 0; i < __PORT_COUNT; i++) { 4530 if (i == PORT_NMEA && bp->nmea_out && bp->port[PORT_NMEA].line != -1) { 4531 bp->port[PORT_NMEA].baud = -1; 4532 4533 reg = ioread32(&bp->nmea_out->uart_baud); 4534 if (reg < ARRAY_SIZE(nmea_baud)) 4535 bp->port[PORT_NMEA].baud = nmea_baud[reg]; 4536 } 4537 ptp_ocp_serial_info(dev, ptp_ocp_tty_port_name(i), bp->port[i].line, 4538 bp->port[i].baud); 4539 } 4540} 4541 4542static void 4543ptp_ocp_detach_sysfs(struct ptp_ocp *bp) 4544{ 4545 struct device *dev = &bp->dev; 4546 4547 sysfs_remove_link(&dev->kobj, "ptp"); 4548 sysfs_remove_link(&dev->kobj, "pps"); 4549} 4550 4551static void 4552ptp_ocp_detach(struct ptp_ocp *bp) 4553{ 4554 int i; 4555 4556 ptp_ocp_debugfs_remove_device(bp); 4557 ptp_ocp_detach_sysfs(bp); 4558 ptp_ocp_attr_group_del(bp); 4559 timer_delete_sync(&bp->watchdog); 4560 ptp_ocp_unregister_ext(bp->ts0); 4561 ptp_ocp_unregister_ext(bp->ts1); 4562 ptp_ocp_unregister_ext(bp->ts2); 4563 ptp_ocp_unregister_ext(bp->ts3); 4564 ptp_ocp_unregister_ext(bp->ts4); 4565 ptp_ocp_unregister_ext(bp->pps); 4566 for (i = 0; i < 4; i++) 4567 ptp_ocp_unregister_ext(bp->signal_out[i]); 4568 for (i = 0; i < __PORT_COUNT; i++) 4569 if (bp->port[i].line != -1) 4570 serial8250_unregister_port(bp->port[i].line); 4571 platform_device_unregister(bp->spi_flash); 4572 platform_device_unregister(bp->i2c_ctrl); 4573 if (bp->i2c_clk) 4574 clk_hw_unregister_fixed_rate(bp->i2c_clk); 4575 if (bp->n_irqs) 4576 pci_free_irq_vectors(bp->pdev); 4577 if (bp->ptp) 4578 ptp_clock_unregister(bp->ptp); 4579 kfree(bp->ptp_info.pin_config); 4580 device_unregister(&bp->dev); 4581} 4582 4583static int 4584ptp_ocp_dpll_lock_status_get(const struct dpll_device *dpll, void *priv, 4585 enum dpll_lock_status *status, 4586 enum dpll_lock_status_error *status_error, 4587 struct netlink_ext_ack *extack) 4588{ 4589 struct ptp_ocp *bp = priv; 4590 4591 *status = bp->sync ? DPLL_LOCK_STATUS_LOCKED : DPLL_LOCK_STATUS_UNLOCKED; 4592 4593 return 0; 4594} 4595 4596static int ptp_ocp_dpll_state_get(const struct dpll_pin *pin, void *pin_priv, 4597 const struct dpll_device *dpll, void *priv, 4598 enum dpll_pin_state *state, 4599 struct netlink_ext_ack *extack) 4600{ 4601 struct ptp_ocp *bp = priv; 4602 int idx; 4603 4604 if (bp->pps_select) { 4605 idx = ioread32(&bp->pps_select->gpio1); 4606 *state = (&bp->sma[idx] == pin_priv) ? DPLL_PIN_STATE_CONNECTED : 4607 DPLL_PIN_STATE_SELECTABLE; 4608 return 0; 4609 } 4610 NL_SET_ERR_MSG(extack, "pin selection is not supported on current HW"); 4611 return -EINVAL; 4612} 4613 4614static int ptp_ocp_dpll_mode_get(const struct dpll_device *dpll, void *priv, 4615 enum dpll_mode *mode, struct netlink_ext_ack *extack) 4616{ 4617 *mode = DPLL_MODE_AUTOMATIC; 4618 return 0; 4619} 4620 4621static int ptp_ocp_dpll_direction_get(const struct dpll_pin *pin, 4622 void *pin_priv, 4623 const struct dpll_device *dpll, 4624 void *priv, 4625 enum dpll_pin_direction *direction, 4626 struct netlink_ext_ack *extack) 4627{ 4628 struct ptp_ocp_sma_connector *sma = pin_priv; 4629 4630 *direction = sma->mode == SMA_MODE_IN ? 4631 DPLL_PIN_DIRECTION_INPUT : 4632 DPLL_PIN_DIRECTION_OUTPUT; 4633 return 0; 4634} 4635 4636static int ptp_ocp_dpll_direction_set(const struct dpll_pin *pin, 4637 void *pin_priv, 4638 const struct dpll_device *dpll, 4639 void *dpll_priv, 4640 enum dpll_pin_direction direction, 4641 struct netlink_ext_ack *extack) 4642{ 4643 struct ptp_ocp_sma_connector *sma = pin_priv; 4644 struct ptp_ocp *bp = dpll_priv; 4645 enum ptp_ocp_sma_mode mode; 4646 int sma_nr = (sma - bp->sma); 4647 4648 if (sma->fixed_dir) 4649 return -EOPNOTSUPP; 4650 mode = direction == DPLL_PIN_DIRECTION_INPUT ? 4651 SMA_MODE_IN : SMA_MODE_OUT; 4652 return ptp_ocp_sma_store_val(bp, 0, mode, sma_nr + 1); 4653} 4654 4655static int ptp_ocp_dpll_frequency_set(const struct dpll_pin *pin, 4656 void *pin_priv, 4657 const struct dpll_device *dpll, 4658 void *dpll_priv, u64 frequency, 4659 struct netlink_ext_ack *extack) 4660{ 4661 struct ptp_ocp_sma_connector *sma = pin_priv; 4662 struct ptp_ocp *bp = dpll_priv; 4663 const struct ocp_selector *tbl; 4664 int sma_nr = (sma - bp->sma); 4665 int i; 4666 4667 if (sma->fixed_fcn) 4668 return -EOPNOTSUPP; 4669 4670 tbl = bp->sma_op->tbl[sma->mode]; 4671 for (i = 0; tbl[i].name; i++) 4672 if (tbl[i].frequency == frequency) 4673 return ptp_ocp_sma_store_val(bp, i, sma->mode, sma_nr + 1); 4674 return -EINVAL; 4675} 4676 4677static int ptp_ocp_dpll_frequency_get(const struct dpll_pin *pin, 4678 void *pin_priv, 4679 const struct dpll_device *dpll, 4680 void *dpll_priv, u64 *frequency, 4681 struct netlink_ext_ack *extack) 4682{ 4683 struct ptp_ocp_sma_connector *sma = pin_priv; 4684 struct ptp_ocp *bp = dpll_priv; 4685 const struct ocp_selector *tbl; 4686 int sma_nr = (sma - bp->sma); 4687 u32 val; 4688 int i; 4689 4690 val = bp->sma_op->get(bp, sma_nr + 1); 4691 tbl = bp->sma_op->tbl[sma->mode]; 4692 for (i = 0; tbl[i].name; i++) 4693 if (val == tbl[i].value) { 4694 *frequency = tbl[i].frequency; 4695 return 0; 4696 } 4697 4698 return -EINVAL; 4699} 4700 4701static const struct dpll_device_ops dpll_ops = { 4702 .lock_status_get = ptp_ocp_dpll_lock_status_get, 4703 .mode_get = ptp_ocp_dpll_mode_get, 4704}; 4705 4706static const struct dpll_pin_ops dpll_pins_ops = { 4707 .frequency_get = ptp_ocp_dpll_frequency_get, 4708 .frequency_set = ptp_ocp_dpll_frequency_set, 4709 .direction_get = ptp_ocp_dpll_direction_get, 4710 .direction_set = ptp_ocp_dpll_direction_set, 4711 .state_on_dpll_get = ptp_ocp_dpll_state_get, 4712}; 4713 4714static void 4715ptp_ocp_sync_work(struct work_struct *work) 4716{ 4717 struct ptp_ocp *bp; 4718 bool sync; 4719 4720 bp = container_of(work, struct ptp_ocp, sync_work.work); 4721 sync = !!(ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC); 4722 4723 if (bp->sync != sync) 4724 dpll_device_change_ntf(bp->dpll); 4725 4726 bp->sync = sync; 4727 4728 queue_delayed_work(system_power_efficient_wq, &bp->sync_work, HZ); 4729} 4730 4731static int 4732ptp_ocp_probe(struct pci_dev *pdev, const struct pci_device_id *id) 4733{ 4734 struct devlink *devlink; 4735 struct ptp_ocp *bp; 4736 int err, i; 4737 u64 clkid; 4738 4739 devlink = devlink_alloc(&ptp_ocp_devlink_ops, sizeof(*bp), &pdev->dev); 4740 if (!devlink) { 4741 dev_err(&pdev->dev, "devlink_alloc failed\n"); 4742 return -ENOMEM; 4743 } 4744 4745 err = pci_enable_device(pdev); 4746 if (err) { 4747 dev_err(&pdev->dev, "pci_enable_device\n"); 4748 goto out_free; 4749 } 4750 4751 bp = devlink_priv(devlink); 4752 err = ptp_ocp_device_init(bp, pdev); 4753 if (err) 4754 goto out_disable; 4755 4756 INIT_DELAYED_WORK(&bp->sync_work, ptp_ocp_sync_work); 4757 4758 /* compat mode. 4759 * Older FPGA firmware only returns 2 irq's. 4760 * allow this - if not all of the IRQ's are returned, skip the 4761 * extra devices and just register the clock. 4762 */ 4763 err = pci_alloc_irq_vectors(pdev, 1, 17, PCI_IRQ_MSI | PCI_IRQ_MSIX); 4764 if (err < 0) { 4765 dev_err(&pdev->dev, "alloc_irq_vectors err: %d\n", err); 4766 goto out; 4767 } 4768 bp->n_irqs = err; 4769 pci_set_master(pdev); 4770 4771 err = ptp_ocp_register_resources(bp, id->driver_data); 4772 if (err) 4773 goto out; 4774 4775 bp->ptp = ptp_clock_register(&bp->ptp_info, &pdev->dev); 4776 if (IS_ERR(bp->ptp)) { 4777 err = PTR_ERR(bp->ptp); 4778 dev_err(&pdev->dev, "ptp_clock_register: %d\n", err); 4779 bp->ptp = NULL; 4780 goto out; 4781 } 4782 4783 err = ptp_ocp_complete(bp); 4784 if (err) 4785 goto out; 4786 4787 ptp_ocp_info(bp); 4788 devlink_register(devlink); 4789 4790 clkid = pci_get_dsn(pdev); 4791 bp->dpll = dpll_device_get(clkid, 0, THIS_MODULE); 4792 if (IS_ERR(bp->dpll)) { 4793 err = PTR_ERR(bp->dpll); 4794 dev_err(&pdev->dev, "dpll_device_alloc failed\n"); 4795 goto out; 4796 } 4797 4798 err = dpll_device_register(bp->dpll, DPLL_TYPE_PPS, &dpll_ops, bp); 4799 if (err) 4800 goto out; 4801 4802 for (i = 0; i < OCP_SMA_NUM; i++) { 4803 bp->sma[i].dpll_pin = dpll_pin_get(clkid, i, THIS_MODULE, &bp->sma[i].dpll_prop); 4804 if (IS_ERR(bp->sma[i].dpll_pin)) { 4805 err = PTR_ERR(bp->sma[i].dpll_pin); 4806 goto out_dpll; 4807 } 4808 4809 err = dpll_pin_register(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, 4810 &bp->sma[i]); 4811 if (err) { 4812 dpll_pin_put(bp->sma[i].dpll_pin); 4813 goto out_dpll; 4814 } 4815 } 4816 queue_delayed_work(system_power_efficient_wq, &bp->sync_work, HZ); 4817 4818 return 0; 4819out_dpll: 4820 while (i--) { 4821 dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]); 4822 dpll_pin_put(bp->sma[i].dpll_pin); 4823 } 4824 dpll_device_put(bp->dpll); 4825out: 4826 ptp_ocp_detach(bp); 4827out_disable: 4828 pci_disable_device(pdev); 4829out_free: 4830 devlink_free(devlink); 4831 return err; 4832} 4833 4834static void 4835ptp_ocp_remove(struct pci_dev *pdev) 4836{ 4837 struct ptp_ocp *bp = pci_get_drvdata(pdev); 4838 struct devlink *devlink = priv_to_devlink(bp); 4839 int i; 4840 4841 cancel_delayed_work_sync(&bp->sync_work); 4842 for (i = 0; i < OCP_SMA_NUM; i++) { 4843 if (bp->sma[i].dpll_pin) { 4844 dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]); 4845 dpll_pin_put(bp->sma[i].dpll_pin); 4846 } 4847 } 4848 dpll_device_unregister(bp->dpll, &dpll_ops, bp); 4849 dpll_device_put(bp->dpll); 4850 devlink_unregister(devlink); 4851 ptp_ocp_detach(bp); 4852 pci_disable_device(pdev); 4853 4854 devlink_free(devlink); 4855} 4856 4857static struct pci_driver ptp_ocp_driver = { 4858 .name = KBUILD_MODNAME, 4859 .id_table = ptp_ocp_pcidev_id, 4860 .probe = ptp_ocp_probe, 4861 .remove = ptp_ocp_remove, 4862}; 4863 4864static int 4865ptp_ocp_i2c_notifier_call(struct notifier_block *nb, 4866 unsigned long action, void *data) 4867{ 4868 struct device *dev, *child = data; 4869 struct ptp_ocp *bp; 4870 bool add; 4871 4872 switch (action) { 4873 case BUS_NOTIFY_ADD_DEVICE: 4874 case BUS_NOTIFY_DEL_DEVICE: 4875 add = action == BUS_NOTIFY_ADD_DEVICE; 4876 break; 4877 default: 4878 return 0; 4879 } 4880 4881 if (!i2c_verify_adapter(child)) 4882 return 0; 4883 4884 dev = child; 4885 while ((dev = dev->parent)) 4886 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME)) 4887 goto found; 4888 return 0; 4889 4890found: 4891 bp = dev_get_drvdata(dev); 4892 if (add) 4893 ptp_ocp_symlink(bp, child, "i2c"); 4894 else 4895 sysfs_remove_link(&bp->dev.kobj, "i2c"); 4896 4897 return 0; 4898} 4899 4900static struct notifier_block ptp_ocp_i2c_notifier = { 4901 .notifier_call = ptp_ocp_i2c_notifier_call, 4902}; 4903 4904static int __init 4905ptp_ocp_init(void) 4906{ 4907 const char *what; 4908 int err; 4909 4910 ptp_ocp_debugfs_init(); 4911 4912 what = "timecard class"; 4913 err = class_register(&timecard_class); 4914 if (err) 4915 goto out; 4916 4917 what = "i2c notifier"; 4918 err = bus_register_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier); 4919 if (err) 4920 goto out_notifier; 4921 4922 what = "ptp_ocp driver"; 4923 err = pci_register_driver(&ptp_ocp_driver); 4924 if (err) 4925 goto out_register; 4926 4927 return 0; 4928 4929out_register: 4930 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier); 4931out_notifier: 4932 class_unregister(&timecard_class); 4933out: 4934 ptp_ocp_debugfs_fini(); 4935 pr_err(KBUILD_MODNAME ": failed to register %s: %d\n", what, err); 4936 return err; 4937} 4938 4939static void __exit 4940ptp_ocp_fini(void) 4941{ 4942 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier); 4943 pci_unregister_driver(&ptp_ocp_driver); 4944 class_unregister(&timecard_class); 4945 ptp_ocp_debugfs_fini(); 4946} 4947 4948module_init(ptp_ocp_init); 4949module_exit(ptp_ocp_fini); 4950 4951MODULE_DESCRIPTION("OpenCompute TimeCard driver"); 4952MODULE_LICENSE("GPL v2");
~/
Read-only file preview.