ptp_idt82p33.c

   1// SPDX-License-Identifier: GPL-2.0
   2//
   3// Copyright (C) 2018 Integrated Device Technology, Inc
   4//
   5
   6#define pr_fmt(fmt) "IDT_82p33xxx: " fmt
   7
   8#include <linux/firmware.h>
   9#include <linux/platform_device.h>
  10#include <linux/module.h>
  11#include <linux/ptp_clock_kernel.h>
  12#include <linux/delay.h>
  13#include <linux/jiffies.h>
  14#include <linux/kernel.h>
  15#include <linux/timekeeping.h>
  16#include <linux/bitops.h>
  17#include <linux/of.h>
  18#include <linux/mfd/rsmu.h>
  19#include <linux/mfd/idt82p33_reg.h>
  20
  21#include "ptp_private.h"
  22#include "ptp_idt82p33.h"
  23
  24MODULE_DESCRIPTION("Driver for IDT 82p33xxx clock devices");
  25MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>");
  26MODULE_VERSION("1.0");
  27MODULE_LICENSE("GPL");
  28MODULE_FIRMWARE(FW_FILENAME);
  29
  30#define EXTTS_PERIOD_MS (95)
  31
  32/* Module Parameters */
  33static u32 phase_snap_threshold = SNAP_THRESHOLD_NS;
  34module_param(phase_snap_threshold, uint, 0);
  35MODULE_PARM_DESC(phase_snap_threshold,
  36"threshold (10000ns by default) below which adjtime would use double dco");
  37
  38static char *firmware;
  39module_param(firmware, charp, 0);
  40
  41static struct ptp_pin_desc pin_config[MAX_PHC_PLL][MAX_TRIG_CLK];
  42
  43static inline int idt82p33_read(struct idt82p33 *idt82p33, u16 regaddr,
  44				u8 *buf, u16 count)
  45{
  46	return regmap_bulk_read(idt82p33->regmap, regaddr, buf, count);
  47}
  48
  49static inline int idt82p33_write(struct idt82p33 *idt82p33, u16 regaddr,
  50				 u8 *buf, u16 count)
  51{
  52	return regmap_bulk_write(idt82p33->regmap, regaddr, buf, count);
  53}
  54
  55static void idt82p33_byte_array_to_timespec(struct timespec64 *ts,
  56					    u8 buf[TOD_BYTE_COUNT])
  57{
  58	time64_t sec;
  59	s32 nsec;
  60	u8 i;
  61
  62	nsec = buf[3];
  63	for (i = 0; i < 3; i++) {
  64		nsec <<= 8;
  65		nsec |= buf[2 - i];
  66	}
  67
  68	sec = buf[9];
  69	for (i = 0; i < 5; i++) {
  70		sec <<= 8;
  71		sec |= buf[8 - i];
  72	}
  73
  74	ts->tv_sec = sec;
  75	ts->tv_nsec = nsec;
  76}
  77
  78static void idt82p33_timespec_to_byte_array(struct timespec64 const *ts,
  79					    u8 buf[TOD_BYTE_COUNT])
  80{
  81	time64_t sec;
  82	s32 nsec;
  83	u8 i;
  84
  85	nsec = ts->tv_nsec;
  86	sec = ts->tv_sec;
  87
  88	for (i = 0; i < 4; i++) {
  89		buf[i] = nsec & 0xff;
  90		nsec >>= 8;
  91	}
  92
  93	for (i = 4; i < TOD_BYTE_COUNT; i++) {
  94		buf[i] = sec & 0xff;
  95		sec >>= 8;
  96	}
  97}
  98
  99static int idt82p33_dpll_set_mode(struct idt82p33_channel *channel,
 100				  enum pll_mode mode)
 101{
 102	struct idt82p33 *idt82p33 = channel->idt82p33;
 103	u8 dpll_mode;
 104	int err;
 105
 106	if (channel->pll_mode == mode)
 107		return 0;
 108
 109	err = idt82p33_read(idt82p33, channel->dpll_mode_cnfg,
 110			    &dpll_mode, sizeof(dpll_mode));
 111	if (err)
 112		return err;
 113
 114	dpll_mode &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT);
 115
 116	dpll_mode |= (mode << PLL_MODE_SHIFT);
 117
 118	err = idt82p33_write(idt82p33, channel->dpll_mode_cnfg,
 119			     &dpll_mode, sizeof(dpll_mode));
 120	if (err)
 121		return err;
 122
 123	channel->pll_mode = mode;
 124
 125	return 0;
 126}
 127
 128static int idt82p33_set_tod_trigger(struct idt82p33_channel *channel,
 129				    u8 trigger, bool write)
 130{
 131	struct idt82p33 *idt82p33 = channel->idt82p33;
 132	int err;
 133	u8 cfg;
 134
 135	if (trigger > WR_TRIG_SEL_MAX)
 136		return -EINVAL;
 137
 138	err = idt82p33_read(idt82p33, channel->dpll_tod_trigger,
 139			    &cfg, sizeof(cfg));
 140
 141	if (err)
 142		return err;
 143
 144	if (write == true)
 145		trigger = (trigger << WRITE_TRIGGER_SHIFT) |
 146			  (cfg & READ_TRIGGER_MASK);
 147	else
 148		trigger = (trigger << READ_TRIGGER_SHIFT) |
 149			  (cfg & WRITE_TRIGGER_MASK);
 150
 151	return idt82p33_write(idt82p33, channel->dpll_tod_trigger,
 152			      &trigger, sizeof(trigger));
 153}
 154
 155static int idt82p33_get_extts(struct idt82p33_channel *channel,
 156			      struct timespec64 *ts)
 157{
 158	struct idt82p33 *idt82p33 = channel->idt82p33;
 159	u8 buf[TOD_BYTE_COUNT];
 160	int err;
 161
 162	err = idt82p33_read(idt82p33, channel->dpll_tod_sts, buf, sizeof(buf));
 163
 164	if (err)
 165		return err;
 166
 167	/* Since trigger is not self clearing itself, we have to poll tod_sts */
 168	if (memcmp(buf, channel->extts_tod_sts, TOD_BYTE_COUNT) == 0)
 169		return -EAGAIN;
 170
 171	memcpy(channel->extts_tod_sts, buf, TOD_BYTE_COUNT);
 172
 173	idt82p33_byte_array_to_timespec(ts, buf);
 174
 175	if (channel->discard_next_extts) {
 176		channel->discard_next_extts = false;
 177		return -EAGAIN;
 178	}
 179
 180	return 0;
 181}
 182
 183static int map_ref_to_tod_trig_sel(int ref, u8 *trigger)
 184{
 185	int err = 0;
 186
 187	switch (ref) {
 188	case 0:
 189		*trigger = HW_TOD_TRIG_SEL_IN12;
 190		break;
 191	case 1:
 192		*trigger = HW_TOD_TRIG_SEL_IN13;
 193		break;
 194	case 2:
 195		*trigger = HW_TOD_TRIG_SEL_IN14;
 196		break;
 197	default:
 198		err = -EINVAL;
 199	}
 200
 201	return err;
 202}
 203
 204static bool is_one_shot(u8 mask)
 205{
 206	/* Treat single bit PLL masks as continuous trigger */
 207	if ((mask == 1) || (mask == 2))
 208		return false;
 209	else
 210		return true;
 211}
 212
 213static int arm_tod_read_with_trigger(struct idt82p33_channel *channel, u8 trigger)
 214{
 215	struct idt82p33 *idt82p33 = channel->idt82p33;
 216	u8 buf[TOD_BYTE_COUNT];
 217	int err;
 218
 219	/* Remember the current tod_sts before setting the trigger */
 220	err = idt82p33_read(idt82p33, channel->dpll_tod_sts, buf, sizeof(buf));
 221
 222	if (err)
 223		return err;
 224
 225	memcpy(channel->extts_tod_sts, buf, TOD_BYTE_COUNT);
 226
 227	err = idt82p33_set_tod_trigger(channel, trigger, false);
 228
 229	if (err)
 230		dev_err(idt82p33->dev, "%s: err = %d", __func__, err);
 231
 232	return err;
 233}
 234
 235static int idt82p33_extts_enable(struct idt82p33_channel *channel,
 236				 struct ptp_clock_request *rq, int on)
 237{
 238	u8 index = rq->extts.index;
 239	struct idt82p33 *idt82p33;
 240	u8 mask = 1 << index;
 241	int err = 0;
 242	u8 old_mask;
 243	u8 trigger;
 244	int ref;
 245
 246	idt82p33  = channel->idt82p33;
 247	old_mask = idt82p33->extts_mask;
 248
 249	if (index >= MAX_PHC_PLL)
 250		return -EINVAL;
 251
 252	if (on) {
 253		/* Return if it was already enabled */
 254		if (idt82p33->extts_mask & mask)
 255			return 0;
 256
 257		/* Use the pin configured for the channel */
 258		ref = ptp_find_pin(channel->ptp_clock, PTP_PF_EXTTS, channel->plln);
 259
 260		if (ref < 0) {
 261			dev_err(idt82p33->dev, "%s: No valid pin found for Pll%d!\n",
 262				__func__, channel->plln);
 263			return -EBUSY;
 264		}
 265
 266		err = map_ref_to_tod_trig_sel(ref, &trigger);
 267
 268		if (err) {
 269			dev_err(idt82p33->dev,
 270				"%s: Unsupported ref %d!\n", __func__, ref);
 271			return err;
 272		}
 273
 274		err = arm_tod_read_with_trigger(&idt82p33->channel[index], trigger);
 275
 276		if (err == 0) {
 277			idt82p33->extts_mask |= mask;
 278			idt82p33->channel[index].tod_trigger = trigger;
 279			idt82p33->event_channel[index] = channel;
 280			idt82p33->extts_single_shot = is_one_shot(idt82p33->extts_mask);
 281
 282			if (old_mask)
 283				return 0;
 284
 285			schedule_delayed_work(&idt82p33->extts_work,
 286					      msecs_to_jiffies(EXTTS_PERIOD_MS));
 287		}
 288	} else {
 289		idt82p33->extts_mask &= ~mask;
 290		idt82p33->extts_single_shot = is_one_shot(idt82p33->extts_mask);
 291
 292		if (idt82p33->extts_mask == 0)
 293			cancel_delayed_work(&idt82p33->extts_work);
 294	}
 295
 296	return err;
 297}
 298
 299static int idt82p33_extts_check_channel(struct idt82p33 *idt82p33, u8 todn)
 300{
 301	struct idt82p33_channel *event_channel;
 302	struct ptp_clock_event event;
 303	struct timespec64 ts;
 304	int err;
 305
 306	err = idt82p33_get_extts(&idt82p33->channel[todn], &ts);
 307	if (err == 0) {
 308		event_channel = idt82p33->event_channel[todn];
 309		event.type = PTP_CLOCK_EXTTS;
 310		event.index = todn;
 311		event.timestamp = timespec64_to_ns(&ts);
 312		ptp_clock_event(event_channel->ptp_clock,
 313				&event);
 314	}
 315	return err;
 316}
 317
 318static u8 idt82p33_extts_enable_mask(struct idt82p33_channel *channel,
 319				     u8 extts_mask, bool enable)
 320{
 321	struct idt82p33 *idt82p33 = channel->idt82p33;
 322	u8 trigger = channel->tod_trigger;
 323	u8 mask;
 324	int err;
 325	int i;
 326
 327	if (extts_mask == 0)
 328		return 0;
 329
 330	if (enable == false)
 331		cancel_delayed_work_sync(&idt82p33->extts_work);
 332
 333	for (i = 0; i < MAX_PHC_PLL; i++) {
 334		mask = 1 << i;
 335
 336		if ((extts_mask & mask) == 0)
 337			continue;
 338
 339		if (enable) {
 340			err = arm_tod_read_with_trigger(&idt82p33->channel[i], trigger);
 341			if (err)
 342				dev_err(idt82p33->dev,
 343					"%s: Arm ToD read trigger failed, err = %d",
 344					__func__, err);
 345		} else {
 346			err = idt82p33_extts_check_channel(idt82p33, i);
 347			if (err == 0 && idt82p33->extts_single_shot)
 348				/* trigger happened so we won't re-enable it */
 349				extts_mask &= ~mask;
 350		}
 351	}
 352
 353	if (enable)
 354		schedule_delayed_work(&idt82p33->extts_work,
 355				      msecs_to_jiffies(EXTTS_PERIOD_MS));
 356
 357	return extts_mask;
 358}
 359
 360static int _idt82p33_gettime(struct idt82p33_channel *channel,
 361			     struct timespec64 *ts)
 362{
 363	struct idt82p33 *idt82p33 = channel->idt82p33;
 364	u8 old_mask = idt82p33->extts_mask;
 365	u8 buf[TOD_BYTE_COUNT];
 366	u8 new_mask = 0;
 367	int err;
 368
 369	/* Disable extts */
 370	if (old_mask)
 371		new_mask = idt82p33_extts_enable_mask(channel, old_mask, false);
 372
 373	err = idt82p33_set_tod_trigger(channel, HW_TOD_RD_TRIG_SEL_LSB_TOD_STS,
 374				       false);
 375	if (err)
 376		return err;
 377
 378	channel->discard_next_extts = true;
 379
 380	if (idt82p33->calculate_overhead_flag)
 381		idt82p33->start_time = ktime_get_raw();
 382
 383	err = idt82p33_read(idt82p33, channel->dpll_tod_sts, buf, sizeof(buf));
 384
 385	if (err)
 386		return err;
 387
 388	/* Re-enable extts */
 389	if (new_mask)
 390		idt82p33_extts_enable_mask(channel, new_mask, true);
 391
 392	idt82p33_byte_array_to_timespec(ts, buf);
 393
 394	return 0;
 395}
 396
 397/*
 398 *   TOD Trigger:
 399 *   Bits[7:4] Write 0x9, MSB write
 400 *   Bits[3:0] Read 0x9, LSB read
 401 */
 402
 403static int _idt82p33_settime(struct idt82p33_channel *channel,
 404			     struct timespec64 const *ts)
 405{
 406	struct idt82p33 *idt82p33 = channel->idt82p33;
 407	struct timespec64 local_ts = *ts;
 408	char buf[TOD_BYTE_COUNT];
 409	s64 dynamic_overhead_ns;
 410	int err;
 411	u8 i;
 412
 413	err = idt82p33_set_tod_trigger(channel, HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
 414				       true);
 415	if (err)
 416		return err;
 417
 418	channel->discard_next_extts = true;
 419
 420	if (idt82p33->calculate_overhead_flag) {
 421		dynamic_overhead_ns = ktime_to_ns(ktime_get_raw())
 422					- ktime_to_ns(idt82p33->start_time);
 423
 424		timespec64_add_ns(&local_ts, dynamic_overhead_ns);
 425
 426		idt82p33->calculate_overhead_flag = 0;
 427	}
 428
 429	idt82p33_timespec_to_byte_array(&local_ts, buf);
 430
 431	/*
 432	 * Store the new time value.
 433	 */
 434	for (i = 0; i < TOD_BYTE_COUNT; i++) {
 435		err = idt82p33_write(idt82p33, channel->dpll_tod_cnfg + i,
 436				     &buf[i], sizeof(buf[i]));
 437		if (err)
 438			return err;
 439	}
 440
 441	return err;
 442}
 443
 444static int _idt82p33_adjtime_immediate(struct idt82p33_channel *channel,
 445				       s64 delta_ns)
 446{
 447	struct idt82p33 *idt82p33 = channel->idt82p33;
 448	struct timespec64 ts;
 449	s64 now_ns;
 450	int err;
 451
 452	idt82p33->calculate_overhead_flag = 1;
 453
 454	err = _idt82p33_gettime(channel, &ts);
 455
 456	if (err)
 457		return err;
 458
 459	now_ns = timespec64_to_ns(&ts);
 460	now_ns += delta_ns + idt82p33->tod_write_overhead_ns;
 461
 462	ts = ns_to_timespec64(now_ns);
 463
 464	err = _idt82p33_settime(channel, &ts);
 465
 466	return err;
 467}
 468
 469static int _idt82p33_adjtime_internal_triggered(struct idt82p33_channel *channel,
 470						s64 delta_ns)
 471{
 472	struct idt82p33 *idt82p33 = channel->idt82p33;
 473	char buf[TOD_BYTE_COUNT];
 474	struct timespec64 ts;
 475	const u8 delay_ns = 32;
 476	s32 remainder;
 477	s64 ns;
 478	int err;
 479
 480	err = _idt82p33_gettime(channel, &ts);
 481
 482	if (err)
 483		return err;
 484
 485	if (ts.tv_nsec > (NSEC_PER_SEC - 5 * NSEC_PER_MSEC)) {
 486		/*  Too close to miss next trigger, so skip it */
 487		mdelay(6);
 488		ns = (ts.tv_sec + 2) * NSEC_PER_SEC + delta_ns + delay_ns;
 489	} else
 490		ns = (ts.tv_sec + 1) * NSEC_PER_SEC + delta_ns + delay_ns;
 491
 492	ts = ns_to_timespec64(ns);
 493	idt82p33_timespec_to_byte_array(&ts, buf);
 494
 495	/*
 496	 * Store the new time value.
 497	 */
 498	err = idt82p33_write(idt82p33, channel->dpll_tod_cnfg, buf, sizeof(buf));
 499	if (err)
 500		return err;
 501
 502	/* Schedule to implement the workaround in one second */
 503	(void)div_s64_rem(delta_ns, NSEC_PER_SEC, &remainder);
 504	if (remainder != 0)
 505		schedule_delayed_work(&channel->adjtime_work, HZ);
 506
 507	return idt82p33_set_tod_trigger(channel, HW_TOD_TRIG_SEL_TOD_PPS, true);
 508}
 509
 510static void idt82p33_adjtime_workaround(struct work_struct *work)
 511{
 512	struct idt82p33_channel *channel = container_of(work,
 513							struct idt82p33_channel,
 514							adjtime_work.work);
 515	struct idt82p33 *idt82p33 = channel->idt82p33;
 516
 517	mutex_lock(idt82p33->lock);
 518	/* Workaround for TOD-to-output alignment issue */
 519	_idt82p33_adjtime_internal_triggered(channel, 0);
 520	mutex_unlock(idt82p33->lock);
 521}
 522
 523static int _idt82p33_adjfine(struct idt82p33_channel *channel, long scaled_ppm)
 524{
 525	struct idt82p33 *idt82p33 = channel->idt82p33;
 526	unsigned char buf[5] = {0};
 527	int err, i;
 528	s64 fcw;
 529
 530	/*
 531	 * Frequency Control Word unit is: 1.6861512 * 10^-10 ppm
 532	 *
 533	 * adjfreq:
 534	 *       ppb * 10^14
 535	 * FCW = -----------
 536	 *         16861512
 537	 *
 538	 * adjfine:
 539	 *       scaled_ppm * 5^12 * 10^5
 540	 * FCW = ------------------------
 541	 *            16861512 * 2^4
 542	 */
 543
 544	fcw = scaled_ppm * 762939453125ULL;
 545	fcw = div_s64(fcw, 8430756LL);
 546
 547	for (i = 0; i < 5; i++) {
 548		buf[i] = fcw & 0xff;
 549		fcw >>= 8;
 550	}
 551
 552	err = idt82p33_dpll_set_mode(channel, PLL_MODE_DCO);
 553
 554	if (err)
 555		return err;
 556
 557	err = idt82p33_write(idt82p33, channel->dpll_freq_cnfg,
 558			     buf, sizeof(buf));
 559
 560	return err;
 561}
 562
 563/* ppb = scaled_ppm * 125 / 2^13 */
 564static s32 idt82p33_ddco_scaled_ppm(long current_ppm, s32 ddco_ppb)
 565{
 566	s64 scaled_ppm = div_s64(((s64)ddco_ppb << 13), 125);
 567	s64 max_scaled_ppm = div_s64(((s64)DCO_MAX_PPB << 13), 125);
 568
 569	current_ppm += scaled_ppm;
 570
 571	if (current_ppm > max_scaled_ppm)
 572		current_ppm = max_scaled_ppm;
 573	else if (current_ppm < -max_scaled_ppm)
 574		current_ppm = -max_scaled_ppm;
 575
 576	return (s32)current_ppm;
 577}
 578
 579static int idt82p33_stop_ddco(struct idt82p33_channel *channel)
 580{
 581	int err;
 582
 583	err = _idt82p33_adjfine(channel, channel->current_freq);
 584	if (err)
 585		return err;
 586
 587	channel->ddco = false;
 588
 589	return 0;
 590}
 591
 592static int idt82p33_start_ddco(struct idt82p33_channel *channel, s32 delta_ns)
 593{
 594	s32 current_ppm = channel->current_freq;
 595	u32 duration_ms = MSEC_PER_SEC;
 596	s32 ppb;
 597	int err;
 598
 599	/* If the ToD correction is less than 5 nanoseconds, then skip it.
 600	 * The error introduced by the ToD adjustment procedure would be bigger
 601	 * than the required ToD correction
 602	 */
 603	if (abs(delta_ns) < DDCO_THRESHOLD_NS)
 604		return 0;
 605
 606	/* For most cases, keep ddco duration 1 second */
 607	ppb = delta_ns;
 608	while (abs(ppb) > DCO_MAX_PPB) {
 609		duration_ms *= 2;
 610		ppb /= 2;
 611	}
 612
 613	err = _idt82p33_adjfine(channel,
 614				idt82p33_ddco_scaled_ppm(current_ppm, ppb));
 615	if (err)
 616		return err;
 617
 618	/* schedule the worker to cancel ddco */
 619	ptp_schedule_worker(channel->ptp_clock,
 620			    msecs_to_jiffies(duration_ms) - 1);
 621	channel->ddco = true;
 622
 623	return 0;
 624}
 625
 626static int idt82p33_measure_one_byte_write_overhead(
 627		struct idt82p33_channel *channel, s64 *overhead_ns)
 628{
 629	struct idt82p33 *idt82p33 = channel->idt82p33;
 630	ktime_t start, stop;
 631	u8 trigger = 0;
 632	s64 total_ns;
 633	int err;
 634	u8 i;
 635
 636	total_ns = 0;
 637	*overhead_ns = 0;
 638
 639	for (i = 0; i < MAX_MEASURMENT_COUNT; i++) {
 640
 641		start = ktime_get_raw();
 642
 643		err = idt82p33_write(idt82p33, channel->dpll_tod_trigger,
 644				     &trigger, sizeof(trigger));
 645
 646		stop = ktime_get_raw();
 647
 648		if (err)
 649			return err;
 650
 651		total_ns += ktime_to_ns(stop) - ktime_to_ns(start);
 652	}
 653
 654	*overhead_ns = div_s64(total_ns, MAX_MEASURMENT_COUNT);
 655
 656	return err;
 657}
 658
 659static int idt82p33_measure_one_byte_read_overhead(
 660		struct idt82p33_channel *channel, s64 *overhead_ns)
 661{
 662	struct idt82p33 *idt82p33 = channel->idt82p33;
 663	ktime_t start, stop;
 664	u8 trigger = 0;
 665	s64 total_ns;
 666	int err;
 667	u8 i;
 668
 669	total_ns = 0;
 670	*overhead_ns = 0;
 671
 672	for (i = 0; i < MAX_MEASURMENT_COUNT; i++) {
 673
 674		start = ktime_get_raw();
 675
 676		err = idt82p33_read(idt82p33, channel->dpll_tod_trigger,
 677				    &trigger, sizeof(trigger));
 678
 679		stop = ktime_get_raw();
 680
 681		if (err)
 682			return err;
 683
 684		total_ns += ktime_to_ns(stop) - ktime_to_ns(start);
 685	}
 686
 687	*overhead_ns = div_s64(total_ns, MAX_MEASURMENT_COUNT);
 688
 689	return err;
 690}
 691
 692static int idt82p33_measure_tod_write_9_byte_overhead(
 693		struct idt82p33_channel *channel)
 694{
 695	struct idt82p33 *idt82p33 = channel->idt82p33;
 696	u8 buf[TOD_BYTE_COUNT];
 697	ktime_t start, stop;
 698	s64 total_ns;
 699	int err = 0;
 700	u8 i, j;
 701
 702	total_ns = 0;
 703	idt82p33->tod_write_overhead_ns = 0;
 704
 705	for (i = 0; i < MAX_MEASURMENT_COUNT; i++) {
 706
 707		start = ktime_get_raw();
 708
 709		/* Need one less byte for applicable overhead */
 710		for (j = 0; j < (TOD_BYTE_COUNT - 1); j++) {
 711			err = idt82p33_write(idt82p33,
 712					     channel->dpll_tod_cnfg + i,
 713					     &buf[i], sizeof(buf[i]));
 714			if (err)
 715				return err;
 716		}
 717
 718		stop = ktime_get_raw();
 719
 720		total_ns += ktime_to_ns(stop) - ktime_to_ns(start);
 721	}
 722
 723	idt82p33->tod_write_overhead_ns = div_s64(total_ns,
 724						  MAX_MEASURMENT_COUNT);
 725
 726	return err;
 727}
 728
 729static int idt82p33_measure_settime_gettime_gap_overhead(
 730		struct idt82p33_channel *channel, s64 *overhead_ns)
 731{
 732	struct timespec64 ts1 = {0, 0};
 733	struct timespec64 ts2;
 734	int err;
 735
 736	*overhead_ns = 0;
 737
 738	err = _idt82p33_settime(channel, &ts1);
 739
 740	if (err)
 741		return err;
 742
 743	err = _idt82p33_gettime(channel, &ts2);
 744
 745	if (!err)
 746		*overhead_ns = timespec64_to_ns(&ts2) - timespec64_to_ns(&ts1);
 747
 748	return err;
 749}
 750
 751static int idt82p33_measure_tod_write_overhead(struct idt82p33_channel *channel)
 752{
 753	s64 trailing_overhead_ns, one_byte_write_ns, gap_ns, one_byte_read_ns;
 754	struct idt82p33 *idt82p33 = channel->idt82p33;
 755	int err;
 756
 757	idt82p33->tod_write_overhead_ns = 0;
 758
 759	err = idt82p33_measure_settime_gettime_gap_overhead(channel, &gap_ns);
 760
 761	if (err) {
 762		dev_err(idt82p33->dev,
 763			"Failed in %s with err %d!\n", __func__, err);
 764		return err;
 765	}
 766
 767	err = idt82p33_measure_one_byte_write_overhead(channel,
 768						       &one_byte_write_ns);
 769
 770	if (err)
 771		return err;
 772
 773	err = idt82p33_measure_one_byte_read_overhead(channel,
 774						      &one_byte_read_ns);
 775
 776	if (err)
 777		return err;
 778
 779	err = idt82p33_measure_tod_write_9_byte_overhead(channel);
 780
 781	if (err)
 782		return err;
 783
 784	trailing_overhead_ns = gap_ns - 2 * one_byte_write_ns
 785			       - one_byte_read_ns;
 786
 787	idt82p33->tod_write_overhead_ns -= trailing_overhead_ns;
 788
 789	return err;
 790}
 791
 792static int idt82p33_check_and_set_masks(struct idt82p33 *idt82p33,
 793					u8 page,
 794					u8 offset,
 795					u8 val)
 796{
 797	int err = 0;
 798
 799	if (page == PLLMASK_ADDR_HI && offset == PLLMASK_ADDR_LO) {
 800		if ((val & 0xfc) || !(val & 0x3)) {
 801			dev_err(idt82p33->dev,
 802				"Invalid PLL mask 0x%x\n", val);
 803			err = -EINVAL;
 804		} else {
 805			idt82p33->pll_mask = val;
 806		}
 807	} else if (page == PLL0_OUTMASK_ADDR_HI &&
 808		offset == PLL0_OUTMASK_ADDR_LO) {
 809		idt82p33->channel[0].output_mask = val;
 810	} else if (page == PLL1_OUTMASK_ADDR_HI &&
 811		offset == PLL1_OUTMASK_ADDR_LO) {
 812		idt82p33->channel[1].output_mask = val;
 813	}
 814
 815	return err;
 816}
 817
 818static void idt82p33_display_masks(struct idt82p33 *idt82p33)
 819{
 820	u8 mask, i;
 821
 822	dev_info(idt82p33->dev,
 823		 "pllmask = 0x%02x\n", idt82p33->pll_mask);
 824
 825	for (i = 0; i < MAX_PHC_PLL; i++) {
 826		mask = 1 << i;
 827
 828		if (mask & idt82p33->pll_mask)
 829			dev_info(idt82p33->dev,
 830				 "PLL%d output_mask = 0x%04x\n",
 831				 i, idt82p33->channel[i].output_mask);
 832	}
 833}
 834
 835static int idt82p33_sync_tod(struct idt82p33_channel *channel, bool enable)
 836{
 837	struct idt82p33 *idt82p33 = channel->idt82p33;
 838	u8 sync_cnfg;
 839	int err;
 840
 841	err = idt82p33_read(idt82p33, channel->dpll_sync_cnfg,
 842			    &sync_cnfg, sizeof(sync_cnfg));
 843	if (err)
 844		return err;
 845
 846	sync_cnfg &= ~SYNC_TOD;
 847	if (enable)
 848		sync_cnfg |= SYNC_TOD;
 849
 850	return idt82p33_write(idt82p33, channel->dpll_sync_cnfg,
 851			      &sync_cnfg, sizeof(sync_cnfg));
 852}
 853
 854static long idt82p33_work_handler(struct ptp_clock_info *ptp)
 855{
 856	struct idt82p33_channel *channel =
 857			container_of(ptp, struct idt82p33_channel, caps);
 858	struct idt82p33 *idt82p33 = channel->idt82p33;
 859
 860	mutex_lock(idt82p33->lock);
 861	(void)idt82p33_stop_ddco(channel);
 862	mutex_unlock(idt82p33->lock);
 863
 864	/* Return a negative value here to not reschedule */
 865	return -1;
 866}
 867
 868static int idt82p33_output_enable(struct idt82p33_channel *channel,
 869				  bool enable, unsigned int outn)
 870{
 871	struct idt82p33 *idt82p33 = channel->idt82p33;
 872	int err;
 873	u8 val;
 874
 875	err = idt82p33_read(idt82p33, OUT_MUX_CNFG(outn), &val, sizeof(val));
 876	if (err)
 877		return err;
 878	if (enable)
 879		val &= ~SQUELCH_ENABLE;
 880	else
 881		val |= SQUELCH_ENABLE;
 882
 883	return idt82p33_write(idt82p33, OUT_MUX_CNFG(outn), &val, sizeof(val));
 884}
 885
 886static int idt82p33_perout_enable(struct idt82p33_channel *channel,
 887				  bool enable,
 888				  struct ptp_perout_request *perout)
 889{
 890	/* Enable/disable individual output instead */
 891	return idt82p33_output_enable(channel, enable, perout->index);
 892}
 893
 894static int idt82p33_enable_tod(struct idt82p33_channel *channel)
 895{
 896	struct idt82p33 *idt82p33 = channel->idt82p33;
 897	struct timespec64 ts = {0, 0};
 898	int err;
 899
 900	err = idt82p33_measure_tod_write_overhead(channel);
 901
 902	if (err) {
 903		dev_err(idt82p33->dev,
 904			"Failed in %s with err %d!\n", __func__, err);
 905		return err;
 906	}
 907
 908	err = _idt82p33_settime(channel, &ts);
 909
 910	if (err)
 911		return err;
 912
 913	return idt82p33_sync_tod(channel, true);
 914}
 915
 916static void idt82p33_ptp_clock_unregister_all(struct idt82p33 *idt82p33)
 917{
 918	struct idt82p33_channel *channel;
 919	u8 i;
 920
 921	for (i = 0; i < MAX_PHC_PLL; i++) {
 922		channel = &idt82p33->channel[i];
 923		cancel_delayed_work_sync(&channel->adjtime_work);
 924		if (channel->ptp_clock)
 925			ptp_clock_unregister(channel->ptp_clock);
 926	}
 927}
 928
 929
 930
 931static int idt82p33_enable(struct ptp_clock_info *ptp,
 932			   struct ptp_clock_request *rq, int on)
 933{
 934	struct idt82p33_channel *channel =
 935			container_of(ptp, struct idt82p33_channel, caps);
 936	struct idt82p33 *idt82p33 = channel->idt82p33;
 937	int err = -EOPNOTSUPP;
 938
 939	mutex_lock(idt82p33->lock);
 940
 941	switch (rq->type) {
 942	case PTP_CLK_REQ_PEROUT:
 943		if (!on)
 944			err = idt82p33_perout_enable(channel, false,
 945						     &rq->perout);
 946		/* Only accept a 1-PPS aligned to the second. */
 947		else if (rq->perout.start.nsec || rq->perout.period.sec != 1 ||
 948			 rq->perout.period.nsec)
 949			err = -ERANGE;
 950		else
 951			err = idt82p33_perout_enable(channel, true,
 952						     &rq->perout);
 953		break;
 954	case PTP_CLK_REQ_EXTTS:
 955		err = idt82p33_extts_enable(channel, rq, on);
 956		break;
 957	default:
 958		break;
 959	}
 960
 961	mutex_unlock(idt82p33->lock);
 962
 963	if (err)
 964		dev_err(idt82p33->dev,
 965			"Failed in %s with err %d!\n", __func__, err);
 966	return err;
 967}
 968
 969static s32 idt82p33_getmaxphase(__always_unused struct ptp_clock_info *ptp)
 970{
 971	return WRITE_PHASE_OFFSET_LIMIT;
 972}
 973
 974static int idt82p33_adjwritephase(struct ptp_clock_info *ptp, s32 offset_ns)
 975{
 976	struct idt82p33_channel *channel =
 977		container_of(ptp, struct idt82p33_channel, caps);
 978	struct idt82p33 *idt82p33 = channel->idt82p33;
 979	s64 offset_regval;
 980	u8 val[4] = {0};
 981	int err;
 982
 983	/* Convert from phaseoffset_fs to register value */
 984	offset_regval = div_s64((s64)(-offset_ns) * 1000000000ll,
 985				IDT_T0DPLL_PHASE_RESOL);
 986
 987	val[0] = offset_regval & 0xFF;
 988	val[1] = (offset_regval >> 8) & 0xFF;
 989	val[2] = (offset_regval >> 16) & 0xFF;
 990	val[3] = (offset_regval >> 24) & 0x1F;
 991	val[3] |= PH_OFFSET_EN;
 992
 993	mutex_lock(idt82p33->lock);
 994
 995	err = idt82p33_dpll_set_mode(channel, PLL_MODE_WPH);
 996	if (err) {
 997		dev_err(idt82p33->dev,
 998			"Failed in %s with err %d!\n", __func__, err);
 999		goto out;
1000	}
1001
1002	err = idt82p33_write(idt82p33, channel->dpll_phase_cnfg, val,
1003			     sizeof(val));
1004
1005out:
1006	mutex_unlock(idt82p33->lock);
1007	return err;
1008}
1009
1010static int idt82p33_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
1011{
1012	struct idt82p33_channel *channel =
1013			container_of(ptp, struct idt82p33_channel, caps);
1014	struct idt82p33 *idt82p33 = channel->idt82p33;
1015	int err;
1016
1017	if (channel->ddco == true)
1018		return 0;
1019
1020	if (scaled_ppm == channel->current_freq)
1021		return 0;
1022
1023	mutex_lock(idt82p33->lock);
1024	err = _idt82p33_adjfine(channel, scaled_ppm);
1025
1026	if (err == 0)
1027		channel->current_freq = scaled_ppm;
1028	mutex_unlock(idt82p33->lock);
1029
1030	if (err)
1031		dev_err(idt82p33->dev,
1032			"Failed in %s with err %d!\n", __func__, err);
1033	return err;
1034}
1035
1036static int idt82p33_adjtime(struct ptp_clock_info *ptp, s64 delta_ns)
1037{
1038	struct idt82p33_channel *channel =
1039			container_of(ptp, struct idt82p33_channel, caps);
1040	struct idt82p33 *idt82p33 = channel->idt82p33;
1041	int err;
1042
1043	if (channel->ddco == true)
1044		return -EBUSY;
1045
1046	mutex_lock(idt82p33->lock);
1047
1048	if (abs(delta_ns) < phase_snap_threshold) {
1049		err = idt82p33_start_ddco(channel, delta_ns);
1050		mutex_unlock(idt82p33->lock);
1051		return err;
1052	}
1053
1054	/* Use more accurate internal 1pps triggered write first */
1055	err = _idt82p33_adjtime_internal_triggered(channel, delta_ns);
1056	if (err && delta_ns > IMMEDIATE_SNAP_THRESHOLD_NS)
1057		err = _idt82p33_adjtime_immediate(channel, delta_ns);
1058
1059	mutex_unlock(idt82p33->lock);
1060
1061	if (err)
1062		dev_err(idt82p33->dev,
1063			"Failed in %s with err %d!\n", __func__, err);
1064	return err;
1065}
1066
1067static int idt82p33_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
1068{
1069	struct idt82p33_channel *channel =
1070			container_of(ptp, struct idt82p33_channel, caps);
1071	struct idt82p33 *idt82p33 = channel->idt82p33;
1072	int err;
1073
1074	mutex_lock(idt82p33->lock);
1075	err = _idt82p33_gettime(channel, ts);
1076	mutex_unlock(idt82p33->lock);
1077
1078	if (err)
1079		dev_err(idt82p33->dev,
1080			"Failed in %s with err %d!\n", __func__, err);
1081	return err;
1082}
1083
1084static int idt82p33_settime(struct ptp_clock_info *ptp,
1085			    const struct timespec64 *ts)
1086{
1087	struct idt82p33_channel *channel =
1088			container_of(ptp, struct idt82p33_channel, caps);
1089	struct idt82p33 *idt82p33 = channel->idt82p33;
1090	int err;
1091
1092	mutex_lock(idt82p33->lock);
1093	err = _idt82p33_settime(channel, ts);
1094	mutex_unlock(idt82p33->lock);
1095
1096	if (err)
1097		dev_err(idt82p33->dev,
1098			"Failed in %s with err %d!\n", __func__, err);
1099	return err;
1100}
1101
1102static int idt82p33_channel_init(struct idt82p33 *idt82p33, u32 index)
1103{
1104	struct idt82p33_channel *channel = &idt82p33->channel[index];
1105
1106	switch (index) {
1107	case 0:
1108		channel->dpll_tod_cnfg = DPLL1_TOD_CNFG;
1109		channel->dpll_tod_trigger = DPLL1_TOD_TRIGGER;
1110		channel->dpll_tod_sts = DPLL1_TOD_STS;
1111		channel->dpll_mode_cnfg = DPLL1_OPERATING_MODE_CNFG;
1112		channel->dpll_freq_cnfg = DPLL1_HOLDOVER_FREQ_CNFG;
1113		channel->dpll_phase_cnfg = DPLL1_PHASE_OFFSET_CNFG;
1114		channel->dpll_sync_cnfg = DPLL1_SYNC_EDGE_CNFG;
1115		channel->dpll_input_mode_cnfg = DPLL1_INPUT_MODE_CNFG;
1116		break;
1117	case 1:
1118		channel->dpll_tod_cnfg = DPLL2_TOD_CNFG;
1119		channel->dpll_tod_trigger = DPLL2_TOD_TRIGGER;
1120		channel->dpll_tod_sts = DPLL2_TOD_STS;
1121		channel->dpll_mode_cnfg = DPLL2_OPERATING_MODE_CNFG;
1122		channel->dpll_freq_cnfg = DPLL2_HOLDOVER_FREQ_CNFG;
1123		channel->dpll_phase_cnfg = DPLL2_PHASE_OFFSET_CNFG;
1124		channel->dpll_sync_cnfg = DPLL2_SYNC_EDGE_CNFG;
1125		channel->dpll_input_mode_cnfg = DPLL2_INPUT_MODE_CNFG;
1126		break;
1127	default:
1128		return -EINVAL;
1129	}
1130
1131	channel->plln = index;
1132	channel->current_freq = 0;
1133	channel->idt82p33 = idt82p33;
1134	INIT_DELAYED_WORK(&channel->adjtime_work, idt82p33_adjtime_workaround);
1135
1136	return 0;
1137}
1138
1139static int idt82p33_verify_pin(struct ptp_clock_info *ptp, unsigned int pin,
1140			       enum ptp_pin_function func, unsigned int chan)
1141{
1142	switch (func) {
1143	case PTP_PF_NONE:
1144	case PTP_PF_EXTTS:
1145		break;
1146	case PTP_PF_PEROUT:
1147	case PTP_PF_PHYSYNC:
1148		return -1;
1149	}
1150	return 0;
1151}
1152
1153static void idt82p33_caps_init(u32 index, struct ptp_clock_info *caps,
1154			       struct ptp_pin_desc *pin_cfg, u8 max_pins)
1155{
1156	struct ptp_pin_desc *ppd;
1157	int i;
1158
1159	caps->owner = THIS_MODULE;
1160	caps->max_adj = DCO_MAX_PPB;
1161	caps->n_per_out = MAX_PER_OUT;
1162	caps->n_ext_ts = MAX_PHC_PLL;
1163	caps->n_pins = max_pins;
1164	caps->adjphase = idt82p33_adjwritephase;
1165	caps->getmaxphase = idt82p33_getmaxphase;
1166	caps->adjfine = idt82p33_adjfine;
1167	caps->adjtime = idt82p33_adjtime;
1168	caps->gettime64 = idt82p33_gettime;
1169	caps->settime64 = idt82p33_settime;
1170	caps->enable = idt82p33_enable;
1171	caps->verify = idt82p33_verify_pin;
1172	caps->do_aux_work = idt82p33_work_handler;
1173
1174	snprintf(caps->name, sizeof(caps->name), "IDT 82P33 PLL%u", index);
1175
1176	caps->pin_config = pin_cfg;
1177
1178	caps->supported_extts_flags = PTP_RISING_EDGE |
1179				      PTP_STRICT_FLAGS;
1180
1181	for (i = 0; i < max_pins; ++i) {
1182		ppd = &pin_cfg[i];
1183
1184		ppd->index = i;
1185		ppd->func = PTP_PF_NONE;
1186		ppd->chan = index;
1187		snprintf(ppd->name, sizeof(ppd->name), "in%d", 12 + i);
1188	}
1189}
1190
1191static int idt82p33_enable_channel(struct idt82p33 *idt82p33, u32 index)
1192{
1193	struct idt82p33_channel *channel;
1194	int err;
1195
1196	if (!(index < MAX_PHC_PLL))
1197		return -EINVAL;
1198
1199	channel = &idt82p33->channel[index];
1200
1201	err = idt82p33_channel_init(idt82p33, index);
1202	if (err) {
1203		dev_err(idt82p33->dev,
1204			"Channel_init failed in %s with err %d!\n",
1205			__func__, err);
1206		return err;
1207	}
1208
1209	idt82p33_caps_init(index, &channel->caps,
1210			   pin_config[index], MAX_TRIG_CLK);
1211
1212	channel->ptp_clock = ptp_clock_register(&channel->caps, NULL);
1213
1214	if (IS_ERR(channel->ptp_clock)) {
1215		err = PTR_ERR(channel->ptp_clock);
1216		channel->ptp_clock = NULL;
1217		return err;
1218	}
1219
1220	if (!channel->ptp_clock)
1221		return -ENOTSUPP;
1222
1223	err = idt82p33_dpll_set_mode(channel, PLL_MODE_DCO);
1224	if (err) {
1225		dev_err(idt82p33->dev,
1226			"Dpll_set_mode failed in %s with err %d!\n",
1227			__func__, err);
1228		return err;
1229	}
1230
1231	err = idt82p33_enable_tod(channel);
1232	if (err) {
1233		dev_err(idt82p33->dev,
1234			"Enable_tod failed in %s with err %d!\n",
1235			__func__, err);
1236		return err;
1237	}
1238
1239	dev_info(idt82p33->dev, "PLL%d registered as ptp%d\n",
1240		 index, channel->ptp_clock->index);
1241
1242	return 0;
1243}
1244
1245static int idt82p33_reset(struct idt82p33 *idt82p33, bool cold)
1246{
1247	int err;
1248	u8 cfg = SOFT_RESET_EN;
1249
1250	if (cold == true)
1251		goto cold_reset;
1252
1253	err = idt82p33_read(idt82p33, REG_SOFT_RESET, &cfg, sizeof(cfg));
1254	if (err) {
1255		dev_err(idt82p33->dev,
1256			"Soft reset failed with err %d!\n", err);
1257		return err;
1258	}
1259
1260	cfg |= SOFT_RESET_EN;
1261
1262cold_reset:
1263	err = idt82p33_write(idt82p33, REG_SOFT_RESET, &cfg, sizeof(cfg));
1264	if (err)
1265		dev_err(idt82p33->dev,
1266			"Cold reset failed with err %d!\n", err);
1267	return err;
1268}
1269
1270static int idt82p33_load_firmware(struct idt82p33 *idt82p33)
1271{
1272	char fname[128] = FW_FILENAME;
1273	const struct firmware *fw;
1274	struct idt82p33_fwrc *rec;
1275	u8 loaddr, page, val;
1276	int err;
1277	s32 len;
1278
1279	if (firmware) /* module parameter */
1280		snprintf(fname, sizeof(fname), "%s", firmware);
1281
1282	dev_info(idt82p33->dev, "requesting firmware '%s'\n", fname);
1283
1284	err = request_firmware(&fw, fname, idt82p33->dev);
1285
1286	if (err) {
1287		dev_err(idt82p33->dev,
1288			"Failed in %s with err %d!\n", __func__, err);
1289		return err;
1290	}
1291
1292	dev_dbg(idt82p33->dev, "firmware size %zu bytes\n", fw->size);
1293
1294	rec = (struct idt82p33_fwrc *) fw->data;
1295
1296	for (len = fw->size; len > 0; len -= sizeof(*rec)) {
1297
1298		if (rec->reserved) {
1299			dev_err(idt82p33->dev,
1300				"bad firmware, reserved field non-zero\n");
1301			err = -EINVAL;
1302		} else {
1303			val = rec->value;
1304			loaddr = rec->loaddr;
1305			page = rec->hiaddr;
1306
1307			rec++;
1308
1309			err = idt82p33_check_and_set_masks(idt82p33, page,
1310							   loaddr, val);
1311		}
1312
1313		if (err == 0) {
1314			/* Page size 128, last 4 bytes of page skipped */
1315			if (loaddr > 0x7b)
1316				continue;
1317
1318			err = idt82p33_write(idt82p33, REG_ADDR(page, loaddr),
1319					     &val, sizeof(val));
1320		}
1321
1322		if (err)
1323			goto out;
1324	}
1325
1326	idt82p33_display_masks(idt82p33);
1327out:
1328	release_firmware(fw);
1329	return err;
1330}
1331
1332static void idt82p33_extts_check(struct work_struct *work)
1333{
1334	struct idt82p33 *idt82p33 = container_of(work, struct idt82p33,
1335						 extts_work.work);
1336	struct idt82p33_channel *channel;
1337	int err;
1338	u8 mask;
1339	int i;
1340
1341	if (idt82p33->extts_mask == 0)
1342		return;
1343
1344	mutex_lock(idt82p33->lock);
1345
1346	for (i = 0; i < MAX_PHC_PLL; i++) {
1347		mask = 1 << i;
1348
1349		if ((idt82p33->extts_mask & mask) == 0)
1350			continue;
1351
1352		err = idt82p33_extts_check_channel(idt82p33, i);
1353
1354		if (err == 0) {
1355			/* trigger clears itself, so clear the mask */
1356			if (idt82p33->extts_single_shot) {
1357				idt82p33->extts_mask &= ~mask;
1358			} else {
1359				/* Re-arm */
1360				channel = &idt82p33->channel[i];
1361				arm_tod_read_with_trigger(channel, channel->tod_trigger);
1362			}
1363		}
1364	}
1365
1366	if (idt82p33->extts_mask)
1367		schedule_delayed_work(&idt82p33->extts_work,
1368				      msecs_to_jiffies(EXTTS_PERIOD_MS));
1369
1370	mutex_unlock(idt82p33->lock);
1371}
1372
1373static int idt82p33_probe(struct platform_device *pdev)
1374{
1375	struct rsmu_ddata *ddata = dev_get_drvdata(pdev->dev.parent);
1376	struct idt82p33 *idt82p33;
1377	int err;
1378	u8 i;
1379
1380	idt82p33 = devm_kzalloc(&pdev->dev,
1381				sizeof(struct idt82p33), GFP_KERNEL);
1382	if (!idt82p33)
1383		return -ENOMEM;
1384
1385	idt82p33->dev = &pdev->dev;
1386	idt82p33->mfd = pdev->dev.parent;
1387	idt82p33->lock = &ddata->lock;
1388	idt82p33->regmap = ddata->regmap;
1389	idt82p33->tod_write_overhead_ns = 0;
1390	idt82p33->calculate_overhead_flag = 0;
1391	idt82p33->pll_mask = DEFAULT_PLL_MASK;
1392	idt82p33->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0;
1393	idt82p33->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1;
1394	idt82p33->extts_mask = 0;
1395	INIT_DELAYED_WORK(&idt82p33->extts_work, idt82p33_extts_check);
1396
1397	mutex_lock(idt82p33->lock);
1398
1399	/* cold reset before loading firmware */
1400	idt82p33_reset(idt82p33, true);
1401
1402	err = idt82p33_load_firmware(idt82p33);
1403	if (err)
1404		dev_warn(idt82p33->dev,
1405			 "loading firmware failed with %d\n", err);
1406
1407	/* soft reset after loading firmware */
1408	idt82p33_reset(idt82p33, false);
1409
1410	if (idt82p33->pll_mask) {
1411		for (i = 0; i < MAX_PHC_PLL; i++) {
1412			if (idt82p33->pll_mask & (1 << i))
1413				err = idt82p33_enable_channel(idt82p33, i);
1414			else
1415				err = idt82p33_channel_init(idt82p33, i);
1416			if (err) {
1417				dev_err(idt82p33->dev,
1418					"Failed in %s with err %d!\n",
1419					__func__, err);
1420				break;
1421			}
1422		}
1423	} else {
1424		dev_err(idt82p33->dev,
1425			"no PLLs flagged as PHCs, nothing to do\n");
1426		err = -ENODEV;
1427	}
1428
1429	mutex_unlock(idt82p33->lock);
1430
1431	if (err) {
1432		idt82p33_ptp_clock_unregister_all(idt82p33);
1433		return err;
1434	}
1435
1436	platform_set_drvdata(pdev, idt82p33);
1437
1438	return 0;
1439}
1440
1441static void idt82p33_remove(struct platform_device *pdev)
1442{
1443	struct idt82p33 *idt82p33 = platform_get_drvdata(pdev);
1444
1445	cancel_delayed_work_sync(&idt82p33->extts_work);
1446
1447	idt82p33_ptp_clock_unregister_all(idt82p33);
1448}
1449
1450static struct platform_driver idt82p33_driver = {
1451	.driver = {
1452		.name = "82p33x1x-phc",
1453	},
1454	.probe = idt82p33_probe,
1455	.remove = idt82p33_remove,
1456};
1457
1458module_platform_driver(idt82p33_driver);