mtk-pm-domains.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2
  3#ifndef __SOC_MEDIATEK_MTK_PM_DOMAINS_H
  4#define __SOC_MEDIATEK_MTK_PM_DOMAINS_H
  5
  6#define MTK_SCPD_ACTIVE_WAKEUP		BIT(0)
  7#define MTK_SCPD_FWAIT_SRAM		BIT(1)
  8#define MTK_SCPD_SRAM_ISO		BIT(2)
  9#define MTK_SCPD_KEEP_DEFAULT_OFF	BIT(3)
 10#define MTK_SCPD_DOMAIN_SUPPLY		BIT(4)
 11/* can't set MTK_SCPD_KEEP_DEFAULT_OFF at the same time */
 12#define MTK_SCPD_ALWAYS_ON		BIT(5)
 13#define MTK_SCPD_EXT_BUCK_ISO		BIT(6)
 14#define MTK_SCPD_HAS_INFRA_NAO		BIT(7)
 15#define MTK_SCPD_STRICT_BUS_PROTECTION	BIT(8)
 16#define MTK_SCPD_SRAM_PDN_INVERTED	BIT(9)
 17#define MTK_SCPD_MODEM_PWRSEQ		BIT(10)
 18#define MTK_SCPD_SKIP_RESET_B		BIT(11)
 19#define MTK_SCPD_INFRA_PWR_CTL		BIT(12)
 20#define MTK_SCPD_CAPS(_scpd, _x)	((_scpd)->data ?		\
 21					 (_scpd)->data->caps & (_x) :	\
 22					 (_scpd)->hwv_data->caps & (_x))
 23
 24#define SPM_VDE_PWR_CON			0x0210
 25#define SPM_MFG_PWR_CON			0x0214
 26#define SPM_VEN_PWR_CON			0x0230
 27#define SPM_ISP_PWR_CON			0x0238
 28#define SPM_DIS_PWR_CON			0x023c
 29#define SPM_CONN_PWR_CON		0x0280
 30#define SPM_MD1_PWR_CON			0x0284
 31#define SPM_VEN2_PWR_CON		0x0298
 32#define SPM_AUDIO_PWR_CON		0x029c
 33#define SPM_MFG_2D_PWR_CON		0x02c0
 34#define SPM_MFG_ASYNC_PWR_CON		0x02c4
 35#define SPM_USB_PWR_CON			0x02cc
 36
 37#define SPM_PWR_STATUS			0x060c
 38#define SPM_PWR_STATUS_2ND		0x0610
 39
 40#define PWR_STATUS_MD1			BIT(0)
 41#define PWR_STATUS_CONN			BIT(1)
 42#define PWR_STATUS_DISP			BIT(3)
 43#define PWR_STATUS_MFG			BIT(4)
 44#define PWR_STATUS_ISP			BIT(5)
 45#define PWR_STATUS_VDEC			BIT(7)
 46#define PWR_STATUS_VENC_LT		BIT(20)
 47#define PWR_STATUS_VENC			BIT(21)
 48#define PWR_STATUS_MFG_2D		BIT(22)
 49#define PWR_STATUS_MFG_ASYNC		BIT(23)
 50#define PWR_STATUS_AUDIO		BIT(24)
 51#define PWR_STATUS_USB			BIT(25)
 52
 53#define SPM_MAX_BUS_PROT_DATA		7
 54
 55enum scpsys_bus_prot_flags {
 56	BUS_PROT_REG_UPDATE = BIT(1),
 57	BUS_PROT_IGNORE_CLR_ACK = BIT(2),
 58	BUS_PROT_INVERTED = BIT(3),
 59};
 60
 61enum scpsys_bus_prot_block {
 62	BUS_PROT_BLOCK_INFRA,
 63	BUS_PROT_BLOCK_INFRA_NAO,
 64	BUS_PROT_BLOCK_SMI,
 65	BUS_PROT_BLOCK_SPM,
 66	BUS_PROT_BLOCK_COUNT,
 67};
 68
 69#define _BUS_PROT_STA(_hwip, _sta_hwip, _set_clr_mask, _set, _clr,	\
 70		      _sta_mask, _sta, _flags)				\
 71	{								\
 72		.bus_prot_block = BUS_PROT_BLOCK_##_hwip,		\
 73		.bus_prot_sta_block = BUS_PROT_BLOCK_##_sta_hwip,	\
 74		.bus_prot_set_clr_mask = (_set_clr_mask),		\
 75		.bus_prot_set = _set,					\
 76		.bus_prot_clr = _clr,					\
 77		.bus_prot_sta_mask = (_sta_mask),			\
 78		.bus_prot_sta = _sta,					\
 79		.flags = _flags						\
 80	}
 81
 82#define _BUS_PROT(_hwip, _set_clr_mask, _set, _clr, _sta_mask,		\
 83		  _sta, _flags)						\
 84	_BUS_PROT_STA(_hwip, _hwip, _set_clr_mask, _set, _clr,		\
 85		      _sta_mask, _sta, _flags)
 86
 87#define BUS_PROT_WR(_hwip, _mask, _set, _clr, _sta)			\
 88		_BUS_PROT(_hwip, _mask, _set, _clr,  _mask, _sta, 0)
 89
 90#define BUS_PROT_WR_IGN(_hwip, _mask, _set, _clr, _sta)		\
 91		_BUS_PROT(_hwip, _mask, _set, _clr, _mask, _sta,	\
 92			  BUS_PROT_IGNORE_CLR_ACK)
 93
 94#define BUS_PROT_UPDATE(_hwip, _mask, _set, _clr, _sta)			\
 95		_BUS_PROT(_hwip, _mask, _set, _clr, _mask, _sta,	\
 96			  BUS_PROT_REG_UPDATE)
 97
 98#define BUS_PROT_INFRA_UPDATE_TOPAXI(_mask)			\
 99		BUS_PROT_UPDATE(INFRA, _mask,			\
100				INFRA_TOPAXI_PROTECTEN,		\
101				INFRA_TOPAXI_PROTECTEN,		\
102				INFRA_TOPAXI_PROTECTSTA1)
103
104struct scpsys_bus_prot_data {
105	u8 bus_prot_block;
106	u8 bus_prot_sta_block;
107	u32 bus_prot_set_clr_mask;
108	u32 bus_prot_set;
109	u32 bus_prot_clr;
110	u32 bus_prot_sta_mask;
111	u32 bus_prot_sta;
112	u8 flags;
113};
114
115/**
116 * enum scpsys_rtff_type - Type of RTFF Hardware for power domain
117 * @SCPSYS_RTFF_NONE:          RTFF HW not present or domain not RTFF managed
118 * @SCPSYS_RTFF_TYPE_GENERIC:  Non-CPU, peripheral-generic RTFF HW
119 * @SCPSYS_RTFF_TYPE_PCIE_PHY: PCI-Express PHY specific RTFF HW
120 * @SCPSYS_RTFF_TYPE_STOR_UFS: Storage (UFS) specific RTFF HW
121 * @SCPSYS_RTFF_TYPE_MAX:      Number of supported RTFF HW Types
122 */
123enum scpsys_rtff_type {
124	SCPSYS_RTFF_NONE = 0,
125	SCPSYS_RTFF_TYPE_GENERIC,
126	SCPSYS_RTFF_TYPE_PCIE_PHY,
127	SCPSYS_RTFF_TYPE_STOR_UFS,
128	SCPSYS_RTFF_TYPE_MAX
129};
130
131/**
132 * enum scpsys_mtcmos_type - Type of power domain controller
133 * @SCPSYS_MTCMOS_TYPE_DIRECT_CTL: Power domains are controlled with direct access
134 * @SCPSYS_MTCMOS_TYPE_HW_VOTER:   Hardware-assisted voted power domain control
135 * @SCPSYS_MTCMOS_TYPE_MAX:        Number of supported power domain types
136 */
137enum scpsys_mtcmos_type {
138	SCPSYS_MTCMOS_TYPE_DIRECT_CTL = 0,
139	SCPSYS_MTCMOS_TYPE_HW_VOTER,
140	SCPSYS_MTCMOS_TYPE_MAX
141};
142
143/**
144 * struct scpsys_domain_data - scp domain data for power on/off flow
145 * @name: The name of the power domain.
146 * @sta_mask: The mask for power on/off status bit.
147 * @sta2nd_mask: The mask for second power on/off status bit.
148 * @ctl_offs: The offset for main power control register.
149 * @sram_pdn_bits: The mask for sram power control bits.
150 * @sram_pdn_ack_bits: The mask for sram power control acked bits.
151 * @ext_buck_iso_offs: The offset for external buck isolation
152 * @ext_buck_iso_mask: The mask for external buck isolation
153 * @caps: The flag for active wake-up action.
154 * @rtff_type: The power domain RTFF HW type
155 * @bp_cfg: bus protection configuration for any subsystem
156 */
157struct scpsys_domain_data {
158	const char *name;
159	u32 sta_mask;
160	u32 sta2nd_mask;
161	int ctl_offs;
162	u32 sram_pdn_bits;
163	u32 sram_pdn_ack_bits;
164	int ext_buck_iso_offs;
165	u32 ext_buck_iso_mask;
166	u16 caps;
167	enum scpsys_rtff_type rtff_type;
168	const struct scpsys_bus_prot_data bp_cfg[SPM_MAX_BUS_PROT_DATA];
169	int pwr_sta_offs;
170	int pwr_sta2nd_offs;
171};
172
173/**
174 * struct scpsys_hwv_domain_data - Hardware Voter power domain data
175 * @name:       Name of the power domain
176 * @set:        Offset of the HWV SET register
177 * @clr:        Offset of the HWV CLEAR register
178 * @done:       Offset of the HWV DONE register
179 * @en:         Offset of the HWV ENABLE register
180 * @set_sta:    Offset of the HWV SET STATUS register
181 * @clr_sta:    Offset of the HWV CLEAR STATUS register
182 * @setclr_bit: The SET/CLR bit to enable/disable the power domain
183 * @sta_bit:    The SET/CLR STA bit to check for on/off ACK
184 * @caps:       The flag for active wake-up action
185 */
186struct scpsys_hwv_domain_data {
187	const char *name;
188	u16 set;
189	u16 clr;
190	u16 done;
191	u16 en;
192	u16 set_sta;
193	u16 clr_sta;
194	u8 setclr_bit;
195	u8 sta_bit;
196	u16 caps;
197};
198
199struct scpsys_soc_data {
200	const struct scpsys_domain_data *domains_data;
201	int num_domains;
202	const struct scpsys_hwv_domain_data *hwv_domains_data;
203	int num_hwv_domains;
204	enum scpsys_bus_prot_block *bus_prot_blocks;
205	int num_bus_prot_blocks;
206	enum scpsys_mtcmos_type type;
207};
208
209#endif /* __SOC_MEDIATEK_MTK_PM_DOMAINS_H */