mt8365-pm-domains.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2
  3#ifndef __SOC_MEDIATEK_MT8365_PM_DOMAINS_H
  4#define __SOC_MEDIATEK_MT8365_PM_DOMAINS_H
  5
  6#include "mtk-pm-domains.h"
  7#include <dt-bindings/power/mediatek,mt8365-power.h>
  8
  9/*
 10 * MT8365 power domain support
 11 */
 12
 13#define MT8365_BUS_PROT_INFRA_WR_TOPAXI(_mask)				\
 14		BUS_PROT_WR(INFRA, _mask,				\
 15			    MT8365_INFRA_TOPAXI_PROTECTEN_SET,		\
 16			    MT8365_INFRA_TOPAXI_PROTECTEN_CLR,		\
 17			    MT8365_INFRA_TOPAXI_PROTECTEN_STA1)
 18
 19#define MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(_mask)			\
 20		BUS_PROT_WR(INFRA, _mask,				\
 21			    MT8365_INFRA_TOPAXI_PROTECTEN_1_SET,	\
 22			    MT8365_INFRA_TOPAXI_PROTECTEN_1_CLR,	\
 23			    MT8365_INFRA_TOPAXI_PROTECTEN_1_STA1)
 24
 25#define MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(port)			\
 26		BUS_PROT_WR(SMI, BIT(port),				\
 27			    MT8365_SMI_COMMON_CLAMP_EN_SET,		\
 28			    MT8365_SMI_COMMON_CLAMP_EN_CLR,		\
 29			    MT8365_SMI_COMMON_CLAMP_EN)
 30
 31#define MT8365_BUS_PROT_WAY_EN(_set_mask, _set, _sta_mask, _sta)	\
 32		_BUS_PROT_STA(INFRA, INFRA_NAO, _set_mask, _set, _set,	\
 33			      _sta_mask, _sta,				\
 34			      BUS_PROT_INVERTED | BUS_PROT_REG_UPDATE)
 35
 36static enum scpsys_bus_prot_block scpsys_bus_prot_blocks_mt8365[] = {
 37	BUS_PROT_BLOCK_INFRA, BUS_PROT_BLOCK_INFRA_NAO, BUS_PROT_BLOCK_SMI
 38};
 39
 40static const struct scpsys_domain_data scpsys_domain_data_mt8365[] = {
 41	[MT8365_POWER_DOMAIN_MM] = {
 42		.name = "mm",
 43		.sta_mask = PWR_STATUS_DISP,
 44		.ctl_offs = 0x30c,
 45		.pwr_sta_offs = 0x0180,
 46		.pwr_sta2nd_offs = 0x0184,
 47		.sram_pdn_bits = GENMASK(8, 8),
 48		.sram_pdn_ack_bits = GENMASK(12, 12),
 49		.bp_cfg = {
 50			MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
 51				MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_0 |
 52				MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_1),
 53			MT8365_BUS_PROT_INFRA_WR_TOPAXI(
 54				MT8365_INFRA_TOPAXI_PROTECTEN_MM_M0 |
 55				MT8365_INFRA_TOPAXI_PROTECTEN_MDMCU_M1 |
 56				MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_0 |
 57				MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_1),
 58			MT8365_BUS_PROT_WAY_EN(
 59				MT8365_INFRA_TOPAXI_SI0_WAY_EN_MMAPB_S,
 60				MT8365_INFRA_TOPAXI_SI0_CTL,
 61				MT8365_INFRA_NAO_TOPAXI_SI0_CTRL_UPDATED,
 62				MT8365_INFRA_NAO_TOPAXI_SI0_STA),
 63			MT8365_BUS_PROT_WAY_EN(
 64				MT8365_INFRA_TOPAXI_SI2_WAY_EN_PERI_M1,
 65				MT8365_INFRA_TOPAXI_SI2_CTL,
 66				MT8365_INFRA_NAO_TOPAXI_SI2_CTRL_UPDATED,
 67				MT8365_INFRA_NAO_TOPAXI_SI2_STA),
 68			MT8365_BUS_PROT_INFRA_WR_TOPAXI(
 69				MT8365_INFRA_TOPAXI_PROTECTEN_MMAPB_S),
 70		},
 71		.caps = MTK_SCPD_STRICT_BUS_PROTECTION | MTK_SCPD_HAS_INFRA_NAO,
 72	},
 73	[MT8365_POWER_DOMAIN_VENC] = {
 74		.name = "venc",
 75		.sta_mask = PWR_STATUS_VENC,
 76		.ctl_offs = 0x0304,
 77		.pwr_sta_offs = 0x0180,
 78		.pwr_sta2nd_offs = 0x0184,
 79		.sram_pdn_bits = GENMASK(8, 8),
 80		.sram_pdn_ack_bits = GENMASK(12, 12),
 81		.bp_cfg = {
 82			MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(1),
 83		},
 84	},
 85	[MT8365_POWER_DOMAIN_AUDIO] = {
 86		.name = "audio",
 87		.sta_mask = PWR_STATUS_AUDIO,
 88		.ctl_offs = 0x0314,
 89		.pwr_sta_offs = 0x0180,
 90		.pwr_sta2nd_offs = 0x0184,
 91		.sram_pdn_bits = GENMASK(12, 8),
 92		.sram_pdn_ack_bits = GENMASK(17, 13),
 93		.bp_cfg = {
 94			MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
 95				MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_MP1_L2C_AFIFO |
 96				MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_AUDIO_M),
 97		},
 98		.caps = MTK_SCPD_ACTIVE_WAKEUP,
 99	},
100	[MT8365_POWER_DOMAIN_CONN] = {
101		.name = "conn",
102		.sta_mask = PWR_STATUS_CONN,
103		.ctl_offs = 0x032c,
104		.pwr_sta_offs = 0x0180,
105		.pwr_sta2nd_offs = 0x0184,
106		.sram_pdn_bits = 0,
107		.sram_pdn_ack_bits = 0,
108		.bp_cfg = {
109			MT8365_BUS_PROT_INFRA_WR_TOPAXI(
110				MT8365_INFRA_TOPAXI_PROTECTEN_AP2CONN_AHB),
111			MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
112				MT8365_INFRA_TOPAXI_PROTECTEN_1_CONN2INFRA_AXI_GALS_MST),
113			MT8365_BUS_PROT_INFRA_WR_TOPAXI(
114				MT8365_INFRA_TOPAXI_PROTECTEN_CONN2INFRA_AHB),
115			MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
116				MT8365_INFRA_TOPAXI_PROTECTEN_1_INFRA2CONN_AHB_GALS_SLV),
117		},
118		.caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_KEEP_DEFAULT_OFF,
119	},
120	[MT8365_POWER_DOMAIN_MFG] = {
121		.name = "mfg",
122		.sta_mask = PWR_STATUS_MFG,
123		.ctl_offs = 0x0338,
124		.pwr_sta_offs = 0x0180,
125		.pwr_sta2nd_offs = 0x0184,
126		.sram_pdn_bits = GENMASK(9, 8),
127		.sram_pdn_ack_bits = GENMASK(13, 12),
128		.bp_cfg = {
129			MT8365_BUS_PROT_INFRA_WR_TOPAXI(BIT(25)),
130			MT8365_BUS_PROT_INFRA_WR_TOPAXI(
131				MT8365_INFRA_TOPAXI_PROTECTEN_MFG_M0 |
132				MT8365_INFRA_TOPAXI_PROTECTEN_INFRA2MFG),
133		},
134	},
135	[MT8365_POWER_DOMAIN_CAM] = {
136		.name = "cam",
137		.sta_mask = BIT(25),
138		.ctl_offs = 0x0344,
139		.pwr_sta_offs = 0x0180,
140		.pwr_sta2nd_offs = 0x0184,
141		.sram_pdn_bits = GENMASK(9, 8),
142		.sram_pdn_ack_bits = GENMASK(13, 12),
143		.bp_cfg = {
144			MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
145				MT8365_INFRA_TOPAXI_PROTECTEN_1_CAM2MM_AXI_GALS_MST),
146			MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(2),
147		},
148	},
149	[MT8365_POWER_DOMAIN_VDEC] = {
150		.name = "vdec",
151		.sta_mask = BIT(31),
152		.ctl_offs = 0x0370,
153		.pwr_sta_offs = 0x0180,
154		.pwr_sta2nd_offs = 0x0184,
155		.sram_pdn_bits = GENMASK(8, 8),
156		.sram_pdn_ack_bits = GENMASK(12, 12),
157		.bp_cfg = {
158			MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(3),
159		},
160	},
161	[MT8365_POWER_DOMAIN_APU] = {
162		.name = "apu",
163		.sta_mask = BIT(16),
164		.ctl_offs = 0x0378,
165		.pwr_sta_offs = 0x0180,
166		.pwr_sta2nd_offs = 0x0184,
167		.sram_pdn_bits = GENMASK(14, 8),
168		.sram_pdn_ack_bits = GENMASK(21, 15),
169		.bp_cfg = {
170			MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
171				MT8365_INFRA_TOPAXI_PROTECTEN_1_APU2AP |
172				MT8365_INFRA_TOPAXI_PROTECTEN_1_APU_CBIP_GALS_MST),
173			MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(4),
174		},
175	},
176	[MT8365_POWER_DOMAIN_DSP] = {
177		.name = "dsp",
178		.sta_mask = BIT(17),
179		.ctl_offs = 0x037C,
180		.pwr_sta_offs = 0x0180,
181		.pwr_sta2nd_offs = 0x0184,
182		.sram_pdn_bits = GENMASK(11, 8),
183		.sram_pdn_ack_bits = GENMASK(15, 12),
184		.bp_cfg = {
185			MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
186				MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_INFRA_GALS_ADB |
187				MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_M |
188				MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_S),
189		},
190		.caps = MTK_SCPD_ACTIVE_WAKEUP,
191	},
192};
193
194static const struct scpsys_soc_data mt8365_scpsys_data = {
195	.domains_data = scpsys_domain_data_mt8365,
196	.num_domains = ARRAY_SIZE(scpsys_domain_data_mt8365),
197	.bus_prot_blocks = scpsys_bus_prot_blocks_mt8365,
198	.num_bus_prot_blocks = ARRAY_SIZE(scpsys_bus_prot_blocks_mt8365),
199};
200
201#endif /* __SOC_MEDIATEK_MT8365_PM_DOMAINS_H */