FILE
mt8195-pm-domains.h
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linux-6.19.14/drivers/pmdomain/mediatek/mt8195-pm-domains.h
1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> 5 */ 6 7#ifndef __SOC_MEDIATEK_MT8195_PM_DOMAINS_H 8#define __SOC_MEDIATEK_MT8195_PM_DOMAINS_H 9 10#include "mtk-pm-domains.h" 11#include <dt-bindings/power/mt8195-power.h> 12 13/* 14 * MT8195 power domain support 15 */ 16static enum scpsys_bus_prot_block scpsys_bus_prot_blocks_mt8195[] = { 17 BUS_PROT_BLOCK_INFRA 18}; 19 20static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { 21 [MT8195_POWER_DOMAIN_PCIE_MAC_P0] = { 22 .name = "pcie_mac_p0", 23 .sta_mask = BIT(11), 24 .ctl_offs = 0x328, 25 .pwr_sta_offs = 0x174, 26 .pwr_sta2nd_offs = 0x178, 27 .sram_pdn_bits = GENMASK(8, 8), 28 .sram_pdn_ack_bits = GENMASK(12, 12), 29 .bp_cfg = { 30 BUS_PROT_WR(INFRA, 31 MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0, 32 MT8195_TOP_AXI_PROT_EN_VDNR_SET, 33 MT8195_TOP_AXI_PROT_EN_VDNR_CLR, 34 MT8195_TOP_AXI_PROT_EN_VDNR_STA1), 35 BUS_PROT_WR(INFRA, 36 MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0, 37 MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, 38 MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, 39 MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), 40 }, 41 }, 42 [MT8195_POWER_DOMAIN_PCIE_MAC_P1] = { 43 .name = "pcie_mac_p1", 44 .sta_mask = BIT(12), 45 .ctl_offs = 0x32C, 46 .pwr_sta_offs = 0x174, 47 .pwr_sta2nd_offs = 0x178, 48 .sram_pdn_bits = GENMASK(8, 8), 49 .sram_pdn_ack_bits = GENMASK(12, 12), 50 .bp_cfg = { 51 BUS_PROT_WR(INFRA, 52 MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1, 53 MT8195_TOP_AXI_PROT_EN_VDNR_SET, 54 MT8195_TOP_AXI_PROT_EN_VDNR_CLR, 55 MT8195_TOP_AXI_PROT_EN_VDNR_STA1), 56 BUS_PROT_WR(INFRA, 57 MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1, 58 MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, 59 MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, 60 MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), 61 }, 62 }, 63 [MT8195_POWER_DOMAIN_PCIE_PHY] = { 64 .name = "pcie_phy", 65 .sta_mask = BIT(13), 66 .ctl_offs = 0x330, 67 .pwr_sta_offs = 0x174, 68 .pwr_sta2nd_offs = 0x178, 69 .caps = MTK_SCPD_ACTIVE_WAKEUP, 70 }, 71 [MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY] = { 72 .name = "ssusb_pcie_phy", 73 .sta_mask = BIT(14), 74 .ctl_offs = 0x334, 75 .pwr_sta_offs = 0x174, 76 .pwr_sta2nd_offs = 0x178, 77 .caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_ALWAYS_ON, 78 }, 79 [MT8195_POWER_DOMAIN_CSI_RX_TOP] = { 80 .name = "csi_rx_top", 81 .sta_mask = BIT(18), 82 .ctl_offs = 0x3C4, 83 .pwr_sta_offs = 0x174, 84 .pwr_sta2nd_offs = 0x178, 85 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 86 }, 87 [MT8195_POWER_DOMAIN_ETHER] = { 88 .name = "ether", 89 .sta_mask = BIT(3), 90 .ctl_offs = 0x344, 91 .pwr_sta_offs = 0x16c, 92 .pwr_sta2nd_offs = 0x170, 93 .sram_pdn_bits = GENMASK(8, 8), 94 .sram_pdn_ack_bits = GENMASK(12, 12), 95 .caps = MTK_SCPD_ACTIVE_WAKEUP, 96 }, 97 [MT8195_POWER_DOMAIN_ADSP] = { 98 .name = "adsp", 99 .sta_mask = BIT(10), 100 .ctl_offs = 0x360, 101 .pwr_sta_offs = 0x16c, 102 .pwr_sta2nd_offs = 0x170, 103 .sram_pdn_bits = GENMASK(8, 8), 104 .sram_pdn_ack_bits = GENMASK(12, 12), 105 .bp_cfg = { 106 BUS_PROT_WR(INFRA, 107 MT8195_TOP_AXI_PROT_EN_2_ADSP, 108 MT8195_TOP_AXI_PROT_EN_2_SET, 109 MT8195_TOP_AXI_PROT_EN_2_CLR, 110 MT8195_TOP_AXI_PROT_EN_2_STA1), 111 }, 112 .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIVE_WAKEUP, 113 }, 114 [MT8195_POWER_DOMAIN_AUDIO] = { 115 .name = "audio", 116 .sta_mask = BIT(8), 117 .ctl_offs = 0x358, 118 .pwr_sta_offs = 0x16c, 119 .pwr_sta2nd_offs = 0x170, 120 .sram_pdn_bits = GENMASK(8, 8), 121 .sram_pdn_ack_bits = GENMASK(12, 12), 122 .bp_cfg = { 123 BUS_PROT_WR(INFRA, 124 MT8195_TOP_AXI_PROT_EN_2_AUDIO, 125 MT8195_TOP_AXI_PROT_EN_2_SET, 126 MT8195_TOP_AXI_PROT_EN_2_CLR, 127 MT8195_TOP_AXI_PROT_EN_2_STA1), 128 }, 129 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP, 130 }, 131 [MT8195_POWER_DOMAIN_MFG0] = { 132 .name = "mfg0", 133 .sta_mask = BIT(1), 134 .ctl_offs = 0x300, 135 .pwr_sta_offs = 0x174, 136 .pwr_sta2nd_offs = 0x178, 137 .sram_pdn_bits = GENMASK(8, 8), 138 .sram_pdn_ack_bits = GENMASK(12, 12), 139 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY, 140 }, 141 [MT8195_POWER_DOMAIN_MFG1] = { 142 .name = "mfg1", 143 .sta_mask = BIT(2), 144 .ctl_offs = 0x304, 145 .pwr_sta_offs = 0x174, 146 .pwr_sta2nd_offs = 0x178, 147 .sram_pdn_bits = GENMASK(8, 8), 148 .sram_pdn_ack_bits = GENMASK(12, 12), 149 .bp_cfg = { 150 BUS_PROT_WR(INFRA, 151 MT8195_TOP_AXI_PROT_EN_MFG1, 152 MT8195_TOP_AXI_PROT_EN_SET, 153 MT8195_TOP_AXI_PROT_EN_CLR, 154 MT8195_TOP_AXI_PROT_EN_STA1), 155 BUS_PROT_WR(INFRA, 156 MT8195_TOP_AXI_PROT_EN_2_MFG1, 157 MT8195_TOP_AXI_PROT_EN_2_SET, 158 MT8195_TOP_AXI_PROT_EN_2_CLR, 159 MT8195_TOP_AXI_PROT_EN_2_STA1), 160 BUS_PROT_WR(INFRA, 161 MT8195_TOP_AXI_PROT_EN_1_MFG1, 162 MT8195_TOP_AXI_PROT_EN_1_SET, 163 MT8195_TOP_AXI_PROT_EN_1_CLR, 164 MT8195_TOP_AXI_PROT_EN_1_STA1), 165 BUS_PROT_WR(INFRA, 166 MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND, 167 MT8195_TOP_AXI_PROT_EN_2_SET, 168 MT8195_TOP_AXI_PROT_EN_2_CLR, 169 MT8195_TOP_AXI_PROT_EN_2_STA1), 170 BUS_PROT_WR(INFRA, 171 MT8195_TOP_AXI_PROT_EN_MFG1_2ND, 172 MT8195_TOP_AXI_PROT_EN_SET, 173 MT8195_TOP_AXI_PROT_EN_CLR, 174 MT8195_TOP_AXI_PROT_EN_STA1), 175 BUS_PROT_WR(INFRA, 176 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1, 177 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, 178 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, 179 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), 180 }, 181 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY, 182 }, 183 [MT8195_POWER_DOMAIN_MFG2] = { 184 .name = "mfg2", 185 .sta_mask = BIT(3), 186 .ctl_offs = 0x308, 187 .pwr_sta_offs = 0x174, 188 .pwr_sta2nd_offs = 0x178, 189 .sram_pdn_bits = GENMASK(8, 8), 190 .sram_pdn_ack_bits = GENMASK(12, 12), 191 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 192 }, 193 [MT8195_POWER_DOMAIN_MFG3] = { 194 .name = "mfg3", 195 .sta_mask = BIT(4), 196 .ctl_offs = 0x30C, 197 .pwr_sta_offs = 0x174, 198 .pwr_sta2nd_offs = 0x178, 199 .sram_pdn_bits = GENMASK(8, 8), 200 .sram_pdn_ack_bits = GENMASK(12, 12), 201 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 202 }, 203 [MT8195_POWER_DOMAIN_MFG4] = { 204 .name = "mfg4", 205 .sta_mask = BIT(5), 206 .ctl_offs = 0x310, 207 .pwr_sta_offs = 0x174, 208 .pwr_sta2nd_offs = 0x178, 209 .sram_pdn_bits = GENMASK(8, 8), 210 .sram_pdn_ack_bits = GENMASK(12, 12), 211 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 212 }, 213 [MT8195_POWER_DOMAIN_MFG5] = { 214 .name = "mfg5", 215 .sta_mask = BIT(6), 216 .ctl_offs = 0x314, 217 .pwr_sta_offs = 0x174, 218 .pwr_sta2nd_offs = 0x178, 219 .sram_pdn_bits = GENMASK(8, 8), 220 .sram_pdn_ack_bits = GENMASK(12, 12), 221 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 222 }, 223 [MT8195_POWER_DOMAIN_MFG6] = { 224 .name = "mfg6", 225 .sta_mask = BIT(7), 226 .ctl_offs = 0x318, 227 .pwr_sta_offs = 0x174, 228 .pwr_sta2nd_offs = 0x178, 229 .sram_pdn_bits = GENMASK(8, 8), 230 .sram_pdn_ack_bits = GENMASK(12, 12), 231 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 232 }, 233 [MT8195_POWER_DOMAIN_VPPSYS0] = { 234 .name = "vppsys0", 235 .sta_mask = BIT(11), 236 .ctl_offs = 0x364, 237 .pwr_sta_offs = 0x16c, 238 .pwr_sta2nd_offs = 0x170, 239 .sram_pdn_bits = GENMASK(8, 8), 240 .sram_pdn_ack_bits = GENMASK(12, 12), 241 .bp_cfg = { 242 BUS_PROT_WR(INFRA, 243 MT8195_TOP_AXI_PROT_EN_VPPSYS0, 244 MT8195_TOP_AXI_PROT_EN_SET, 245 MT8195_TOP_AXI_PROT_EN_CLR, 246 MT8195_TOP_AXI_PROT_EN_STA1), 247 BUS_PROT_WR(INFRA, 248 MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0, 249 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 250 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 251 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 252 BUS_PROT_WR(INFRA, 253 MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND, 254 MT8195_TOP_AXI_PROT_EN_SET, 255 MT8195_TOP_AXI_PROT_EN_CLR, 256 MT8195_TOP_AXI_PROT_EN_STA1), 257 BUS_PROT_WR(INFRA, 258 MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND, 259 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 260 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 261 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 262 BUS_PROT_WR(INFRA, 263 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0, 264 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, 265 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, 266 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), 267 }, 268 }, 269 [MT8195_POWER_DOMAIN_VDOSYS0] = { 270 .name = "vdosys0", 271 .sta_mask = BIT(13), 272 .ctl_offs = 0x36C, 273 .pwr_sta_offs = 0x16c, 274 .pwr_sta2nd_offs = 0x170, 275 .sram_pdn_bits = GENMASK(8, 8), 276 .sram_pdn_ack_bits = GENMASK(12, 12), 277 .bp_cfg = { 278 BUS_PROT_WR(INFRA, 279 MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0, 280 MT8195_TOP_AXI_PROT_EN_MM_SET, 281 MT8195_TOP_AXI_PROT_EN_MM_CLR, 282 MT8195_TOP_AXI_PROT_EN_MM_STA1), 283 BUS_PROT_WR(INFRA, 284 MT8195_TOP_AXI_PROT_EN_VDOSYS0, 285 MT8195_TOP_AXI_PROT_EN_SET, 286 MT8195_TOP_AXI_PROT_EN_CLR, 287 MT8195_TOP_AXI_PROT_EN_STA1), 288 BUS_PROT_WR(INFRA, 289 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0, 290 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, 291 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, 292 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), 293 }, 294 }, 295 [MT8195_POWER_DOMAIN_VPPSYS1] = { 296 .name = "vppsys1", 297 .sta_mask = BIT(12), 298 .ctl_offs = 0x368, 299 .pwr_sta_offs = 0x16c, 300 .pwr_sta2nd_offs = 0x170, 301 .sram_pdn_bits = GENMASK(8, 8), 302 .sram_pdn_ack_bits = GENMASK(12, 12), 303 .bp_cfg = { 304 BUS_PROT_WR(INFRA, 305 MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1, 306 MT8195_TOP_AXI_PROT_EN_MM_SET, 307 MT8195_TOP_AXI_PROT_EN_MM_CLR, 308 MT8195_TOP_AXI_PROT_EN_MM_STA1), 309 BUS_PROT_WR(INFRA, 310 MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND, 311 MT8195_TOP_AXI_PROT_EN_MM_SET, 312 MT8195_TOP_AXI_PROT_EN_MM_CLR, 313 MT8195_TOP_AXI_PROT_EN_MM_STA1), 314 BUS_PROT_WR(INFRA, 315 MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1, 316 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 317 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 318 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 319 }, 320 }, 321 [MT8195_POWER_DOMAIN_VDOSYS1] = { 322 .name = "vdosys1", 323 .sta_mask = BIT(14), 324 .ctl_offs = 0x370, 325 .pwr_sta_offs = 0x16c, 326 .pwr_sta2nd_offs = 0x170, 327 .sram_pdn_bits = GENMASK(8, 8), 328 .sram_pdn_ack_bits = GENMASK(12, 12), 329 .bp_cfg = { 330 BUS_PROT_WR(INFRA, 331 MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1, 332 MT8195_TOP_AXI_PROT_EN_MM_SET, 333 MT8195_TOP_AXI_PROT_EN_MM_CLR, 334 MT8195_TOP_AXI_PROT_EN_MM_STA1), 335 BUS_PROT_WR(INFRA, 336 MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND, 337 MT8195_TOP_AXI_PROT_EN_MM_SET, 338 MT8195_TOP_AXI_PROT_EN_MM_CLR, 339 MT8195_TOP_AXI_PROT_EN_MM_STA1), 340 BUS_PROT_WR(INFRA, 341 MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1, 342 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 343 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 344 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 345 }, 346 }, 347 [MT8195_POWER_DOMAIN_DP_TX] = { 348 .name = "dp_tx", 349 .sta_mask = BIT(16), 350 .ctl_offs = 0x378, 351 .pwr_sta_offs = 0x16c, 352 .pwr_sta2nd_offs = 0x170, 353 .sram_pdn_bits = GENMASK(8, 8), 354 .sram_pdn_ack_bits = GENMASK(12, 12), 355 .bp_cfg = { 356 BUS_PROT_WR(INFRA, 357 MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX, 358 MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, 359 MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, 360 MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), 361 }, 362 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 363 }, 364 [MT8195_POWER_DOMAIN_EPD_TX] = { 365 .name = "epd_tx", 366 .sta_mask = BIT(17), 367 .ctl_offs = 0x37C, 368 .pwr_sta_offs = 0x16c, 369 .pwr_sta2nd_offs = 0x170, 370 .sram_pdn_bits = GENMASK(8, 8), 371 .sram_pdn_ack_bits = GENMASK(12, 12), 372 .bp_cfg = { 373 BUS_PROT_WR(INFRA, 374 MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX, 375 MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, 376 MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, 377 MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), 378 }, 379 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 380 }, 381 [MT8195_POWER_DOMAIN_HDMI_TX] = { 382 .name = "hdmi_tx", 383 .sta_mask = BIT(18), 384 .ctl_offs = 0x380, 385 .pwr_sta_offs = 0x16c, 386 .pwr_sta2nd_offs = 0x170, 387 .sram_pdn_bits = GENMASK(8, 8), 388 .sram_pdn_ack_bits = GENMASK(12, 12), 389 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP, 390 }, 391 [MT8195_POWER_DOMAIN_WPESYS] = { 392 .name = "wpesys", 393 .sta_mask = BIT(15), 394 .ctl_offs = 0x374, 395 .pwr_sta_offs = 0x16c, 396 .pwr_sta2nd_offs = 0x170, 397 .sram_pdn_bits = GENMASK(8, 8), 398 .sram_pdn_ack_bits = GENMASK(12, 12), 399 .bp_cfg = { 400 BUS_PROT_WR(INFRA, 401 MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS, 402 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 403 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 404 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 405 BUS_PROT_WR(INFRA, 406 MT8195_TOP_AXI_PROT_EN_MM_WPESYS, 407 MT8195_TOP_AXI_PROT_EN_MM_SET, 408 MT8195_TOP_AXI_PROT_EN_MM_CLR, 409 MT8195_TOP_AXI_PROT_EN_MM_STA1), 410 BUS_PROT_WR(INFRA, 411 MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND, 412 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 413 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 414 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 415 }, 416 }, 417 [MT8195_POWER_DOMAIN_VDEC0] = { 418 .name = "vdec0", 419 .sta_mask = BIT(20), 420 .ctl_offs = 0x388, 421 .pwr_sta_offs = 0x16c, 422 .pwr_sta2nd_offs = 0x170, 423 .sram_pdn_bits = GENMASK(8, 8), 424 .sram_pdn_ack_bits = GENMASK(12, 12), 425 .bp_cfg = { 426 BUS_PROT_WR(INFRA, 427 MT8195_TOP_AXI_PROT_EN_MM_VDEC0, 428 MT8195_TOP_AXI_PROT_EN_MM_SET, 429 MT8195_TOP_AXI_PROT_EN_MM_CLR, 430 MT8195_TOP_AXI_PROT_EN_MM_STA1), 431 BUS_PROT_WR(INFRA, 432 MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0, 433 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 434 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 435 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 436 BUS_PROT_WR(INFRA, 437 MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND, 438 MT8195_TOP_AXI_PROT_EN_MM_SET, 439 MT8195_TOP_AXI_PROT_EN_MM_CLR, 440 MT8195_TOP_AXI_PROT_EN_MM_STA1), 441 BUS_PROT_WR(INFRA, 442 MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND, 443 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 444 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 445 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 446 }, 447 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 448 }, 449 [MT8195_POWER_DOMAIN_VDEC1] = { 450 .name = "vdec1", 451 .sta_mask = BIT(21), 452 .ctl_offs = 0x38C, 453 .pwr_sta_offs = 0x16c, 454 .pwr_sta2nd_offs = 0x170, 455 .sram_pdn_bits = GENMASK(8, 8), 456 .sram_pdn_ack_bits = GENMASK(12, 12), 457 .bp_cfg = { 458 BUS_PROT_WR(INFRA, 459 MT8195_TOP_AXI_PROT_EN_MM_VDEC1, 460 MT8195_TOP_AXI_PROT_EN_MM_SET, 461 MT8195_TOP_AXI_PROT_EN_MM_CLR, 462 MT8195_TOP_AXI_PROT_EN_MM_STA1), 463 BUS_PROT_WR(INFRA, 464 MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND, 465 MT8195_TOP_AXI_PROT_EN_MM_SET, 466 MT8195_TOP_AXI_PROT_EN_MM_CLR, 467 MT8195_TOP_AXI_PROT_EN_MM_STA1), 468 }, 469 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 470 }, 471 [MT8195_POWER_DOMAIN_VDEC2] = { 472 .name = "vdec2", 473 .sta_mask = BIT(22), 474 .ctl_offs = 0x390, 475 .pwr_sta_offs = 0x16c, 476 .pwr_sta2nd_offs = 0x170, 477 .sram_pdn_bits = GENMASK(8, 8), 478 .sram_pdn_ack_bits = GENMASK(12, 12), 479 .bp_cfg = { 480 BUS_PROT_WR(INFRA, 481 MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2, 482 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 483 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 484 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 485 BUS_PROT_WR(INFRA, 486 MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND, 487 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 488 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 489 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 490 }, 491 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 492 }, 493 [MT8195_POWER_DOMAIN_VENC] = { 494 .name = "venc", 495 .sta_mask = BIT(23), 496 .ctl_offs = 0x394, 497 .pwr_sta_offs = 0x16c, 498 .pwr_sta2nd_offs = 0x170, 499 .sram_pdn_bits = GENMASK(8, 8), 500 .sram_pdn_ack_bits = GENMASK(12, 12), 501 .bp_cfg = { 502 BUS_PROT_WR(INFRA, 503 MT8195_TOP_AXI_PROT_EN_MM_VENC, 504 MT8195_TOP_AXI_PROT_EN_MM_SET, 505 MT8195_TOP_AXI_PROT_EN_MM_CLR, 506 MT8195_TOP_AXI_PROT_EN_MM_STA1), 507 BUS_PROT_WR(INFRA, 508 MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND, 509 MT8195_TOP_AXI_PROT_EN_MM_SET, 510 MT8195_TOP_AXI_PROT_EN_MM_CLR, 511 MT8195_TOP_AXI_PROT_EN_MM_STA1), 512 BUS_PROT_WR(INFRA, 513 MT8195_TOP_AXI_PROT_EN_MM_2_VENC, 514 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 515 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 516 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 517 }, 518 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 519 }, 520 [MT8195_POWER_DOMAIN_VENC_CORE1] = { 521 .name = "venc_core1", 522 .sta_mask = BIT(24), 523 .ctl_offs = 0x398, 524 .pwr_sta_offs = 0x16c, 525 .pwr_sta2nd_offs = 0x170, 526 .sram_pdn_bits = GENMASK(8, 8), 527 .sram_pdn_ack_bits = GENMASK(12, 12), 528 .bp_cfg = { 529 BUS_PROT_WR(INFRA, 530 MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1, 531 MT8195_TOP_AXI_PROT_EN_MM_SET, 532 MT8195_TOP_AXI_PROT_EN_MM_CLR, 533 MT8195_TOP_AXI_PROT_EN_MM_STA1), 534 BUS_PROT_WR(INFRA, 535 MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1, 536 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 537 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 538 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 539 }, 540 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 541 }, 542 [MT8195_POWER_DOMAIN_IMG] = { 543 .name = "img", 544 .sta_mask = BIT(29), 545 .ctl_offs = 0x3AC, 546 .pwr_sta_offs = 0x16c, 547 .pwr_sta2nd_offs = 0x170, 548 .sram_pdn_bits = GENMASK(8, 8), 549 .sram_pdn_ack_bits = GENMASK(12, 12), 550 .bp_cfg = { 551 BUS_PROT_WR(INFRA, 552 MT8195_TOP_AXI_PROT_EN_MM_IMG, 553 MT8195_TOP_AXI_PROT_EN_MM_SET, 554 MT8195_TOP_AXI_PROT_EN_MM_CLR, 555 MT8195_TOP_AXI_PROT_EN_MM_STA1), 556 BUS_PROT_WR(INFRA, 557 MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND, 558 MT8195_TOP_AXI_PROT_EN_MM_SET, 559 MT8195_TOP_AXI_PROT_EN_MM_CLR, 560 MT8195_TOP_AXI_PROT_EN_MM_STA1), 561 }, 562 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 563 }, 564 [MT8195_POWER_DOMAIN_DIP] = { 565 .name = "dip", 566 .sta_mask = BIT(30), 567 .ctl_offs = 0x3B0, 568 .pwr_sta_offs = 0x16c, 569 .pwr_sta2nd_offs = 0x170, 570 .sram_pdn_bits = GENMASK(8, 8), 571 .sram_pdn_ack_bits = GENMASK(12, 12), 572 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 573 }, 574 [MT8195_POWER_DOMAIN_IPE] = { 575 .name = "ipe", 576 .sta_mask = BIT(31), 577 .ctl_offs = 0x3B4, 578 .pwr_sta_offs = 0x16c, 579 .pwr_sta2nd_offs = 0x170, 580 .sram_pdn_bits = GENMASK(8, 8), 581 .sram_pdn_ack_bits = GENMASK(12, 12), 582 .bp_cfg = { 583 BUS_PROT_WR(INFRA, 584 MT8195_TOP_AXI_PROT_EN_MM_IPE, 585 MT8195_TOP_AXI_PROT_EN_MM_SET, 586 MT8195_TOP_AXI_PROT_EN_MM_CLR, 587 MT8195_TOP_AXI_PROT_EN_MM_STA1), 588 BUS_PROT_WR(INFRA, 589 MT8195_TOP_AXI_PROT_EN_MM_2_IPE, 590 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 591 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 592 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 593 }, 594 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 595 }, 596 [MT8195_POWER_DOMAIN_CAM] = { 597 .name = "cam", 598 .sta_mask = BIT(25), 599 .ctl_offs = 0x39C, 600 .pwr_sta_offs = 0x16c, 601 .pwr_sta2nd_offs = 0x170, 602 .sram_pdn_bits = GENMASK(8, 8), 603 .sram_pdn_ack_bits = GENMASK(12, 12), 604 .bp_cfg = { 605 BUS_PROT_WR(INFRA, 606 MT8195_TOP_AXI_PROT_EN_2_CAM, 607 MT8195_TOP_AXI_PROT_EN_2_SET, 608 MT8195_TOP_AXI_PROT_EN_2_CLR, 609 MT8195_TOP_AXI_PROT_EN_2_STA1), 610 BUS_PROT_WR(INFRA, 611 MT8195_TOP_AXI_PROT_EN_MM_CAM, 612 MT8195_TOP_AXI_PROT_EN_MM_SET, 613 MT8195_TOP_AXI_PROT_EN_MM_CLR, 614 MT8195_TOP_AXI_PROT_EN_MM_STA1), 615 BUS_PROT_WR(INFRA, 616 MT8195_TOP_AXI_PROT_EN_1_CAM, 617 MT8195_TOP_AXI_PROT_EN_1_SET, 618 MT8195_TOP_AXI_PROT_EN_1_CLR, 619 MT8195_TOP_AXI_PROT_EN_1_STA1), 620 BUS_PROT_WR(INFRA, 621 MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND, 622 MT8195_TOP_AXI_PROT_EN_MM_SET, 623 MT8195_TOP_AXI_PROT_EN_MM_CLR, 624 MT8195_TOP_AXI_PROT_EN_MM_STA1), 625 BUS_PROT_WR(INFRA, 626 MT8195_TOP_AXI_PROT_EN_MM_2_CAM, 627 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 628 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 629 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 630 }, 631 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 632 }, 633 [MT8195_POWER_DOMAIN_CAM_RAWA] = { 634 .name = "cam_rawa", 635 .sta_mask = BIT(26), 636 .ctl_offs = 0x3A0, 637 .pwr_sta_offs = 0x16c, 638 .pwr_sta2nd_offs = 0x170, 639 .sram_pdn_bits = GENMASK(8, 8), 640 .sram_pdn_ack_bits = GENMASK(12, 12), 641 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 642 }, 643 [MT8195_POWER_DOMAIN_CAM_RAWB] = { 644 .name = "cam_rawb", 645 .sta_mask = BIT(27), 646 .ctl_offs = 0x3A4, 647 .pwr_sta_offs = 0x16c, 648 .pwr_sta2nd_offs = 0x170, 649 .sram_pdn_bits = GENMASK(8, 8), 650 .sram_pdn_ack_bits = GENMASK(12, 12), 651 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 652 }, 653 [MT8195_POWER_DOMAIN_CAM_MRAW] = { 654 .name = "cam_mraw", 655 .sta_mask = BIT(28), 656 .ctl_offs = 0x3A8, 657 .pwr_sta_offs = 0x16c, 658 .pwr_sta2nd_offs = 0x170, 659 .sram_pdn_bits = GENMASK(8, 8), 660 .sram_pdn_ack_bits = GENMASK(12, 12), 661 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 662 }, 663}; 664 665static const struct scpsys_soc_data mt8195_scpsys_data = { 666 .domains_data = scpsys_domain_data_mt8195, 667 .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8195), 668 .bus_prot_blocks = scpsys_bus_prot_blocks_mt8195, 669 .num_bus_prot_blocks = ARRAY_SIZE(scpsys_bus_prot_blocks_mt8195), 670}; 671 672#endif /* __SOC_MEDIATEK_MT8195_PM_DOMAINS_H */
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