FILE
mt8192-pm-domains.h

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linux-6.19.14/drivers/pmdomain/mediatek/mt8192-pm-domains.h C
  1/* SPDX-License-Identifier: GPL-2.0-only */
  2
  3#ifndef __SOC_MEDIATEK_MT8192_PM_DOMAINS_H
  4#define __SOC_MEDIATEK_MT8192_PM_DOMAINS_H
  5
  6#include "mtk-pm-domains.h"
  7#include <dt-bindings/power/mt8192-power.h>
  8
  9/*
 10 * MT8192 power domain support
 11 */
 12static enum scpsys_bus_prot_block scpsys_bus_prot_blocks_mt8192[] = {
 13	BUS_PROT_BLOCK_INFRA
 14};
 15
 16static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
 17	[MT8192_POWER_DOMAIN_AUDIO] = {
 18		.name = "audio",
 19		.sta_mask = BIT(21),
 20		.ctl_offs = 0x0354,
 21		.pwr_sta_offs = 0x016c,
 22		.pwr_sta2nd_offs = 0x0170,
 23		.sram_pdn_bits = GENMASK(8, 8),
 24		.sram_pdn_ack_bits = GENMASK(12, 12),
 25		.bp_cfg = {
 26			BUS_PROT_WR(INFRA,
 27				    MT8192_TOP_AXI_PROT_EN_2_AUDIO,
 28				    MT8192_TOP_AXI_PROT_EN_2_SET,
 29				    MT8192_TOP_AXI_PROT_EN_2_CLR,
 30				    MT8192_TOP_AXI_PROT_EN_2_STA1),
 31		},
 32	},
 33	[MT8192_POWER_DOMAIN_CONN] = {
 34		.name = "conn",
 35		.sta_mask = PWR_STATUS_CONN,
 36		.ctl_offs = 0x0304,
 37		.pwr_sta_offs = 0x016c,
 38		.pwr_sta2nd_offs = 0x0170,
 39		.sram_pdn_bits = 0,
 40		.sram_pdn_ack_bits = 0,
 41		.bp_cfg = {
 42			BUS_PROT_WR(INFRA,
 43				    MT8192_TOP_AXI_PROT_EN_CONN,
 44				    MT8192_TOP_AXI_PROT_EN_SET,
 45				    MT8192_TOP_AXI_PROT_EN_CLR,
 46				    MT8192_TOP_AXI_PROT_EN_STA1),
 47			BUS_PROT_WR(INFRA,
 48				    MT8192_TOP_AXI_PROT_EN_CONN_2ND,
 49				    MT8192_TOP_AXI_PROT_EN_SET,
 50				    MT8192_TOP_AXI_PROT_EN_CLR,
 51				    MT8192_TOP_AXI_PROT_EN_STA1),
 52			BUS_PROT_WR(INFRA,
 53				    MT8192_TOP_AXI_PROT_EN_1_CONN,
 54				    MT8192_TOP_AXI_PROT_EN_1_SET,
 55				    MT8192_TOP_AXI_PROT_EN_1_CLR,
 56				    MT8192_TOP_AXI_PROT_EN_1_STA1),
 57		},
 58		.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
 59	},
 60	[MT8192_POWER_DOMAIN_MFG0] = {
 61		.name = "mfg0",
 62		.sta_mask = BIT(2),
 63		.ctl_offs = 0x0308,
 64		.pwr_sta_offs = 0x016c,
 65		.pwr_sta2nd_offs = 0x0170,
 66		.sram_pdn_bits = GENMASK(8, 8),
 67		.sram_pdn_ack_bits = GENMASK(12, 12),
 68		.caps = MTK_SCPD_DOMAIN_SUPPLY,
 69	},
 70	[MT8192_POWER_DOMAIN_MFG1] = {
 71		.name = "mfg1",
 72		.sta_mask = BIT(3),
 73		.ctl_offs = 0x030c,
 74		.pwr_sta_offs = 0x016c,
 75		.pwr_sta2nd_offs = 0x0170,
 76		.sram_pdn_bits = GENMASK(8, 8),
 77		.sram_pdn_ack_bits = GENMASK(12, 12),
 78		.bp_cfg = {
 79			BUS_PROT_WR(INFRA,
 80				    MT8192_TOP_AXI_PROT_EN_1_MFG1,
 81				    MT8192_TOP_AXI_PROT_EN_1_SET,
 82				    MT8192_TOP_AXI_PROT_EN_1_CLR,
 83				    MT8192_TOP_AXI_PROT_EN_1_STA1),
 84			BUS_PROT_WR(INFRA,
 85				    MT8192_TOP_AXI_PROT_EN_2_MFG1,
 86				    MT8192_TOP_AXI_PROT_EN_2_SET,
 87				    MT8192_TOP_AXI_PROT_EN_2_CLR,
 88				    MT8192_TOP_AXI_PROT_EN_2_STA1),
 89			BUS_PROT_WR(INFRA,
 90				    MT8192_TOP_AXI_PROT_EN_MFG1,
 91				    MT8192_TOP_AXI_PROT_EN_SET,
 92				    MT8192_TOP_AXI_PROT_EN_CLR,
 93				    MT8192_TOP_AXI_PROT_EN_STA1),
 94			BUS_PROT_WR(INFRA,
 95				    MT8192_TOP_AXI_PROT_EN_2_MFG1_2ND,
 96				    MT8192_TOP_AXI_PROT_EN_2_SET,
 97				    MT8192_TOP_AXI_PROT_EN_2_CLR,
 98				    MT8192_TOP_AXI_PROT_EN_2_STA1),
 99		},
100		.caps = MTK_SCPD_DOMAIN_SUPPLY,
101	},
102	[MT8192_POWER_DOMAIN_MFG2] = {
103		.name = "mfg2",
104		.sta_mask = BIT(4),
105		.ctl_offs = 0x0310,
106		.pwr_sta_offs = 0x016c,
107		.pwr_sta2nd_offs = 0x0170,
108		.sram_pdn_bits = GENMASK(8, 8),
109		.sram_pdn_ack_bits = GENMASK(12, 12),
110	},
111	[MT8192_POWER_DOMAIN_MFG3] = {
112		.name = "mfg3",
113		.sta_mask = BIT(5),
114		.ctl_offs = 0x0314,
115		.pwr_sta_offs = 0x016c,
116		.pwr_sta2nd_offs = 0x0170,
117		.sram_pdn_bits = GENMASK(8, 8),
118		.sram_pdn_ack_bits = GENMASK(12, 12),
119	},
120	[MT8192_POWER_DOMAIN_MFG4] = {
121		.name = "mfg4",
122		.sta_mask = BIT(6),
123		.ctl_offs = 0x0318,
124		.pwr_sta_offs = 0x016c,
125		.pwr_sta2nd_offs = 0x0170,
126		.sram_pdn_bits = GENMASK(8, 8),
127		.sram_pdn_ack_bits = GENMASK(12, 12),
128	},
129	[MT8192_POWER_DOMAIN_MFG5] = {
130		.name = "mfg5",
131		.sta_mask = BIT(7),
132		.ctl_offs = 0x031c,
133		.pwr_sta_offs = 0x016c,
134		.pwr_sta2nd_offs = 0x0170,
135		.sram_pdn_bits = GENMASK(8, 8),
136		.sram_pdn_ack_bits = GENMASK(12, 12),
137	},
138	[MT8192_POWER_DOMAIN_MFG6] = {
139		.name = "mfg6",
140		.sta_mask = BIT(8),
141		.ctl_offs = 0x0320,
142		.pwr_sta_offs = 0x016c,
143		.pwr_sta2nd_offs = 0x0170,
144		.sram_pdn_bits = GENMASK(8, 8),
145		.sram_pdn_ack_bits = GENMASK(12, 12),
146	},
147	[MT8192_POWER_DOMAIN_DISP] = {
148		.name = "disp",
149		.sta_mask = BIT(20),
150		.ctl_offs = 0x0350,
151		.pwr_sta_offs = 0x016c,
152		.pwr_sta2nd_offs = 0x0170,
153		.sram_pdn_bits = GENMASK(8, 8),
154		.sram_pdn_ack_bits = GENMASK(12, 12),
155		.bp_cfg = {
156			BUS_PROT_WR_IGN(INFRA,
157					MT8192_TOP_AXI_PROT_EN_MM_DISP,
158					MT8192_TOP_AXI_PROT_EN_MM_SET,
159					MT8192_TOP_AXI_PROT_EN_MM_CLR,
160					MT8192_TOP_AXI_PROT_EN_MM_STA1),
161			BUS_PROT_WR_IGN(INFRA,
162					MT8192_TOP_AXI_PROT_EN_MM_2_DISP,
163					MT8192_TOP_AXI_PROT_EN_MM_2_SET,
164					MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
165					MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
166			BUS_PROT_WR(INFRA,
167				    MT8192_TOP_AXI_PROT_EN_DISP,
168				    MT8192_TOP_AXI_PROT_EN_SET,
169				    MT8192_TOP_AXI_PROT_EN_CLR,
170				    MT8192_TOP_AXI_PROT_EN_STA1),
171			BUS_PROT_WR(INFRA,
172				    MT8192_TOP_AXI_PROT_EN_MM_DISP_2ND,
173				    MT8192_TOP_AXI_PROT_EN_MM_SET,
174				    MT8192_TOP_AXI_PROT_EN_MM_CLR,
175				    MT8192_TOP_AXI_PROT_EN_MM_STA1),
176			BUS_PROT_WR(INFRA,
177				    MT8192_TOP_AXI_PROT_EN_MM_2_DISP_2ND,
178				    MT8192_TOP_AXI_PROT_EN_MM_2_SET,
179				    MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
180				    MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
181		},
182	},
183	[MT8192_POWER_DOMAIN_IPE] = {
184		.name = "ipe",
185		.sta_mask = BIT(14),
186		.ctl_offs = 0x0338,
187		.pwr_sta_offs = 0x016c,
188		.pwr_sta2nd_offs = 0x0170,
189		.sram_pdn_bits = GENMASK(8, 8),
190		.sram_pdn_ack_bits = GENMASK(12, 12),
191		.bp_cfg = {
192			BUS_PROT_WR(INFRA,
193				    MT8192_TOP_AXI_PROT_EN_MM_IPE,
194				    MT8192_TOP_AXI_PROT_EN_MM_SET,
195				    MT8192_TOP_AXI_PROT_EN_MM_CLR,
196				    MT8192_TOP_AXI_PROT_EN_MM_STA1),
197			BUS_PROT_WR(INFRA,
198				    MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND,
199				    MT8192_TOP_AXI_PROT_EN_MM_SET,
200				    MT8192_TOP_AXI_PROT_EN_MM_CLR,
201				    MT8192_TOP_AXI_PROT_EN_MM_STA1),
202		},
203	},
204	[MT8192_POWER_DOMAIN_ISP] = {
205		.name = "isp",
206		.sta_mask = BIT(12),
207		.ctl_offs = 0x0330,
208		.pwr_sta_offs = 0x016c,
209		.pwr_sta2nd_offs = 0x0170,
210		.sram_pdn_bits = GENMASK(8, 8),
211		.sram_pdn_ack_bits = GENMASK(12, 12),
212		.bp_cfg = {
213			BUS_PROT_WR(INFRA,
214				    MT8192_TOP_AXI_PROT_EN_MM_2_ISP,
215				    MT8192_TOP_AXI_PROT_EN_MM_2_SET,
216				    MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
217				    MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
218			BUS_PROT_WR(INFRA,
219				    MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND,
220				    MT8192_TOP_AXI_PROT_EN_MM_2_SET,
221				    MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
222				    MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
223		},
224	},
225	[MT8192_POWER_DOMAIN_ISP2] = {
226		.name = "isp2",
227		.sta_mask = BIT(13),
228		.ctl_offs = 0x0334,
229		.pwr_sta_offs = 0x016c,
230		.pwr_sta2nd_offs = 0x0170,
231		.sram_pdn_bits = GENMASK(8, 8),
232		.sram_pdn_ack_bits = GENMASK(12, 12),
233		.bp_cfg = {
234			BUS_PROT_WR(INFRA,
235				    MT8192_TOP_AXI_PROT_EN_MM_ISP2,
236				    MT8192_TOP_AXI_PROT_EN_MM_SET,
237				    MT8192_TOP_AXI_PROT_EN_MM_CLR,
238				    MT8192_TOP_AXI_PROT_EN_MM_STA1),
239			BUS_PROT_WR(INFRA,
240				    MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND,
241				    MT8192_TOP_AXI_PROT_EN_MM_SET,
242				    MT8192_TOP_AXI_PROT_EN_MM_CLR,
243				    MT8192_TOP_AXI_PROT_EN_MM_STA1),
244		},
245	},
246	[MT8192_POWER_DOMAIN_MDP] = {
247		.name = "mdp",
248		.sta_mask = BIT(19),
249		.ctl_offs = 0x034c,
250		.pwr_sta_offs = 0x016c,
251		.pwr_sta2nd_offs = 0x0170,
252		.sram_pdn_bits = GENMASK(8, 8),
253		.sram_pdn_ack_bits = GENMASK(12, 12),
254		.bp_cfg = {
255			BUS_PROT_WR(INFRA,
256				    MT8192_TOP_AXI_PROT_EN_MM_2_MDP,
257				    MT8192_TOP_AXI_PROT_EN_MM_2_SET,
258				    MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
259				    MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
260			BUS_PROT_WR(INFRA,
261				    MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND,
262				    MT8192_TOP_AXI_PROT_EN_MM_2_SET,
263				    MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
264				    MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
265		},
266	},
267	[MT8192_POWER_DOMAIN_VENC] = {
268		.name = "venc",
269		.sta_mask = BIT(17),
270		.ctl_offs = 0x0344,
271		.pwr_sta_offs = 0x016c,
272		.pwr_sta2nd_offs = 0x0170,
273		.sram_pdn_bits = GENMASK(8, 8),
274		.sram_pdn_ack_bits = GENMASK(12, 12),
275		.bp_cfg = {
276			BUS_PROT_WR(INFRA,
277				    MT8192_TOP_AXI_PROT_EN_MM_VENC,
278				    MT8192_TOP_AXI_PROT_EN_MM_SET,
279				    MT8192_TOP_AXI_PROT_EN_MM_CLR,
280				    MT8192_TOP_AXI_PROT_EN_MM_STA1),
281			BUS_PROT_WR(INFRA,
282				    MT8192_TOP_AXI_PROT_EN_MM_VENC_2ND,
283				    MT8192_TOP_AXI_PROT_EN_MM_SET,
284				    MT8192_TOP_AXI_PROT_EN_MM_CLR,
285				    MT8192_TOP_AXI_PROT_EN_MM_STA1),
286		},
287	},
288	[MT8192_POWER_DOMAIN_VDEC] = {
289		.name = "vdec",
290		.sta_mask = BIT(15),
291		.ctl_offs = 0x033c,
292		.pwr_sta_offs = 0x016c,
293		.pwr_sta2nd_offs = 0x0170,
294		.sram_pdn_bits = GENMASK(8, 8),
295		.sram_pdn_ack_bits = GENMASK(12, 12),
296		.bp_cfg = {
297			BUS_PROT_WR(INFRA,
298				    MT8192_TOP_AXI_PROT_EN_MM_VDEC,
299				    MT8192_TOP_AXI_PROT_EN_MM_SET,
300				    MT8192_TOP_AXI_PROT_EN_MM_CLR,
301				    MT8192_TOP_AXI_PROT_EN_MM_STA1),
302			BUS_PROT_WR(INFRA,
303				    MT8192_TOP_AXI_PROT_EN_MM_VDEC_2ND,
304				    MT8192_TOP_AXI_PROT_EN_MM_SET,
305				    MT8192_TOP_AXI_PROT_EN_MM_CLR,
306				    MT8192_TOP_AXI_PROT_EN_MM_STA1),
307		},
308	},
309	[MT8192_POWER_DOMAIN_VDEC2] = {
310		.name = "vdec2",
311		.sta_mask = BIT(16),
312		.ctl_offs = 0x0340,
313		.pwr_sta_offs = 0x016c,
314		.pwr_sta2nd_offs = 0x0170,
315		.sram_pdn_bits = GENMASK(8, 8),
316		.sram_pdn_ack_bits = GENMASK(12, 12),
317	},
318	[MT8192_POWER_DOMAIN_CAM] = {
319		.name = "cam",
320		.sta_mask = BIT(23),
321		.ctl_offs = 0x035c,
322		.pwr_sta_offs = 0x016c,
323		.pwr_sta2nd_offs = 0x0170,
324		.sram_pdn_bits = GENMASK(8, 8),
325		.sram_pdn_ack_bits = GENMASK(12, 12),
326		.bp_cfg = {
327			BUS_PROT_WR(INFRA,
328				    MT8192_TOP_AXI_PROT_EN_2_CAM,
329				    MT8192_TOP_AXI_PROT_EN_2_SET,
330				    MT8192_TOP_AXI_PROT_EN_2_CLR,
331				    MT8192_TOP_AXI_PROT_EN_2_STA1),
332			BUS_PROT_WR(INFRA,
333				    MT8192_TOP_AXI_PROT_EN_MM_CAM,
334				    MT8192_TOP_AXI_PROT_EN_MM_SET,
335				    MT8192_TOP_AXI_PROT_EN_MM_CLR,
336				    MT8192_TOP_AXI_PROT_EN_MM_STA1),
337			BUS_PROT_WR(INFRA,
338				    MT8192_TOP_AXI_PROT_EN_1_CAM,
339				    MT8192_TOP_AXI_PROT_EN_1_SET,
340				    MT8192_TOP_AXI_PROT_EN_1_CLR,
341				    MT8192_TOP_AXI_PROT_EN_1_STA1),
342			BUS_PROT_WR(INFRA,
343				    MT8192_TOP_AXI_PROT_EN_MM_CAM_2ND,
344				    MT8192_TOP_AXI_PROT_EN_MM_SET,
345				    MT8192_TOP_AXI_PROT_EN_MM_CLR,
346				    MT8192_TOP_AXI_PROT_EN_MM_STA1),
347			BUS_PROT_WR(INFRA,
348				    MT8192_TOP_AXI_PROT_EN_VDNR_CAM,
349				    MT8192_TOP_AXI_PROT_EN_VDNR_SET,
350				    MT8192_TOP_AXI_PROT_EN_VDNR_CLR,
351				    MT8192_TOP_AXI_PROT_EN_VDNR_STA1),
352		},
353	},
354	[MT8192_POWER_DOMAIN_CAM_RAWA] = {
355		.name = "cam_rawa",
356		.sta_mask = BIT(24),
357		.ctl_offs = 0x0360,
358		.pwr_sta_offs = 0x016c,
359		.pwr_sta2nd_offs = 0x0170,
360		.sram_pdn_bits = GENMASK(8, 8),
361		.sram_pdn_ack_bits = GENMASK(12, 12),
362	},
363	[MT8192_POWER_DOMAIN_CAM_RAWB] = {
364		.name = "cam_rawb",
365		.sta_mask = BIT(25),
366		.ctl_offs = 0x0364,
367		.pwr_sta_offs = 0x016c,
368		.pwr_sta2nd_offs = 0x0170,
369		.sram_pdn_bits = GENMASK(8, 8),
370		.sram_pdn_ack_bits = GENMASK(12, 12),
371	},
372	[MT8192_POWER_DOMAIN_CAM_RAWC] = {
373		.name = "cam_rawc",
374		.sta_mask = BIT(26),
375		.ctl_offs = 0x0368,
376		.pwr_sta_offs = 0x016c,
377		.pwr_sta2nd_offs = 0x0170,
378		.sram_pdn_bits = GENMASK(8, 8),
379		.sram_pdn_ack_bits = GENMASK(12, 12),
380	},
381};
382
383static const struct scpsys_soc_data mt8192_scpsys_data = {
384	.domains_data = scpsys_domain_data_mt8192,
385	.num_domains = ARRAY_SIZE(scpsys_domain_data_mt8192),
386	.bus_prot_blocks = scpsys_bus_prot_blocks_mt8192,
387	.num_bus_prot_blocks = ARRAY_SIZE(scpsys_bus_prot_blocks_mt8192),
388};
389
390#endif /* __SOC_MEDIATEK_MT8192_PM_DOMAINS_H */
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