FILE
mt8188-pm-domains.h
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linux-6.19.14/drivers/pmdomain/mediatek/mt8188-pm-domains.h
1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (c) 2022 MediaTek Inc. 4 * Author: Garmin Chang <garmin.chang@mediatek.com> 5 */ 6 7#ifndef __SOC_MEDIATEK_MT8188_PM_DOMAINS_H 8#define __SOC_MEDIATEK_MT8188_PM_DOMAINS_H 9 10#include "mtk-pm-domains.h" 11#include <dt-bindings/power/mediatek,mt8188-power.h> 12 13/* 14 * MT8188 power domain support 15 */ 16 17static enum scpsys_bus_prot_block scpsys_bus_prot_blocks_mt8188[] = { 18 BUS_PROT_BLOCK_INFRA 19}; 20 21static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = { 22 [MT8188_POWER_DOMAIN_MFG0] = { 23 .name = "mfg0", 24 .sta_mask = BIT(1), 25 .ctl_offs = 0x300, 26 .pwr_sta_offs = 0x174, 27 .pwr_sta2nd_offs = 0x178, 28 .sram_pdn_bits = BIT(8), 29 .sram_pdn_ack_bits = BIT(12), 30 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY, 31 }, 32 [MT8188_POWER_DOMAIN_MFG1] = { 33 .name = "mfg1", 34 .sta_mask = BIT(2), 35 .ctl_offs = 0x304, 36 .pwr_sta_offs = 0x174, 37 .pwr_sta2nd_offs = 0x178, 38 .sram_pdn_bits = BIT(8), 39 .sram_pdn_ack_bits = BIT(12), 40 .bp_cfg = { 41 BUS_PROT_WR(INFRA, 42 MT8188_TOP_AXI_PROT_EN_MFG1_STEP1, 43 MT8188_TOP_AXI_PROT_EN_SET, 44 MT8188_TOP_AXI_PROT_EN_CLR, 45 MT8188_TOP_AXI_PROT_EN_STA), 46 BUS_PROT_WR(INFRA, 47 MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP2, 48 MT8188_TOP_AXI_PROT_EN_2_SET, 49 MT8188_TOP_AXI_PROT_EN_2_CLR, 50 MT8188_TOP_AXI_PROT_EN_2_STA), 51 BUS_PROT_WR(INFRA, 52 MT8188_TOP_AXI_PROT_EN_1_MFG1_STEP3, 53 MT8188_TOP_AXI_PROT_EN_1_SET, 54 MT8188_TOP_AXI_PROT_EN_1_CLR, 55 MT8188_TOP_AXI_PROT_EN_1_STA), 56 BUS_PROT_WR(INFRA, 57 MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP4, 58 MT8188_TOP_AXI_PROT_EN_2_SET, 59 MT8188_TOP_AXI_PROT_EN_2_CLR, 60 MT8188_TOP_AXI_PROT_EN_2_STA), 61 BUS_PROT_WR(INFRA, 62 MT8188_TOP_AXI_PROT_EN_MFG1_STEP5, 63 MT8188_TOP_AXI_PROT_EN_SET, 64 MT8188_TOP_AXI_PROT_EN_CLR, 65 MT8188_TOP_AXI_PROT_EN_STA), 66 BUS_PROT_WR(INFRA, 67 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP6, 68 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, 69 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, 70 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA), 71 }, 72 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY, 73 }, 74 [MT8188_POWER_DOMAIN_MFG2] = { 75 .name = "mfg2", 76 .sta_mask = BIT(3), 77 .ctl_offs = 0x308, 78 .pwr_sta_offs = 0x174, 79 .pwr_sta2nd_offs = 0x178, 80 .sram_pdn_bits = BIT(8), 81 .sram_pdn_ack_bits = BIT(12), 82 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 83 }, 84 [MT8188_POWER_DOMAIN_MFG3] = { 85 .name = "mfg3", 86 .sta_mask = BIT(4), 87 .ctl_offs = 0x30C, 88 .pwr_sta_offs = 0x174, 89 .pwr_sta2nd_offs = 0x178, 90 .sram_pdn_bits = BIT(8), 91 .sram_pdn_ack_bits = BIT(12), 92 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 93 }, 94 [MT8188_POWER_DOMAIN_MFG4] = { 95 .name = "mfg4", 96 .sta_mask = BIT(5), 97 .ctl_offs = 0x310, 98 .pwr_sta_offs = 0x174, 99 .pwr_sta2nd_offs = 0x178, 100 .sram_pdn_bits = BIT(8), 101 .sram_pdn_ack_bits = BIT(12), 102 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 103 }, 104 [MT8188_POWER_DOMAIN_PEXTP_MAC_P0] = { 105 .name = "pextp_mac_p0", 106 .sta_mask = BIT(10), 107 .ctl_offs = 0x324, 108 .pwr_sta_offs = 0x174, 109 .pwr_sta2nd_offs = 0x178, 110 .sram_pdn_bits = BIT(8), 111 .sram_pdn_ack_bits = BIT(12), 112 .bp_cfg = { 113 BUS_PROT_WR(INFRA, 114 MT8188_TOP_AXI_PROT_EN_PEXTP_MAC_P0_STEP1, 115 MT8188_TOP_AXI_PROT_EN_SET, 116 MT8188_TOP_AXI_PROT_EN_CLR, 117 MT8188_TOP_AXI_PROT_EN_STA), 118 BUS_PROT_WR(INFRA, 119 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_PEXTP_MAC_P0_STEP2, 120 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, 121 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, 122 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), 123 }, 124 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 125 }, 126 [MT8188_POWER_DOMAIN_PEXTP_PHY_TOP] = { 127 .name = "pextp_phy_top", 128 .sta_mask = BIT(12), 129 .ctl_offs = 0x328, 130 .pwr_sta_offs = 0x174, 131 .pwr_sta2nd_offs = 0x178, 132 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 133 }, 134 [MT8188_POWER_DOMAIN_CSIRX_TOP] = { 135 .name = "pextp_csirx_top", 136 .sta_mask = BIT(17), 137 .ctl_offs = 0x3C4, 138 .pwr_sta_offs = 0x174, 139 .pwr_sta2nd_offs = 0x178, 140 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 141 }, 142 [MT8188_POWER_DOMAIN_ETHER] = { 143 .name = "ether", 144 .sta_mask = BIT(1), 145 .ctl_offs = 0x338, 146 .pwr_sta_offs = 0x16C, 147 .pwr_sta2nd_offs = 0x170, 148 .sram_pdn_bits = BIT(8), 149 .sram_pdn_ack_bits = BIT(12), 150 .bp_cfg = { 151 BUS_PROT_WR(INFRA, 152 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_ETHER_STEP1, 153 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, 154 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, 155 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), 156 }, 157 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP, 158 }, 159 [MT8188_POWER_DOMAIN_HDMI_TX] = { 160 .name = "hdmi_tx", 161 .sta_mask = BIT(18), 162 .ctl_offs = 0x37C, 163 .pwr_sta_offs = 0x16C, 164 .pwr_sta2nd_offs = 0x170, 165 .sram_pdn_bits = BIT(8), 166 .sram_pdn_ack_bits = BIT(12), 167 .bp_cfg = { 168 BUS_PROT_WR(INFRA, 169 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_HDMI_TX_STEP1, 170 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, 171 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, 172 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), 173 }, 174 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP, 175 }, 176 [MT8188_POWER_DOMAIN_ADSP_AO] = { 177 .name = "adsp_ao", 178 .sta_mask = BIT(10), 179 .ctl_offs = 0x35C, 180 .pwr_sta_offs = 0x16C, 181 .pwr_sta2nd_offs = 0x170, 182 .ext_buck_iso_offs = 0x3EC, 183 .ext_buck_iso_mask = BIT(10), 184 .bp_cfg = { 185 BUS_PROT_WR(INFRA, 186 MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP1, 187 MT8188_TOP_AXI_PROT_EN_2_SET, 188 MT8188_TOP_AXI_PROT_EN_2_CLR, 189 MT8188_TOP_AXI_PROT_EN_2_STA), 190 BUS_PROT_WR(INFRA, 191 MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP2, 192 MT8188_TOP_AXI_PROT_EN_2_SET, 193 MT8188_TOP_AXI_PROT_EN_2_CLR, 194 MT8188_TOP_AXI_PROT_EN_2_STA), 195 }, 196 .caps = MTK_SCPD_ALWAYS_ON | MTK_SCPD_EXT_BUCK_ISO, 197 }, 198 [MT8188_POWER_DOMAIN_ADSP_INFRA] = { 199 .name = "adsp_infra", 200 .sta_mask = BIT(9), 201 .ctl_offs = 0x358, 202 .pwr_sta_offs = 0x16C, 203 .pwr_sta2nd_offs = 0x170, 204 .sram_pdn_bits = BIT(8), 205 .sram_pdn_ack_bits = BIT(12), 206 .bp_cfg = { 207 BUS_PROT_WR(INFRA, 208 MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP1, 209 MT8188_TOP_AXI_PROT_EN_2_SET, 210 MT8188_TOP_AXI_PROT_EN_2_CLR, 211 MT8188_TOP_AXI_PROT_EN_2_STA), 212 BUS_PROT_WR(INFRA, 213 MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP2, 214 MT8188_TOP_AXI_PROT_EN_2_SET, 215 MT8188_TOP_AXI_PROT_EN_2_CLR, 216 MT8188_TOP_AXI_PROT_EN_2_STA), 217 }, 218 .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_ALWAYS_ON, 219 }, 220 [MT8188_POWER_DOMAIN_ADSP] = { 221 .name = "adsp", 222 .sta_mask = BIT(8), 223 .ctl_offs = 0x354, 224 .pwr_sta_offs = 0x16C, 225 .pwr_sta2nd_offs = 0x170, 226 .sram_pdn_bits = BIT(8), 227 .sram_pdn_ack_bits = BIT(12), 228 .bp_cfg = { 229 BUS_PROT_WR(INFRA, 230 MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP1, 231 MT8188_TOP_AXI_PROT_EN_2_SET, 232 MT8188_TOP_AXI_PROT_EN_2_CLR, 233 MT8188_TOP_AXI_PROT_EN_2_STA), 234 BUS_PROT_WR(INFRA, 235 MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP2, 236 MT8188_TOP_AXI_PROT_EN_2_SET, 237 MT8188_TOP_AXI_PROT_EN_2_CLR, 238 MT8188_TOP_AXI_PROT_EN_2_STA), 239 }, 240 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIVE_WAKEUP, 241 }, 242 [MT8188_POWER_DOMAIN_AUDIO] = { 243 .name = "audio", 244 .sta_mask = BIT(6), 245 .ctl_offs = 0x34C, 246 .pwr_sta_offs = 0x16C, 247 .pwr_sta2nd_offs = 0x170, 248 .sram_pdn_bits = BIT(8), 249 .sram_pdn_ack_bits = BIT(12), 250 .bp_cfg = { 251 BUS_PROT_WR(INFRA, 252 MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1, 253 MT8188_TOP_AXI_PROT_EN_2_SET, 254 MT8188_TOP_AXI_PROT_EN_2_CLR, 255 MT8188_TOP_AXI_PROT_EN_2_STA), 256 BUS_PROT_WR(INFRA, 257 MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2, 258 MT8188_TOP_AXI_PROT_EN_2_SET, 259 MT8188_TOP_AXI_PROT_EN_2_CLR, 260 MT8188_TOP_AXI_PROT_EN_2_STA), 261 }, 262 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP, 263 }, 264 [MT8188_POWER_DOMAIN_AUDIO_ASRC] = { 265 .name = "audio_asrc", 266 .sta_mask = BIT(7), 267 .ctl_offs = 0x350, 268 .pwr_sta_offs = 0x16C, 269 .pwr_sta2nd_offs = 0x170, 270 .sram_pdn_bits = BIT(8), 271 .sram_pdn_ack_bits = BIT(12), 272 .bp_cfg = { 273 BUS_PROT_WR(INFRA, 274 MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP1, 275 MT8188_TOP_AXI_PROT_EN_2_SET, 276 MT8188_TOP_AXI_PROT_EN_2_CLR, 277 MT8188_TOP_AXI_PROT_EN_2_STA), 278 BUS_PROT_WR(INFRA, 279 MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP2, 280 MT8188_TOP_AXI_PROT_EN_2_SET, 281 MT8188_TOP_AXI_PROT_EN_2_CLR, 282 MT8188_TOP_AXI_PROT_EN_2_STA), 283 }, 284 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 285 }, 286 [MT8188_POWER_DOMAIN_VPPSYS0] = { 287 .name = "vppsys0", 288 .sta_mask = BIT(11), 289 .ctl_offs = 0x360, 290 .pwr_sta_offs = 0x16C, 291 .pwr_sta2nd_offs = 0x170, 292 .sram_pdn_bits = BIT(8), 293 .sram_pdn_ack_bits = BIT(12), 294 .bp_cfg = { 295 BUS_PROT_WR(INFRA, 296 MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP1, 297 MT8188_TOP_AXI_PROT_EN_SET, 298 MT8188_TOP_AXI_PROT_EN_CLR, 299 MT8188_TOP_AXI_PROT_EN_STA), 300 BUS_PROT_WR(INFRA, 301 MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP2, 302 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 303 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 304 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 305 BUS_PROT_WR(INFRA, 306 MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP3, 307 MT8188_TOP_AXI_PROT_EN_SET, 308 MT8188_TOP_AXI_PROT_EN_CLR, 309 MT8188_TOP_AXI_PROT_EN_STA), 310 BUS_PROT_WR(INFRA, 311 MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP4, 312 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 313 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 314 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 315 BUS_PROT_WR(INFRA, 316 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0_STEP5, 317 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, 318 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, 319 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA), 320 }, 321 }, 322 [MT8188_POWER_DOMAIN_VDOSYS0] = { 323 .name = "vdosys0", 324 .sta_mask = BIT(13), 325 .ctl_offs = 0x368, 326 .pwr_sta_offs = 0x16C, 327 .pwr_sta2nd_offs = 0x170, 328 .sram_pdn_bits = BIT(8), 329 .sram_pdn_ack_bits = BIT(12), 330 .bp_cfg = { 331 BUS_PROT_WR(INFRA, 332 MT8188_TOP_AXI_PROT_EN_MM_VDOSYS0_STEP1, 333 MT8188_TOP_AXI_PROT_EN_MM_SET, 334 MT8188_TOP_AXI_PROT_EN_MM_CLR, 335 MT8188_TOP_AXI_PROT_EN_MM_STA), 336 BUS_PROT_WR(INFRA, 337 MT8188_TOP_AXI_PROT_EN_VDOSYS0_STEP2, 338 MT8188_TOP_AXI_PROT_EN_SET, 339 MT8188_TOP_AXI_PROT_EN_CLR, 340 MT8188_TOP_AXI_PROT_EN_STA), 341 BUS_PROT_WR(INFRA, 342 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0_STEP3, 343 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, 344 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, 345 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA), 346 }, 347 }, 348 [MT8188_POWER_DOMAIN_VDOSYS1] = { 349 .name = "vdosys1", 350 .sta_mask = BIT(14), 351 .ctl_offs = 0x36C, 352 .pwr_sta_offs = 0x16C, 353 .pwr_sta2nd_offs = 0x170, 354 .sram_pdn_bits = BIT(8), 355 .sram_pdn_ack_bits = BIT(12), 356 .bp_cfg = { 357 BUS_PROT_WR(INFRA, 358 MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP1, 359 MT8188_TOP_AXI_PROT_EN_MM_SET, 360 MT8188_TOP_AXI_PROT_EN_MM_CLR, 361 MT8188_TOP_AXI_PROT_EN_MM_STA), 362 BUS_PROT_WR(INFRA, 363 MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP2, 364 MT8188_TOP_AXI_PROT_EN_MM_SET, 365 MT8188_TOP_AXI_PROT_EN_MM_CLR, 366 MT8188_TOP_AXI_PROT_EN_MM_STA), 367 BUS_PROT_WR(INFRA, 368 MT8188_TOP_AXI_PROT_EN_MM_2_VDOSYS1_STEP3, 369 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 370 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 371 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 372 }, 373 }, 374 [MT8188_POWER_DOMAIN_DP_TX] = { 375 .name = "dp_tx", 376 .sta_mask = BIT(16), 377 .ctl_offs = 0x374, 378 .pwr_sta_offs = 0x16C, 379 .pwr_sta2nd_offs = 0x170, 380 .sram_pdn_bits = BIT(8), 381 .sram_pdn_ack_bits = BIT(12), 382 .bp_cfg = { 383 BUS_PROT_WR(INFRA, 384 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_DP_TX_STEP1, 385 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, 386 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, 387 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), 388 }, 389 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 390 }, 391 [MT8188_POWER_DOMAIN_EDP_TX] = { 392 .name = "edp_tx", 393 .sta_mask = BIT(17), 394 .ctl_offs = 0x378, 395 .pwr_sta_offs = 0x16C, 396 .pwr_sta2nd_offs = 0x170, 397 .sram_pdn_bits = BIT(8), 398 .sram_pdn_ack_bits = BIT(12), 399 .bp_cfg = { 400 BUS_PROT_WR(INFRA, 401 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_EDP_TX_STEP1, 402 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, 403 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, 404 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), 405 }, 406 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 407 }, 408 [MT8188_POWER_DOMAIN_VPPSYS1] = { 409 .name = "vppsys1", 410 .sta_mask = BIT(12), 411 .ctl_offs = 0x364, 412 .pwr_sta_offs = 0x16C, 413 .pwr_sta2nd_offs = 0x170, 414 .sram_pdn_bits = BIT(8), 415 .sram_pdn_ack_bits = BIT(12), 416 .bp_cfg = { 417 BUS_PROT_WR(INFRA, 418 MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP1, 419 MT8188_TOP_AXI_PROT_EN_MM_SET, 420 MT8188_TOP_AXI_PROT_EN_MM_CLR, 421 MT8188_TOP_AXI_PROT_EN_MM_STA), 422 BUS_PROT_WR(INFRA, 423 MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP2, 424 MT8188_TOP_AXI_PROT_EN_MM_SET, 425 MT8188_TOP_AXI_PROT_EN_MM_CLR, 426 MT8188_TOP_AXI_PROT_EN_MM_STA), 427 BUS_PROT_WR(INFRA, 428 MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS1_STEP3, 429 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 430 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 431 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 432 }, 433 }, 434 [MT8188_POWER_DOMAIN_WPE] = { 435 .name = "wpe", 436 .sta_mask = BIT(15), 437 .ctl_offs = 0x370, 438 .pwr_sta_offs = 0x16C, 439 .pwr_sta2nd_offs = 0x170, 440 .sram_pdn_bits = BIT(8), 441 .sram_pdn_ack_bits = BIT(12), 442 .bp_cfg = { 443 BUS_PROT_WR(INFRA, 444 MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP1, 445 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 446 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 447 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 448 BUS_PROT_WR(INFRA, 449 MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP2, 450 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 451 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 452 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 453 }, 454 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 455 }, 456 [MT8188_POWER_DOMAIN_VDEC0] = { 457 .name = "vdec0", 458 .sta_mask = BIT(19), 459 .ctl_offs = 0x380, 460 .pwr_sta_offs = 0x16C, 461 .pwr_sta2nd_offs = 0x170, 462 .sram_pdn_bits = BIT(8), 463 .sram_pdn_ack_bits = BIT(12), 464 .bp_cfg = { 465 BUS_PROT_WR(INFRA, 466 MT8188_TOP_AXI_PROT_EN_MM_VDEC0_STEP1, 467 MT8188_TOP_AXI_PROT_EN_MM_SET, 468 MT8188_TOP_AXI_PROT_EN_MM_CLR, 469 MT8188_TOP_AXI_PROT_EN_MM_STA), 470 BUS_PROT_WR(INFRA, 471 MT8188_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2, 472 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 473 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 474 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 475 }, 476 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 477 }, 478 [MT8188_POWER_DOMAIN_VDEC1] = { 479 .name = "vdec1", 480 .sta_mask = BIT(20), 481 .ctl_offs = 0x384, 482 .pwr_sta_offs = 0x16C, 483 .pwr_sta2nd_offs = 0x170, 484 .sram_pdn_bits = BIT(8), 485 .sram_pdn_ack_bits = BIT(12), 486 .bp_cfg = { 487 BUS_PROT_WR(INFRA, 488 MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP1, 489 MT8188_TOP_AXI_PROT_EN_MM_SET, 490 MT8188_TOP_AXI_PROT_EN_MM_CLR, 491 MT8188_TOP_AXI_PROT_EN_MM_STA), 492 BUS_PROT_WR(INFRA, 493 MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP2, 494 MT8188_TOP_AXI_PROT_EN_MM_SET, 495 MT8188_TOP_AXI_PROT_EN_MM_CLR, 496 MT8188_TOP_AXI_PROT_EN_MM_STA), 497 }, 498 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 499 }, 500 [MT8188_POWER_DOMAIN_VENC] = { 501 .name = "venc", 502 .sta_mask = BIT(22), 503 .ctl_offs = 0x38C, 504 .pwr_sta_offs = 0x16C, 505 .pwr_sta2nd_offs = 0x170, 506 .sram_pdn_bits = BIT(8), 507 .sram_pdn_ack_bits = BIT(12), 508 .bp_cfg = { 509 BUS_PROT_WR(INFRA, 510 MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP1, 511 MT8188_TOP_AXI_PROT_EN_MM_SET, 512 MT8188_TOP_AXI_PROT_EN_MM_CLR, 513 MT8188_TOP_AXI_PROT_EN_MM_STA), 514 BUS_PROT_WR(INFRA, 515 MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP2, 516 MT8188_TOP_AXI_PROT_EN_MM_SET, 517 MT8188_TOP_AXI_PROT_EN_MM_CLR, 518 MT8188_TOP_AXI_PROT_EN_MM_STA), 519 BUS_PROT_WR(INFRA, 520 MT8188_TOP_AXI_PROT_EN_MM_2_VENC_STEP3, 521 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 522 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 523 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 524 }, 525 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 526 }, 527 [MT8188_POWER_DOMAIN_IMG_VCORE] = { 528 .name = "vcore", 529 .sta_mask = BIT(28), 530 .ctl_offs = 0x3A4, 531 .pwr_sta_offs = 0x16C, 532 .pwr_sta2nd_offs = 0x170, 533 .ext_buck_iso_offs = 0x3EC, 534 .ext_buck_iso_mask = BIT(12), 535 .bp_cfg = { 536 BUS_PROT_WR(INFRA, 537 MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP1, 538 MT8188_TOP_AXI_PROT_EN_MM_SET, 539 MT8188_TOP_AXI_PROT_EN_MM_CLR, 540 MT8188_TOP_AXI_PROT_EN_MM_STA), 541 BUS_PROT_WR(INFRA, 542 MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP2, 543 MT8188_TOP_AXI_PROT_EN_MM_SET, 544 MT8188_TOP_AXI_PROT_EN_MM_CLR, 545 MT8188_TOP_AXI_PROT_EN_MM_STA), 546 BUS_PROT_WR(INFRA, 547 MT8188_TOP_AXI_PROT_EN_MM_2_IMG_VCORE_STEP3, 548 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 549 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 550 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 551 }, 552 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY | 553 MTK_SCPD_EXT_BUCK_ISO, 554 }, 555 [MT8188_POWER_DOMAIN_IMG_MAIN] = { 556 .name = "img_main", 557 .sta_mask = BIT(29), 558 .ctl_offs = 0x3A8, 559 .pwr_sta_offs = 0x16C, 560 .pwr_sta2nd_offs = 0x170, 561 .sram_pdn_bits = BIT(8), 562 .sram_pdn_ack_bits = BIT(12), 563 .bp_cfg = { 564 BUS_PROT_WR(INFRA, 565 MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP1, 566 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 567 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 568 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 569 BUS_PROT_WR(INFRA, 570 MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP2, 571 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 572 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 573 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 574 }, 575 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 576 }, 577 [MT8188_POWER_DOMAIN_DIP] = { 578 .name = "dip", 579 .sta_mask = BIT(30), 580 .ctl_offs = 0x3AC, 581 .pwr_sta_offs = 0x16C, 582 .pwr_sta2nd_offs = 0x170, 583 .sram_pdn_bits = BIT(8), 584 .sram_pdn_ack_bits = BIT(12), 585 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 586 }, 587 [MT8188_POWER_DOMAIN_IPE] = { 588 .name = "ipe", 589 .sta_mask = BIT(31), 590 .ctl_offs = 0x3B0, 591 .pwr_sta_offs = 0x16C, 592 .pwr_sta2nd_offs = 0x170, 593 .sram_pdn_bits = BIT(8), 594 .sram_pdn_ack_bits = BIT(12), 595 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 596 }, 597 [MT8188_POWER_DOMAIN_CAM_VCORE] = { 598 .name = "cam_vcore", 599 .sta_mask = BIT(27), 600 .ctl_offs = 0x3A0, 601 .pwr_sta_offs = 0x16C, 602 .pwr_sta2nd_offs = 0x170, 603 .ext_buck_iso_offs = 0x3EC, 604 .ext_buck_iso_mask = BIT(11), 605 .bp_cfg = { 606 BUS_PROT_WR(INFRA, 607 MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP1, 608 MT8188_TOP_AXI_PROT_EN_MM_SET, 609 MT8188_TOP_AXI_PROT_EN_MM_CLR, 610 MT8188_TOP_AXI_PROT_EN_MM_STA), 611 BUS_PROT_WR(INFRA, 612 MT8188_TOP_AXI_PROT_EN_2_CAM_VCORE_STEP2, 613 MT8188_TOP_AXI_PROT_EN_2_SET, 614 MT8188_TOP_AXI_PROT_EN_2_CLR, 615 MT8188_TOP_AXI_PROT_EN_2_STA), 616 BUS_PROT_WR(INFRA, 617 MT8188_TOP_AXI_PROT_EN_1_CAM_VCORE_STEP3, 618 MT8188_TOP_AXI_PROT_EN_1_SET, 619 MT8188_TOP_AXI_PROT_EN_1_CLR, 620 MT8188_TOP_AXI_PROT_EN_1_STA), 621 BUS_PROT_WR(INFRA, 622 MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP4, 623 MT8188_TOP_AXI_PROT_EN_MM_SET, 624 MT8188_TOP_AXI_PROT_EN_MM_CLR, 625 MT8188_TOP_AXI_PROT_EN_MM_STA), 626 BUS_PROT_WR(INFRA, 627 MT8188_TOP_AXI_PROT_EN_MM_2_CAM_VCORE_STEP5, 628 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 629 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 630 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 631 }, 632 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY | 633 MTK_SCPD_EXT_BUCK_ISO, 634 }, 635 [MT8188_POWER_DOMAIN_CAM_MAIN] = { 636 .name = "cam_main", 637 .sta_mask = BIT(24), 638 .ctl_offs = 0x394, 639 .pwr_sta_offs = 0x16C, 640 .pwr_sta2nd_offs = 0x170, 641 .sram_pdn_bits = BIT(8), 642 .sram_pdn_ack_bits = BIT(12), 643 .bp_cfg = { 644 BUS_PROT_WR(INFRA, 645 MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP1, 646 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 647 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 648 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 649 BUS_PROT_WR(INFRA, 650 MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP2, 651 MT8188_TOP_AXI_PROT_EN_2_SET, 652 MT8188_TOP_AXI_PROT_EN_2_CLR, 653 MT8188_TOP_AXI_PROT_EN_2_STA), 654 BUS_PROT_WR(INFRA, 655 MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP3, 656 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 657 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 658 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 659 BUS_PROT_WR(INFRA, 660 MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP4, 661 MT8188_TOP_AXI_PROT_EN_2_SET, 662 MT8188_TOP_AXI_PROT_EN_2_CLR, 663 MT8188_TOP_AXI_PROT_EN_2_STA), 664 }, 665 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 666 }, 667 [MT8188_POWER_DOMAIN_CAM_SUBA] = { 668 .name = "cam_suba", 669 .sta_mask = BIT(25), 670 .ctl_offs = 0x398, 671 .pwr_sta_offs = 0x16C, 672 .pwr_sta2nd_offs = 0x170, 673 .sram_pdn_bits = BIT(8), 674 .sram_pdn_ack_bits = BIT(12), 675 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 676 }, 677 [MT8188_POWER_DOMAIN_CAM_SUBB] = { 678 .name = "cam_subb", 679 .sta_mask = BIT(26), 680 .ctl_offs = 0x39C, 681 .pwr_sta_offs = 0x16C, 682 .pwr_sta2nd_offs = 0x170, 683 .sram_pdn_bits = BIT(8), 684 .sram_pdn_ack_bits = BIT(12), 685 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 686 }, 687}; 688 689static const struct scpsys_soc_data mt8188_scpsys_data = { 690 .domains_data = scpsys_domain_data_mt8188, 691 .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8188), 692 .bus_prot_blocks = scpsys_bus_prot_blocks_mt8188, 693 .num_bus_prot_blocks = ARRAY_SIZE(scpsys_bus_prot_blocks_mt8188), 694}; 695 696#endif /* __SOC_MEDIATEK_MT8188_PM_DOMAINS_H */
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