FILE
mt8183-pm-domains.h

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linux-6.19.14/drivers/pmdomain/mediatek/mt8183-pm-domains.h C
  1/* SPDX-License-Identifier: GPL-2.0-only */
  2
  3#ifndef __SOC_MEDIATEK_MT8183_PM_DOMAINS_H
  4#define __SOC_MEDIATEK_MT8183_PM_DOMAINS_H
  5
  6#include "mtk-pm-domains.h"
  7#include <dt-bindings/power/mt8183-power.h>
  8
  9/*
 10 * MT8183 power domain support
 11 */
 12static enum scpsys_bus_prot_block scpsys_bus_prot_blocks_mt8183[] = {
 13	BUS_PROT_BLOCK_INFRA, BUS_PROT_BLOCK_SMI
 14};
 15
 16static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
 17	[MT8183_POWER_DOMAIN_AUDIO] = {
 18		.name = "audio",
 19		.sta_mask = PWR_STATUS_AUDIO,
 20		.ctl_offs = 0x0314,
 21		.pwr_sta_offs = 0x0180,
 22		.pwr_sta2nd_offs = 0x0184,
 23		.sram_pdn_bits = GENMASK(11, 8),
 24		.sram_pdn_ack_bits = GENMASK(15, 12),
 25	},
 26	[MT8183_POWER_DOMAIN_CONN] = {
 27		.name = "conn",
 28		.sta_mask = PWR_STATUS_CONN,
 29		.ctl_offs = 0x032c,
 30		.pwr_sta_offs = 0x0180,
 31		.pwr_sta2nd_offs = 0x0184,
 32		.sram_pdn_bits = 0,
 33		.sram_pdn_ack_bits = 0,
 34		.bp_cfg = {
 35			BUS_PROT_WR(INFRA,
 36				    MT8183_TOP_AXI_PROT_EN_CONN,
 37				    MT8183_TOP_AXI_PROT_EN_SET,
 38				    MT8183_TOP_AXI_PROT_EN_CLR,
 39				    MT8183_TOP_AXI_PROT_EN_STA1),
 40		},
 41	},
 42	[MT8183_POWER_DOMAIN_MFG_ASYNC] = {
 43		.name = "mfg_async",
 44		.sta_mask = PWR_STATUS_MFG_ASYNC,
 45		.ctl_offs = 0x0334,
 46		.pwr_sta_offs = 0x0180,
 47		.pwr_sta2nd_offs = 0x0184,
 48		.sram_pdn_bits = 0,
 49		.sram_pdn_ack_bits = 0,
 50		.caps = MTK_SCPD_DOMAIN_SUPPLY,
 51	},
 52	[MT8183_POWER_DOMAIN_MFG] = {
 53		.name = "mfg",
 54		.sta_mask = PWR_STATUS_MFG,
 55		.ctl_offs = 0x0338,
 56		.pwr_sta_offs = 0x0180,
 57		.pwr_sta2nd_offs = 0x0184,
 58		.sram_pdn_bits = GENMASK(8, 8),
 59		.sram_pdn_ack_bits = GENMASK(12, 12),
 60		.caps = MTK_SCPD_DOMAIN_SUPPLY,
 61	},
 62	[MT8183_POWER_DOMAIN_MFG_CORE0] = {
 63		.name = "mfg_core0",
 64		.sta_mask = BIT(7),
 65		.ctl_offs = 0x034c,
 66		.pwr_sta_offs = 0x0180,
 67		.pwr_sta2nd_offs = 0x0184,
 68		.sram_pdn_bits = GENMASK(8, 8),
 69		.sram_pdn_ack_bits = GENMASK(12, 12),
 70	},
 71	[MT8183_POWER_DOMAIN_MFG_CORE1] = {
 72		.name = "mfg_core1",
 73		.sta_mask = BIT(20),
 74		.ctl_offs = 0x0310,
 75		.pwr_sta_offs = 0x0180,
 76		.pwr_sta2nd_offs = 0x0184,
 77		.sram_pdn_bits = GENMASK(8, 8),
 78		.sram_pdn_ack_bits = GENMASK(12, 12),
 79	},
 80	[MT8183_POWER_DOMAIN_MFG_2D] = {
 81		.name = "mfg_2d",
 82		.sta_mask = PWR_STATUS_MFG_2D,
 83		.ctl_offs = 0x0348,
 84		.pwr_sta_offs = 0x0180,
 85		.pwr_sta2nd_offs = 0x0184,
 86		.sram_pdn_bits = GENMASK(8, 8),
 87		.sram_pdn_ack_bits = GENMASK(12, 12),
 88		.bp_cfg = {
 89			BUS_PROT_WR(INFRA,
 90				    MT8183_TOP_AXI_PROT_EN_1_MFG,
 91				    MT8183_TOP_AXI_PROT_EN_1_SET,
 92				    MT8183_TOP_AXI_PROT_EN_1_CLR,
 93				    MT8183_TOP_AXI_PROT_EN_STA1_1),
 94			BUS_PROT_WR(INFRA,
 95				    MT8183_TOP_AXI_PROT_EN_MFG,
 96				    MT8183_TOP_AXI_PROT_EN_SET,
 97				    MT8183_TOP_AXI_PROT_EN_CLR,
 98				    MT8183_TOP_AXI_PROT_EN_STA1),
 99		},
100	},
101	[MT8183_POWER_DOMAIN_DISP] = {
102		.name = "disp",
103		.sta_mask = PWR_STATUS_DISP,
104		.ctl_offs = 0x030c,
105		.pwr_sta_offs = 0x0180,
106		.pwr_sta2nd_offs = 0x0184,
107		.sram_pdn_bits = GENMASK(8, 8),
108		.sram_pdn_ack_bits = GENMASK(12, 12),
109		.bp_cfg = {
110			BUS_PROT_WR(INFRA,
111				    MT8183_TOP_AXI_PROT_EN_1_DISP,
112				    MT8183_TOP_AXI_PROT_EN_1_SET,
113				    MT8183_TOP_AXI_PROT_EN_1_CLR,
114				    MT8183_TOP_AXI_PROT_EN_STA1_1),
115			BUS_PROT_WR(INFRA,
116				    MT8183_TOP_AXI_PROT_EN_DISP,
117				    MT8183_TOP_AXI_PROT_EN_SET,
118				    MT8183_TOP_AXI_PROT_EN_CLR,
119				    MT8183_TOP_AXI_PROT_EN_STA1),
120			BUS_PROT_WR(SMI,
121				    MT8183_SMI_COMMON_SMI_CLAMP_DISP,
122				    MT8183_SMI_COMMON_CLAMP_EN_SET,
123				    MT8183_SMI_COMMON_CLAMP_EN_CLR,
124				    MT8183_SMI_COMMON_CLAMP_EN),
125		},
126	},
127	[MT8183_POWER_DOMAIN_CAM] = {
128		.name = "cam",
129		.sta_mask = BIT(25),
130		.ctl_offs = 0x0344,
131		.pwr_sta_offs = 0x0180,
132		.pwr_sta2nd_offs = 0x0184,
133		.sram_pdn_bits = GENMASK(9, 8),
134		.sram_pdn_ack_bits = GENMASK(13, 12),
135		.bp_cfg = {
136			BUS_PROT_WR(INFRA,
137				    MT8183_TOP_AXI_PROT_EN_MM_CAM,
138				    MT8183_TOP_AXI_PROT_EN_MM_SET,
139				    MT8183_TOP_AXI_PROT_EN_MM_CLR,
140				    MT8183_TOP_AXI_PROT_EN_MM_STA1),
141			BUS_PROT_WR(INFRA,
142				    MT8183_TOP_AXI_PROT_EN_CAM,
143				    MT8183_TOP_AXI_PROT_EN_SET,
144				    MT8183_TOP_AXI_PROT_EN_CLR,
145				    MT8183_TOP_AXI_PROT_EN_STA1),
146			BUS_PROT_WR_IGN(INFRA,
147					MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND,
148					MT8183_TOP_AXI_PROT_EN_MM_SET,
149					MT8183_TOP_AXI_PROT_EN_MM_CLR,
150					MT8183_TOP_AXI_PROT_EN_MM_STA1),
151			BUS_PROT_WR(SMI,
152				    MT8183_SMI_COMMON_SMI_CLAMP_CAM,
153				    MT8183_SMI_COMMON_CLAMP_EN_SET,
154				    MT8183_SMI_COMMON_CLAMP_EN_CLR,
155				    MT8183_SMI_COMMON_CLAMP_EN),
156		},
157	},
158	[MT8183_POWER_DOMAIN_ISP] = {
159		.name = "isp",
160		.sta_mask = PWR_STATUS_ISP,
161		.ctl_offs = 0x0308,
162		.pwr_sta_offs = 0x0180,
163		.pwr_sta2nd_offs = 0x0184,
164		.sram_pdn_bits = GENMASK(9, 8),
165		.sram_pdn_ack_bits = GENMASK(13, 12),
166		.bp_cfg = {
167			BUS_PROT_WR(INFRA,
168				    MT8183_TOP_AXI_PROT_EN_MM_ISP,
169				    MT8183_TOP_AXI_PROT_EN_MM_SET,
170				    MT8183_TOP_AXI_PROT_EN_MM_CLR,
171				    MT8183_TOP_AXI_PROT_EN_MM_STA1),
172			BUS_PROT_WR_IGN(INFRA,
173					MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND,
174					MT8183_TOP_AXI_PROT_EN_MM_SET,
175					MT8183_TOP_AXI_PROT_EN_MM_CLR,
176					MT8183_TOP_AXI_PROT_EN_MM_STA1),
177			BUS_PROT_WR(SMI,
178				    MT8183_SMI_COMMON_SMI_CLAMP_ISP,
179				    MT8183_SMI_COMMON_CLAMP_EN_SET,
180				    MT8183_SMI_COMMON_CLAMP_EN_CLR,
181				    MT8183_SMI_COMMON_CLAMP_EN),
182		},
183	},
184	[MT8183_POWER_DOMAIN_VDEC] = {
185		.name = "vdec",
186		.sta_mask = BIT(31),
187		.ctl_offs = 0x0300,
188		.pwr_sta_offs = 0x0180,
189		.pwr_sta2nd_offs = 0x0184,
190		.sram_pdn_bits = GENMASK(8, 8),
191		.sram_pdn_ack_bits = GENMASK(12, 12),
192		.bp_cfg = {
193			BUS_PROT_WR(SMI,
194				    MT8183_SMI_COMMON_SMI_CLAMP_VDEC,
195				    MT8183_SMI_COMMON_CLAMP_EN_SET,
196				    MT8183_SMI_COMMON_CLAMP_EN_CLR,
197				    MT8183_SMI_COMMON_CLAMP_EN),
198		},
199	},
200	[MT8183_POWER_DOMAIN_VENC] = {
201		.name = "venc",
202		.sta_mask = PWR_STATUS_VENC,
203		.ctl_offs = 0x0304,
204		.pwr_sta_offs = 0x0180,
205		.pwr_sta2nd_offs = 0x0184,
206		.sram_pdn_bits = GENMASK(11, 8),
207		.sram_pdn_ack_bits = GENMASK(15, 12),
208		.bp_cfg = {
209			BUS_PROT_WR(SMI,
210				    MT8183_SMI_COMMON_SMI_CLAMP_VENC,
211				    MT8183_SMI_COMMON_CLAMP_EN_SET,
212				    MT8183_SMI_COMMON_CLAMP_EN_CLR,
213				    MT8183_SMI_COMMON_CLAMP_EN),
214		},
215	},
216	[MT8183_POWER_DOMAIN_VPU_TOP] = {
217		.name = "vpu_top",
218		.sta_mask = BIT(26),
219		.ctl_offs = 0x0324,
220		.pwr_sta_offs = 0x0180,
221		.pwr_sta2nd_offs = 0x0184,
222		.sram_pdn_bits = GENMASK(8, 8),
223		.sram_pdn_ack_bits = GENMASK(12, 12),
224		.bp_cfg = {
225			BUS_PROT_WR(INFRA,
226				    MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP,
227				    MT8183_TOP_AXI_PROT_EN_MM_SET,
228				    MT8183_TOP_AXI_PROT_EN_MM_CLR,
229				    MT8183_TOP_AXI_PROT_EN_MM_STA1),
230			BUS_PROT_WR(INFRA,
231				    MT8183_TOP_AXI_PROT_EN_VPU_TOP,
232				    MT8183_TOP_AXI_PROT_EN_SET,
233				    MT8183_TOP_AXI_PROT_EN_CLR,
234				    MT8183_TOP_AXI_PROT_EN_STA1),
235			BUS_PROT_WR(INFRA,
236				    MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND,
237				    MT8183_TOP_AXI_PROT_EN_MM_SET,
238				    MT8183_TOP_AXI_PROT_EN_MM_CLR,
239				    MT8183_TOP_AXI_PROT_EN_MM_STA1),
240			BUS_PROT_WR(SMI,
241				    MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP,
242				    MT8183_SMI_COMMON_CLAMP_EN_SET,
243				    MT8183_SMI_COMMON_CLAMP_EN_CLR,
244				    MT8183_SMI_COMMON_CLAMP_EN),
245		},
246	},
247	[MT8183_POWER_DOMAIN_VPU_CORE0] = {
248		.name = "vpu_core0",
249		.sta_mask = BIT(27),
250		.ctl_offs = 0x33c,
251		.pwr_sta_offs = 0x0180,
252		.pwr_sta2nd_offs = 0x0184,
253		.sram_pdn_bits = GENMASK(11, 8),
254		.sram_pdn_ack_bits = GENMASK(13, 12),
255		.bp_cfg = {
256			BUS_PROT_WR(INFRA,
257				    MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0,
258				    MT8183_TOP_AXI_PROT_EN_MCU_SET,
259				    MT8183_TOP_AXI_PROT_EN_MCU_CLR,
260				    MT8183_TOP_AXI_PROT_EN_MCU_STA1),
261			BUS_PROT_WR(INFRA,
262				    MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND,
263				    MT8183_TOP_AXI_PROT_EN_MCU_SET,
264				    MT8183_TOP_AXI_PROT_EN_MCU_CLR,
265				    MT8183_TOP_AXI_PROT_EN_MCU_STA1),
266		},
267		.caps = MTK_SCPD_SRAM_ISO,
268	},
269	[MT8183_POWER_DOMAIN_VPU_CORE1] = {
270		.name = "vpu_core1",
271		.sta_mask = BIT(28),
272		.ctl_offs = 0x0340,
273		.pwr_sta_offs = 0x0180,
274		.pwr_sta2nd_offs = 0x0184,
275		.sram_pdn_bits = GENMASK(11, 8),
276		.sram_pdn_ack_bits = GENMASK(13, 12),
277		.bp_cfg = {
278			BUS_PROT_WR(INFRA,
279				    MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1,
280				    MT8183_TOP_AXI_PROT_EN_MCU_SET,
281				    MT8183_TOP_AXI_PROT_EN_MCU_CLR,
282				    MT8183_TOP_AXI_PROT_EN_MCU_STA1),
283			BUS_PROT_WR(INFRA,
284				    MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND,
285				    MT8183_TOP_AXI_PROT_EN_MCU_SET,
286				    MT8183_TOP_AXI_PROT_EN_MCU_CLR,
287				    MT8183_TOP_AXI_PROT_EN_MCU_STA1),
288		},
289		.caps = MTK_SCPD_SRAM_ISO,
290	},
291};
292
293static const struct scpsys_soc_data mt8183_scpsys_data = {
294	.domains_data = scpsys_domain_data_mt8183,
295	.num_domains = ARRAY_SIZE(scpsys_domain_data_mt8183),
296	.bus_prot_blocks = scpsys_bus_prot_blocks_mt8183,
297	.num_bus_prot_blocks = ARRAY_SIZE(scpsys_bus_prot_blocks_mt8183),
298};
299
300#endif /* __SOC_MEDIATEK_MT8183_PM_DOMAINS_H */
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